SN74LS165 8-Bit Parallel-to-Serial Shift Register The SN74LS165 is an 8-bit parallel load or serial-in register with complementary outputs available from the last stage. Parallel inputing occurs asynchronously when the Parallel Load (PL) input is LOW. With PL HIGH, serial shifting occurs on the rising edge of the clock; new data enters via the Serial Data (DS) input. The 2-input OR clock can be used to combine two independent clock sources, or one input can act as an active LOW clock enable. http://onsemi.com LOW POWER SCHOTTKY GUARANTEED OPERATING RANGES Symbol VCC Parameter Supply Voltage Min Typ Max Unit 4.75 5.0 5.25 V 0 25 70 °C TA Operating Ambient Temperature Range IOH Output Current – High – 0.4 mA IOL Output Current – Low 8.0 mA 16 1 PLASTIC N SUFFIX CASE 648 16 1 SOIC D SUFFIX CASE 751B ORDERING INFORMATION Semiconductor Components Industries, LLC, 1999 December, 1999 – Rev. 6 1 Device Package Shipping SN74LS165N 16 Pin DIP 2000 Units/Box SN74LS165D 16 Pin 2500/Tape & Reel Publication Order Number: SN74LS165/D SN74LS165 CONNECTION DIAGRAM DIP (TOP VIEW) VCC CP2 P3 P2 P1 P0 DS Q7 16 15 14 13 12 11 10 9 NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package. 1 PL 2 CP1 3 P4 4 P5 5 P6 6 P7 8 GND 7 Q7 LOADING (Note a) PIN NAMES CP1, CP2 DS PL P0 – P7 Q7 Q7 Clock (LOW–to–HIGH Going Edge) Inputs Serial Data Input Asynchronous Parallel Load (Active LOW) Input Parallel Data Inputs Serial Output from Last State Complementary Output NOTES: a) 1 TTL Unit Load (U.L.) = 40 mA HIGH/1.6 mA LOW. LOGIC SYMBOL 1 11 12 13 14 3 4 5 6 10 PL P0 P1 P2 P3 P4 P5 P6 P7 DS Q7 9 2 15 CP 7 Q7 VCC = PIN 16 GND = PIN 8 http://onsemi.com 2 HIGH LOW 0.5 U.L. 0.5 U.L. 1.5 U.L. 0.5 U.L. 10 U.L. 10 U.L. 0.25 U.L. 0.25 U.L. 0.75 U.L. 0.25 U.L. 5 U.L. 5 U.L. SN74LS165 LOGIC DIAGRAM 11 12 13 14 3 4 5 6 P0 P1 P2 P3 P4 P5 P6 P7 10 DS 2 CP1 15 CP2 PRESET Q0 S CP PRESET Q1 S CP PRESET S Q2 CP PRESET S Q3 CP PRESET Q4 S CP PRESET S Q5 CP PRESET S Q6 CP PRESET Q7 S CP R CLQ0 R CL Q1 R CLQ2 R CLQ3 R CLQ4 R CLQ5 R CLQ6 R CL Q7 9 7 1 PL VCC = PIN 16 GND = PIN 8 = PIN NUMBERS FUNCTIONAL DESCRIPTION The SN74LS165 contains eight clocked master/slave RS flip-flops connected as a shift register, with auxiliary gating to provide overriding asynchronous parallel entry. Parallel data enters when the PL signal is LOW. The parallel data can change while PL is LOW, provided that the recommended setup and hold times are observed. For clock operation, PL must be HIGH. The two clock inputs perform identically; one can be used as a clock inhibit by applying a HIGH signal. To avoid double clocking, however, the inhibit signal should only go HIGH while the clock is HIGH. Otherwise, the rising inhibit signal will cause the same response as a rising clock edge. The flip-flops are edge-triggered for serial operations. The serial input data can change at any time, provided only that the recommended setup and hold times are observed, with respect to the rising edge of the clock. TRUTH TABLE CP CONTENTS PL L H H H H RESPONSE 1 2 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 X L H X P0 DS Q0 DS Q0 P1 Q0 Q1 Q0 Q1 P2 Q1 Q2 Q1 Q2 P3 Q2 Q3 Q2 Q3 P4 Q3 Q4 Q3 Q4 P5 Q4 Q5 Q4 Q5 P6 Q5 Q6 Q5 Q6 P7 Q6 Q7 Q6 Q7 L H H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial http://onsemi.com 3 Parallel Entry Right Shift No Change Right Shift No Change SN74LS165 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol Parameter VIH Input HIGH Voltage VIL Input LOW Voltage VIK Input Clamp Diode Voltage VOH Output HIGH Voltage VOL O Output LOW Voltage Min Typ 2.0 0.8 – 0.65 2.7 Input LOW Current Other Inputs PL Input IOS Short Circuit Current (Note 1) ICC Power Supply Current Unit Test Conditions V Guaranteed Input HIGH Voltage for All Inputs V Guaranteed Input LOW Voltage for All Inputs V VCC = MIN, IIN = – 18 mA V VCC = MIN, IOH = MAX, VIN = VIH or VIL per Truth Table VCC = VCC MIN, VIN = VIL or VIH per Truth Table 0.25 0.4 V IOL = 4.0 mA 0.35 0.5 V IOL = 8.0 mA 20 60 µA VCC = MAX, VIN = 2.7 V mA VCC = MAX, VIN = 7.0 V – 0.4 – 1.2 mA VCC = MAX, VIN = 0.4 V – 100 mA VCC = MAX 36 mA VCC = MAX Other Inputs PL Input IIL – 1.5 3.5 Input HIGH Current Other Inputs PL Input IIH Max 0.1 0.3 – 20 Note 1: Not more than one output should be shorted at a time, nor for more than 1 second. AC CHARACTERISTICS (TA = 25°C) Limits Symbol Parameter Min Typ 25 35 Max Unit fMAX Maximum Input Clock Frequency tPLH tPHL Propagation Delay PL to Output 22 22 35 35 ns tPLH tPHL Propagation Delay Clock to Output 27 28 40 40 ns tPLH tPHL Propagation Delay P7 to Q7 14 21 25 30 ns tPLH tPHL Propagation Delay P7 to Q7 21 16 30 25 ns Max Unit Test Conditions MHz VCC = 5.0 V CL = 15 pF F AC SETUP REQUIREMENTS (TA = 25°C) Limits Symbol Parameter Min Typ tW CP Clock Pulse Width 25 ns tW PL Pulse Width 15 ns ts Parallel Data Setup Time 10 ns ts Serial Data Setup Time 20 ns ts CP1 to CP2 Setup Time1 30 ns th Hold Time 0 ns Recovery Time, PL to CP 45 ns trec 1 The role of CP1 and CP2 in an application may be interchanged. http://onsemi.com 4 Test Conditions VCC = 5.0 V SN74LS165 DEFINITION OF TERMS: SETUP TIME (ts) — is defined as the minimum time required for the correct logic level to be present at the logic input prior to the clock transition from LOW-to-HIGH in order to be recognized and transferred to the outputs. HOLD TIME (th) — is defined as the minimum time following the clock transition from LOW-to-HIGH that the logic level must be maintained at the input in order to ensure continued recognition. A negative hold time indicates that the correct logic level may be released prior to the clock transition from LOW-to-HIGH and still be recognized. RECOVERY TIME (trec) — is defined as the minimum time required between the end of the PL pulse and the clock transition from LOW-to-HIGH in order to recognize and transfer loaded Data to the Q outputs. AC WAVEFORMS CP1 tW 1/fmax ts CP2 PL 1.3 V tW 1.3 V tPHL 1.3 V Q7 OR Q7 Figure 1. PL OR CP Figure 2. 1.3 V 1.3 V th(H) ts(H) 1.3 V 1.3 V 1.3 V 1.3 V Pn 1.3 V tPLH tPLH tPHL Q7 OR Q7 1.3 V 1.3 V PL th(L) ts(L) 1.3 V 1.3 V trec tW 1.3 V CP Figure 3. 1.3 V Figure 4. http://onsemi.com 5 SN74LS165 PACKAGE DIMENSIONS N SUFFIX PLASTIC PACKAGE CASE 648–08 ISSUE R NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. –A– 16 9 1 8 B F C L S –T– SEATING PLANE K H G D M J 16 PL 0.25 (0.010) M T A M http://onsemi.com 6 DIM A B C D F G H J K L M S INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0_ 10 _ 0.020 0.040 MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0_ 10 _ 0.51 1.01 SN74LS165 PACKAGE DIMENSIONS D SUFFIX PLASTIC SOIC PACKAGE CASE 751B–05 ISSUE J –A– 16 9 1 8 –B– P NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 8 PL 0.25 (0.010) M B S G R K F X 45 _ C –T– SEATING PLANE J M D 16 PL 0.25 (0.010) M T B S A S http://onsemi.com 7 DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019 SN74LS165 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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