PD - 97273F IRF6712SPbF IRF6712STRPbF DirectFET Power MOSFET Typical values (unless otherwise specified) l RoHS Compliant and Halogen Free VDSS l Low Profile (<0.7 mm) VGS RDS(on) RDS(on) l Dual Sided Cooling Compatible 25V max ±20V max 3.8mΩ@ 10V 6.7mΩ@ 4.5V l Ultra Low Package Inductance Qg l Optimized for High Frequency Switching Qgd Qgs2 Qrr Qoss Vgs(th) 4.0nC 1.7nC 14nC 10nC 1.9V tot 12nC l Ideal for CPU Core DC-DC Converters l Optimized for both Sync.FET and some Control FET application l Low Conduction and Switching Losses l Compatible with existing Surface Mount Techniques l 100% Rg tested DirectFET ISOMETRIC SQ Applicable DirectFET Outline and Substrate Outline (see p.7,8 for details) SX SQ ST MQ MX MT MP Description The IRF6712SPbF combines the latest HEXFET® Power MOSFET Silicon technology with the advanced DirectFETTM packaging to achieve the lowest on-state resistance in a package that has the footprint of a MICRO-8 and only 0.7 mm profile. The DirectFET package is compatible with existing layout geometries used in power applications, PCB assembly equipment and vapor phase, infra-red or convection soldering techniques, when application note AN-1035 is followed regarding the manufacturing methods and processes. The DirectFET package allows dual sided cooling to maximize thermal transfer in power systems, improving previous best thermal resistance by 80%. The IRF6712SPbF balances both low resistance and low charge along with ultra low package inductance to reduce both conduction and switching losses. The reduced total losses make this product ideal for high efficiency DC-DC converters that power the latest generation of processors operating at higher frequencies. The IRF6712SPbF has been optimized for parameters that are critical in synchronous buck operating from 12 volt bus converters including Rds(on) and gate charge to minimize losses. Absolute Maximum Ratings Parameter Drain-to-Source Voltage Gate-to-Source Voltage Continuous Drain Current, VGS @ 10V Continuous Drain Current, VGS @ 10V Continuous Drain Current, VGS @ 10V VGS ID @ TA = 25°C ID @ TA = 70°C ID @ TC = 25°C IDM EAS IAR g Pulsed Drain Current Single Pulse Avalanche Energy Avalanche Current g h Typical RDS(on) (mΩ) 12 ID = 17A 10 8 T J = 125°C 6 4 TJ = 25°C 2 0 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 VGS, Gate -to -Source Voltage (V) Fig 1. Typical On-Resistance Vs. Gate Voltage Notes: Click on this section to link to the appropriate technical paper. Click on this section to link to the DirectFET Website. Surface mounted on 1 in. square Cu board, steady state. www.irf.com e e f VGS, Gate-to-Source Voltage (V) VDS Max. Units 25 ±20 17 13 68 130 13 13 V A mJ A 14.0 ID= 13A 12.0 VDS= 20V VDS= 13V 10.0 8.0 6.0 4.0 2.0 0.0 0 5 10 15 20 25 30 35 QG Total Gate Charge (nC) Fig 2. Typical Total Gate Charge vs Gate-to-Source Voltage TC measured with thermocouple mounted to top (Drain) of part. Repetitive rating; pulse width limited by max. junction temperature. Starting TJ = 25°C, L = 0.14mH, RG = 25Ω, IAS = 13A. 1 04/29/09 IRF6712SPbF Static @ TJ = 25°C (unless otherwise specified) Parameter BVDSS ∆ΒVDSS/∆TJ RDS(on) VGS(th) ∆VGS(th)/∆TJ IDSS IGSS gfs Qg Qgs1 Qgs2 Qgd Qgodr Qsw Qoss RG td(on) tr td(off) tf Ciss Coss Crss Conditions Min. Typ. Max. Units Drain-to-Source Breakdown Voltage Breakdown Voltage Temp. Coefficient 25 ––– ––– 18 ––– ––– Static Drain-to-Source On-Resistance ––– ––– 3.8 6.7 4.9 8.7 Gate Threshold Voltage Gate Threshold Voltage Coefficient 1.4 ––– 1.9 -6.1 2.4 ––– V mV/°C Drain-to-Source Leakage Current ––– ––– ––– ––– 1.0 150 µA VDS = 25V, VGS = 0V Gate-to-Source Forward Leakage Gate-to-Source Reverse Leakage ––– ––– ––– ––– 100 -100 nA VDS = 25V, VGS = 0V, TJ = 125°C VGS = 20V Forward Transconductance Total Gate Charge 40 ––– ––– 12 ––– 18 S VGS = -20V VDS = 13V, ID = 13A Pre-Vth Gate-to-Source Charge Post-Vth Gate-to-Source Charge ––– ––– 2.9 1.7 ––– ––– Gate-to-Drain Charge Gate Charge Overdrive Switch Charge (Qgs2 + Qgd) ––– ––– 4.0 3.5 ––– ––– Output Charge ––– ––– 5.8 10 ––– ––– Gate Resistance Turn-On Delay Time ––– ––– 1.7 11 3.0 ––– Ω Rise Time Turn-Off Delay Time ––– ––– 40 14 ––– ––– ns Fall Time Input Capacitance ––– ––– 12 1570 ––– ––– Output Capacitance Reverse Transfer Capacitance ––– ––– 490 210 ––– ––– Min. Typ. Max. Units V VGS = 0V, ID = 250µA mV/°C Reference to 25°C, ID = 1mA mΩ VGS = 10V, ID = 17A i i VGS = 4.5V, ID = 13A VDS = VGS, ID = 50µA VDS = 13V nC VGS = 4.5V ID = 13A See Fig. 15 nC VDS = 16V, VGS = 0V i VDD = 13V, VGS = 4.5V ID = 13A RG = 1.8Ω pF See Fig. 17 VGS = 0V VDS = 13V ƒ = 1.0MHz Diode Characteristics Parameter IS Continuous Source Current (Body Diode) ––– ––– 17 ISM Pulsed Source Current (Body Diode) ––– ––– 2.7 VSD Diode Forward Voltage ––– 0.81 1.0 trr Qrr g Reverse Recovery Time Reverse Recovery Charge ––– ––– 17 14 26 21 Conditions A MOSFET symbol showing the V integral reverse p-n junction diode. TJ = 25°C, IS = 13A, VGS = 0V ns nC TJ = 25°C, IF = 13A di/dt = 200A/µs i i Notes: Pulse width ≤ 400µs; duty cycle ≤ 2%. 2 www.irf.com IRF6712SPbF Absolute Maximum Ratings e e f PD @TA = 25°C PD @TA = 70°C PD @TC = 25°C TP TJ TSTG Max. Units 2.2 1.4 36 270 -40 to + 150 W Parameter Power Dissipation Power Dissipation Power Dissipation Peak Soldering Temperature Operating Junction and Storage Temperature Range °C Thermal Resistance Parameter el jl kl fl RθJA RθJA RθJA RθJC RθJ-PCB Typ. Max. Units ––– 12.5 20 ––– 1.0 58 ––– ––– 3.5 ––– °C/W Junction-to-Ambient Junction-to-Ambient Junction-to-Ambient Junction-to-Case Junction-to-PCB Mounted Linear Derating Factor e 0.017 W/°C 100 Thermal Response ( Z thJA ) D = 0.50 10 0.20 0.10 0.05 1 0.02 0.01 τJ 0.1 0.01 0.001 1E-006 R1 R1 τJ τ1 R2 R2 R3 R3 R4 R4 Ri (°C/W) R5 R5 τA τ1 τ2 τ2 τ3 τ3 τ4 τ4 τ5 τA τ5 Ci= τi/Ri Ci= τi/Ri SINGLE PULSE ( THERMAL RESPONSE ) 1E-005 0.0001 τi (sec) 1.61955 0.000126 2.14056 0.001354 22.2887 0.375850 20.0457 7.41 11.9144 99 Notes: 1. Duty Factor D = t1/t2 2. Peak Tj = P dm x Zthja + Tc 0.001 0.01 0.1 1 10 100 1000 t1 , Rectangular Pulse Duration (sec) Fig 3. Maximum Effective Transient Thermal Impedance, Junction-to-Ambient Notes: Used double sided cooling , mounting pad with large heatsink. Mounted on minimum footprint full size board with metalized Rθ is measured at TJ of approximately 90°C. back and with small clip heatsink. Surface mounted on 1 in. square Cu (still air). www.irf.com Mounted to a PCB with small clip heatsink (still air) Mounted on minimum footprint full size board with metalized back and with small clip heatsink (still air) 3 IRF6712SPbF ≤60µs PULSE WIDTH Tj = 25°C 1000 TOP ID, Drain-to-Source Current (A) 100 BOTTOM 10 VGS 10V 5.0V 4.5V 4.0V 3.5V 3.0V 2.8V 2.5V TOP 100 1 0.1 ≤60µs PULSE WIDTH Tj = 150°C ID, Drain-to-Source Current (A) 1000 2.5V BOTTOM VGS 10V 5.0V 4.5V 4.0V 3.5V 3.0V 2.8V 2.5V 10 2.5V 0.01 1 0.1 1 10 100 0.1 VDS, Drain-to-Source Voltage (V) Fig 4. Typical Output Characteristics ID = 17A Typical RDS(on) (Normalized) ID, Drain-to-Source Current (A) 100 2.0 VDS = 15V ≤60µs PULSE WIDTH 100 TJ = 150°C TJ = 25°C TJ = -40°C 10 1 0.1 V GS = 10V 1.5 V GS = 4.5V 1.0 0.5 1 2 3 4 5 25 VGS = 0V, f = 1 MHZ C iss = C gs + C gd, C ds SHORTED T J = 25°C C rss = C gd Vgs = 4.0V Vgs = 4.5V Vgs = 5.0V Vgs = 10V 20 Typical RDS(on) ( mΩ) C oss = C ds + C gd Ciss 1000 20 40 60 80 100 120 140 160 Fig 7. Normalized On-Resistance vs. Temperature Fig 6. Typical Transfer Characteristics 10000 -60 -40 -20 0 T J , Junction Temperature (°C) VGS, Gate-to-Source Voltage (V) C, Capacitance(pF) 10 Fig 5. Typical Output Characteristics 1000 Coss Crss 15 10 5 0 100 1 10 100 VDS, Drain-to-Source Voltage (V) Fig 8. Typical Capacitance vs.Drain-to-Source Voltage 4 1 V DS, Drain-to-Source Voltage (V) 0 50 100 150 ID, Drain Current (A) Fig 9. Typical On-Resistance Vs. Drain Current and Gate Voltage www.irf.com IRF6712SPbF 1000 1000 ID, Drain-to-Source Current (A) ISD, Reverse Drain Current (A) VGS = 0V OPERATION IN THIS AREA LIMITED BY R DS(on) 100 100 10 T J = 150°C T J = 25°C T J = -40°C 1 100µsec 10 10msec 1msec 1 T A = 25°C T J = 150°C Single Pulse 0.1 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 0.10 3.5 Fig 10. Typical Source-Drain Diode Forward Voltage 3.0 Typical VGS(th) Gate threshold Voltage (V) ID, Drain Current (A) 60 50 40 30 20 10 2.5 2.0 ID = 50µA ID = 100µA 1.5 100 125 ID = 250µA ID = 1.0mA ID = 1.0A 1.0 0 75 100.00 Fig11. Maximum Safe Operating Area 70 50 10.00 VDS, Drain-to-Source Voltage (V) VSD, Source-to-Drain Voltage (V) 25 1.00 -75 -50 -25 150 0 25 50 75 100 125 150 T J , Temperature ( °C ) T C , Case Temperature (°C) Fig 12. Maximum Drain Current vs. Case Temperature Fig 13. Typical Threshold Voltage vs. Junction Temperature EAS , Single Pulse Avalanche Energy (mJ) 60 ID 3.8A 5.4A BOTTOM 13A TOP 50 40 30 20 10 0 25 50 75 100 125 150 Starting T J , Junction Temperature (°C) Fig 14. Maximum Avalanche Energy vs. Drain Current www.irf.com 5 IRF6712SPbF Id Vds Vgs L VCC DUT 0 20K 1K Vgs(th) S Qgodr Fig 15a. Gate Charge Test Circuit Qgd Qgs2 Qgs1 Fig 15b. Gate Charge Waveform V(BR)DSS 15V DRIVER L VDS tp D.U.T V RGSG + - VDD IAS 20V tp A I AS 0.01Ω Fig 16b. Unclamped Inductive Waveforms Fig 16a. Unclamped Inductive Test Circuit VDS VGS RG RD VDS 90% D.U.T. + - V DD VGS Pulse Width ≤ 1 µs Duty Factor ≤ 0.1 % 10% VGS td(on) Fig 17a. Switching Time Test Circuit 6 tr t d(off) tf Fig 17b. Switching Time Waveforms www.irf.com IRF6712SPbF Driver Gate Drive D.U.T + - RG * • • • • *** D.U.T. ISD Waveform Reverse Recovery Current + dv/dt controlled by RG Driver same type as D.U.T. I SD controlled by Duty Factor "D" D.U.T. - Device Under Test V DD ** P.W. Period VGS=10V Circuit Layout Considerations • Low Stray Inductance • Ground Plane • Low Leakage Inductance Current Transformer - D= Period P.W. + + Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt Re-Applied Voltage - Body Diode VDD Forward Drop Inductor Curent Ripple ≤ 5% * Use P-Channel Driver for P-Channel Measurements ** Reverse Polarity for P-Channel ISD *** VGS = 5V for Logic Level Devices Fig 18. Diode Reverse Recovery Test Circuit for HEXFET® Power MOSFETs DirectFET Board Footprint, SQ Outline (Small Size Can, Q-Designation). Please see DirectFET application note AN-1035 for all details regarding the assembly of DirectFET. This includes all recommendations for stencil and substrate designs. G = GATE D = DRAIN S = SOURCE D D G D www.irf.com S D 7 IRF6712SPbF DirectFET Outline Dimension, SQ Outline (Small Size Can, Q-Designation). Please see DirectFET application note AN-1035 for all details regarding the assembly of DirectFET. This includes all recommendations for stencil and substrate designs. DIMENSIONS METRIC MAX CODE MIN 4.85 4.75 A 3.95 B 3.70 2.85 C 2.75 0.45 0.35 D 0.52 E 0.48 0.82 0.78 F 0.92 G 0.88 0.82 H 0.78 N/A J N/A 0.97 K 0.93 2.10 L 2.00 M 0.616 0.676 R 0.020 0.080 0.17 P 0.08 IMPERIAL MIN MAX 0.187 0.191 0.146 0.156 0.108 0.112 0.014 0.018 0.019 0.020 0.031 0.032 0.035 0.036 0.031 0.032 N/A N/A 0.037 0.038 0.079 0.083 0.0235 0.0274 0.0008 0.0031 0.003 0.007 DirectFET Part Marking Line above the last character of the date code indicates "Lead-Free" Note: For the most current drawing please refer to IR website at http://www.irf.com/package/ 8 www.irf.com IRF6712SPbF DirectFET Tape & Reel Dimension (Showing component orientation). NOTE: Controlling dimensions in mm Std reel quantity is 4800 parts. (ordered as IRF6712TRPBF). For 1000 parts on 7" reel, order IRF6712TR1PBF REEL DIMENSIONS STANDARD OPTION (QTY 4800) TR1 OPTION IMPERIAL METRIC METRIC MIN MAX MIN MIN CODE MAX MAX 12.992 A N.C N.C 177.77 N.C 330.0 0.795 B N.C 19.06 20.2 N.C N.C 0.504 C 0.520 13.5 12.8 13.2 12.8 0.059 D N.C 1.5 1.5 N.C N.C 3.937 E 58.72 100.0 N.C N.C N.C N.C F N.C N.C 18.4 0.724 13.50 0.488 G 0.567 11.9 12.4 14.4 12.01 H 0.469 0.606 11.9 11.9 15.4 12.01 (QTY 1000) IMPERIAL MIN MAX 6.9 N.C 0.75 N.C 0.53 0.50 0.059 N.C 2.31 N.C N.C 0.53 0.47 N.C 0.47 N.C Loaded Tape Feed Direction NOTE: CONTROLLING DIMENSIONS IN MM CODE A B C D E F G H DIMENSIONS METRIC IMPERIAL MIN MIN MAX MAX 0.311 7.90 0.319 8.10 0.154 0.161 3.90 4.10 0.469 11.90 0.484 12.30 0.215 5.45 0.219 5.55 0.158 4.00 0.165 4.20 0.197 5.00 0.205 5.20 0.059 1.50 N.C N.C 0.059 1.50 0.063 1.60 Note: For the most current drawing please refer to IR website at http://www.irf.com/package/ Data and specifications subject to change without notice. This product has been designed and qualified for the Consumer market. Qualification Standards can be found on IR’s Web site. IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information.04/2009 www.irf.com 9