IRF IRF6717MTRPBF

PD - 97345A
IRF6717MPbF
IRF6717MTRPbF
DirectFET™ Power MOSFET ‚
Typical values (unless otherwise specified)
l RoHs Compliant and Halgen Free 
VDSS
l Low Profile (<0.7 mm)
VGS
RDS(on)
RDS(on)
l Dual Sided Cooling Compatible 
25V max ±20V max 0.95mΩ@ 10V 1.6mΩ@ 4.5V
l Ultra Low Package Inductance
Qg
l Optimized for High Frequency Switching 
tot
46nC
Qgd
Qgs2
Qrr
Qoss
Vgs(th)
14nC
6.6nC
31nC
35nC
1.8V
l Ideal for CPU Core DC-DC Converters
l Optimized for Sync. FET socket of Sync. Buck Converter
l Low Conduction and Switching Losses
l Compatible with existing Surface Mount Techniques 
l100% Rg tested
MX
DirectFET™ ISOMETRIC
Applicable DirectFET Outline and Substrate Outline (see p.7,8 for details)
SQ
SX
ST
MQ
MT
MX
MP
Description
The IRF6717MPbF combines the latest HEXFET® Power MOSFET Silicon technology with the advanced DirectFETTM packaging to achieve
the lowest on-state resistance in a package that has the footprint of a SO-8 and only 0.7 mm profile. The DirectFET package is compatible
with existing layout geometries used in power applications, PCB assembly equipment and vapor phase, infra-red or convection soldering
techniques, when application note AN-1035 is followed regarding the manufacturing methods and processes. The DirectFET package allows
dual sided cooling to maximize thermal transfer in power systems, improving previous best thermal resistance by 80%.
The IRF6717MPbF balances both low resistance and low charge along with ultra low package inductance to reduce both conduction and
switching losses. The reduced total losses make this product ideal for high efficiency DC-DC converters that power the latest generation of
processors operating at higher frequencies. The IRF6717MPbF has been optimized for parameters that are critical in synchronous buck
including Rds(on), gate charge and Cdv/dt-induced turn on immunity. The IRF6717MPbF offers particularly low Rds(on) and high Cdv/dt
immunity for synchronous FET applications.
Absolute Maximum Ratings
Parameter
VDS
Drain-to-Source Voltage
Gate-to-Source Voltage
Continuous Drain Current, VGS @ 10V
Continuous Drain Current, VGS @ 10V
Continuous Drain Current, VGS @ 10V
Pulsed Drain Current
Single Pulse Avalanche Energy
Avalanche Current
VGS
ID @ TA = 25°C
ID @ TA = 70°C
ID @ TC = 25°C
IDM
EAS
IAR
g
h
g
VGS, Gate-to-Source Voltage (V)
Typical RDS(on) (mΩ)
6
ID = 30A
5
4
3
2
T J = 125°C
1
TJ = 25°C
0
2
4
6
8
10
12
14
16
18
20
VGS, Gate -to -Source Voltage (V)
Fig 1. Typical On-Resistance vs. Gate Voltage
Notes:
 Click on this section to link to the appropriate technical paper.
‚ Click on this section to link to the DirectFET Website.
ƒ Surface mounted on 1 in. square Cu board, steady state.
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e
e
f
Max.
Units
25
±20
38
30
220
300
290
30
V
A
mJ
A
14.0
ID= 30A
12.0
VDS= 20V
VDS= 13V
10.0
8.0
6.0
4.0
2.0
0.0
0
20
40
60
80
100
120
QG Total Gate Charge (nC)
Fig 2. Typical Total Gate Charge vs Gate-to-Source Voltage
„ TC measured with thermocouple mounted to top (Drain) of part.
… Repetitive rating; pulse width limited by max. junction temperature.
† Starting TJ = 25°C, L = 0.64mH, RG = 25Ω, IAS = 30A.
1
04/30/09
IRF6717MPbF
Static @ TJ = 25°C (unless otherwise specified)
Parameter
BVDSS
∆ΒVDSS/∆TJ
RDS(on)
VGS(th)
∆VGS(th)/∆TJ
IDSS
Min.
Typ. Max. Units
Drain-to-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
25
–––
–––
18
Static Drain-to-Source On-Resistance
–––
–––
0.95
1.6
Gate Threshold Voltage
Gate Threshold Voltage Coefficient
1.35
–––
1.8
-6.7
Drain-to-Source Leakage Current
–––
–––
Conditions
V VGS = 0V, ID = 250µA
mV/°C Reference to 25°C, ID = 1mA
1.25
mΩ VGS = 10V, ID = 38A
VGS = 4.5V, ID = 30A
2.1
2.35
V VDS = VGS, ID = 150µA
–––
–––
i
i
–––
mV/°C
–––
–––
1.0
150
µA
VDS = 20V, VGS = 0V
IGSS
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
–––
–––
–––
–––
100
-100
nA
VDS = 20V, VGS = 0V, TJ = 125°C
VGS = 20V
gfs
Qg
Qgs1
Forward Transconductance
Total Gate Charge
140
–––
–––
46
–––
69
S
VGS = -20V
VDS = 13V, ID =30A
Pre-Vth Gate-to-Source Charge
Post-Vth Gate-to-Source Charge
–––
–––
14
6.6
–––
–––
Gate-to-Drain Charge
Gate Charge Overdrive
Switch Charge (Qgs2 + Qgd)
–––
–––
14
11
–––
–––
Output Charge
–––
–––
20.6
35
–––
–––
Gate Resistance
Turn-On Delay Time
–––
–––
1.3
25
2.2
–––
Rise Time
Turn-Off Delay Time
–––
–––
37
19
–––
–––
Fall Time
Input Capacitance
–––
–––
15
6750
–––
–––
Output Capacitance
Reverse Transfer Capacitance
–––
–––
1700
730
–––
–––
Min.
Typ. Max. Units
Continuous Source Current
(Body Diode)
–––
–––
ISM
Pulsed Source Current
(Body Diode)
–––
–––
300
VSD
Diode Forward Voltage
–––
–––
trr
Reverse Recovery Time
Reverse Recovery Charge
–––
–––
27
31
Qgs2
Qgd
Qgodr
Qsw
Qoss
RG
td(on)
tr
td(off)
tf
Ciss
Coss
Crss
VDS = 13V
nC
VGS = 4.5V
ID = 30A
See Fig. 15
nC
VDS = 16V, VGS = 0V
Ω
i
VDD = 13V, VGS = 4.5V
ID = 30A
ns
RG= 1.8Ω
pF
VGS = 0V
VDS = 13V
ƒ = 1.0MHz
Diode Characteristics
Parameter
IS
Qrr
g
Conditions
A
MOSFET symbol
showing the
1.0
V
integral reverse
p-n junction diode.
TJ = 25°C, IS = 30A, VGS = 0V
41
47
ns
nC
120
TJ = 25°C, IF =30A
di/dt = 175A/µs
i
i
Notes:
… Repetitive rating; pulse width limited by max. junction temperature.
‡ Pulse width ≤ 400µs; duty cycle ≤ 2%.
2
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IRF6717MPbF
Absolute Maximum Ratings
e
e
f
Max.
Units
2.8
1.8
96
270
-40 to + 150
W
Parameter
Power Dissipation
Power Dissipation
Power Dissipation
Peak Soldering Temperature
Operating Junction and
Storage Temperature Range
PD @TA = 25°C
PD @TA = 70°C
PD @TC = 25°C
TP
TJ
TSTG
°C
Thermal Resistance
Parameter
el
jl
kl
fl
RθJA
RθJA
RθJA
RθJC
RθJ-PCB
Junction-to-Ambient
Junction-to-Ambient
Junction-to-Ambient
Junction-to-Case
Junction-to-PCB Mounted
Linear Derating Factor
e
Typ.
Max.
Units
–––
12.5
20
–––
1.0
45
–––
–––
1.3
–––
°C/W
0.022
W/°C
Thermal Response ( Z thJA )
100
10
1
D = 0.50
0.20
0.10
0.05
0.02
0.01
τJ
0.1
R1
R1
τJ
τ1
R2
R2
R3
R3
R4
R4
R5
R5
R6
R6
R7
R7
τ2
τ2
τ3
τ3
τ4
τ4
τ5
τ5
τ6
τ7
τ6
τi (sec)
0.0116
0.000007
0.0289
3.55E-06
0.2249
0.000076
0.3032
0.006892
0.7515
0.001645
2.7510
0.009995
17.682
38.19138
R8
R8
τA
τ1
Ri (°C/W)
τA
τ7
Ci= τi/Ri
Ci= τi/Ri
23.053
1.05185
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthja + Tc
0.01
SINGLE PULSE
( THERMAL RESPONSE )
0.001
1E-006
1E-005
0.0001
0.001
0.01
0.1
1
10
100
1000
t1 , Rectangular Pulse Duration (sec)
Fig 3. Maximum Effective Transient Thermal Impedance, Junction-to-Ambient 
Notes:
ˆ Used double sided cooling, mounting pad with large heatsink.
‰ Mounted on minimum footprint full size board with metalized
Š Rθ is measured at TJ of approximately 90°C.
back and with small clip heatsink.
ƒ Surface mounted on 1 in. square Cu
(still air).
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‰ Mounted to a PCB with
small clip heatsink (still air)
‰ Mounted on minimum
footprint full size board with
metalized back and with small
clip heatsink (still air)
3
IRF6717MPbF
1000
1000
ID, Drain-to-Source Current (A)
Tj = 25°C
TOP
100
BOTTOM
VGS
10V
5.0V
4.5V
3.5V
3.3V
3.0V
2.8V
2.5V
≤60µs PULSE WIDTH
Tj = 150°C
ID, Drain-to-Source Current (A)
≤60µs PULSE WIDTH
100
10
2.5V
1
0.1
1
BOTTOM
2.5V
1
10
100
0.1
1
10
100
V DS, Drain-to-Source Voltage (V)
Fig 4. Typical Output Characteristics
Fig 5. Typical Output Characteristics
1000
2.0
VDS = 15V
≤60µs PULSE WIDTH
ID = 38A
Typical RDS(on) (Normalized)
ID, Drain-to-Source Current (A)
VGS
10V
5.0V
4.5V
3.5V
3.3V
3.0V
2.8V
2.5V
10
VDS, Drain-to-Source Voltage (V)
100
TJ = 150°C
TJ = 25°C
TJ = -40°C
10
1
0.1
V GS = 10V
V GS = 4.5V
1.5
1.0
0.5
1
2
3
4
5
6
VGS = 0V,
f = 1 MHZ
C iss = C gs + C gd, C ds SHORTED
C rss = C gd
Typical RDS(on) ( mΩ)
Ciss
Coss
Crss
1000
T J = 25°C
Vgs = 3.5V
Vgs = 4.0V
Vgs = 4.5V
Vgs = 5.0V
Vgs = 10V
5
C oss = C ds + C gd
10000
20 40 60 80 100 120 140 160
Fig 7. Normalized On-Resistance vs. Temperature
Fig 6. Typical Transfer Characteristics
100000
-60 -40 -20 0
T J , Junction Temperature (°C)
VGS, Gate-to-Source Voltage (V)
C, Capacitance(pF)
TOP
4
3
2
1
100
0
1
10
100
VDS, Drain-to-Source Voltage (V)
Fig 8. Typical Capacitance vs.Drain-to-Source Voltage
4
0
50
100
150
200
ID, Drain Current (A)
Fig 9. Typical On-Resistance vs.
Drain Current and Gate Voltage
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IRF6717MPbF
1000
100
10
T J = 150°C
1
T J = 25°C
T J = -40°C
OPERATION IN THIS AREA
LIMITED BY R DS(on)
100µsec
ID, Drain-to-Source Current (A)
ISD, Reverse Drain Current (A)
1000
100
1msec
10
1
TA = 25°C
TJ = 150°C
VGS = 0V
Single Pulse
0.1
0
0.0
0.5
1.0
1.5
2.0
0.01
2.5
0.10
1.00
10.00
100.00
VDS, Drain-to-Source Voltage (V)
VSD, Source-to-Drain Voltage (V)
Fig 10. Typical Source-Drain Diode Forward Voltage
Fig11. Maximum Safe Operating Area
2.5
VGS(th) , Gate Threshold Voltage (V)
240
200
ID, Drain Current (A)
10msec
DC
160
120
80
40
2.0
ID = 150µA
1.5
1.0
0.5
0
25
50
75
100
125
-75 -50 -25
150
0
25
50
75 100 125 150
T J , Temperature ( °C )
T C , Case Temperature (°C)
Fig 12. Maximum Drain Current vs. Case Temperature
Fig 13. Typical Threshold Voltage vs. Junction
Temperature
EAS , Single Pulse Avalanche Energy (mJ)
1200
ID
19A
24A
BOTTOM 30A
TOP
1000
800
600
400
200
0
25
50
75
100
125
150
Starting T J , Junction Temperature (°C)
Fig 14. Maximum Avalanche Energy vs. Drain Current
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5
IRF6717MPbF
Id
Vds
Vgs
L
VCC
DUT
0
1K
Vgs(th)
Qgs1 Qgs2
Fig 15a. Gate Charge Test Circuit
Qgd
Qgodr
Fig 15b. Gate Charge Waveform
V(BR)DSS
15V
DRIVER
L
VDS
D.U.T
VGS
RG
20V
tp
+
- VDD
IAS
I AS
0.01Ω
tp
Fig 16a. Unclamped Inductive Test Circuit
VDS
VGS
RG
RD
Fig 16b. Unclamped Inductive Waveforms
VDS
90%
D.U.T.
+
- VDD
V10V
GS
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
Fig 17a. Switching Time Test Circuit
6
A
10%
VGS
td(on)
tr
td(off)
tf
Fig 17b. Switching Time Waveforms
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IRF6717MPbF
D.U.T
Driver Gate Drive
+
ƒ
+
‚
-
„
*
D.U.T. ISD Waveform
Reverse
Recovery
Current
+
Body Diode Forward
Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt

RG
•
•
•
•
di/dt controlled by RG
Driver same type as D.U.T.
I SD controlled by Duty Factor "D"
D.U.T. - Device Under Test
VDD
P.W.
Period
VGS=10V
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
-
D=
Period
P.W.
Re-Applied
Voltage
+
Body Diode
VDD
Forward Drop
Inductor
Current
Inductor Curent
-
Ripple ≤ 5%
ISD
* VGS = 5V for Logic Level Devices
Fig 18. Diode Reverse Recovery Test Circuit for N-Channel
HEXFET® Power MOSFETs
DirectFET™ Board Footprint, MX Outline
(Medium Size Can, X-Designation).
Please see DirectFET application note AN-1035 for all details regarding the assembly of DirectFET.
This includes all recommendations for stencil and substrate designs.
G = GATE
D = DRAIN
S = SOURCE
D
D
S
G
S
D
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D
7
IRF6717MPbF
DirectFET™ Outline Dimension, MX Outline
(Medium Size Can, X-Designation).
Please see AN-1035 for DirectFET assembly details and stencil and substrate design recommendations
DIMENSIONS
CODE
A
B
C
D
E
F
G
H
J
K
L
M
N
P
METRIC
MIN MAX
6.25 6.35
4.80 5.05
3.85 3.95
0.35 0.45
0.68 0.72
0.68 0.72
1.38 1.42
0.80 0.84
0.38 0.42
0.88 1.02
2.28 2.42
0.59 0.70
0.03 0.08
0.08 0.17
IMPERIAL
MIN
MAX
0.246
0.250
0.189
0.201
0.152
0.156
0.014
0.018
0.027
0.028
0.027
0.028
0.054
0.056
0.031
0.033
0.015
0.017
0.035
0.040
0.090
0.095
0.023
0.028
0.001
0.003
0.003
0.007
DirectFET™ Part Marking
GATE MARKING
LOGO
PART NUMBER
BATCH NUMBER
DATE CODE
Line above the last character of
the date code indicates "Lead-Free"
Note: For the most current drawing please refer to IR website at http://www.irf.com/package
8
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IRF6717MPbF
DirectFET™ Tape & Reel Dimension (Showing component orientation).
NOTE: Controlling dimensions in mm
Std reel quantity is 4800 parts. (ordered as IRF6717MTRPBF). For 1000 parts on 7"
reel, order IRF6717MTR1PBF
REEL DIMENSIONS
TR1 OPTION (QTY 1000)
STANDARD OPTION (QTY 4800)
METRIC
METRIC
IMPERIAL
IMPERIAL
MAX
MIN
MIN
CODE
MAX
MAX
MAX
MIN
MIN
N.C
6.9
12.992
A
N.C
177.77
330.0
N.C
N.C
0.75
0.795
B
N.C
N.C
19.06
20.2
N.C
N.C
0.53
0.504
C
0.50
0.520
13.5
12.8
13.2
12.8
0.059
0.059
D
N.C
1.5
1.5
N.C
N.C
N.C
2.31
3.937
E
N.C
58.72
100.0
N.C
N.C
N.C
F
0.53
N.C
N.C
N.C
N.C
18.4
0.724
13.50
G
N.C
0.47
0.488
0.567
11.9
12.4
14.4
12.01
H
0.47
0.469
N.C
0.606
11.9
11.9
15.4
12.01
LOADED TAPE FEED DIRECTION
NOTE: CONTROLLING
DIMENSIONS IN MM
CODE
A
B
C
D
E
F
G
H
DIMENSIONS
IMPERIAL
METRIC
MIN
MAX
MIN
MAX
0.311
0.319
7.90
8.10
0.154
0.161
3.90
4.10
0.469
0.484
11.90
12.30
0.215
0.219
5.45
5.55
0.201
0.209
5.10
5.30
0.256
0.264
6.50
6.70
0.059
N.C
1.50
N.C
0.059
0.063
1.50
1.60
Note: For the most current drawing please refer to IR website at http://www.irf.com/package
Data and specifications subject to change without notice.
This product has been designed and qualified for the Consumer market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information.04/2009
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9