VISHAY VCUT05A4-05S

VCUT05A4-05S
Vishay Semiconductors
4-Line Bidirectional Symmetrical (BiSy) ESD-Protection Diode in
SOT-23-5L
Features
•
•
•
•
•
•
SOT-23-5L package
4-line ESD-protection
Working range ± 5.5 V
Low leakage current < 0.1 µA
Low load capacitance CD = 16 pF
ESD-protection acc. IEC 61000-4-2
± 20 kV contact discharge
± 30 kV air discharge
• Pin plating tin (e3)
• Compliant to RoHS directive 2002/95/EC and in
accordance to WEEE 2002/96/EC
5
1
4
2
3
21953
21952
YYY
YYY = Type code (see table below)
XX = Date code
XX
XX
Marking (example only)
21954
Ordering Information
Ordering code
Taped units per reel
(8 mm tape on 7" reel)
Minimum order quantity
VCUT05A4-05S-G-08
3000
15 000
Device name
VCUT05A4-05S
Package Data
Device name
Package
name
Type
code
Weight
Molding compound
flammability rating
Moisture sensitivity level
Soldering conditions
VCUT05A4-05S
SOT-23-5L
5A4
15.5 mg
UL 94 V-0
MSL level 1
(according J-STD-020)
260 °C/10 s at terminals
Absolute Maximum Ratings
Test conditions
Symbol
Value
Unit
Peak pulse current
Parameter
Acc. IEC 61000-4-5, 8/20 µs/single shot
IPPM
3.5
A
Peak pulse power
Pin 1 to pin 2,
acc. IEC 61000-4-5, 8/20 µs/single shot
PPP
56
W
ESD immunity
Operating temperature
Contact discharge acc. IEC61000-4-2; 10 pulses
Air discharge acc. IEC61000-4-2; 10 pulses
Junction temperature
VESD
Tj
± 20
± 30
- 40 to + 85
kV
°C
** Please see document “Vishay Material Category Policy”: http://www.vishay.com/doc?99902
Document Number 85202
Rev. 1.1, 28-May-10
For technical support, please contact: [email protected]
www.vishay.com
1
VCUT05A4-05S
Vishay Semiconductors
Cut the spikes with VCUT05A4-05S:
The VCUT05A4-05S is a Bidirectional and Symmetrical (BiSy) ESD-protection device which clamps positive
and negative overvoltage transients to ground. Connected between the signal or data line and the ground the
VCUT05A4-05S offers a high isolation (low leakage current, low capacitance) within the specified working
range.
Electrical Characteristics (Tamb = 25 °C, unless otherwise specified)
VCUT05A4-05S
Parameter
Test conditions/remarks
Symbol
Number of lines which can be protected
Nlines
Reverse stand-off voltage
at I = 0.1 µA
VRWM
Reverse current
at V = 5.5 V
IR
Reverse breakdown voltage
at I = 1 mA
VBR
at IPP = 1 A
VC
12
V
at IPP = IPPM = 3.5 A
VC
16
V
at V = 0 V; f = 1 MHz
CD
20
pF
Protection paths
Min.
Typ.
Max.
Unit
4
lines
5.5
V
0.1
7
µA
7.5
V
Reverse clamping voltage
Capacitance
16
Typical Characteristics (Tamb = 25 °C, unless otherwise specified)
120 %
IPPM
Discharge Current IESD
80 %
80 %
60 %
53 %
40 %
27 %
Time (ns)
Figure 1. ESD Discharge Current Wave Form
acc. IEC 61000-4-2 (330 Ω/150 pF)
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20 µs to 50 %
20 %
0%
- 10 0 10 20 30 40 50 60 70 80 90 100
20557
60 %
40 %
20 %
2
8 µs to 100 %
100 %
Rise time = 0.7 ns to 1 ns
100 %
0%
0
20548
10
20
30
40
Time (µs)
Figure 2. 8/20 µs Peak Pulse Current Wave Form
acc. IEC 61000-4-5
For technical support, please contact: [email protected]
Document Number 85202
Rev. 1.1, 28-May-10
VCUT05A4-05S
Vishay Semiconductors
120
18
acc. IEC 61000-4-2
+ 8 kV
contact discharge
f = 1 MHz
16
100
14
80
VC-ESD (V)
CD (pF)
12
10
8
6
60
Pin 1, 3, 4, and 5 to Pin 2
40
20
Pin 1, 3, 4, and 5 to Pin 2
4
0
- 20
2
0
-8
-6
-4
-2
22014
0
2
4
6
- 40
- 10 0
8
VR (V)
Figure 3. Typical Capacitance CD vs.
Reverse Voltage VR
t (ns)
Figure 6. Typical Clamping Performance at + 8 kV
Contact Discharge (acc. IEC 61000-4-2)
10
40
Pin 1, 3, 4, and 5 to Pin 2
8
10 20 30 40 50 60 70 80 90
22017
acc. IEC 61000-4-2
- 8 kV
contact discharge
20
6
0
VC-ESD (V)
VR (V)
4
2
0
-2
- 20
- 40
Pin 2 to Pin 1, 3, 4, and 5
-4
- 60
-6
- 80
-8
Pin 2 to Pin 1, 3, 4, and 5
- 10
0.01
0.1
1
10
100
- 100
- 10 0
1000 10 000
IR (µA)
22015
Figure 4. Typical Reverse Voltage VR vs. Reverse Current IR
t (ns)
Figure 7. Typical Clamping Performance at - 8 kV
Contact Discharge (acc. IEC 61000-4-2)
250
20
Pin 1, 3, 4, and 5 to Pin 2
200
15
Positive surge
150
Positive surge
10
acc. IEC 61000-4-2
contact discharge
Measured
acc. IEC 61000-4-5
(8/20 µs - wave form)
0
VC-ESD (V)
100
5
VC (V)
10 20 30 40 50 60 70 80 90
22018
VC
50
0
- 50
VC-ESD
- 100
-5
Negative surge
- 150
- 10
Negative surge
- 200
Pin 2 to Pin 1, 3, 4, and 5
- 250
- 15
0
1
22016
2
3
4
5
IPP (A)
Figure 5. Typical Peak Clamping Voltage VC vs.
Peak Pulse Current IPP
Document Number 85202
Rev. 1.1, 28-May-10
0
5
10
22019-1
15
20
25
30
VESD (kV)
Figure 8. Typical Peak Clamping Voltage at ESD
Contact Discharge (acc. IEC 61000-4-2)
For technical support, please contact: [email protected]
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3
VCUT05A4-05S
Vishay Semiconductors
0.45 (0.018)
0.45 (0.018)
0.40 (0.015)
0.40 (0.015)
1.15 (0.045)
0° 8
°
0.2 (0.008)
0.11 (0.004)
0.550 (0.022) ref.
0.19 (0.007)
3.0 (0.118)
2.8 (0.110)
0.90 (0.035)
1.1 (0.043) max.
Package Dimensions in millimeters (inches): SOT-23-5L
0.5 (0.020)
0.3 (0.012)
3.00 (0.118)
2.60 (0.102)
0.45 (0.018)
foot print recommendation:
0.97 (0.038)
0.97 (0.038)
0.93 (0.037)
0.93 (0.037)
0.95 (0.037)
0.9 (0.035)
2.4 (0.094)
1.70 (0.067)
1.50 (0.059)
0.5 (0.020)
0.40 (0.015)
0.95 (0.037)
Document no.: S8-3929.01-001 (4)
Rev. 1 - Date: 15.Jan.2010
21955
Orientation in Blistertape
Unreeling direction
5
Pin 1
location
1
4
2
3
Top view
S8-V-3929.01-003 (4)
Date: 23. 11. 2009
22006
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4
For technical support, please contact: [email protected]
Document Number 85202
Rev. 1.1, 28-May-10
Legal Disclaimer Notice
Vishay
Disclaimer
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Document Number: 91000
Revision: 11-Mar-11
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1