ONSEMI NCP1608BDR2G

NCP1608
Critical Conduction Mode
PFC Controller Utilizing OTA
The NCP1608 is an active power factor correction (PFC)
controller specifically designed for use as a pre−converter in ac−dc
adapters, electronic ballasts, and other medium power off−line
converters (typically up to 350 W). It uses Critical Conduction Mode
(CrM) to ensure near unity power factor across a wide range of input
voltages and output power. The NCP1608 minimizes the number of
external components by integrating safety features, making it an
excellent choice for designing robust PFC stages. It is available in a
SOIC−8 package.
General Features
• Near Unity Power Factor
• No Input Voltage Sensing Requirement
• Latching PWM for Cycle−by−Cycle On Time Control (Voltage
Mode)
• Wide Control Range for High Power Application (>150 W) Noise
•
•
•
•
•
•
•
•
Immunity
Transconductance Amplifier
High Precision Voltage Reference (±1.6% Over the Temperature
Range)
Very Low Startup Current Consumption (≤ 35 mA)
Low Typical Operating Current Consumption (2.1 mA)
Source 500 mA / Sink 800 mA Totem Pole Gate Driver
Undervoltage Lockout with Hysteresis
Pin−to−Pin Compatible with Industry Standards
This is a Pb−Free and Halide−Free Device
MARKING
DIAGRAM
8
8
1
SOIC−8
D SUFFIX
CASE 751
A
L
Y
W
G
1
1608B
ALYW
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
PIN CONNECTION
FB
Control
Ct
CS
VCC
DRV
GND
ZCD
(Top View)
ORDERING INFORMATION
Device
Package
Shipping†
NCP1608BDR2G
SOIC−8
(Pb−Free)
2500 / Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
Safety Features
•
•
•
•
•
http://onsemi.com
Overvoltage Protection
Undervoltage Protection
Open/Floating Feedback Loop Protection
Overcurrent Protection
Accurate and Programmable On Time Limitation
Typical Applications
•
•
•
•
Solid State Lighting
Electronic Light Ballast
AC Adapters, TVs, Monitors
All Off−Line Appliances Requiring Power Factor Correction
© Semiconductor Components Industries, LLC, 2009
April, 2009 − Rev. 0
1
Publication Order Number:
NCP1608/D
NCP1608
Vin
L
Vout
D
NB:NZCD
LOAD
(Ballast,
SMPS, etc.)
RZCD
+
EMI
Filter
AC Line
Rout1
Cin
1
2
3
Rout2
4
CCOMP
Ct
VCC
NCP1608
8
VCC
FB
+
M
7
Control DRV
Cbulk
6
Ct
GND
CS
ZCD
5
Rsense
Figure 1. Typical Application
+ OVP
−
+
Vout
Cbulk
VOVP
− UVP
+
+
Rout1
Rout2
D
Haversine
L
Vin
Control
POK
+
VUVP
FB
E/A −
+
+
RFB
VDDGD
VDD Reg
mVDD
VREF
Fault
VEAH
Clamp
POK
PWM
Icharge
−
+
Add Ct
Offset
Ct
S Q
DRV
CS
+ OCP
−
LEB
+
Rsense
+
RZCD
VDD
gm
VDD
ZCD
UVLO
VControl
NB:NZCD
M
+
-
(Enable EA)
CCOMP
Ct
VCC
VCC
RQ
VCC
VILIM
+
−
S Q
VZCD(ARM)
+
UVLO
Demag
RQ
RQ
+
−
Reset
VZCD(TRIG)
S Q
Off Timer
ZCD Clamp
DRV
S Q
VDDGD
mVDD
GND
RQ
S Q
mVDD
RQ
All SR Latches are Reset Dominant
Figure 2. Block Diagram
http://onsemi.com
2
POK
NCP1608
Table 1. PIN FUNCTION DESCRIPTION
Pin
Name
Function
1
FB
The FB pin is the inverting input of the internal error amplifier. A resistor divider scales the output voltage to VREF to maintain regulation. The feedback voltage is used for overvoltage and undervoltage protections. The controller is disabled
when this pin is forced to a voltage less than VUVP, a voltage greater than VOVP, or floating.
2
Control
The Control pin is the output of the internal error amplifier. A compensation network is connected between the Control pin
and ground to set the loop bandwidth. A low bandwidth yields a high power factor and a low Total Harmonic Distortion (THD).
3
Ct
The Ct pin sources a current to charge an external timing capacitor. The circuit controls the power switch on time by comparing the Ct voltage to an internal voltage derived from VControl. The Ct pin discharges the external timing capacitor at the
end of the on time.
4
CS
The CS pin limits the cycle−by−cycle current through the power switch. When the CS voltage exceeds VILIM, the drive
turns off. The sense resistor that connects to the CS pin programs the maximum switch current.
5
ZCD
The voltage of an auxiliary winding is sensed by this pin to detect the inductor demagnetization for CrM operation.
6
GND
The GND pin is analog ground.
7
DRV
The integrated driver has a typical source impedance of 12 W and a typical sink impedance of 6 W.
8
VCC
The VCC pin is the positive supply of the controller. The controller is enabled when VCC exceeds VCC(on) and is disabled
when VCC decreases to less than VCC(off).
Table 2. MAXIMUM RATINGS
Rating
FB Voltage
FB Current
Symbol
Value
Unit
VFB
−0.3 to 10
V
IFB
±10
mA
Control Voltage
VControl
−0.3 to 6.5
V
Control Current
IControl
−2 to 10
mA
VCt
−0.3 to 6
V
Ct Voltage
Ct Current
ICt
±10
mA
CS Voltage
VCS
−0.3 to 6
V
ICS
±10
mA
VZCD
−0.3 to 10
V
CS Current
ZCD Voltage
ZCD Current
IZCD
±10
mA
DRV Voltage
VDRV
−0.3 to VCC
V
DRV Sink Current
IDRV(sink)
800
mA
IDRV(source)
500
mA
Supply Voltage
VCC
−0.3 to 20
V
Supply Current
ICC
±20
mA
Power Dissipation (TA = 70°C, 2.0 Oz Cu, 55 mm2 Printed Circuit Copper Clad)
PD
450
mW
RqJA
RqJA
RqJA
178
168
127
DRV Source Current
Thermal Resistance Junction−to−Ambient
(2.0 Oz Cu, 55 mm2 Printed Circuit Copper Clad)
Junction−to−Air, Low conductivity PCB (Note 3)
Junction−to−Air, High conductivity PCB (Note 4)
°C/W
Operating Junction Temperature Range
Maximum Junction Temperature
Storage Temperature Range
Lead Temperature (Soldering, 10 s)
TJ
−40 to 125
°C
TJ(MAX)
150
°C
TSTG
−65 to 150
°C
TL
300
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. This device series contains ESD protection and exceeds the following tests:
Pins 1– 8: Human Body Model 2000 V per JEDEC Standard JESD22−A114E.
Pins 1– 8: Machine Model Method 200 V per JEDEC Standard JESD22−A115−A.
2. This device contains Latch−Up protection and exceeds ± 100 mA per JEDEC Standard JESD78.
3. As mounted on a 40x40x1.5 mm FR4 substrate with a single layer of 80 mm2 of 2 oz copper traces and heat spreading area. As specified for
a JEDEC 51 low conductivity test PCB. Test conditions were under natural convection or zero air flow.
4. As mounted on a 40x40x1.5 mm FR4 substrate with a single layer of 650 mm2 of 2 oz copper traces and heat spreading area. As specified
for a JEDEC 51 high conductivity test PCB. Test conditions were under natural convection or zero air flow.
http://onsemi.com
3
NCP1608
Table 3. ELECTRICAL CHARACTERISTICS
VFB = 2.4 V, VControl = 4 V, Ct = 1 nF, VCS = 0 V, VZCD = 0 V, CDRV = 1 nF, VCC = 12 V, unless otherwise specified
(For typical values, TJ = 25°C. For min/max values, TJ = −40°C to 125°C, unless otherwise specified)
Characteristic
Test Conditions
Symbol
Min
Typ
Max
Unit
Startup Voltage Threshold
VCC Increasing
VCC(on)
11
12
12.5
V
Minimum Operating Voltage
VCC Decreasing
VCC(off)
8.8
9.5
10.2
V
HUVLO
2.2
2.5
2.8
V
0 V < VCC < VCC(on) − 200 mV
Icc(startup)
−
24
35
mA
CDRV = open, 70 kHz Switching,
VCS = 2 V
Icc1
−
1.4
1.7
mA
70 kHz Switching, VCS = 2 V
Icc2
−
2.1
2.6
mA
No Switching, VFB = 0 V
Icc(fault)
−
0.75
0.95
mA
VOVP/VREF
105
106
108
%
VOVP(HYS)
20
60
100
mV
VFB = 2 V to 3 V ramp,
dV/dt = 1 V/ms
VFB = VOVP to VDRV = 10%
tOVP
−
500
800
ns
Undervoltage Detect Threshold
VFB = Decreasing
VUVP
0.25
0.31
0.4
V
Undervoltage Detect Threshold
Propagation Delay
VFB = 1 V to 0 V ramp,
dV/dt = 10 V/ms
VFB = VUVP to VDRV = 10%
tUVP
100
200
300
ns
TJ = 25°C
TJ = −40°C to 125°C
VREF
2.475
2.460
2.500
2.500
2.525
2.540
V
VCC(on) + 200 mV < VCC < 20 V
VREF(line)
−10
−
10
mV
VFB = 2.6 V
VFB = 1.08*VREF
VFB = 0.5 V
IEA(sink)
IEA(sink)OVP
IEA(source)
6
10
−110
10
20
−210
20
30
−250
mA
VFB = 2.4 V to 2.6 V
TJ = 25°C
TJ = −40°C to 125°C
gm
90
70
110
110
120
135
VFB = VUVP to VREF
RFB
2
4.6
10
MW
VFB = 2.5 V
IFB
0.25
0.54
1.25
mA
VFB = 0 V
IControl
−1
−
1
mA
IControl(pullup) = 10 mA,
VFB = VREF
VEAH
5
5.5
6
V
VControl = Decreasing until
VDRV is low, VCt = 0 V
Ct(offset)
0.37
0.65
0.88
V
VEAH – Ct(offset)
VEA(DIFF)
4.5
4.9
5.3
V
STARTUP AND SUPPLY CIRCUITS
Supply Voltage Hysteresis
Startup Current Consumption
No Load Switching
Current Consumption
Switching Current Consumption
Fault Condition Current Consumption
OVERVOLTAGE AND UNDERVOLTAGE PROTECTION
Overvoltage Detect Threshold
VFB = Increasing
Overvoltage Hysteresis
Overvoltage Detect Threshold
Propagation Delay
ERROR AMPLIFIER
Voltage Reference
Voltage Reference Line Regulation
Error Amplifier Current Capability
Transconductance
Feedback Pin Internal Pull Down
Resistor
Feedback Bias Current
Control Bias Current
Maximum Control Voltage
Minimum Control Voltage to Generate
Drive Pulses
Control Voltage Range
http://onsemi.com
4
mS
NCP1608
Table 3. ELECTRICAL CHARACTERISTICS (Continued)
VFB = 2.4 V, VControl = 4 V, Ct = 1 nF, VCS = 0 V, VZCD = 0 V, CDRV = 1 nF, VCC = 12 V, unless otherwise specified
(For typical values, TJ = 25°C. For min/max values, TJ = −40°C to 125°C, unless otherwise specified)
Characteristic
Test Conditions
Symbol
Min
Typ
Max
Unit
VControl = open
VCt(MAX)
4.775
4.93
5.025
V
VControl = open
VCt = 0 V to VCt(MAX)
Icharge
235
275
297
mA
VControl = open
VCt = VCt(MAX) −100 mV to 500 mV
tCt(discharge)
−
50
150
ns
dV/dt = 30 V/ms
VCt = VControl − Ct(offset)
to VDRV = 10%
tPWM
−
130
220
ns
VILIM
0.45
0.5
0.55
V
VCS = 2 V, VDRV = 90% to 10%
tLEB
100
190
350
ns
dV/dt = 10 V/ms
VCS = VILIM to VDRV = 10%
tCS
40
100
170
ns
VCS = 2 V
ICS
−1
−
1
mA
RAMP CONTROL
Ct Peak Voltage
On Time Capacitor Charge Current
Ct Capacitor Discharge Duration
PWM Propagation Delay
CURRENT SENSE
Current Sense Voltage Threshold
Leading Edge Blanking Duration
Overcurrent Detection Propagation
Delay
Current Sense Bias Current
ZERO CURRENT DETECTION
ZCD Arming Threshold
VZCD = Increasing
VZCD(ARM)
1.25
1.4
1.55
V
ZCD Triggering Threshold
VZCD = Decreasing
VZCD(TRIG)
0.6
0.7
0.83
V
VZCD(HYS)
500
700
900
mV
ZCD Hysteresis
ZCD Bias Current
VZCD = 5 V
IZCD
−2
−
+2
mA
Positive Clamp Voltage
IZCD = 3 mA
VCL(POS)
9.8
10
12
V
Negative Clamp Voltage
IZCD = −2 mA
VCL(NEG)
−0.9
−0.7
−0.5
V
ZCD Propagation Delay
VZCD = 2 V to 0 V ramp,
dV/dt = 20 V/ms
VZCD = VZCD(TRIG) to VDRV = 90%
tZCD
−
100
170
ns
tSYNC
−
70
−
ns
Falling VDRV = 10% to
Rising VDRV = 90%
tstart
75
165
300
ms
Isource = 100 mA
Isink = 100 mA
ROH
ROL
−
−
12
6
20
13
W
10% to 90%
trise
−
35
80
ns
90% to 10%
tfall
−
25
70
ns
VCC = VCC(on)−200 mV,
Isink = 10 mA
Vout(start)
−
−
0.2
V
Minimum ZCD Pulse Width
Maximum Off Time in Absence of ZCD
Transition
DRIVE
Drive Resistance
Rise Time
Fall Time
Drive Low Voltage
http://onsemi.com
5
NCP1608
80
VOVP(HYS), OVERVOLTAGE
HYSTERESIS (mV)
107.0
106.5
106.0
105.5
105.0
−50
VUVP, UNDERVOLTAGE DETECT THRESHOLD (V)
VOVP/VREF, OVERVOLTAGE DETECT
THRESHOLD
TYPICAL CHARACTERISTICS
−25
0
25
50
75
100
125
60
50
40
−50
150
−25
0
25
50
75
100
125
150
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 3. Overvoltage Detect Threshold vs.
Junction Temperature
Figure 4. Overvoltage Hysteresis vs. Junction
Temperature
RFB, FEEDBACK PIN INTERNAL PULL
DOWN RESISTOR (MW)
0.330
0.325
0.320
0.315
0.310
0.305
0.300
−50
−25
0
25
50
75
100
125
150
7
6
5
4
3
2
1
0
−50
−25
0
25
50
75
100
125
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 5. Undervoltage Detect Threshold vs.
Junction Temperature
Figure 6. Feedback Pin Internal Pull Down
Resistor vs. Junction Temperature
2.53
2.52
2.51
2.50
50
Device in UVP
0
−50
−100
2.49
−150
2.48
−200
2.47
2.46
−50
150
100
IEA, ERROR AMPLIFIER OUTPUT
CURRENT (mA)
2.54
VREF, REFERENCE VOLTAGE (V)
70
−25
0
25
50
75
100
125
150
−250
0
TJ, JUNCTION TEMPERATURE (°C)
0.5
1.0
1.5
2.0
2.5
VFB, FEEDBACK VOLTAGE (V)
Figure 7. Reference Voltage vs. Junction
Temperature
Figure 8. Error Amplifier Output Current vs.
Feedback Voltage
http://onsemi.com
6
3.0
NCP1608
TYPICAL CHARACTERISTICS
220
14
12
10
8
6
−50
−25
0
25
50
75
100
125
210
205
200
195
190
0
25
50
75
100
125
150
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 10. Error Amplifier Source Current vs.
Junction Temperature
115
110
105
100
95
90
−25
0
25
50
75
100
125
150
TJ, JUNCTION TEMPERATURE (°C)
200
200
180
180
Phase
160
160
140
140
120
120
Transconductance
100
100
80
60
40
20
0
80
RControl = 100 kW
CControl = 2 pF
VFB = 2.5 Vdc, 1 Vac
VCC = 12 V
TA = 25°C
0.01
0.1
60
40
1
10
100
20
0
1000
f, FREQUENCY (kHz)
Figure 11. Error Amplifier Transconductance
vs. Junction Temperature
Figure 12. Error Amplifier Transconductance
and Phase vs. Frequency
1.0
278
Icharge, Ct CHARGE CURRENT (mA)
Ct(offset), MINIMUM CONTROL VOLTAGE
TO GENERATE DRIVE PULSES (V)
−25
Figure 9. Error Amplifier Sink Current vs.
Junction Temperature
120
0.9
0.8
0.7
0.6
0.5
0.4
0.3
−50
VFB = 0.5 V
185
180
−50
150
125
85
−50
215
q, PHASE (DEGREES)
gm, ERROR AMPLIFIER TRANSCONDUCTANCE (mS)
IEA(source), ERROR AMPLIFIER
SOURCE CURRENT (mA)
VFB = 2.6 V
gm, ERROR AMPLIFIER TRANSCONDUCTANCE (mS)
IEA(sink), ERROR AMPLIFIER SINK
CURRENT (mA)
16
−25
0
25
50
75
100
125
150
276
274
272
270
268
266
264
−50
TJ, JUNCTION TEMPERATURE (°C)
−25
0
25
50
75
100
125
150
TJ, JUNCTION TEMPERATURE (°C)
Figure 13. Minimum Control Voltage to Generate
Drive Pulses vs. Junction Temperature
Figure 14. On Time Capacitor Charge Current
vs. Junction Temperature
http://onsemi.com
7
NCP1608
TYPICAL CHARACTERISTICS
tPWM, PWM PROPAGATION DELAY (ns)
VCt(MAX), Ct PEAK VOLTAGE (V)
6.0
5.5
5.0
4.5
−25
0
25
50
75
100
125
150
160
150
140
130
120
110
100
−50
−25
0
25
50
75
100
125
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 15. Ct Peak Voltage vs. Junction
Temperature
Figure 16. PWM Propagation Delay vs.
Junction Temperature
150
220
tLEB, LEADING EDGE BLANKING
DURATION (ns)
0.520
0.515
0.510
0.505
0.500
0.495
0.490
0.485
0.480
−50
−25
0
25
50
75
100
125
210
200
190
180
−50
150
−25
0
25
50
75
100
125
150
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 17. Current Sense Voltage Threshold
vs. Junction Temperature
Figure 18. Leading Edge Blanking Duration vs.
Junction Temperature
190
18
185
16
DRIVE RESISTANCE (W)
tstart, MAXIMUM OFF TIME IN
ABSENCE OF ZCD TRANSITION (ms)
VILIM, CURRENT SENSE VOLTAGE THRESHOLD (V)
4.0
−50
170
180
175
170
165
160
155
ROH
14
12
10
8
ROL
6
4
2
150
−50
−25
0
25
50
75
100
125
150
0
−50
−25
0
25
50
75
100
125
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 19. Maximum Off Time in Absence of
ZCD Transition vs. Junction Temperature
Figure 20. Drive Resistance vs. Junction
Temperature
http://onsemi.com
8
150
NCP1608
TYPICAL CHARACTERISTICS
26
VCC(on)
12
VCC, SUPPLY VOLTAGE
THRESHOLDS (V)
ICC(startup), STARTUP CURRENT
CONSUMPTION (mA)
13
11
10
VCC(off)
9
−25
0
25
50
75
100
125
22
20
18
16
14
−50
150
−25
0
25
50
75
100
125
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 21. Supply Voltage Thresholds vs.
Junction Temperature
Figure 22. Startup Current Consumption vs.
Junction Temperature
2.16
ICC2, SWITCHING CURRENT
CONSUMPTION (mA)
8
−50
24
2.14
2.12
2.10
2.08
2.06
2.04
2.02
2.00
−50
−25
0
25
50
75
100
125
150
TJ, JUNCTION TEMPERATURE (°C)
Figure 23. Switching Current Consumption vs.
Junction Temperature
http://onsemi.com
9
150
NCP1608
• Overcurrent Protection. The peak current is accurately
Introduction
The NCP1608 is a voltage mode, power factor correction
(PFC) controller designed to drive cost effective
pre-converters to comply with input line harmonic
regulations. This controller operates in CrM suitable for
applications up to 350 W. Its voltage mode scheme enables
it to obtain near unity power factor without the need for a
line-sensing network. A high precision transconductance
error amplifier regulates the output voltage. The controller
implements comprehensive safety features for robust
designs.
The key features of the NCP1608 are:
• Constant On Time (Voltage Mode) CrM Operation. A
high power factor is achieved without the need for
input voltage sensing. This enables low standby power
consumption.
• Accurate and Programmable On Time Limitation. The
NCP1608 uses an accurate current source and an
external capacitor to generate the on time.
• Wide Control Range. In high power applications (>
150 W), inadvertent skipping can occur at high input
voltage and high output power if noise immunity is
not provided. The noise immunity provided by the
NCP1608 prevents inadvertent skipping.
• High Precision Voltage Reference. The error amplifier
reference voltage is guaranteed at 2.5 V ±1.6% over
process and temperature. This results in accurate
output voltages.
• Low Startup Current Consumption. The current
consumption is reduced to a minimum (< 35 mA)
during startup, enabling fast, low loss charging of
VCC. The NCP1608 includes undervoltage lockout and
provides sufficient VCC hysteresis during startup to
reduce the value of the VCC capacitor.
• Powerful Output Driver. A Source 500 mA / Sink
800 mA totem pole gate driver enables rapid turn on
and turn off times. This enables improved efficiencies
and the ability to drive higher power MOSFETs. A
combination of active and passive circuitry ensures
that the driver output voltage does not float high if
VCC does not exceed VCC(on).
• Accurate Fixed Overvoltage Protection (OVP). The
OVP feature protects the PFC stage against excessive
output overshoots that may damage the application.
Overshoots typically occur during startup or transient
loads.
• Undervoltage Protection (UVP). The UVP feature
protects the application if there is a disconnection in
the power path to Cbulk (i.e. Cbulk is unable to charge).
• Protection Against Open Feedback Loop. The OVP
and UVP features protect against the disconnection of
the output divider network to the FB pin. An internal
resistor (RFB) protects the application when the FB pin
is floating (Floating Pin Protection, FPP).
•
limited on a cycle-by-cycle basis. The maximum peak
current is adjustable by modifying the current sense
resistor. An integrated LEB filter reduces the
probability of noise inadvertently triggering the
overcurrent limit.
Shutdown Feature. The PFC pre-converter is shutdown
by forcing the FB pin voltage to less than VUVP. In
shutdown mode, the ICC current consumption is
reduced and the error amplifier is disabled.
Application Information
Most electronic ballasts and switching power supplies
use a diode bridge rectifier and a bulk storage capacitor to
produce a dc voltage from the utility ac line (Figure 24).
This DC voltage is then processed by additional circuitry
to drive the desired output.
Rectifiers
AC
Line
Converter
+
Bulk
Storage
Capacitor
Load
Figure 24. Typical Circuit without PFC
This rectifying circuit consumes current from the line
when the instantaneous ac voltage exceeds the capacitor
voltage. This occurs near the line voltage peak and the
resulting current is non-sinusoidal with a large harmonic
content. This results in a reduced power factor (typically <
0.6). Consequently, the apparent input power is higher than
the real power delivered to the load. If multiple devices are
connected to the same input line, the effect increases and
a “line sag” is produced (Figure 25).
Vpeak
Rectified DC
0
Line
Sag
AC Line Voltage
0
AC Line Current
Figure 25. Typical Line Waveforms without PFC
Government regulations and utilities require reduced
line current harmonic content. Power factor correction is
implemented with either a passive or an active circuit to
comply with regulations. Passive circuits contain a
combination of large capacitors, inductors, and rectifiers
that operate at the ac line frequency. Active circuits use a
http://onsemi.com
10
NCP1608
high frequency switching converter to regulate the input
current harmonics. Active circuits operate at a higher
frequency, which enables them to be physically smaller,
weigh less, and operate more efficiently than a passive
circuit. With proper control of an active PFC stage, almost
any complex load emulates a linear resistance, which
significantly reduces the harmonic current content. Active
PFC circuits are the most popular way to meet harmonic
content requirements because of the aforementioned
benefits. Generally, active PFC circuits consist of inserting
a PFC pre−converter between the rectifier bridge and the
bulk capacitor (Figure 26).
PFC Pre−converter
Rectifiers
AC Line
+
High
Frequency
Bypass
Capacitor
Converter
+
NCP1608
Bulk
Storage
Capacitor
Load
Figure 26. Active PFC Pre−Converter with the NCP1608
The boost (or step up) converter is the most popular
topology for active power factor correction. With the
proper control, it produces a constant voltage while
consuming a sinusoidal current from the line. For medium
power (<350 W) applications, CrM is the preferred control
method. CrM occurs at the boundary between
discontinuous conduction mode (DCM) and continuous
Diode Bridge
+
Diode Bridge
IL
Vin
Vdrain
AC Line
Vdrain
L
−
The power switch is ON
The power switch is OFF
With the power switch voltage being about zero, the
input voltage is applied across the inductor. The inductor
current linearly increases with a (Vin/L) slope.
The inductor current flows through the diode. The inductor
voltage is (Vout − Vin) and the inductor current linearly decays
with a (Vout − Vin)/L slope.
(Vout − Vin)/L
Vin/L
IL(peak)
Vdrain
Vin
+
−
Inductor
Current
IL
+
L
+
AC Line
conduction mode (CCM). In CrM, the driver on time begins
when the boost inductor current reaches zero. CrM
operation is an ideal choice for medium power PFC boost
stages because it combines the reduced peak currents of
CCM operation with the zero current switching of DCM
operation. The operation and waveforms in a PFC boost
converter are illustrated in Figure 27.
Critical Conduction Mode:
Next current cycle starts
when the core is reset.
Vout
Vin
If next cycle does not start
then Vdrain rings towards Vin
Figure 27. Schematic and Waveforms of an Ideal CrM Boost Converter
http://onsemi.com
11
+
Vout
NCP1608
When the switch is closed, the inductor current increases
linearly to the peak value. When the switch opens, the
inductor current linearly decreases to zero. When the
inductor current decreases to zero, the drain voltage of the
switch (Vdrain) is floating and begins to decrease. If the next
switching cycle does not begin, then Vdrain rings towards
Vin. A derivation of equations found in AND8123 leads to
the result that high power factor in CrM operation is
achieved when the on time (ton) of the switch is constant
during an ac cycle and is calculated using Equation 1.
ton +
2 @ P OUT @ L
IL(peak)
(eq. 1)
Iin(t)
ON
OFF
Figure 28. Inductor Waveform During CrM Operation
Where Pout is the output power, L is the boost inductor, h
is the efficiency, and Vac is the rms input voltage.
A description of the switching over an ac line cycle is
illustrated in Figure 28. The on time is constant, but the off
time varies and is dependent on the instantaneous line
voltage. The constant on time causes the peak inductor
current (IL(peak)) to scale with the ac line voltage. The
NCP1608 represents an ideal method to implement a
constant on time CrM control in a cost effective and robust
solution by incorporating an accurate regulation circuit, a
low current consumption startup circuit, and advanced
protection features.
+ OVP
−
IL(t)
Iin(peak)
MOSFET
h @ Vac 2
Vin(t)
Vin(peak)
Error Amplifier Regulation
The NCP1608 regulates the boost output voltage using
an internal error amplifier (EA). The negative terminal of
the EA is pinned out to FB, the positive terminal is
connected to a 2.5 V ± 1.6% reference (VREF), and the EA
output is pinned out to Control (Figure 29).
A feature of using a transconductance type amplifier is
that the FB pin voltage is only determined by the resistor
divider network connected to the output voltage, not the
operation of the amplifier. This enables the FB pin to be
used for sensing overvoltage or undervoltage conditions
independently of the error amplifier.
OVP Fault
+
VOVP
Vout
+
Rout1
− UVP
+
POK
UVP Fault
VUVP
FB
−
+
Rout2
+
RFB
EA
gm
VREF
PWM BLOCK
(Enable EA)
ton(MAX)
Slope +
Control
VControl
Ct
I charge
ton
CCOMP
tPWM
Ct(offset)
VEAH
VControl
Figure 29. Error Amplifier and On Time Regulation Circuits
http://onsemi.com
12
NCP1608
A resistor divider (Rout1 and Rout2) scales down the boost
output voltage (Vout) and is connected to the FB pin. If the
output voltage is less than the target output voltage, then
VFB is less than VREF and the EA increases the control
voltage (VControl). This increases the on time of the driver,
which increases the power delivered to the output. The
increase in delivered power causes Vout to increase until the
target output voltage is achieved. Alternatively, if Vout is
greater than the target output voltage, then VControl
decreases to cause the on time to decrease until Vout
decreases to the target output voltage. This cause and effect
regulates Vout so that the scaled down Vout that is applied
to FB through Rout1 and Rout2 is equal to VREF. The
presence of RFB (4.6 MW typical value) for FPP is included
in the divider network calculation.
The output voltage is set using Equation 2:
ǒ
Vout + V REF @ R out1 @
R out2 ) R FB
)1
R out2 @ R FB
Ǔ
Rout1 +
V out
I bias(out)
(eq. 3)
Where Ibias(out) is the output divider network bias current.
Rout2 is dependent on Vout, Rout1, and RFB.
Rout2 is calculated using Equation 4:
Rout2 +
ǒ
R out1 @ R FB
Ǔ
Vout
R FB @
* 1 * Rout1
VREF
(eq. 4)
The PFC stage consumes a sinusoidal current from a
sinusoidal line voltage. The converter provides the load
with a power that matches the average demand only. The
output capacitor (Cbulk) compensates for the difference
between the delivered power and the power consumed by
the load. When the power delivered to the load is less than
the power consumed by the load, Cbulk discharges. When
the delivered power is greater than the power consumed by
the load, Cbulk charges to store the excess energy. The
situation is depicted in Figure 30.
(eq. 2)
The divider network bias current is selected to optimize
the tradeoff of noise immunity and power dissipation. Rout1
is calculated using the optimized bias current and output
voltage using Equation 3:
Iac
Vac
Pin
Pout
Vout
Figure 30. Output Voltage Ripple for a Constant Output Power
Due to the charging/discharging of Cbulk, Vout contains
a ripple at a frequency of either 100 Hz (for a 50 Hz line
frequency in Europe) or 120 Hz (for a 60 Hz line frequency
in the USA). The Vout ripple is attenuated by the regulation
loop to ensure VControl is constant during the ac line cycle
for the proper shaping of the line current. To ensure VControl
is constant during the ac line cycle, the loop bandwidth is
typically set below 20 Hz. A type 1 compensation network
consists of a capacitor connected between the Control and
ground pins (see Figure 1). In this configuration, the
capacitor necessary to attenuate the Vout ripple is
calculated using Equation 5:
CCOMP +
gm
2 @ p @ f CROSS
Where fCROSS is the crossover frequency and gm is error
amplifier transconductance. The crossover frequency is set
below 20 Hz.
On Time Sequence
The switching pattern consists of constant on times and
variable off times for a given rms input voltage and output
load. The NCP1608 controls the on time with the capacitor
connected to the Ct pin. A current source charges the Ct
capacitor to a voltage derived from the Control pin voltage
(VCt(off)). VCt(off) is calculated using Equation 6:
VCt(off) + V Control − Ct(offset) +
(eq. 5)
2 @ P out @ L @ I charge
h @ Vac 2 @ Ct
(eq. 6)
When VCt(off) is reached, the drive turns off (Figure 31).
http://onsemi.com
13
NCP1608
IL
VControl
Control
IL(peak)
VDD
Icharge
Ct
+
DRV
VCt
VCt(off)
PWM
−
+
MOSFET Conduction
Diode Conduction
0A
DRV
ton
Ct(offset)
0V
Vdrain
Vout
VControl − Ct(offset)
0V
VZCD(WIND)
ton
VZCD(WIND),off
DRV
0V
Figure 31. On Time Generation
VZCD(WIND),on
VControl varies with the rms input voltage and output
load, which naturally satisfies Equation 1. The on time is
constant during the ac line cycle if the values of
compensation components are sufficient to filter out the
Vout ripple. The maximum on time of the controller occurs
when VControl is at the maximum. The Ct capacitor is sized
to ensure that the required on time is reached at maximum
output power and the minimum input voltage condition.
The maximum on time is calculated using Equation 7:
ton(MAX) +
Ct @ VCt(MAX)
Icharge
VZCD
VCL(POS)
VZCD(ARM)
VZCD(TRIG)
ton
2 @ Pout @ L @ Icharge
h @ Vac LL 2 @ V Ct(MAX)
tdiode
toff
(eq. 7)
TSW
Combining Equation 7 with Equation 1, results in
Equation 8:
Ct w
0V
VCL(NEG)
Figure 32. Ideal CrM Waveforms Using a ZCD
Winding
The voltage induced on the ZCD winding during the switch
on time (VZCD(WIND),on) is calculated using Equation 9:
(eq. 8)
To calculate the minimum Ct value:
VCt(MAX) = 4.775 V (minimum value),
Icharge = 297 mA (maximum value), and VacLL is the
minimum rms input voltage.
VZCD(WIND),on +
−Vin
N B : N ZCD
(eq. 9)
Where Vin is the instantaneous input voltage and NB:NZCD
is the turns ratio of the boost winding to the ZCD winding.
The voltage induced on the ZCD winding during the
switch off time (VZCD(WIND),off) is calculated using
Equation 10:
Off Time Sequence
In CrM operation, the on time is constant during the ac
line cycle and the off time varies with the instantaneous
input voltage. When the inductor current reaches zero, the
drain voltage (Vdrain in Figure 27) resonates towards Vin.
Measuring Vdrain is a way to determine when the inductor
current reaches zero. To measure the high voltage Vdrain
directly is generally not economical or practical. Instead,
a winding is added to the boost inductor. This winding,
called the Zero Current Detection (ZCD) winding,
provides a scaled representation of the inductor voltage
that is sensed by the controller. Figure 32 shows waveforms
of ideal CrM operation using a ZCD winding.
VZCD(WIND),off +
V out * V in
N B : N ZCD
(eq. 10)
When the inductor current reaches zero, the ZCD pin
voltage (VZCD) follows the ZCD winding voltage
(VZCD(WIND)) and begins to decrease and ring towards zero
volts. The NCP1608 detects the falling edge of VZCD and
turns the driver on. To ensure that a ZCD event is not
inadvertently detected, the NCP1608 logic verifies that
VZCD exceeds VZCD(ARM) and then senses that VZCD
decreases to less than VZCD(TRIG) (Figure 33).
http://onsemi.com
14
NCP1608
Vin
NB
NZCD
+
−
Q
Reset
Dominant
Latch
R
Q
VZCD(ARM)
+
+
−
Rsense
Demag
S
DRIVE
VZCD(TRIG)
+
ZCD
RZCD
ZCD Clamp
Figure 33. Implementation of the ZCD Block
This sequence achieves CrM operation. The maximum
VZCD(ARM) sets the maximum turns ratio and is calculated
using Equation 11:
NB : N ZCD v
V out * ǒǸ2 @ Vac HLǓ
VZCD(ARM)
MOSFET Conduction
Diode Conduction
IL(peak)
(eq. 11)
0A
IL(NEG)
DRV
Where VacHL is the maximum rms input voltage and
VZCD(ARM) = 1.55 V (maximum value).
The NCP1608 prevents excessive voltages on the ZCD
pin by clamping VZCD. When the ZCD winding is negative,
the ZCD pin is internally clamped to VCL(NEG). Similarly,
when the ZCD winding is positive, the ZCD pin is
internally clamped to VCL(POS). A resistor (RZCD in
Figure 33) is necessary to limit the current into the ZCD
pin. The maximum ZCD pin current (IZCD(MAX)) is limited
to less than 10 mA. RZCD is calculated using Equation 12:
Ǹ2 @ Vac
HL
RZCD w
I ZCD(MAX) @ (N B : N ZCD)
tz
IL
0V
Vdrain
Vout
0V
Minimum Voltage Turn on
VZCD(WIND)
VZCD(WIND),off
0V
VZCD(WIND),on
(eq. 12)
VZCD
VCL(POS)
The value of RZCD and the parasitic capacitance of the
ZCD pin determine when the ZCD winding signal is
detected and the drive turn on begins. A large RZCD value
creates a long delay before detecting the ZCD event. In this
case, the controller operates in DCM and the power factor
is reduced. If the RZCD value is too small, the drive turns
on when the drain voltage is high and efficiency is reduced.
A popular strategy for selecting RZCD is to use the RZCD
value that achieves minimum drain voltage turn on. This
value is found experimentally. Figure 34 shows the realistic
waveforms for CrM operation due to RZCD and the ZCD pin
capacitance.
VZCD(ARM)
VZCD(TRIG)
VCL(NEG)
ton
0V
tdiode
toff
RZCD Delay
TSW
Figure 34. Realistic CrM Waveforms Using a ZCD
Winding with RZCD and the ZCD Pin Capacitance
http://onsemi.com
15
NCP1608
During the delay caused by RZCD and the ZCD pin capacitance, the equivalent drain capacitance (CEQ(drain)) discharges
through the path shown in Figure 35.
L
IL
Iin
AC Line
+
EMI
Filter
Vout
D
+
Cin
CEQ(drain)
Cbulk
Figure 35. Equivalent Drain Capacitance Discharge Path
stored in the inductor (L) to be reduced. The result is that
VZCD does not exceed VZCD(ARM) and the drive remains off
until tstart expires. This sequence results in pulse skipping
and reduced power factor.
CEQ(drain) is the combined parasitic capacitances of the
MOSFET, the diode, and the inductor. Cin is charged by the
energy discharged by CEQ(drain). The charging of Cin
reverse biases the bridge rectifier and causes the input
current (Iin) to decrease to zero. The zero input current
causes THD to increase. To reduce THD, the ratio (tz / TSW)
is minimized, where tZ is the period from when IL = 0 A to
when the drive turns on. The ratio (tz / TSW) is inversely
proportional to the square root of L.
During startup, there is no energy in the ZCD winding
and no voltage signal to activate the ZCD comparators.
This means that the drive never turns on. To enable the PFC
stage to start under these conditions, an internal watchdog
timer (tstart) is integrated into the controller. This timer
turns the drive on if the drive has been off for more than
165 ms (typical value). This feature is deactivated during a
fault mode (OVP or UVP), and reactivated when the fault
is removed.
Noise Induced Voltage Spike
VControl
Ct(offset)
Low VControl Voltage
VCt
VCt(off)
VControl − Ct(offset)
Low VCt(off) Voltage
DRV
VZCD
Wide Control Range
VZCD(ARM)
is Not Exceeded
VZCD(ARM)
The Ct charging threshold (VCt(off)) decreases as the
output power is decreased from the maximum output
power to the minimum output power in the application. In
high power applications (>150 W), VControl is reduced to
a low voltage at a large output power and Ct(offset) remains
constant. The result is that VCt(off) is reduced to a low
voltage at a large output power. The low VControl and
VCt(off) voltages are susceptible to noise. The large output
power combined with the low VControl and VCt(off) increase
the probability of noise interfering with the control signals
and on time duration (Figures 36 and 37). The noise induces
voltage spikes on the Control pin and Ct pin that reduces the
drive on time from the on time determined by the feedback
loop (ton(loop)). The reduced on time causes the energy
VZCD(TRIG)
0V
VCL(NEG)
ton(loop)
ton
DRV Remains Off
tstart
Figure 36. Control Pin Noise Induced On Time
Reduction and Pulse Skipping
http://onsemi.com
16
NCP1608
VCt(off), Ct CHARGING THRESHOLD (V)
VControl
Ct(offset)
Low VControl Voltage
VCt
Noise Induced Voltage Spike
VCt(off)
VControl − Ct(offset)
Low VCt(off) Voltage
DRV
VZCD
0.50
Vac = 265 Vac
0.45
NCP1608
0.40
0.35
0.30
0.25
3 V Control
Range
0.20
0.15
0.10
0.05
0
25
75
125
175
Pout, OUTPUT POWER (W)
225
275
Figure 38. Comparison of Ct Charging Threshold
vs. Output Power
VZCD(ARM)
is Not Exceeded
VZCD(ARM)
0.55
VZCD(TRIG)
Startup
VCL(NEG)
Generally, a resistor connected between the rectified ac
line and VCC charges the VCC capacitor to VCC(on). The low
startup current consumption (< 35 mA) enables minimized
standby power dissipation and reduced startup durations.
When VCC exceeds VCC(on), the internal references and
logic of the NCP1608 are enabled. The controller includes
an undervoltage lockout (UVLO) feature that ensures that
the NCP1608 is enabled until VCC decreases to less than
VCC(off). This hysteresis ensures sufficient time for the
auxiliary winding to supply VCC (Figure 39).
0V
ton(loop)
ton
DRV Remains Off
tstart
Figure 37. Ct Pin Noise Induced On Time
Reduction and Pulse Skipping
The wide control range of the NCP1608 increases
VControl and VCt(off) in comparison to devices with less
control range. Figure 38 compares VCt(off) of the NCP1608
to a device with a 3 V control range for an application with
the following parameters:
Pout = 250 W
VCC
VCC(on)
VCC(off)
Figure 39. Typical VCC Startup Waveform
L = 200 mH
h = 92%
VacLL = 85 Vac
VacHL = 265 Vac
Figure 38 shows that VCt(off) of the NCP1608 is 50%
larger than the 3 V control range device. The 50% increase
enables the NCP1608 to prevent inadvertent skipping at
high input voltages and high output power.
When the PFC pre-converter is loaded by a switch−mode
power supply (SMPS), it is generally preferable for the
SMPS controller to startup first. The SMPS then supplies
the NCP1608 VCC. Advanced controllers, such as the
NCP1230 or NCP1381, control the enabling of the PFC
stage (see Figure 40) and achieve optimal system
performance. This sequence eliminates the startup resistors
and improves the standby power dissipation of the system.
http://onsemi.com
17
NCP1608
D
+
8
3
4
NCP1608
1
2
PFC(Vcc)
1
8
2
7
6
3
6
5
4
5
+
7
Cbulk
VCC
+
+
+
NCP1230
Figure 40. NCP1608 Supplied by a Downstream SMPS Controller (NCP1230)
Soft Start
VCC
When VCC exceeds VCC(on), tstart begins counting. When
tstart expires, the error amplifier is enabled and begins
charging the compensation network. The drive is enabled
when VControl exceeds Ct(offset). The charging of the
compensation network slowly increases the drive on time
from the minimum time (tPWM) to the steady state on time.
This creates a natural soft start mode that reduces the stress
of the power components (Figure 41).
Iswitch
Output Driver
VREF
VCC(on)
VCC(off)
FB
The NCP1608 includes a powerful output driver capable
of sourcing 500 mA and sinking 800 mA. This enables the
controller to drive power MOSFETs efficiently for medium
power (≤ 350 W) applications. Additionally, the driver
stage provides both passive and active pull down clamps
(Figure 42). The clamps are active when VCC is off and
force the driver output to a voltage less than the turn on
threshold voltage of a power MOSFET.
Control
Natural Soft Start
Ct(offset)
Vout
tstart
Figure 41. Startup Timing Diagram Showing the
Natural Soft Start of the Control Pin
VCC
+
−
VDD
UVLO
UVLO
DRV IN
DRV
VddGD
VDD REG
mVDD
GND
Figure 42. Output Driver Stage and Pull Down Clamps
http://onsemi.com
18
+
NCP1608
Overvoltage Protection (OVP)
The Cbulk value is sized to ensure that OVP is not
inadvertently triggered by the 100 Hz or 120 Hz ripple of
Vout. The minimum value of Cbulk is calculated using
Equation 14:
The low bandwidth of the feedback network causes
active PFC stages to react to changes in output load or input
voltages slowly. Consequently, there is a risk of overshoots
during transient conditions (i.e. startup, load steps, etc.).
For reliable operation, it is critical that overvoltage
protection (OVP) prevents the output voltage from
exceeding the ratings of the PFC stage components. The
NCP1608 detects excessive Vout voltages and disables the
driver until Vout decreases. OVP ensures that Vout is within
the PFC stage component ratings. A comparator connected
to the FB pin provides the OVP protection. The maximum
PFC output voltage (the OVP voltage that activates an OVP
fault) is calculated using Equation 13:
Vout(OVP)
Cbulk w
ǒ
Vripple(peak−peak) v 2 @ ǒVout(OVP) * VoutǓ
ǒǒ
(eq. 15)
The OVP logic includes hysteresis (VOVP(HYS)) to
ensure that Vout has sufficient time to discharge before the
NCP1608 attempts to restart and to ensure noise immunity.
The output voltage at which the NCP1608 attempts a restart
(Vout(OVPL)) is calculated using Equation 16:
Ǔ
Where VOVP/VREF is the OVP detection threshold.
Vout(OVPL) +
(eq. 14)
Where Vripple(peak-peak) is the peak−to−peak output voltage
ripple and fline is the ac line frequency.
Vripple(peak-peak) is calculated using Equation 15:
(eq. 13)
V
R
) RFB
+ OVP @ V REF @ R out1 @ out2
)1
VREF
R out2 @ RFB
P out
2 @ p @ V ripple(peak−peak) @ fline @ Vout
Ǔ
V OVP
@ V REF * V OVP(HYS)
VREF
Ǔǒ
@ R out1 @
Rout2 ) RFB
)1
Rout2 @ RFB
Ǔ
(eq. 16)
Figure 43 depicts the operation of the OVP circuitry.
Vout
Vout(OVP)
Vout(OVPL)
DRV
OVP Fault
Figure 43. OVP Operation
Undervoltage Protection (UVP)
Open Feedback Loop Protection
When the input voltage is applied to the PFC stage, Vout
is forced to equate to the peak of the line voltage. The
NCP1608 detects an undervoltage fault if Vout is unusually
low, such that VFB is less than VUVP . During an UVP fault,
the drive and error amplifier are disabled. The UVP feature
protects the application if there is a disconnection in the
power path to Cbulk (i.e. Cbulk is unable to charge) or if Rout1
is disconnected.
The output voltage that causes a UVP fault is calculated
using Equation 17:
The NCP1608 features comprehensive protection
against open feedback loop conditions by including OVP,
UVP, and FPP. Figure 44 illustrates three conditions in
which the feedback loop is open. The corresponding
number below describes each condition shown in
Figure 44.
1. UVP Protection: The connection from Rout1 to
the FB pin is open. Rout2 pulls down the FB pin
to ground. The UVP comparator detects an UVP
fault, the drive and error amplifier are disabled.
2. OVP Protection: The connection from Rout2 to
the FB pin is open. Rout1 pulls up the FB pin to
Vout. The ESD diode clamps the FB voltage to
10 V and Rout1 limits the current into the FB pin.
The OVP comparator detects an OVP fault and
the drive is disabled.
ǒ
Vout(UVP) + V UVP @ R out1 @
R out2 ) R FB
)1
R out2 @ R FB
Ǔ
(eq. 17)
http://onsemi.com
19
NCP1608
3. FPP Protection: The FB pin is floating. The
internal pull down resistor RFB pulls down the FB
voltage below VUVP. The UVP comparator
detects an UVP fault, the drive and error
amplifier are disabled.
UVP and OVP protect the system from low bulk voltages
and rapid operating point changes respectively, while FPP
protects the system against floating feedback pin
+ OVP
−
+
Vout
VOVP
UVP
−
+
+
Rout1
Condition 1
FB
VUVP
E/A
Condition 3
Condition 2
Rout2
POK
(Enable EA)
−
+
gm
+
Cbulk
conditions. If FPP is not implemented and a manufacturing
error causes the FB pin to float, then VFB is dependent on
the coupling within the system and the surrounding
environment. The coupled VFB may be within the
regulation limits (i.e. VUVP < VFB < VREF) and cause the
controller to deliver excessive power. The result is that Vout
increases until a component fails due to the voltage stress.
RFB
VREF
Fault
VControl
Control
VEAH
Clamp
CCOMP
Figure 44. Open Feedback Loop Protection
Overcurrent Protection (OCP)
Shutdown Mode
The dedicated CS pin of the NCP1608 senses the peak
current and limits the driver on time if the voltage of the CS
pin exceeds VILIM. The maximum peak current is
programmed by adjusting Rsense. The peak current is
calculated using Equation 18:
The NCP1608 enables the user to set the controller in a
standby mode of operation. To shutdown the controller, the
FB pin is forced to less than VUVP. When using the FB pin
for shutdown (Figure 46), the designer must ensure that no
significant leakage current exists in the shutdown circuitry.
Any leakage current affects the output voltage regulation.
IL(peak) +
V ILIM
R sense
(eq. 18)
Vout
An internal LEB filter (Figure 45) reduces the
probability of switching noise inadvertently triggering the
overcurrent limit. This filter blanks out the CS signal for a
duration of tLEB. If additional filtering is necessary, a small
RC filter is connected between Rsense and the CS pin.
CS
DRV
+
−
LEB
+
Rsense
Rout1
NCP1608
OCP
Shutdown
Rout2
1
8
2
7
3
6
4
5
VILIM
optional
Figure 45. OCP Circuitry with Optional
External RC Filter
Figure 46. Shutting Down the PFC Stage
http://onsemi.com
20
NCP1608
Application Information
The electronic design tool allows the user to easily
determine most of the system parameters of a boost
pre−converter. The demonstration board is a boost
pre−converter that delivers 100 W at 400 V. The circuit
schematic is shown in Figure 47. The pre−converter design
is described in Application Note AND8396/D.
ON Semiconductor provides an electronic design tool, a
demonstration board, and an application note to facilitate
the design of the NCP1608 and reduce development cycle
time. All the tools can be downloaded or ordered at
www.onsemi.com.
Rstart1
Rstart2
Lboost
Dboost
J3
NTC
t°
F1
Bridge
L1
L2
J2
C1
C2
J1
Rct
Rcomp1
Ccomp
Ccomp1
D1
Daux
CVcc
+
Ro1a
Dvcc
Rzcd
Rctup2
Cin
C3
R1
Rctup1
Ro1b
U1
NCP1608
1
8
Vcc
FB
2
7
Control DRV
3
6
GND
Ct
4
ZCD 5
CS
Rcs
Ct2 Ct1
Cbulk +
Ccs
21
Rdrv
Q1
Rout2a
Rout2b
Czcd
Figure 47. Application Schematic
http://onsemi.com
CVcc2 Ddrv
Rs3 Rs2 Rs1
NCP1608
BOOST DESIGN EQUATIONS Components are identified in Figure 1
rms Input Current
Maximum Inductor Peak
Current
IL(peak),MAX +
Inductor Value
Vac 2 @
Lv
Maximum On Time
Ǔ
Ǹ2 @ V @ P @ f
out
out
SW(MIN)
Ct w
Vout
1*
Where VacHL is the maximum line
input voltage. VZCD(ARM) is shown in
the specification table. The maximum
value of VZCD(ARM) is used for this
calculation.
VZCD(ARM)
Where IZCD(MAX) is maximum rated
current for the ZCD pin (10 mA)
Ǹ2 @ Vac
HL
I ZCD(MAX) @ (N B : N ZCD)
ǒ
R out2 ) R FB
)1
R out2 @ R FB
Ǔ
R FB @
ǒ
Rout1 @ RFB
Ǔ
Vout
* 1 * Rout1
VREF
ǒ
) RFB
V OVP
R
@ V REF @ R out1 @ out2
)1
VREF
R out2 @ RFB
ǒǒ
VOVP
VREF
Where VREF is the internal reference
voltage and RFB is the pull down resistor used for FPP. VREF and RFB are
shown in the specification table.
Ibias(out) is the bias current of the output voltage divider.
V out
I bias(out)
Rout2 +
Vout(OVPL) +
Icharge and VCt(MAX) are shown in the
specification table.
V out * ǒǸ2 @ Vac HLǓ
Vout + V REF @ R out1 @
Vout(OVP) +
Ǔ
h @ Vac LL @ V Ct(MAX)
RZCD w
Rout1 +
Vac @ |sin q| @ Ǹ2
V out
2
NB : N ZCD v
Maximum Output Voltage
for OVP Detection and
Recovery
ǒ
*1
2 @ Pout @ L @ Icharge
Inductor Turns to ZCD
Turns Ratio
Resistor from ZCD
winding to the ZCD pin
The off time is a maximum at the
peak of the ac line voltage and approaches zero at the ac line zero
crossings. Theta (q) represents the
angle of the ac line voltage.
t on
Vac 2 @ h
@
2 @ L @ P out
On Time Capacitor
The maximum on time occurs at the
minimum line input voltage and maximum output power.
2 @ L @ P out
h @ Vac LL 2
Vac@Ťsin qŤ@Ǹ2
fSW +
fSW(MIN) is the minimum desired
switching frequency. The maximum L
is calculated at both the minimum
line input voltage and maximum line
input voltage.
Vout
* Vac @ h
Ǹ2
toff +
Switching Frequency
Where VacLL is the minimum line input voltage. IL(peak),MAX occurs at
minimum line input voltage.
Ǹ2 @ 2 @ P
out
h @ Vac LL
ǒ
ton(MAX) +
Off Time
Output Voltage and Output
Divider
h (the efficiency of only the PFC
stage) is generally in the range of 90
− 95%. Vac is the rms ac line input
voltage.
Pout
Iac +
h @ Vac
Ǔ
Ǔǒ
Ǔ
Output Capacitor rms
Current
IC(RMS) +
Ǔ
R out2 ) R FB
@ VREF −V OVP(HYS) @ R out1 @
)1
R out2 @ R FB
Output Capacitor
Cbulk w
VOVP/VREF and VOVP(HYS) are
shown in the specification table.
P out
2 @ p @ V ripple(peak−peak) @ fline @ Vout
Ǹ
Ǹ2 @ 32 @ P 2
out
* Iload(RMS) 2
9 @ p @ Vac LL @ Vout @ h2
http://onsemi.com
22
Where fline is the ac line frequency
and Vripple(peak−peak) is the peak−to−
peak output ripple voltage. Use fline =
47 Hz for universal input worst case.
The ripple voltage must not exceed
the OVP voltage for Vout.
Where Iload(RMS) is the rms load current.
NCP1608
BOOST DESIGN EQUATIONS Components are identified in Figure 1 (Continued)
Minimum Output Voltage
for UVP Recovery
Inductor rms Current
Output Diode rms
Current
MOSFET rms Current
ǒ
Vout(UVP) + V UVP @ R out1 @
IL(RMS) +
ID(RMS),MAX + 4 @
3
ǒ
Type 1 Compensation
ǸǸ2p@ 2 @
Ǔ
Rsense +
PR
sense
R out2 @ R FB
)1
Ǔ
VUVP is shown in the specification
table.
2 @ P out
Ǹ3 @ Vac @ h
LL
Pout
IM(RMS) + 2 @
@
Ǹ3
h @ Vac LL
MOSFET Sense Resistor
R out2 ) R FB
P out
h @ ǸVac LL @ Vout
Ǹ ǒ
1*
Ǔ
Ǹ2 @ 8 @ Vac
LL
3 @ p @ Vout
V ILIM
I L(peak)
VILIM is shown in the specification
table.
+ I M(RMS) 2 @ Rsense
gm
CCOMP +
2 @ p @ f CROSS
http://onsemi.com
23
Where fCROSS is the crossover frequency and is typically less than
20 Hz. gm is shown in the specification table.
NCP1608
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AJ
−X−
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
A
8
5
S
B
0.25 (0.010)
M
Y
M
1
4
−Y−
K
G
C
N
DIM
A
B
C
D
G
H
J
K
M
N
S
X 45 _
SEATING
PLANE
−Z−
0.10 (0.004)
H
D
0.25 (0.010)
M
Z Y
S
X
M
J
S
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0 _
8 _
0.25
0.50
5.80
6.20
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0 _
8 _
0.010
0.020
0.228
0.244
SOLDERING FOOTPRINT*
1.52
0.060
7.0
0.275
4.0
0.155
0.6
0.024
1.270
0.050
SCALE 6:1
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
The products described herein (NCP1608), may be covered by one or more of the following U.S. patents: 6,362,067, 5,359,281, 5,073,850. There may be
other patents pending.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any
liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental
damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over
time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under
its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body,
or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death
may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees,
subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of
personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part.
SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: [email protected]
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5773−3850
http://onsemi.com
24
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your loca
Sales Representative
NCP1608/D