FINAL Am79C98 Twisted-Pair Ethernet Transceiver (TPEX) DISTINCTIVE CHARACTERISTICS ■ CMOS device provides compliant operation and low operating current from a single +5 V supply ■ Power Down mode provides reduced power consumption for battery-powered applications. Reset capability allows use in remote MAU applications. ■ Pin-selectable twisted-pair receive polarity detection and automatic inversion of the receive signal. Polarity indication output pin can directly drive an LED. ■ Pin-selectable twisted-pair Link Integrity Test capability conforming to the IEEE 802.3 standard for 10BASE-T. Link status pin can directly drive an LED. ■ Internal twisted-pair transmitter digital predistortion circuit reduces medium-induced jitter and ensures compliance with the 10BASE-T transmit and receive waveform requirements ■ Pin-selectable SQE Test (heartbeat) enable ■ Transmit and receive status indications are available on separate, dedicated pins ■ AUI loopback, Jabber Control, and SQE Test functions comply with the 10BASE-T standard IEEE Std 802.3i-1990 GENERAL DESCRIPTION The Am79C98 Twisted-Pair Ethernet Transceiver (TPEX) is an integrated circuit that implements the medium attachment unit (MAU) functions for the twisted-pair medium, as specified by the IEEE 802.3 standard (Type 10BASE-T). This device provides the necessary electrical and functional interface between the IEEE 802.3 standard attachment unit interface (AUI) and the twisted-pair cable. A network based on the 10BASE-T standard can use unshielded twisted-pair cables, providing an economical solution to networking by allowing the use of existing telephone wiring. The Am79C98 provides a minimal component count and cost-effective solution to the design and implementation of 10BASE-T standard networks. Publication# 14395 Rev: D Amendment/0 Issue Date: May 1994 TPEX provides twisted-pair driver and receiver circuits, including on-board transmit digital predistortion, receiver squelch, and an AUI port with pin-selectable SQE Test enable. The device also provides a number of additional features, including pin-selectable TwistedPair Receive Polarity Detection and Automatic Polarity Reversal, Link Status indication, Link Test disable function, and transmit and receive status. The Twisted-Pair Polarity and Link Status pins can be used to drive LEDs directly. The Am79C98 is fabricated in CMOS technology and requires a single +5 V supply. The device is available in 24-pin SKINNYDIP® plastic dual in-line and 28-pin plastic leaded chip carrier (PLCC) packaging. 1 2 Am79C98 Attachment Unit Interface (AUI) TEST PRDN/RST REXT DI– DI+ SQE TEST CI– CI+ XMT DO– DO+ Line Driver Line Driver Line Receiver and Squelch Circuit Voltage Controlled Oscillator Collision and Loopback Jabber Control Polarity Detect and Auto Reversal Line Receiver and Smart Squelch Link Test Line Driver and Predistortion RXPOL RXD– RXD+ RCV LNKST TXD+ TXD– TXP+ TXP– Twisted-Pair Interface BLOCK DIAGRAM 14395D-1 AMD RELATED AMD PRODUCTS Part No. Description Am7996 IEEE-802.3/Ethernet/Cheapernet Tap Transceiver Am79C100 Twisted-Pair Ethernet Transceiver Plus (TPEX+) Am79C90 CMOS Local Area Network Controller for Ethernet (C-LANCE) Am79C900 Integrated Local Area Communications ControllerTM (ILACCTM) Am79C940 Media Access Controller for Ethernet (MACETM) Am79C960 PCnet-ISA Single-Chip Ethernet Controller (for ISA bus) Am79C961 PCnet-ISA+ Single-Chip Ethernet Controller (with Microsoft Plug n’ Play support) Am79C965 PCnet-32 Single-Chip Ethernet Controller (for 386DX, 486 and VL buses) Am79C970 PCnet-PCI Single-Chip Ethernet Controller (for PCI bus) Am79C974 PCnet-SCSI Combination Ethernet and SCSI Controller for PCI Systems Am79C981 Integrated Multiport Repeater PlusTM (IMR+TM) Am79C987 Hardware Implemented Management Information BaseTM (HIMIBTM) CONNECTION DIAGRAM Top View DIP TXP+ TXD– TXD+ PLCC CI– 2 23 TXD– DI+ 3 22 TXP+ DI– 4 21 TXP– DVSS 5 25 TXP– DVSS 5 20 DVDD DVSS 6 24 DVDD XMT 6 19 TEST XMT 7 23 DVDD LNKST 7 18 SQE^TEST LNKST 8 22 TEST AVSS 8 17 AVDD AVSS 9 21 SQE^TEST 16 AVSS 20 9 RXD+ 10 AVDD DO– 11 19 10 15 RXD– DO+ AVDD PRDN/RST 11 14 RXPOL 12 13 RCV Note: Pin 1 is marked for orientation 3 2 1 28 27 26 RXD+ RXD– RCV RXPOL 14395D-2 REXT 12 13 14 15 16 17 18 PRDN/RST REXT 4 DO– DO+ CI+ TXD+ CI– 24 DI+ 1 DI– CI+ 14395D-3 Am79C98 3 AMD LOGIC SYMBOL DVDD Attachment Unit Interface (AUI) AVDD DO+ DO– TXD+ TXP+ DI+ DI– TXD– TXP– CI+ CI– RXD+ RXD– Am79C98 SQE TEST LNKST TEST RXPOL REXT XMT PRDN/RST RCV DVSS Twisted Pair Interface AVSS 14395D-4 4 Am79C98 ORDERING INFORMATION Standard Products AMD standard products are available in several packages and operating ranges. The order number (valid combination) is formed by a combination of the elements below. AM79C98 OPTIONAL PROCESSING Blank = Standard Processing TECHNOLOGY C = CMOS Electrically Erasable PACKAGE TYPE P = 24-Pin Plastic DIP (PD 3024) J = 28-Pin Plastic Leaded Chip Carrier (PL 028) SPEED Not Applicable DEVICE NUMBER/DESCRIPTION Am79C98 Twisted-Pair Ethernet Transceiver (TPEX) Valid Combinations Valid Combinations AM79C98 PC, JC Valid combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations. Am79C98 5 PIN DESCRIPTION AVDD PRDN/RST Power Down/Reset Input, Active LOW Analog Power AVSS Driving this input LOW resets the internal logic of TPEX and places the device in a special Power Down mode. In the Power Down/Reset mode, all output drivers are placed in their inactive state. Analog Ground RCV This pin is the ground reference for analog portions of the TPEX circuitry. Receive Output CI+, CI– This pin is driven HIGH while TPEX is receiving data on the RXD pins and is transferring the received signal onto the AUI DI pair. The RCV and XMT pins are simultaneously driven HIGH during collision. This pin supplies +5 V to analog portions of the TPEX circuitry. Control In Output AUI port differential driver. REXT DI+, DI– External Resistor Input An external precision resistor is connected between this pin and AVDD in order to provide a voltage reference for the internal voltage-controlled oscillator (VCO). Data In Output AUI port differential driver. DO+, DO– Data Out Input AUI port differential receiver. RXD+, RXD– DVDD Digital Power This pin supplies +5 V to digital portions of the TPEX circuitry. DVSS Digital Ground This pin is the ground reference for digital portions of TPEX circuitry. LNKST Link Status Open Drain, Input/Output When this pin is tied LOW, the internal Link Test Receive function is disabled and the Transmit and Receive functions will remain active irrespective of arriving idle Link Test pulses and data. TPEX continues to generate idle Link Test pulses irrespective of the status of this pin. As an output, this pin is driven LOW if the link is identified as functional. However, if the link is determined to be nonfunctional, due to missing idle Link Test pulses or data packets, then this pin is not driven. In the LOW output state, the pin is capable of sinking a maximum of 16 mA and can be used to drive an LED. This pin is internally pulled HIGH when inactive. Receive Data Input 10BASE-T port differential receivers. RXPOL Receive Polarity Open Drain, Input/Output The twisted-pair receiver is capable of detecting a receive signal with reversed polarity (wiring error). The RXPOL pin is normally in the LOW state, indicating correct polarity of the received signal. If the receiver detects reversed polarity, then this pin is not driven (goes HIGH) and the polarity of subsequent packets is inverted. In the LOW output state, this pin can sink up to a maximum of 16 mA and is therefore capable of driving an LED. This feature can be disabled by strapping this pin LOW. In this case, the Receive Polarity correction circuit is disabled and the internal receive signal remains noninverted, irrespective of the received signal. This pin is internally pulled HIGH when inactive. SQE TEST Signal Quality Test (Heartbeat) Enable Input, Active LOW The SQE Test function is enabled by tying this input LOW. This input is internally pulled HIGH when inactive. 6 Am79C98 TEST TXP+, TXP– Test Input, Active HIGH Transmit Predistortion Output This pin should be tied HIGH for normal operation. If this pin is driven LOW, TPEX will enter Loopback Test mode. The type of loopback is determined by the state of the SQE TEST pin. If this pin is in the LOW state (Station MAU), TPEX transfers data independently from DO to the TXD/TXP circuit and from RXD to the DI circuit. If the SQE TEST is in the HIGH state (Repeater MAU), then data on the RXD circuit is transmitted back onto the TXD/TXP circuit and data on the DO circuit is transmitted onto the DI pair. Transmit waveform predistortion control. XMT Transmit Output This pin is driven HIGH while TPEX is receiving data on the AUI DO pair and is transmitting data on the TXD/ TXP pins. The XMT and RCV pins are simultaneously driven HIGH during collision. TXD+, TXD– Transmit Data Output 10BASE-T port differential drivers. Am79C98 7 FUNCTIONAL DESCRIPTION The Twisted-Pair Ethernet Transceiver (TPEX) complies with the requirements specified by the IEEE 802.3 standard for the attachment unit interface (AUI) and the standard for 10BASE-T medium attachment unit (MAU). TPEX also implements a number of features in addition to the IEEE 802.3 standard. An outline of functions implemented by the Am79C98 is given below. Attachment Unit Interface (DO+/–, DI+/–, CI+/–) The AUI electrical and functional characteristics comply with those specified by the IEEE 802.3, Sections 7 and 14 (drafted). The AUI pins can be wired directly to the isolation transformer, for a remote MAU application, or to another device (e.g., Am7992 serial interface adapter). The end-of-packet SQE Test function (heartbeat) can be disabled to allow the device to be employed in a repeater application. Twisted-Pair Transmit Function Data transmission to the 10BASE-T medium occurs when valid AUI signals appear on the DO+/–differential pair. This data stream is routed to the differential driver circuitry in the TXD+/– pins. The driver circuitry provides necessary electrical driving capability and predistortion control for transmitting signals over maximum-length twisted-pair cable, as specified by the IEEE 802.3 10BASE-T standard. The transmit function meets the propagation delays and jitter specified by the standard. During transmission, the XMT pin is driven HIGH and can be used for status information. Twisted-Pair Receive Function The receiver complies with the receiver specifications of the IEEE 802.3 10BASE-T standard, including noise immunity and received signal rejection criteria (“Smart Squelch”). Signals meeting these criteria appearing at the RXD+/– differential input pair are routed to the DI+/– outputs. The receiver function meets the propagation delays and jitter requirements specified by the standard. Receiver squelch level drops to approximately half its threshold value after unsquelch to allow reception of minimum amplitude signals and to offset carrier fade in the event of worst-case signal attenuation and crosstalk noise conditions. During receive, the RCV pin is driven HIGH and can be used for status information. Link Test Function The Link Test function is implemented as specified by the IEEE 802.3 10BASE-T standard. During periods of transmit pair inactivity, Link Test pulses will be periodically sent over the twisted-pair medium to allow constant monitoring of medium integrity. When the Link Test function is enabled, the absence of Link Test pulses on the RXD+/– pair will cause the TPEX to go into a Link Fail state. In Link Fail state, data transmission, 8 Am79C98 data reception, and the collision detection functions are disabled, and remain disabled until valid data or >2 consecutive Link Test pulses appear on the RXD+/– pair. During Link Fail, the LNKST pin is internally pulled HIGH. When the link is identified as functional, the LNKST pin is driven LOW and is capable of directly driving a “link OK” LED. In order to interoperate with systems that do not implement Link Test, this function can be disabled by grounding the LNKST pin. When disabled, the driver and receiver functions remain enabled irrespective of the presence or absence of data or Link Test pulses on the RXD+/– pair. The transmitter continues to generate Link Test pulses in the absence of transmit data even if the Link Test function is disabled. Polarity Detection and Reversal The TPEX receive function includes the ability to invert the polarity of the signals appearing at the RXD± pair if the polarity of the received signal is reversed (such as in the case of a wiring error). This feature allows data packets received from a reverse-wired RXD± input pair to be corrected in the TPEX prior to transfer to the DTE via the AUI interface (DI±). The polarity detection function is activated following reset or Link Fail, and will reverse the receive polarity based on both the polarity of any previous Link Test pulses and the polarity of subsequent packets with a valid end transmit delimiter (ETD). When in the Link Fail state, TPEX will recognize Link Test pulses of either positive or negative polarity. Exit from the Link Fail state is caused by the reception of five to six consecutive Link Test pulses of identical polarity. On entry to the Link Pass state, the polarity of the last five Link Test pulses is used to determine the initial receive polarity configuration and the receiver is reconfigured to subsequently recognize only Link Test pulses of the previously established polarity. This link pulse algorithm is employed only until ETD polarity determination is made, as described later in this section. Positive Link Test pulses are defined as received signals with a positive amplitude greater than 520 mV and a pulse width of 60 ns to 200 ns. This positive excursion may be followed by a negative excursion. This definition is consistent with the expected received signal at a correctly wired receiver when a Link Test pulse that fits the template of Figure 14-12 in the 10BASE-T standard is generated at a transmitter and passed through 100 m of twisted-pair cable. Negative Link Test pulses are defined as received signals with a negative amplitude greater than 520 mV and a pulse width of 60 ns to 200 ns. This negative excursion may be followed by a positive excursion. This definition is consistent with the expected received signal at a reverse wired receiver when a Link Test pulse that fits the template of Figure 14-12 in the 10BASE-T standard is generated at a transmitter and passed through 100 m of twisted-pair cable. The polarity detection/correction algorithm will remain “armed” until two consecutive packets with valid ETD of identical polarity are detected. When “armed,” the receiver is capable of changing the initial or previous polarity configuration based on the most recent ETD polarity. On receipt of the first packet with valid ETD following reset or Link Fail, TPEX will utilize the inferred polarity information to configure its RXD± input, regardless of its previous state. On receipt of a second packet with a valid ETD with correct polarity, the detection/correction algorithm will “lock in” the initial polarity. If the second (or subsequent) packet is not detected as confirming the previous polarity decision, the most recently detected ETD polarity will be used as the new default. Note that packets with invalid ETD have no effect on updating the previous polarity decision. Once two consecutive packets with valid ETD have been received, TPEX will disable the detection/correction algorithm until either a Link Fail condition occurs or PRDN/RST is asserted. During polarity reversal, the RXPOL pin is internally pulled HIGH. During normal polarity conditions, the RXPOL pin is driven LOW and is capable of directly driving a “Polarity OK” LED using an integrated 16 mA driver. If desired, the polarity reversal function can be disabled by grounding the RXPOL pin. Twisted-Pair Interface Status Two outputs (XMT and RCV) indicate whether TPEX is transmitting (AUI to twisted-pair) or receiving (twistedpair to AUI). Both signals are asserted during a collision. In Link Fail mode, RCV is disabled. In Jabber Detect mode, XMT is disabled. Both signals are active HIGH. Collision Detect Function Simultaneous carrier sense (presence of valid data signals) by both the AUI DO+/– pair and the RXD+/– pair constitutes a collision, thereby causing a 10 MHz signal to be asserted on the CI+/– output pair. The CI+/– output meets the drive requirements for the AUI. This 10 MHz signal will remain on the CI+/– pair until one of the two colliding states changes from active to idle. The CI+/– output pair stays HIGH for two bit times at the end of a collision, decreasing to the idle level within eighty bit times after the last LOW-to-HIGH transition. Both the XMT and RCV pins are driven HIGH during collision. Signal Quality Error (SQE) Test (Heartbeat) Function When the SQE TEST pin is driven LOW, TPEX will routinely exercise the collision detection circuitry by generating an SQE message at the end of every trans- mission. This signal is a self-test indication to the DTE that the MAU collision circuitry is functional. An SQE message consists of a 10 MHz signal on the CI+/– pair with a duration of 8 bit times (800 ns). When enabled, an SQE Test will occur at the end of every transmission, starting eight bit times (800 ns) after the last transition of the transmitted signal. For repeater applications, the SQE Test function can be disabled by tying the SQE TEST pin HIGH or by leaving it disconnected. Jabber Function The Jabber function inhibits the twisted-pair transmit function of TPEX if the DO+/– circuit is active longer than the time permitted to transmit the maximumlength 802.3/Ethernet data packet (50 ms nominal). This prevents any one node from disrupting the network due to a “stuck on” or faulty transmitter. If this maximum transmit time is exceeded, TPEX transmitter circuitry is disabled and a 10 MHz signal is driven onto the CI+/– pair. Once the transmit data stream is removed from the DO+/– pair of inputs, an “unjab” time of 250 ms to 750 ms will elapse before TPEX removes the 10 MHz signal from the CI+/– pair and re-enables the transmit path. Power Down In addition to on-board power-on-reset circuitry, the PRDN/RST pin is used as the master reset for TPEX. PRDN/RST must be driven LOW for a minimum of two microseconds for reset to occur. The PRDN/RST pin can also be used to put the TPEX into an inactive state, causing the device to consume less power. This feature is useful in battery-powered or low-duty-cycle systems. Driving PRDN/RST LOW resets the internal logic of TPEX and places the device into idle mode. In this mode, the twisted-pair driver pins (TXD+/–,TXP+/–) are driven LOW, the AUI pins (CI+/–, DI+/–) are driven HIGH, the LNKST and RXPOL pins are in the inactive state, and XMT and RCV are LOW. TPEX will remain in idle as long as PRDN/RST is asserted. Following the rising edge of the signal on PRDN/RST, TPEX will remain in the reset state for 10 µs. Test Modes TPEX implements two types of loopback test modes suitable for Station (DTE) or Repeater applications. The Test mode is entered by driving the TEST pin HIGH. The two types of test modes available are: 1. Station (DTE): SQE TEST pin LOW. Data on DO+/– pair is transmitted onto the TXD+/– and TXP+/– pairs and data on the RXD+/– input pair is transmitted onto the DI+/– output pair. The jabber function and collision detection functions are disabled. 2. Repeater: SQE TEST pin HIGH. Data on DO+/– pair is looped back onto the DI+/– pair and data on the RXD+/– pair is retransmitted on the twisted-pair drivers (TXD+/– and TXP+/– pairs). Am79C98 9 In both modes, the jabber circuitry, collision detection, and collision oscillator functions are disabled and the AUI and RXD+/– squelch circuits are active. based MAU. Specifically, the transmitted waveforms are heavily influenced by filter characteristics and the twisted-pair receivers employ several criteria to continuously monitor the incoming signal’s amplitude and timing characteristics to determine when and if to assert the internal carrier sense. For these reasons, it is crucial that the values and tolerances of the external components be as specified. Several manufacturers produce a module that combines the functions of the transmit and receive filters and the pulse transformers into one package. TPEX External Components Figure 1 shows a typical twisted-pair port external components schematic. The resistors used should have a ±1% tolerance to ensure interoperability with 10BASE-T-compliant networks. Filters and pulse transformers are necessary devices that have a major influence on the performance and compliance of a TPEX- TXD+ TXP+ Am79C100 TPEX TXD– TXP– 57.6 324.0 1:1 768.0 57.6 324.0 XMIT Filter TD– Twisted-Pair Cable 1:1 RXD+ RXD– TD+ 100 Ω RECV Filter RD+ RD– Module 14395D-5 Note: The filter/transformer module shown is available from the following manufacturers: Belfuse, TDK, Pulse Engineering, PCA, Valor Electronics, and Nano Pulse. Figure 1. Typical Twisted-Pair Port External Components 10 Am79C98 12 Am79C98 24.3 kΩ 1% RXD+ RXD- CI+ CI- DVDD RCV XMT RXPOL DVSS DGTL GND 4.7µF 0.1µF PWDN/RST TEST REXT LNKST TXP- DI- SQE^TEST TXD- DI+ Am79C98 TXP+ DO- AVSS TXD+ AVDD 0.1µF DO+ 40.2 Ω 100 Ω Optional 47 pF 0.01µF COL DGTL GND 74HC132 100 K RCV RCV Filter Note 1 XMT Filter Filter and Transformer Module XMT RX POL OK 47 pF 0.1 µF ANLG GND 768.0 Ω Note 2 LINK OK 324.0 Ω 57.6 Ω 324.0 Ω 57.6 Ω ANLG GND Figure 3. Typical TPEX System Application DGTL +5 V ANLG +5 V 1. Compatible filter modules, with a brief description of package type and features are included in Table 1 of this section. 2. The resistor values are recommended for general purpose use, and should allow compliance to the 10BASE-T specification for template fit and jitter performance. However, the overall performance of the transmitter is also affected by the transmit filter configuration. 3. Compatible AUI transformer modules, with a brief description of package type and features are included in Table 2 of this section. Notes: Note 3 Pulse Transformer 40.2 Ω 0.01µF Enable Heartbeat DGTL GND Optional AUI Connector Optional ANLG +5 V 2 1 6 330 Ω 14395D-7 DGTL +5 V RD– RD+ 3 TD– TD+ RJ45 Connector AMD AMD Table 1. TPEX Compatible Media Interface Modules Manufacturer Part # Package Description Bel Fuse A556-2006-DE 16-pin 0.3” DIL Transmit and receive filters and transformers Bel Fuse 0556-2006-00 14-pin SIP Transmit and receive filters and transformers Bel Fuse 0556-2006-01 14-pin SIP Transmit and receive filters, transformers and common mode chokes Valor Electronics PT3877 16-pin 0.3” DIL Transmit and receive filters and transformers Valor Electronics PT3983 8-pin 0.3” DIL Transmit and receive common mode chokes Valor Electronics FL1012 16-pin 0.3” DIL Transmit and receive filters and transformers, transmit common mode choke Nano pulse NP6612 16-pin 0.3” DIL Transmit and receive filters, transformers and common mode chokes Nano pulse NP6581 8-pin 0.3” DIL Transmit and receive common mode chokes Nano pulse NP6696 24-pin 0.6” DIL Transmit and receive filters, transformers and common mode chokes TDK TLA 470 14-pin SIP Transmit and receive filters and transformers TDK HIM3000 24-pin 0.6” DIL Transmit and receive filters, transformers and common mode chokes Pulse Engineering PE65421 16-pin 0.3” DIL Transmit and receive filters and transformers Pulse Engineering SUPRA 1.1 16-pin 0.5” DIL Transmit and receive filters and transformers, transmit common mode choke Bel Fuse 0556-6392-00 16-pin 0.5” DIL Transmit and receive filters, transformers, and common mode chokes Table 2. Am79C98 TPEX Compatible AUI Transformers Manufacturer Part # Package Description Bel Fuse A553-0506-AB 16-pin 0.3” DIL 50 µH Valor Electronics LT6031 16-pin 0.3” DIL 50 µH TDK TLA 100-3E 16-pin 0.3” DIL 100 µH Pulse Engineering PE64106 16-pin 0.3” DIL 50 µH Am79C98 13 AMD ABSOLUTE MAXIMUM RATINGS OPERATING RANGES Storage Temperature: . . . . . . . . . . . -65°C to +150°C Commercial (C) Devices Temperature (TA): . . . . . . . . . . . . . . . . 0°C to +70°C Supply Voltages (AVDD, DVDD): . . . . . . . . . +5 V ± 5% Ambient Temperature Under Bias: . . . . 0°C to +70°C Supply Voltage to AVSS or DVSS (AVDD, DVDD): . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V Operating ranges define those limits between which the functionality of the device is guaranteed. Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability. DC CHARACTERISTICS over COMMERCIAL operating range unless otherwise specified Parameter Symbol Parameter Description Test Conditions Min Max Unit Digital Input Voltage VIL Input LOW Voltage DVSS-0.5 0.8 V VIH Input HIGH Voltage 2.0 0.5 + DVDD V 0.4 V Digital Output Voltage VOL Output LOW Voltage IOL1 = 16 mA (Open drain) IOL2 = 4.0 mA VOH Output HIGH Voltage IOH = -0.4 mA 2.4 V Digital Input Leakage Current IILL Input Leakage Current 0 < VIN < DVDD + 0.5 V 10 µA IILD Input Leakage Current (Open drain pins, output inactive) 0 < VIN < DVDD + 0.5 V 500 µA IIAXD Input Current at DO+, DO- -1 < Vin < AVDD + 0.5 V -500 500 µA VAICM DO+/- Open Circuit Input Common Mode Voltage (Bias) IIN = 0 V AVDD - 3.0 AVDD - 1.0 V VAIDV Differential Mode Input Voltage Range (DO+/-) AVDD = 5 V -2.5 +2.5 V VASQ DO+/- Squelch Threshold AUI -275 mV VATH DO+ Switching Threshold -35 +35 mV VAOD Differential Output Voltage |(DI+) - (DI-)| OR |(CI+) - (CI-)| RL = 78 Ω 620 1100 mV VAODI DI+/- & CI+/Differential Output Voltage Imbalance RL = 78 Ω (Note 1) -25 +25 mV VAODOFF DI+/- & CI+/Differential Idle Output Voltage RL = 78 Ω -40 +40 mV IAODOFF DI+/- & CI+/Differential Idle Output Current RL = 78 Ω (Note 1) -1 1 mA DI+/- & CI+/- Common Mode Output Voltage RL = 78 Ω 2.5 AVDD V VAOCM 14 (Note 1) 160 Am79C98 AMD DC CHARACTERISTICS (continued) Parameter Symbol Parameter Description Test Conditions Min Max Unit –500 500 µA Twisted Pair Interface IIRXD Input Current at RXD+/– AVSS < VIN < AVDD RRXD RXD+/– Differential Input Resistance (Note 1) VTIVB RXD+, RXD– Open Circuit Input Voltage (Bias) IIN = 0 mA VTIDV Differential Mode Input Voltage Range (RXD+/–) VTSQ+ 10 KΩ AVDD - 3.0 AVDD - 1.5 V AVDD = +5 V –3.1 3.1 V RXD Positive Squelch Threshold (Peak) Sinusoid 5 MHz < f< 10 MHz 300 520 mV VTSQ– RXD Negative Squelch Threshold (Peak) Sinusoid 5 MHz < f< 10 MHz –520 –300 mV VTHS+ RXD Post-Squelch Positive Threshold (Peak) Sinusoid 5 MHz < f< 10 MHz 150 293 mV VTHS– RXD Post-Squelch Negative Threshold (Peak) Sinusoid 5 MHz < f< 10 MHz –293 –150 mV RXD Switching Threshold (Note 1) –60 60 mV VTXH TXD+/– and TXP+/– Output HIGH Voltage (Note 2) DVSS = 0 V DVDD - 0.6 DVDD V VTXL TXD+/– and TXP+/– Output LOW Voltage (Note 2) DVDD = +5 V DVSS DVSS + 0.6 V VTXI TXD+/– and TXP+/– Differential Output Voltage Imbalance –40 +40 mV –40 +40 mV VRXDTH VTXOFF RTX IIREXT TXD+/– and TXP+/– Differential Idle Output Voltage DVDD = +5 V TXD+/– and TXP+/– Differential Driver Output Impedance (Note 1) 40 Ω Input Current at REXT Pin REXT = 24.3K Ω ± 1% AVDD = +5 V 120 µA Power Supply Current (Transmitting 10 MHz Data) (Typical TP load) PRDN/RST = HIGH 115 mA Power Supply Current (Transmitting 10 MHz Data) (No TP load) PRDN/RST = HIGH 90 mA Power Supply Current in Power Down Mode PRDN/RST = LOW 4 mA Power Supply Current IDD IDDPRDN Am79C98 15 AMD SWITCHING CHARACTERISTICS over COMMERCIAL Parameter Symbol Parameter Description Transmit Timing Max Unit tPWODO DO Pulse Width Accept/Reject Threshold |VIN| > |VASQ| (Note 3) 15 35 ns tPWKDO DO Pulse Width Maintain/Turn-Off Threshold |VIN| > |VASQ| (Note 4) 105 200 ns tTON Transmit Start Up Delay 300 ns tTSD Transmit Static Propagation Delay (DO to TXD) 120 ns tDODION DO to DI Startup Delay 300 ns tDODISD DO to DI Static Propagation Delay 100 ns 450 ns tTR Transmitter Rise Time (10% to 90%) 10 ns tTF Transmitter Fall Time (90% to 10%) 10 ns tTM Transmitter Rise and Fall Time Mismatch 4 ns tTHD DO L–>H to TXD+ L–>H and TXD- H->L Delay Steady State (Note 1) tTSD – 1.0 tTSD + 1.0 ns tTLD DO H–>L to TXD+ H–>L and TXD– L–>H Delay Steady State (Note 1) tTSD – 1.0 tTSD + 1.0 ns tTHDP DO L–>H to TXP+ H–>L and TXP- L->H Delay Steady State (Note 1) tTSD + 40 tTSD + 60 ns tTLDP DO H–>L to TXP+ L–>H and TXP– H->L Delay Steady State (Note 1) tTSD + 40 tTSD + 60 ns tTETD Transmit End of Transmission 250 tXMTON XMT Asserted Delay 100 ns tXMTOFF XMT De-asserted Delay 300 ns 8 24 ms tPERLP Idle Signal Period tPWLP Idle Link Test Pulse Width (Note 1) 75 120 ns tPWPLP Predistortion Idle Link Test Pulse Width (Note 1) 40 60 ns tJA Transmit Jabber Activation Time 20 150 ms tJR Transmit Jabber Reset Time 250 750 ms Transmit Jabber Recovery Time (Minimum time gap between transmitted packets to prevent jabber activation) 1.0 – µs tJREC 16 Min Am79C98 AMD SWITCHING CHARACTERISTICS (continued) Parameter Symbol Parameter Description Receive Timing tPWKRD Min Max Unit RXD Pulse Width Maintain/Turn-Off Threshold |VIN| >|VTHS| (Note 5) 136 200 ns tRON Receiver Start Up Delay (RXD to DI+/–) 5 MHz Sinusoid 200 400 ns tRVB First Validly Timed Bit on DI+/– (RXD to DI) tRON + 100 ns tRSD Receiver Static Propagation Delay (RXD to DI) 70 ns tRETD DI End of Transmission tRHD RXD L–>H to DI+ L–>H and DI– H–>L Delay (Note 1) tRSD – 2.5 tRSD + 2.5 ns tRLD RXD H–>L to DI+ H–>L and DI- L->H Delay (Note 1) tRSD – 2.5 tRSD + 2.5 ns tRR DI+, DI–, CI+, CI– Rise Time (10% to 90%) 5.0 ns tRF DI+, DI–, CI+, CI– Fall Time (10% to 90%) 5.0 ns tRM DI+/– & CI+/– Rise and Fall Time Mismatch (|tRR – tRF|) 2.0 ns tRON + 100 ns tRSD + 250 ns tRCVON RCV Asserted Delay tRCVOFF RCV De-asserted Delay 200 tRON – 50 ns Collision Detection and SQE Test tCON Collision Turn-On Delay (CI+/–) 500 ns tCOFF Collision Turn-Off Delay (CI+/–) 500 ns tPER Collision Period (CI+/–) 87 117 ns tCPW Collision Output Pulse Width (CI+/-) 40 60 ns tSQED SQE Test Delay Time 600 1600 ns tSQEL SQE Test Length 500 1500 ns Notes: 1. Parameter not tested. 2. Uses switching test load. 3. DO pulses narrower than tPWODO (min) will be rejected; pulses wider than tPWODO (max) will turn internal DO carrier sense on. 4. DO pulses narrower than tPWKDO (min) will maintain internal DO carrier sense on; pulses wider than tPWKDO (max) will turn internal DO carrier sense off. 5. RXD pulses narrower than tPWKRD (min) will maintain internal RXD carrier sense on; pulses wider than tPWKRD (max) will turn internal RXD carrier sense off. Am79C98 17 AMD SWITCHING WAVEFORMS tPWPLP TXD+ TXP+ tPWPLP TXD– TXP– tPWLP tPERLP 14395D-9 TP Idle Link Test Pulse SWITCHING TEST CIRCUITS DVDD 294 Ω TXD+ TXD– Test Point 294 Ω 100 pF Includes test jig capacitance DVSS 14395D-10 TXD Switching Test Circuit DVDD 715 Ω TXP+ TXP– Test Point 100 pF Includes test jig capacitance 715 Ω DVSS 14395D-11 TXP Switching Test Circuit Am79C98 19 AMD RECEIVE TEST CIRCUIT DVDD 52.3 Ω DI+ DI– CI+ CI– Test Point 154 Ω 100 pF DVSS 14395D-13 AUI DI, CI Switching Test Circuit DO + / – RXD + / – tCON tCOFF CI + CI – tCPW tPER 14395D-14 Collision Timing DO + / – CI + tSQED CI – tSQEL 14395D-15 SQE Test Timing (SQE^Test Pin Connected to VSS) Am79C98 21 Trademarks Copyright © 1998 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD logo, and combinations thereof are trademarks of Advanced Micro Devices, Inc. Am186, Am386, Am486, Am29000, bIMR, eIMR, eIMR+, GigaPHY, HIMIB, ILACC, IMR, IMR+, IMR2, ISA-HUB, MACE, Magic Packet, PCnet, PCnet-FAST, PCnet-FAST+, PCnet-Mobile, QFEX, QFEXr, QuASI, QuEST, QuIET, TAXIchip, TPEX, and TPEX Plus are trademarks of Advanced Micro Devices, Inc. Microsoft is a registered trademark of Microsoft Corporation. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.