FINAL Am7992B Serial Interface Adapter (SIA) DISTINCTIVE CHARACTERISTICS ■ Compatible with lEEE 802.3/Ethernet/Cheapernet specifications ■ Crystal/TTL oscillator-controlled Manchester encoder ■ Manchester decoder acquires clock and data within four bit times with an accuracy of ±3 ns ■ Guaranteed carrier and collision detection squelch threshold limits — Carrier/collision detected for inputs greater than –275 mV — No carrier/collision for inputs less than –175 mV ■ Input signal conditioning rejects transient noise — Transients <10 ns for collision detector inputs — Transients <20 ns for carrier detector inputs ■ Receiver decodes Manchester data with worst case ±19 ns of clock jitter (at 10 MHz) ■ TTL-compatible host interface ■ Transmit accuracy +0.01% (without adjustments) GENERAL DESCRIPTION The Am7992B Serial Interface Adapter (SIA) is a Manchester encoder/decoder compatible with IEEE 802.3, Cheapernet, and Ethernet specifications. In an IEEE 802.3/Ethernet application, the Am7992B interfaces the Am7990 Local Area Network Controller for Ethernet (LANCE) to the Ethernet transceiver device, acquires clock and data within four bit times, and decodes Manchester data with worst case ±19 ns phase jitter at 10 MHz. SIA provides both guaranteed signal threshold limits and transient noise suppression circuitry in both data and collision paths to minimize false start conditions. Receive Data (RX) Receive Clock (RCLK) Controller Interface Carrier Present (RENA) Collision (CLSN) Manchester Decoder Data Receiver Receive+ Carrier Detect Noise Reject Filter Receive– Collision Detect Noise Reject Filter Collision+ Transmit Data (TX) Manchester Encoder Transmit Enable (TENA) Transmit Clock (TCLK) Transmit– Crystal OSC XTAL2 Amendment/0 Transmit+ XTAL1 20 MHz Publication# 03378 Rev: I Issue Date: May 1993 Collision– Transceiver Interface BLOCK DIAGRAM 03378I-1 1 AMD RELATED PRODUCTS Part No. Description Am7990 Local Area Network Controller for Ethernet (LANCE) Am7996 IEEE 802.3/Ethernet/Cheapernet/Transceiver Am79C900 Integrated Local Area Communications ControllerTM (ILACCTM) CONNECTION DIAGRAMS Receive+ 4 3 2 1 28 27 26 RX 2 23 Collision– RENA 3 22 Receive+ RCLK 4 21 Receive– TSEL 5 20 TEST RCLK 5 25 Receive- GND1 6 19 VCC1 NC 6 24 TEST GND2 7 18 VCC2 TSEL 7 23 VCC1 15 GND3 TCLK 11 14 Transmit+ TENA 12 13 Transmit– 22 GND2 9 21 VCC2 X1 10 20 PF X2 11 19 RF 12 13 14 15 16 17 18 GND3 10 8 Transmit+ TX GND1 NC RF Transmit- PF 16 TENA 17 9 TCLK 8 X2 NC TX X1 03378I-2 03378I-3 Note: Pin 1 is marked for orientation. 2 Colision- Collision+ NC 24 CLSN 1 RX CLSN Colision+ PLCC RENA DIP Am7992B ORDERING INFORMATION Standard Products AMD standard products are available in several packages and operating ranges. The order number (valid combination) is formed by a combination of the elements below. AM7992B D C B OPTIONAL PROCESSING Blank = Standard Processing B = Burn-In OPERATING CONDITIONS C = Commercial (0°C to +70°C) PACKAGE TYPE D = 24-Pin (Slim) Ceramic DIP (CD3024) J = 28-Pin PLCC (PL 028) P = 24-Pin (Slim) Plastic DIP (PD3024) SPEED Not Applicable DEVICE NUMBER/DESCRIPTION Am7992B Serial Interface Adapter Valid Combinations Valid Combinations AM7992B DC, DCB, JC, JCTR, PC Valid combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations. Am7992B 3 PIN DESCRIPTION CLSN TCLK Collision (Output, TTL Active HIGH) Signals at the Collision± terminals meeting threshold and pulse-width requirements will produce a logic HIGH at CLSN output. When no signal is present at Collision±, CLSN output will be LOW. RX Transmit+, Transmit– Receive Data (Output) A MOS/TTL output, recovered data. When there is no signal at Receive± and TEST is HIGH, RX is HIGH. RX is actuated with RCLK and remains active until RENA is deasserted at the end of the message. During reception, RX is synchronous with RCLK and changes after the rising edge of RCLK. When TEST is LOW, RX is enabled. RENA Receive Enable (Output, TTL Active HIGH) When there is no signal at Receive+, RENA is LOW. Signals meeting threshold and pulse-width “on” requirements will produce a logic HIGH at RENA. When RENA is HIGH, Receive+ signals meeting threshold and pulse-width “off” requirements will produce a LOW at RENA. RCLK Transmit (Outputs) A differential line output. This line pair is intended to operate into terminated transmission lines. For signals meeting setup and hold time to TCLK at TENA and TX, Manchester clock and data are outputted at Transmit+/ Transmit–. When operating into a 78 Ω terminated transmission line, signaling meets the required output levels and skew for both Ethernet and IEEE 802.3 drop cables. Receive+, Receive– Receiver (Inputs) A differential input. A pair of internally biased line receivers consisting of a carrier detect receiver with offset threshold and noise filtering to detect the line activity, and a data recovery receiver with no offset for Manchester data decoding. Collision+, Collision– Receive Clock (Output) A MOS/TTL output, recovered clock. When there is no signal at Receive± and TEST is HIGH, RCLK is LOW. RCLK is activated 1/4 bit time after the second negative Manchester preamble clock transition at Receive± and remains active until after an end of message. When TEST is LOW, RCLK is enabled and meets minimum pulse-width specifications. TX Transmit (Input) TTL-compatible input. When TENA is HIGH, signals at TX meeting setup and hold time to TCLK will be encoded as normal Manchester at Transmit+ and Transmit–. ■ TX HIGH: Transmit+ is negative with respect to Transmit– for first half of data bit cell. ■ TX LOW: Transmit+ is positive with respect to Transmit– for first half of data bit cell. TENA Transmit Enable (Input) TTL-compatible input. Active HIGH data encoder enable. Signals meeting setup and hold time to TCLK will allow encoding of Manchester data from TX to Transmit+ and Transmit–. 4 Transmit Clock (Output) MOS/TTL output. TCLK provides symmetrical HIGH and LOW clock signals at data rate for reference timing of data to be encoded. It also provides clock signals for the controller chip (Am7990—LANCE) and an internal timing reference for receive path voltage-controlled oscillators. Am7992B Collision (Inputs) A differential input. An internally biased line receiver input with offset threshold and noise filtering. Signals at Collision± have no effect on data-path functions. TSEL Transmit Mode Select (Output, Open Collector; Input, Sense Amplifier) ■ TSEL LOW: Idle transmit state Transmit+ is positive with respect to Transmit–. ■ TSEL HIGH: Idle transmit state Transmit+ and Transmit– are equal, providing “zero” differential to operate transformer-coupled loads. When connected with an RC network, TSEL is held LOW during transmission. At the end of transmission the open collector output is disabled, allowing TSEL to rise and provide a smooth transmission from logic HIGH to “zero” differential idle. Delay and output return to zero are externally controlled by the RC network at TSEL and Transmit± load inductance. X1, X2 TEST Biased Crystal Oscillator (Input) X1 is the input and X2 is the bypass port. When connected for crystal operation, the system clock that appears at TCLK is half the frequency of the crystal oscillator. X1 may be driven from an external source of two times the data rate. Test Control (Input) A static input that is connected to VCC for Am7992B/ Am7990 operation and to ground for testing of Receive ± path threshold and RCLK output HIGH parameters. When TEST is grounded, RX is enabled and RCLK is enabled except during clock acquisition, when RCLK is HIGH. RF Frequency Setting Voltage-Controlled Oscillator (VCO) Loop Filter (Output) This loop filter output is a reference voltage for the receive path phase detector. It also is a reference for timing noise immunity circuits in the collision and receive enable path. Nominal reference VCO gain is 1.25 TCLK frequency MHz/V. PF Receive Path VCO Phase-Locked Loop Filter (Input) This loop filter input is the control for receive path loop damping. Frequency of the receive VCO is internally limited to transmit frequency ±12%. Nominal receive VCO gain is 0.25 reference VCO gain MHz/V. GND1 High Current Ground GND2 Logic Ground GND3 Voltage-Controlled Oscillator Ground VCC1 High Current and Logic Supply VCC2 Voltage-Controlled Oscillator Supply Am7992B 5 FUNCTIONAL DESCRIPTION Transmitter Timing and Operation The Am7992B serial interface adapter (SIA) has three basic functions. It is a Manchester encoder/line driver in the transmit path, a Manchester decoder with noise filtering and quick lock-on characteristics in the receive path, and a signal detector/converter (10 MHz differential to TTL) in the collision path. In addition, the SIA provides the interface between the TTL logic environment of the Local Area Network Controller for Ethernet (LANCE) and the differential signaling environment in the transceiver cable. A 20 MHz fundamental mode crystal oscillator provides the basic timing reference in the SIA. It is divided by two to create the Transmit Clock reference (TCLK). Both 20 MHz and 10 MHz clocks are fed into the Manchester Encoder to generate the transitions in the encoded data stream. The 10 MHz clock, TCLK, is used by the SIA to internally synchronize Transmit (TX) data and Transmit Enable (TENA). TCLK is also used as a stable bit rate clock by the receive section of the SIA and by other devices in the system (the Am7990 LANCE uses TCLK to drive its internal state machine). The oscillator may use an external 0.005% crystal or an external TTL-level input as a reference, which will achieve a transmit accuracy of 0.01% (no external adjustments are required). Transmit Path The transmit section encodes separate clock and NRZ data input signals meeting the setup and hold time to TCLK at TENA and TX into a standard Manchester II serial bit stream. The transmit outputs (Transmit+/ Transmit–) are designed to operate into terminated transmission lines. When operating into a 78 Ω terminated transmission line, signaling meets the required output levels and skew for IEEE 802.3/Ethernet/ Cheapernet. TX TENA Manchester Encoder Transmission is enabled when TENA is activated. As long as TENA remains HIGH, signals at TX will be encoded as Manchester and will appear at Transmit+ and Transmit–. When TENA goes LOW, the differential transmit outputs go to one of two idle states determined by the circuit configuration of TSEL: TSEL HIGH: The idle state of Transmit± yields “zero” differential to operate transformer-coupled loads (see Figure 2, Transmitter Timing—End of Transmission waveform diagram and Typical Performance Curve diagram). DO± TSEL LOW: In this idle state, Transmit+ is positive to Transmit– (logical HIGH) (see figures and diagrams as referenced above). TCLK OSC I 03378I-4 The End of Transmission—Return to Zero is determined by the external RX network at TSEL and by the load at Transmit±. Figure 1. Transmit Section VCC TSEL PIN 5 R1 C1 510 C2 20 pF R2 680 pF 3K TSEL PIN 5 A. TSEL LOW B. TSEL HIGH 03378I-5 03378I-6 Figure 2. Transmit Mode Select (TSEL) Connection 6 Am7992B ALS Driver or Equivalent X1 03378I-7 Figure 3. TTL Clock Driver Circuit for X1 external clock having the following characteristics must be used to ensure less than +0.5 ns jitter at Transmit+ (see the X1 Driven from External Source waveform diagram and the TTL Clock Driver Circuit for X1, Figure 3): ■ Clock Frequency: 20 MHz ±0.01% ■ Rise/Fall Time (tR/tF): <4 ns, monotonic ■ X1 HIGH/LOW Time (tHlGH/tLOW): > 20 ns SIA Oscillator Specification for External Crystal ■ X1 Falling Edge-to-Falling Edge Jitter: < ±0.2 ns at 1.5 V input When using a crystal to drive the Am7992B oscillator, the following crystal specification should be used to ensure a transmit accuracy of 0.01%: Receiver Path Limit Min Nominal Max Unit Resonant Frequency Error with CL = 50 pF –50 0 +50 PPM Change in Resonant Frequency Temperature with CL = 50 pF –40 +40 PPM Parallel Resonant Frequency with CL = 50 pF Motional Crystal Capacitance, C1 20 MHz 0.022 pF The principle functions of the receiver are to signal the LANCE that there is information on the receive pair and to separate the incoming Manchester-encoded data stream into clock and NRZ data. The receiver section (see Figures 4 and 5) consists of two parallel paths. The receive data path is a zero threshold, wide bandwidth line receiver. The carrier path is an offset threshold bandpass-detecting line receiver. Both receivers share common bias networks to allow operation over an input common mode range of 0 V to 5.5V. RX Some crystal manufacturers have generated crystals to this specification. One such manufacturer is ReevesHoffman. Their ordering part number for this crystal is RH#04-20423-312. Another manufacturer is Epson— Par t #MA 506-200M-50 pF, which is a surfacemounted crystal. RCLK RENA Manchester Decoder Data Receiver DI± Carrier Detect Noise Reject Filter 03378I-8 Figure 4. Receiver Specification for External TTL Level When driving the oscillator from an external clock source, X 2 must be left floating (unconnected). An Am7992B 7 RX Q D RCLK 40.0 MHz VCO Phase Detector + Data REC DIV Clock Gating Noise Reject Filter RENA Carrier REC + – 03378I-9 Figure 5. Receiver Section Detail Input Signal Conditioning The Carrier Receiver detects the presence of an incoming data packet by discerning and rejecting noise from expected Manchester data. It also controls the stop and start of the phase-locked loop during clock acquisition. In the Am7992B, clock acquisition requires a valid Manchester bit pattern of 1010 to lock on the incoming message (see Receive Timing—Start of Reception Clock Acquisition waveform diagram). Transient noise pulses less than 20 ns wide are rejected by the Carrier Receiver as noise and DC inputs more positive than –175 mV are also suppressed. Carrier is detected for input signal wider than 45 ns with amplitude more negative than –275 mV. When input amplitude and pulse-width conditions are met at Receive±, RENA is asserted and a clock acquisition cycle is initiated. Clock Acquisition When there is no activity at Receive± (receiver is idle), the receive oscillator is phase locked to TCLK. The first negative clock transition (first valid Manchester “0”) after RENA is asserted interrupts the receive oscillator and presets the INTRCLK (internal clock) to the HIGH state. The oscillator is then restarted at the second Manchester “0” (bit time 4) and is phase locked to it. As a result, the SIA acquires the clock from the incoming Manchester bit stream in four bit times with a “1010” Manchester bit pattern. The 10 MHz INTRCLK and INTPLLCLK are derived from the internal oscillator, which runs at four times the data rate (40.0 MHz). The three clocks generated internally are utilized in the following manner: ■ INTRCLK: After clock acquisition, INTRCLK strobes the incoming data at 1/4 bit time. Receive data path sets the input to the data decode register (Figure 5). ■ INTPLLCLK: At clock acquisition, INTPLLCLK is phase locked to the incoming Manchester clock transition at bit cell center (BCC). The transition at 8 Am7992B BCC is compared to INTPLLCLK and phase correction is applied to maintain INTRCLK at 1/4 bit time in the Manchester cell. ■ INTCARR: From star t to end of a message, INTCARR is active and establishes RENA turn-off synchronously with RCLK rising edge. Internal carrier goes active when there is a negative transition that is more negative than –275 mV and has a pulse width greater or equal to 45 ns. Internal carrier goes inactive typically 155 ns after the last positive transition at Receive±. When TEST is strapped LOW, RCLK and RX are enabled 1/4 bit time after clock acquisition in bit cell 5. RX is at HIGH state when the receiver is idle and TEST is strapped HIGH (no RLCK). RX, however, is undefined when clock is acquired and may remain HIGH or change to LOW state whenever RCLK is enabled. At the 1/4 bit time of clock transition in bit cell 5, RCLK makes its first external transition. It also strobes the incoming fifth bit Manchester “1.” RX may make a transition after the RCLK rising edge in bit cell 5, but its state is still undefined. The Manchester “1” at bit 5 is clocked to RX output at 1/4 bit time in bit cell 6. PLL Tracking After clock acquisition, the INTPLLCLK is compared to the incoming transitions at BCC and the resulting phase error is applied to a correction circuit. This circuit ensures that INTPLLCLK remains locked on the received signal. Individual bit cell phase corrections of the VCO are limited to 10% of the phase difference between BCC and INTPLLCLK. Hence, input data jitter is reduced in RCLK by 10 to 1. Carrier Tracking and End of Message The carrier receiver monitors Receive± input after RENA is asserted for an end of message. INTCARR deasserts typically 155 ns to 165 ns after the incoming message transitions positive. This initiates the end of reception cycle. INTCARR is strobed at 3/4 bit time by the falling edge of INTRCLK. The time delay from the Differential l/O Terminations last rising edge of the message to INTCARR deassert allows the last bit to be strobed by RCLK and transferred by the LANCE without an extra bit at the end of the message. When RENA deasserts (see Receive Timing—End of Reception waveform diagrams), a RENA hold-off timer inhibits RENA assertion for at least 120 ns. The differential input for the Manchester data (Receive±) is externally terminated by two 40.2-ohm ±1% resistors and one optional common-mode bypass capacitor. The differential input impedance, ZlDF and the common-mode input, ZlCM, are specified so that the Ethernet specification for cable termination impedance is met using standard 1% resistor terminators. The Collision± differential inputs are terminated in exactly the same way as the receive inputs (see Figure 6). Data Decoding The data receiver is a comparator with clocked output to minimize noise sensitivity to the Receive± inputs. Input error (VIRD) is less than ±35 mV to minimize sensitivity to input rise and fall time. RCLK strobes the data receiver output at 1/4 bit time to determine the value of the Manchester bit and clocks the data out at RX on the following RCLK. The data receiver also generates the signal used for phase detector comparison to the internal Am7992B VCO. Collision Detection A transceiver detects collisions on the network and generates a 10 MHz signal at the Collision± inputs. This collision signal passes through an input stage that detects signal levels and pulse duration. When the signal is detected by the Am7992B, it sets the CLSN line HIGH. This condition continues for approximately 160 ns after the last LOW-to-HlGH transition on Collision±. VCC C2 R1 20 pF 510 Ω 40.2 Ω 1% C1 680 pF R2 3 KΩ 100 pF 20 MHz Parallel Mode. Crystal 50 pF 0.005% Accuracy 100 pF 1 CLSN Collision+ 24 2 RX Collision– 23 3 RENA Receive+ 22 4 RCLK Receive– 21 5 TSEL TEST 20 6 GND1 VCC1 19 7 GND2 VCC2 18 8 X1 PF 17 9 X2 RF 16 10 TX GND3 15 11 TCLK Transmit+ 14 12 TENA Transmit– 13 40.2 Ω 1% A C4 40.2 Ω 1% 40.2 Ω 1% 0.1 µF B 0.1 µF VCC C5 4.7 µF 4700 pF 0.1 µF 0.1 µF 03378I-10 Notes: 1. Connect R1, R2, C1, C2 for 0 differential nontransmit. Connect to ground for logic 1 differential nontransmit. 2. Pin 20 shown for normal device operation. 3. The inclusion of C4 and C5 is necessary to reduce the common-mode loading on certain transceivers that are direct coupled. 4. C2 reduces the amount of noise from the power supply and crosstalk from RCLK that can be coupled from TSEL through to the transmit ± outputs. Figure 6. External Component Diagram Am7992B 9 Jitter Tolerance Definition and Test The Receive Timing—Start of Reception Clock Acquisition waveform diagram shows the internal timing relationships implemented for decoding Manchester data in the Am7992B. The Am7992B utilizes a clock capture circuit to align its internal data strobe with an incoming bit stream. The clock acquisition circuitry requires four valid bits with the values 1010. Clock is phase locked to the negative transition at BCC of the second “0” in thepattern. Since data is strobed at 1/4 bit time, Manchester transitions that shift from their nominal placement through 1/4 bit time will result in improperly decoded data. For IEEE 802.3/Ethernet, this results in the loss of a message. With this as the criterion for an error, a definition of “jitter handling” is: That peak deviation from nominal input transition approaching or crossing 1/4 bit cell position for which the Am7992B will properly decode data. Four events of signal are needed to adequately test the ability of the Am7992B to decode data properly from the Manchester bit stream. For each of the four events, two time points within a received message are tested (See Input Jitter Timing Waveforms): 1. Jitter tolerance at clock acquisition, the measure of clock capture (case 1–4). 2. Jitter tolerance within a message after the analogue PLL has reduced clock acquisition error to a minimum (case 5–8). The test signals utilized to jitter the input data are artificial in that they may not be realizable on networks (examples are cases 2, 3, and 4 at clock acquisition). However, each pattern relates to setup and hold time measurements for the data decode register (Figure 5). Receive+ and Receive– are driven with the inputs shown to produce the zero crossing distortion at the differential inputs for the applicable test. Cases 4 and 8 require only a single zero to implement when tested at the end of message. Levels used to test jitter are within the common-mode and differential-mode ranges of the receive inputs and also are available from automatic test equipment. It is assumed that the incoming message is asynchronous with the local TCLK frequency for the Am7992B. This ensures that proper clock acquisition has been established with random phase and frequency error in incoming messages. An additional condition placed on the jitter tolerance test is that it must meet all test requirements within 10 ms after power is applied. This forces the Am7992B crystal oscillator to start and lock the analog PLL to within acceptable limits for receiving from a cold start. Case 1 of the test corresponds to the expected Manchester data at clock acquisition, and average values for clock leading jitter tolerance are 21.5 ns. For cases 5 through 8, average values are 24.4 ns. Cases 5 through 8 are jittered at bit times 55 or 56 as applicable. The Am7992B, then, has on average 0.6 ns static phase error for the noise-free case. The four events to test are shown in the Input Jitter Timing Waveform diagram. They are: 1. BCC jitter for a 01-bit pattern 2. BCC jitter for a 10-bit pattern 3. BCB jitter for an 11-bit pattern 4. BCB jitter for an X0-bit pattern 10 Am7992B AMD APPLICATION MAU AUI Cable DTE TAP Am7996 Transceiver ETHERNET Local CPU Local Memory Am7990 LANCE Am7992B SIA Power Supply Local Bus AUI – Attachment Unit Interface DTE – Data Terminal Equipment MAU – Medium Attachment Unit ETHERNET COAX DTE CHEAPERNET Local CPU Local Memory Am7990 LANCE Am7992B SIA Am7996 Transceiver RG58 BNC “T” Power Supply Local Bus 03378I-11 Figure 7. Typical ETHERNET Node Am7992B 11 AMD ABSOLUTE MAXIMUM RATINGS OPERATING RANGES Storage Temperature . . . . . . . . . . . –65°C to +150°C Commercial (C) Devices Ambient Temperature with Power Applied . . . . . . . . . . . . . . . . . . . . 0°C to +70°C Temperature (TC) . . . . . . . . . . . . . . . . . 0°C to +70°C Supply Voltage Continuous . . . . . . . . . . . . . . . +7.0 V DC Voltage Applied to Outputs . . . –0.5 V to VCC Max DC Input Voltage (Logic Inputs) . . . . . . . . . . . +5.5 V Supply Voltage (VCC) . . . . . . . . . . . . . . . +5.0 V ±10% Operating ranges define those limits between which the functionality of the device is guaranteed. DC Input Voltage (Receive±/Collision±) . . . . . . . . . . . . . –6 V to +16 V Transmit± Output Current . . . . . . –50 mA to +25 mA DC Output Current, Into Outputs . . . . . . . . . . 100 mA DC Input Current (Logic Inputs) . . . . . . . . . . ±30 mA Transmit± Applied Voltage . . . . . . . . . . 0 V to +16 V Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. Programming conditions may differ. 12 Am7992B AMD DC CHARACTERISTICS over operating ranges unless otherwise specified Parameter Description Test Conditions Com’l Min Max VOH Output HIGH Voltage RX, RENA, CLSN, TCLK, RCLK IOH = –1.0 mA, VCC = Min 2.4 VOL Output LOW Voltage IOL = 16 mA, VCC = Min Parameter Symbol VOD RCLK, TSEL, TCLK, RENA, RX, CLSN IOL = 1 mA, VCC = Min Differential Output Voltage TX+ > TX– for VO RL = 78 Ω Unit V 0.5 V 0.4 V 550 770 mV –550 –770 mV VOD OFF Transmit Differential Output Idle Voltage VCC = Min, RL = 78 Ω (Note 1) –20 20 mV IOD OFF Transmit Differential Output Idle Current TSEL = HIGH (Note 2) –0.5 0.5 mA VCMT Transmit Output Common-Mode Voltage RL = 78 Ω, VCC = Min 0 5 V VODI Transmit Differential Output Voltage Imbalance ||VO| – |VO|| 20 mV (Transmit+) – (Transmit–) TX+ < TX– for VO (Note 1) VIH Input HIGH Voltage TX, TENA IIH Input HIGH Current TX, TENA, TEST VIL Input LOW Current TX, TENA IIL Input LOW Current TX, TENA, TEST VCC = Max, VIN = 0.4 V Differential Input Threshold (Receive Data) VCM = 0 V, (Note 4) VIRD 2.0 VCC = Max, VIN = 2.7 V V +50 µA 0.8 V –400 µA Ceramic Package –35 +35 mV Plastic Package –65 +65 mV VIRVD Differential Mode Input Voltage Range (Receive ±/Collision ±) (Note 3) –1.5 +1.5 V VIRVC Receive ± and Collision ± Common Mode Voltage (Note 2) 0 5.5 V VIDC Differential Input Threshold to Detect Carrier VCM = 0 V (Note 4) –175 –275 mV ICC Power Supply Current VCC = Max (Note 5) 180 mA VIB Input Breakdown Voltage (TX, TENA, TEST) II = 1 mA, VCC = Max VIC 5.5 V Input Clamp Voltage IIN = –18 mA, VCC = Min –1.2 V VODP Undershoot Voltage on Transmit Return to Zero (End of Message) (Note 3) –100 mV ISC Short Circuit Current RCLK, RX, TCLK, CLSN, RENA VCC = Max (Note 6) –150 mA RIDF Differential Input Resistance VCC = 0 to Max (Note 3) 6 RICM Common Mode Input Resistance VCC = 0 to Max (Note 3) 1.5 VICM Receive and Collision Input Bias Voltage IIN = 0, VCC = Max 1.5 IILD Receive and Collision Input LOW Current IIHD –40 kΩ kΩ 4.2 V VIN = –1 V, VCC = Max –1.64 mA Receive and Collision Input HIGH Current VIN = 6 V, VCC = Min +1.10 mA IIHZ Receive and Collision Input HIGH Current Power Off VCC = 0, VIN = +6 V 1.86 mA IIHX Oscillator (X1) Input HIGH Current VIN = 2.4 V, VCC = Max +800 µA IILX Oscillator (X1) Input LOW Current VIN = 0.4 V, VCC = Max –1.2 mA VIHX Oscillator (X1) Input HIGH Voltage (Note 3) VILX Oscillator (X1) Input LOW Voltage (Note 3) 2.0 V 0.8 V Note: See notes following Switching Characteristics table. Am7992B 13 AMD SWITCHING CHARACTERISTICS over operating ranges unless otherwise specified No. Parameters Description Test Conditions Min Max Unit 118 ns Receiver Specification 1 tRCT RCLK Cycle Time 85 2 tRCH RCLK HIGH Time 38 ns 3 tRCL RCLK LOW Time 38 ns 4 tRCR RCLK Rise Time 8 ns 5 tRCF RCLK Fall Time 8 ns 6 tRDR RX Rise Time 8 ns 7 tRDF RX Fall Time 8 ns 8 tRDH RX Hold Time (RCLK ↑ to RX Change) (Note 8) 5 ns 9 tRDS RX Prop Delay (RCLK ↑ to RX Stable) 25 ns 10 tDPH RENA Turn-On Delay (VIDC Max on Receive ± to RENAH) 80 ns 11 tDPO RENA Turn-On Delay (VIDC Min on Receive ± to RENAL) (Note 9) 300 ns 12 tDPL RENA LOW Time (Note 10) 13 tRPWR Receive ± Input Pulse Width to Reject (|Input| > |VIDC Max|) 14 tRPWO Receive ± Input Pulse Width to Turn-On (|Input| > |VIDC Max|) 15 tRLT 16 tREDH RENA Hold Time (RCLK ↑ to RENAL) 17 tRPWN 120 ns 20 (Note 4) 45 Decoder Acquisition Time ns ns 450 ns 80 ns Receive ± Input Pulse Width to Not Turn-Off INTCARR 165 ns 10 ns 40 Collision Specification 14 18 tCPWR Collision ± Input Pulse Width to Not Turn-On CLSN (|Input| > |VIDC Min|) 19 tCPWO Collision ± Input Pulse Width to Turn-On CLSN (|Input| > |VIDC Max|) 26 ns 160 ns (Note 4) 20 tCPWE Collision ± Input Pulse Width to Turn-Off CLSN (|Input| > |VIDC Max|) 21 tCPWN Collision ± Input Pulse Width to Not Turn-Off CLSN (|Input| < |VIDC Max|) 80 ns 22 tCPH CLSN Turn-On Delay (VIDC Max on Collision ± to CLSNH) 50 ns 23 tCPO CLSN Turn-Off Delay (VIDC Max on Collision ± to CLSNL) 160 ns Am7992B AMD SWITCHING CHARACTERISTICS (continued) No. Parameters Description Test Conditions Min Max Unit (Note 11) 45 ns 45 ns Transmitter Specification 24 tTCL TCLK LOW Time 25 tTCH TCLK HIGH Time 26 tTCR TCLK Rise Time 27 tTCF TCLK Rise Time 28 tTDS, tTES TX and TENA Setup Time to TCLK 29 tTDH, tTEH TX and TENA Hold Time to TCLK 30 tTOCE 31 tOD TCLK HIGH to Transmit ± Output 32 tTOR Transmit ± Output Rise Time 33 tTOF Transmit ± Output Fall Time 34 tXTCH X1 to TCLK Propagation Delay for HIGH 35 tXTCL X1 to TCLK Propagation Delay for LOW 36 tEJ1 Clock Acquisition Jitter Tolerance VCC = 5.0 V (Note 1) 37 tEJ51 Jitter Tolerance After 50 Bit Times VCC = 5.0 V (Note 1) 19 (Note 1) Transmit ± Output, (Bit Cell Center to Edge) 8 ns 8 ns 5 ns 5 ns 49.5 50.5 ns 100 ns 4 ns 4 ns 18 ns 5 18 ns 16 21.5 ns 24.4 ns 20% – 80% 5 (Notes 7 & 12) *Min = 4.5 V, Max = 5.5 V, TOSC = 50 ns; in production test, all differential input test conditions are done single-ended, non-VIRD levels are forces on DUT for waveform swing (levels chosen are due to tester limitations) and a distortion-free preamble is applied to Receive± inputs. Notes: 1. Tested but to values in excess of limits. Test accuracy not sufficient to allow screening guardbands. 2. Correlated to other tested parameter: IOD OFF = VOD OFF/RL. 3. Not tested. 4. Test done by monitoring output functionally. 5. Receive, Collision and Transmit functions are inactive: X1 driven by 20 MHz. 6. Not more than one output should be shorted at a time. Duration of the short circuit test should not exceed one second. 7. TCLK changes state on X1 rising edge, but initial state of TCLK is not defined. When TENA is High, TX data is Manchester encoded on the falling edge of X1 after the rising edge of TCLK. 8. Assumes 50 pF capacitance loading on RCLK and RX. 9. Test is done only for last BIT = 1, which is worst case. 10. Test done from 0.8 V of falling to 2.0 V of rising edge. 11. Test correlated to TTCH. 12. Measured from 50% point of X1 driving the input in production test. Am7992B 15 AMD KEY TO SWITCHING WAVEFORMS WAVEFORM INPUTS OUTPUTS Must be Steady Will be Steady May Change from H to L Will be Changing from H to L May Change from L to H Will be Changing from L to H Don’t Care, Any Change Permitted Changing, State Unknown Does Not Apply Center Line is HighImpedance “Off” State KS000010 16 Am7992B AMD SWITCHING WAVEFORMS Bit Cell 1 1 Receive± (Measured Differentially) Bit Cell 2 0 Bit Cell 3 1 Bit Cell 4 0 Bit Cell 5 1 (Note A) (Note E) BCC 1 BCB BCC 0 BCB BCC 1 BCB BCC 0 BCB BCC 1 BCB INTCARR 10 RENA (Note D) VCO Enable VCO (Note B) INTRCLK RCK Enable RCLK 15 (Note C) RX (Note F) INTPLLCLK 03378I-12 Notes: A. Minimum Width > 45 ns. B. RCLK = INTRCLK when TEST LOW. C. RX undefined until bit time 5 (1st decoded bit). D. Oscillator Interrupt may occur at 2nd INTRCLK after Bit 2 Clock Transition. E. Timing Diagram does not include Internal Propagation Delays. F. First valid data at RX (Bit 5). Receive Timing – Start of Reception Clock Acquisition Am7992B 17 AMD SWITCHING WAVEFORMS Receive+ (Measured Differentially) 1 0 Bit (N – 1) Bit N (Note B) BCC BCB BCC BCB (Note A) INTCARR 11 12 RENA 17 VCO Enable VCO INTRCLK RCK Enable RCLK RX Bit (N – 1) Bit N PLL CLK 03378I-13 Notes: A. INTCARR deasserts 1.55 bit times after last Receive± Rising Edge. B. Start of Next Packet. Receive Timing – End of Reception (Last Bit = 0) 18 Am7992B AMD SWITCHING WAVEFORMS Receive± (Measured Differentially) 0 Bit (N – 1) BCC 1 Bit N BCB BCC INTCARR (Note A) 17 VCO Enable VCO INTRCLK RCK Enable RCLK RX Bit (N – 1) Bit N 16 RENA 11 PLL CLK Note: A. INTCARR deasserts 1.55 bit times after last Receive± Rising Edge. 03378I-14 Receive Timing – End of Reception (Last Bit = 1) Am7992B 19 AMD SWITCHING WAVEFORMS (Note A) X1 TCLK TENA TX TSEL (Note B) VH Transmit+ (Note C) VL VH Transmit– (Note C) Transmit± (Measured Differentially) VL 1 (Note B) 0 1 31 03378I-15 Notes: A. X1 20 MHz Sine Wave from Crystal Oscillator or driven with X1 driven from External Source Waveform. B. TSEL connected as shown in Figure 2B. For Figure 2A, Transmit+ is HIGH when TENA is LOW. C. When Idle Transmit ± Zero Differential is 1/2 (VH + VL). Transmit Timing – Start of Packet 20 Am7992B AMD SWITCHING WAVEFORMS X1 TCLK TENA 29 TSEL CASE 1 TX (Last Bit = 0) Transmit+ Transmit– 0.5 VO at 2 µs VO 30 Transmit± (Measured Differentially) 30 VO Bit (N – 2) BCC Bit (N – 1) BCB BCC Bit N BCB BCC BCB CASE 2 TX (Last Bit = 1) Transmit+ Transmit– 0.5 VO at 2 µs VO Transmit± (Measured Differentially) VO 03378I-16 Transmit Timing – End of Transmission* *TSEL Components (see Figure 2B). See Typical Performance Curve for Response at End of Transmission with Inductive Loads. Am7992B 21 AMD SWITCHING WAVEFORMS Collision Presence± + 0V VIDC Max – VIDC Max 22 CLSN 23 2.0 V .8 V 03378I-17 Collision Timing X1 TCLK 2V 2V TENA 31 80% 80% Transmit± (Measured Differentially) 50% 20% 33 20% 32 03378I-18 Transmit Timing (at start of packet) 22 Am7992B AMD SWITCHING WAVEFORMS Receive± (Measured Differentially) +1.5 V VIRVD VIDC Min (–175 mV) 0V 0V 0V VIDC Max (–275 mV) VIRVD 14 –1.5 V 17 13 10 2.0 V RENA 03378I-19 Receive± Input Pulse Width Timing Collision± (Measured Differentially) +1.5 V VIRVD VIDC Min (–175 mV) VIDC Max (–275 mV) 0V 0V 0V VIRVD 19 –1.5 V 20 21 18 22 2.0 V CLSN 03378I-20 Collision± Input Pulse Width Timing 1 2 3 4 0.2 V RCLK 0.8 V 9 8 5 2.0 V RX 0.8 V 6 7 8 03378I-21 RCLK and RX Timing Am7992B 23 AMD SWITCHING WAVEFORMS 25 TCLK 24 2.0 V 0.8 V 0.8 V 26 27 28 29 2.0 0.8 TX 0.8 V 2.0 0.8 28 2.0 V 0.8 V TENA 03378I-22 TCLK and TX Timing TOSC X1 Driving Input 2.0 1.5 1.5 1.5 1.5 0.8 tHIGH* tLOW* tR* tF* 2.0 TCLK 0.8 35 34 ‘A’ Transmit+, Transmit– (Note A) ‘B’ 0V BCC (Bit Cell Center) BCB (Bit Cell Boundary) Note: A. Encode Manchester clock transition (BCC) at Point ‘A’ and bit cell edge (BCB) at point ‘B’. *See Specification for External TTL Level in Functional Description section. X1 Driven from External Source 24 Am7992B 03378I-23 AMD SWITCHING WAVEFORMS 1 Bit Number 2 3 4 BCB INTRCLK BCC BCC BCC BCC 5 6 7 8 55 56 57 58 BCC BCC BCC BCC PLL CLK 1/4 Bit Cell 4.5 V Receive+ Receive– (Note A) Receive± 1.5 V 3V 0V 0 +4.5 V 1.5 V 0 –1.5 V 4.5 V Strobe RX tEJI tEJ51 A RX BCB +3 V Receive+ 0 +4.5 V Receive– (Note B) Receive± +1.5 V +1.5 V 0 –1.5 V –4.5 V tEJI tEJ51 B RX Strobe RX BCB Receive+ Receive– (Note C) Receive± +3 V 0 +4.5 V +1.5 V +1.5 V 0 –1.5 V tEJI tEJ51 C RX Strobe RX Receive+ +4.5 V +1.5 V +3 V Receive– 0 Receive± +1.5 V 0 –1.5 V (Note D) tEJI tEJ51 D RX 1/4 Bit Cell Strobe RX Notes: A. Case 1, 5 Data Bit Pattern 0, 1 Rising clock edge moved toward 1/4 bit cell RCLK data strobe. Case 1 uses bit 5, Case 5 uses bit 55. 03378I-24 B. Case 2, 6 Data Bit Pattern 1, 0 Falling clock edge moved toward 1/4 bit cell RCLK data strobe. Case 2 uses bit 6, Case 6 uses bit 56. C. Case 3, 7 Data Bit Pattern 1, 1 Falling bit cell edge moved toward 1/4 bit cell RCLK data strobe. Case 3 uses bit 6, Case 7 uses bit 56. D. Case 4, 8 Data Bit Pattern X, 0 Rising bit cell edge moved toward 1/4 bit cell RCLK data strobe. Case 4 uses bit 5, Case 8 uses bit 55. Input Jitter Timing Am7992B 25 AMD TYPICAL PERFORMANCE CURVE 600 R = 78 Ω* 500 R = 78 Ω 3 L = 95 µH 400 Differential Output Voltage (VO) 300 (mV) R = 78 Ω 2 L = 75 µH 200 R = 78 Ω 1 L = 60 µH 100 0 –100 1.0 2.0 3.0 4.0 5.0 Time (µs) 6.0 03378I-25 End of Transmission – Differential Output Voltage* *Equivalent Load: L R Notes: 60 µH 1. 802.3 Test Load: L Test R Test Am7992B 75 µH NOM. 2. 802.3 10BASE5 Network Connection: Am7996 75 µH NOM. AUI Am7992B 80.4 VO Am7996 95 µH 3. 802.3 10BASE2 Network Connection: 80.4 VO 03378I-26 26 Am7992B AMD SWITCHING TEST CIRCUITS Transmit+ DUT RL = 78 Ω DUT 50 pF Transmit– 03378I-27 03378I-28 A. Test Load for RX, RENA, RCLK, TCLK, CLSN B. Transmit± Output + DUT – DC Voltage 03378I-29 C. Receive± and Collision± Input Am7992B 27