PRELIMINARY
Am79C988A
Quad Integrated Ethernet Transceiver (QuIET™)
DISTINCTIVE CHARACTERISTICS
■ Four independent 10BASE-T transceivers
compliant with IEEE 802.3 Section 14
(10BASE-T MAUs)
■ Direct interface with AMD's Am79C983A IMR2™
repeater device
■ On-chip filtering
— Eliminates external transmit and receive filters
— Meets IEEE 802.3 (Section 14.3) electrical
requirements
— Enables port switching when used with the IMR2
device
■ Automatic polarity detection and correction
■ Serial management interface allows transfer of
command and status data between the QuIET
device and a controller (IMR2 or other device)
■ Standard Ethernet (Normal) and Full-Duplex
modes
■ Extended distance option to accommodate
lines longer than 100 meters
■ Test functions provided for Loopback, Link Test,
Reverse Polarity, and Jabber
■ 44-pin PLCC CMOS device with a single 5-V
supply
GENERAL DESCRIPTION
The Am79C988A Quad Integrated Ethernet Transceiver
(QuIET) device consists of four independent 10BASE-T
transceivers which are compliant with the IEEE 802.3
Section 14 (Medium Attachment Unit for 10BASE-T
Cabling) standard. When combined with AMD's
Integrated Multiport Repeater 2 (IMR2™) chip, the
QuIET device provides a system-level solution to
designing a managed 10BASE-T repeater.
The QuIET device interfaces directly with the Pseudo
AUI (PAUI™) ports on the IMR2 (Am79C983A) device
and can also be connected to standard AUI ports. Command and status data are exchanged with the IMR2
device via a serial management interface. Port switching can be easily implemented with the IMR2/QuIET
chipset to move individual ports between multiple Ethernet segments under software control.
The QuIET device includes on-chip filtering for both
transmit and receive functions, thus eliminating the
need for external filters. On-chip filtering meets IEEE
802.3 (Section 14.3) electrical requirements. The
QuIET device provides automatic polarity detection and
correction and can operate in either normal or fullduplex mode.
For application examples on building fully-managed
repeaters using the QuIET and IMR2 devices, refer to
AMD’s IMR2 Technical Manual (PID 19898A).
The QuIET chip is packaged in a 44-pin plastic leaded
chip carrier (PLCC). The device is fabricated in CMOS
technology and requires a single 5-V supply.
This document contains information on a product under development at Advanced Micro Devices. The information
is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed
product without notice.
Publication# 19880 Rev: B Amendment/+2
Issue Date: November 1997
P R E L I M I N A R Y
BLOCK DIAGRAM
QuIET Device
PDO[0]
PDI[0]
PCI[0]
PDO Squelch
Line Driver and
Wave-Shaping
PAUI Port
Line Drivers
and Receivers
TXD+
TXD[0]+
TXD-
TXD[0]-
Line Receiver and RXD+
Smart Squelch RXDPDO[1]
PDI[1]
PCI[1]
PDO Squelch
PAUI Port
Line Drivers
and Receivers
Line Driver and
Wave-Shaping
TXD+
TXD[1]+
TXD-
TXD[1]-
Line Receiver and RXD+
Smart Squelch RXDPDO[2]
PDI[2]
PCI[2]
PCI[3]
Line Driver and
Wave-Shaping
TXD+
TXD[2]+
TXD-
TXD[2]-
Line Receiver and RXD+
Smart Squelch RXD-
PDO Squelch
PAUI Port
Line Drivers
and Receivers
Line Driver and
Wave-Shaping
RXD[2]+
RXD[2]-
TXD+
TXD[3]+
TXD-
TXD[3]-
Line Receiver and RXD+
Smart Squelch RXD-
REXT
RXD[1]+
RXD[1]-
PDO Squelch
PAUI Port
Line Drivers
and Receivers
PDO[3]
PDI[3]
RXD[0]+
RXD[0]-
RXD[3]+
RXD[3]-
Internal Bias Reference
and Phase-Lock Loop
SDATA
DIR
CLK
Serial Management Port
Control and Status
Collision, Loopback,
Jabber and Link Test
RST
19880B-1
2
Am79C988A
P R E L I M I N A R Y
RELATED AMD PRODUCTS
Part No.
Description
Am79C981
Integrated Multiport Repeater+ (IMR+™)
Am79C982
basic Integrated Multiport Repeater (bIMR™)
Am79C983A
Integrated Multiport Repeater 2 (IMR2™)
Am79C987
Hardware Implemented Management Information Base (HIMIB™)
Am7990
Local Area Network Controller for Ethernet (LANCE)
Am7996
IEEE 802.3/Ethernet/Cheapernet Transceiver
Am79C90
CMOS Local Area Network Controller for Ethernet (C-LANCE)
Am79C98
Twisted Pair Ethernet Transceiver (TPEX)
Am79C100
Twisted Pair Ethernet Transceiver Plus (TPEX+)
Am79C900
Integrated Local Area Communications Controller (ILACC™)
Am79C940
Media Access Controller for Ethernet (MACE™)
Am79C960
PCnet™-ISA Single-Chip Ethernet Controller (for ISA bus)
Am79C961
PCnet™-ISA+ Single-Chip Ethernet Controller for ISA (with Microsoft® Plug n’ Play® Support)
Am79C961A
PCnet™-ISA II Full Duplex Single-Chip Ethernet Controller for ISA
Am79C965
PCnet™-32 Single-Chip 32-Bit Ethernet Controller
Am79C970
PCnet™-PCI Single-Chip Ethernet Controller (for PCI bus)
Am79C970A
PCnet™-PCI II Full Duplex Single-Chip Ethernet Controller (for PCI bus)
Am79C974
PCnet™-SCSI Combination Ethernet and SCSI Controller for PCI Systems
Am79C988A
3
P R E L I M I N A R Y
RXD0-
1 44 43 42 41 40
AVSS
2
RXD0+
AVDD
RXD1+
3
RXD1-
RXD2+
5 4
RXD2-
RXD3-
6
AVSS
RXD3+
CONNECTION DIAGRAM
DVSS
7
39
DVSS
PCI3
8
38
RST
PDI3
9
37
REXT
PDO3
10
36
TEST
PCI2
11
35
DIR
34
CLK
33
SDATA
PDI2
12
PDO2
13
Am79C988A
PCI1
14
32
DVDD
PDI1
15
31
TXD3+
PDO1
16
30
TXD3-
PCI0
17
29
AVSS
TXD2+
AVDD
TXD2-
TXD1+
TXD1-
AVSS
TXD0-
TXD0+
AVDD
PDO0
PDI0
18 19 20 21 22 23 24 25 26 27 28
19880B-2
4
Am79C988A
P R E L I M I N A R Y
LOGIC DIAGRAM
Ports
PAUI
TP
PAUI
TP
PAUI
TP
PAUI
TP
Serial
Interface
19880B-3
LOGIC SYMBOL
DVDD
Pseudo Attachment
Unit Interface
(PAUI) Ports
(4 Ports)
AVDD
PDO
PDI
TXD+
TXD-
PCI
RXD+
RXD-
Twisted
Pair Ports
(4 Ports)
Am79C988A
SDATA
DIR
Serial
Management
Interface
CLK
RST
DVSS
AVSS
19880B-4
Am79C988A
5
P R E L I M I N A R Y
ORDERING INFORMATION
Standard Products
AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed
by a combination of:
Am79C988B
J
C
OPTIONAL PROCESSING
Blank = Standard processing
TEMPERATURE RANGE
C = Commercial (0˚C to +70˚C)
PACKAGE TYPE
J = 44-pin Plastic Leaded chip carrier
(PL 044)
SPEED OPTION
Not applicable
DEVICE NUMBER/DESCRIPTION
Am79C988B
Quad Integrated Ethernet
Transceiver (QuIET™)
Valid Combinations
Valid Combinations
Am79C988B
6
JC\T
Valid Combinations table list configurations planned to be
supported in volume for this device. Consult the local AMD
sales office to confirm availability of specific valid combinations and to check on newly released combinations.
Am79C988A
P R E L I M I N A R Y
PIN DESCRIPTION
Analog
Digital
PDO0-3
Pseudo AUI Data Output
Input
Single-ended receiver. Data input from the IMR2 device.
SDATA
Serial Data
Input/Output
Transfers command and status data between the
QuIET device and the IMR2 chip.
DIR
Direction
Input
PDI0-3
Pseudo AUI Data Input
Output
Single-ended output driver. Data output to the
IMR2 device.
PCI0-3
Pseudo AUI Collision Input
Output
Single-ended output driver. Collision output to the
IMR2 device.
TXD+0-3, TXD-0-3
Transmit Data
Output
10BASE-T port differential drivers.
RXD+0-3, RXD-0-3
Receive Data
Input
10BASE-T port differential receivers.
Selects the direction of command data and status data
transfer between the QuIET device and the IMR2 chip.
RST
Reset
Input, Active Low
Resets the internal registers of the QuIET device.
CLK
Clock
Input
20-Mhz clock signal. The clock signal should be the
same one that is used by all IMR2 devices connected
to the QuIET chip.
TEST
Input, Active High
Reserved for factory use only. This pin does have an
internal pull-down, but should be tied LOW for
normal operation.
REXT
External Resistor
Input
REXT must be tied to AVDD through a 13 kΩ ±1%
resistor.This provides the current reference for all internal analog functions.
AVDD
DVDD
Digital Power
Power Pin
These pins supply +5-V power to the digital portion of
the device. These pins should be decoupled and kept
separate from the analog power plane.
Analog Power
Power Pin
These pins supply +5-V power to the analog portion of
the device. These pins should be decoupled and kept
separate from the digital power plane.
DVSS
Digital Ground
Ground Pin
These pins provide the ground reference for the digital
portions of the QuIET circuitry.
AVSS
Analog Ground
Ground Pin
Note: All digital I/O pins are CMOS and TTL compatible.
These pins provide the ground reference for the analog
portions of the QuIET circuitry.
Am79C988A
7
P R E L I M I N A R Y
FUNCTIONAL DESCRIPTION
Overview
in IEEE 802.3, Section 14.3.1.3. Proper termination is
shown in Figure 2. Each receiver has internal filtering and
does not require external filter modules.
The Am79C988A Quad Integrated Ethernet Transceiver
(QuIET™) device consists of four independent 10BASE-T
transceivers which are compliant with the IEEE 802.3 Section 14 (Medium Attachment Unit for 10BASE-T Cabling)
standard. The QuIET device includes on-chip filtering for
both transmit and receive functions, thus eliminating the
need for external filters. It provides automatic polarity
detection and correction and can operate in either normal
or full-duplex mode.
The QuIET device interfaces directly with the Pseudo
AUI (PAUI™) ports on the IMR2 (Am79C983A) device.
PAUI ports are functionally equivalent to the AUI interface as described in IEEE 802.3 Section 7, but are
single-ended and do not have the drive capability
specified in the standard. The QuIET device can also
be connected to standard AUI ports. Command and
status data is exchanged with the IMR2 device via a
serial management interface.
Twisted Pair Transmitters
Each TXD port is a differential twisted pair driver. When
properly terminated, TXD meets the 10BASE-T transmitter electrical requirements as specified in IEEE 802.3
Section 14.3.1.2. Proper termination, Figure 1, consists
of a single 110 ohm +1% resistor across TXD+ and TXDand a 1:1 standard Ethernet transformer. A common
mode may be required for EMI considerations. An external capacitor is not required. The load is a twisted
pair cable that meets IEEE 802.3, Section 14.4 requirements. The cable is terminated at the other end by a
100 ohm load.
The TXD signal is filtered on the chip to reduce harmonic
content per IEEE 802.3 Section 14.3.2.1 (10BASE-T).
Since filtering is performed by the QuIET device, the
TXD signal can be connected directly to a standard
transformer. External filter modules are not required.
RXD+
1:1
100 Ω
Twisted Pair
100 Ω
RXD-
19880B-6
Figure 2. RXD Termination
Receive squelch threshold voltage can be programmed
for extended distance mode. In this mode, the differential
receive threshold is reduced to allow cable lengths greater
than the 100 meters specified in the IEEE 802.3 Standard.
Polarity Detection and Reversal
The receive function includes the ability to invert the polarity of the signals appearing at the RXD+ pair if the
polarity of the received signal is reversed (such as in the
case of a wiring error). The polarity detection function is
activated following Reset or Link Fail, and will reverse the
receive polarity based on both the polarity of any previous
Link Test Pulses and the polarity of subsequent packets
with a valid End Transmit Delimiter (ETD).
When in the Link Fail State, the QuIET device will recognize Link Test Pulses of either positive or negative polarity. Exit from the Link Fail state is caused by the reception
of five-to-seven consecutive Link Test Pulses of identical
polarity. Both Link Test Pulses and packets are used to
determine the initial receive polarity. Once correct polarity
is established, the receiver subsequently accepts only
Link Test Pulses that are recognized as TRUE rather than
inverted.
The Link Test pulse follows the template of Figure
14-12 of the IEEE 802.3 10BASE-T standard.
Link Test Function
1:1
TXD+
110 Ω
TXD-
Twisted Pair
100 Ω
19880B-5
Figure 1. TXD Termination
Twisted Pair Receivers
Each RXD port is a differential twisted-pair receiver.
When properly terminated, RXD ports will meet the electrical requirements for 10BASE-T receivers as specified
8
The Link Test function is implemented as specified in
the IEEE 802.3 10BASE-T standard. A Link Test pulse
is transmitted if a port has been idle for a period of more
than approximately 16 (+/-8) milliseconds (ms).
The QuIET device monitors the 10BASE-T ports for
packet and Link Pulse activity. If neither a packet nor a
Link Test pulse is received for 79 ms to 102 ms, the port
will enter the Link Test Fail State and the QuIET device
will inhibit the transmit and receive functions for that
port. Link pulses are transmitted when idle conditions
are met. When a packet or five-to-seven consecutive
Link Test pulses is received, the port exits the Link Fail
State and transmit/receive functions are restored.
Am79C988A
P R E L I M I N A R Y
PAUI Ports
Note: The IMR2 device only supports Normal operation.
The PAUI ports are functionally equivalent to AUI ports
as described in IEEE 802.3, Section 7. However, they
are single ended and, therefore, are not an exact match
with the electrical specifications.
Full-Duplex Mode
PDO, PDI, and PCI are functionally similar to DO, DI,
and CI, respectively. PDO is the PAUI input from the
IMR2 device. This signal is transmitted by the corresponding TXD port. PDI is the data output to the IMR2
device and is the data received by the corresponding
RXD port. PDI also loops back data received by PDO
to the IMR2 device. PCI is the collision output to the
IMR2 device and indicates either a collision on the corresponding port or an excessive continuous data stream
on the corresponding PDO. PCI sends a 10-MHz square
wave during collision and jabber.
Collision Handling
Collision is defined for the QuIET device as data being
simultaneously transmitted and received at the corresponding TXD and RXD pins. When a collision is detected, the QuIET device sends a 10 MHz signal over
the corresponding PCI pin. This is the only action taken
by the QuIET device. The generation of the JAM signal
is performed by the IMR2 device.
Jabber Protection
The Jabber function inhibits the twisted pair transmit
function of the port if the PDO circuit is active for an
excessive period (> 30 ms). If the maximum transmit
time is exceeded, the transmitter circuitry is disabled,
PDO to PDI loopback is disabled, and a 10 MHz signal
is transmitted by PCI. Once the data stream is removed
from PDO, 350 ms will elapse before PCI stops transmitting the 10 MHz signal and the TXD circuitry is enabled again. Note that a properly functioning repeater
device will never jabber because of the MAU Jabber
Lockup Protection (MJLP).
Transceiver Modes
In Full-Duplex mode a port can transmit and receive simultaneously, and Collision and PAUI Loopback functions are
disabled. The normal loopback of PDO to PDI is disabled
to allow the RXD signal to be transmitted on PDI.
PCI is disabled and Jabber status is only available to
the controller through the serial management interface.
The serial management interface also transmits Jabber
status when the QuIET device is in Normal mode.
Serial Management Interface
Command and status data are transferred between the
QuIET device and the IMR2 device via SDATA. (See
Figure 4 for proper interconnections.) The direction of
SDATA is set by DIR. All activity on SDATA starts at the
edge (rising or falling) of DIR.
The DIR pin of the QuIET device connects to DIR[1] of
the IMR2 device. The IMR2 device continually cycles
DIR[1] LOW and HIGH. LOW is status reporting (SDATA
Write) and HIGH is management commands (SDATA
Read). The controller (IMR2 device) should keep DIR
at one level for the entire bit stream. The status bit
stream is described in the Status Reporting section, and
the command bit stream is described in the Management Commands section. Each bit on SDATA is held for
2-bit times (200 ns).
Status Reporting
When DIR switches from HIGH to LOW, the QuIET device drives SDATA with status information (left to right)
in the format shown below. After the 29th bit, the SDATA
driver turns off. The SDATA driver also turns off if DIR
switches HIGH before the 29th bit.
Status Information Format
01010A0A1A2A3B0B1B2B3C0C1C2C3D0D1D2D3SSSSSSSS
01010
The QuIET transceivers have two modes of operation:
Normal and Full Duplex. In Normal mode, the data flows
only in one direction at a time. In Full-Duplex mode, the
collision circuitry and the loopback circuitry are disabled. Therefore, transmit and receive can occur simultaneously. The transceiver mode is selected through the
serial management interface, which is explained further
in the Management Commands and Transceiver Mode
Selection sections.
An
Preamble
QuIET device ID (0000 for QuIET device)
Bn
0 Link Fail
Cn
1 Link Pass
0 Received Polarity Reversed
Dn
1 Received Polarity Correct
0 No Jabber
S
1 Jabber
Not used, logic HIGH
Normal Mode
Preamble
The QuIET device defaults to the Normal mode at power
up and reset. In this mode, no twisted pair port can
transmit and receive data simultaneously. If a port receives data when it is transmitting, the QuIET device
sends a collision signal to the IMR2 device via the corresponding PCI pin.
The 01010 preamble is an indication to the IMR2 that
the transceiver is a QuIET device.
QuIET Device ID
A0A1A2A3
The QuIET device returns 0000.
Am79C988A
9
P R E L I M I N A R Y
Link Status
Extended Distance Option
B0B1B2B3
E0E1E2E3
The QuIET device reports the Link Status of each port.
If Link Test is disabled, Link Status indicates a Link Pass.
This command modifies the RXD circuit of the transceiver to accommodate signal-attenuation lines longer
than 100 meters.
Bn
0
1
Link Fail
Link Pass
En
Receive Polarity Status
0 Disable Extended Distance Option
1 Enable Extended Distance Option
Link Test Enable
C0C1C2C3
The QuIET device reports the polarity status of each port.
F0F1F2F3
Cn
This command enables the corresponding port to perform a Link Test. Link Status will report Link Pass if the
Link Test is disabled.
0
1
Reversed Polarity
True Polarity
Jabber Condition
Fn
D0D1D2D3
The QuIET device reports the Jabber Condition status
for each port. Jabber is defined as continuous transmissions by a port for more than 30 ms.
Dn
0
1
No Jabber
Jabber
Management Commands
When DIR switches from LOW to HIGH, the QuIET device reads the command sequence over SDATA. Each
management command character is held for 2-bit times
(200 ns). The command format is as follows.
Management Command Format
Extended Distance
Link Test
Transmit Link Test Pulses
I
Enable Polarity Correction
0 Enabled
Loopback Test (All Ports)
0 Enabled
Transceiver Mode
1 Disabled
0 Full Duplex
1 Normal (Default
condition - IMR2 only
supports Normal)
K
CMOS/PAUI Mode
0 CMOS Mode
Not used
Disable Link Pulse Transmit
Enable Link Pulse Transmit
Auto Polarity Correction Enable
0
1
Enable Auto Polarity
Disable Auto Polarity
I
0
1
Enable Loopback Test
Disable Loopback Test
Transceiver Mode Selection
This command sets the QuIET device either in Full-Duplex or Normal mode. The default is Normal mode.
Logic HIGH
Note: The QuIET device requires DIR to be high for a
minimum of 29 data bits (one bit is four MCLKs), which
automatically occurs with the IMR2 device. If any other
type of controller is used, DIR must still be high at least
29-bit times. After I, SDATA can be all ones.
10
0
1
J0J1J2J3
1 PAUI Mode
S
Gn
This command enables or disables the loopback test
for the twisted pair ports. When enabled, the signal on
RXD is retransmitted on TXD. The default condition is
loopback test disabled. Note that the TXD drivers have
on-chip filtering, which may cause the TXD output to
be different from the corresponding RXD input during
this test.
1 Disabled
Jn
This command enables the corresponding port to transmit a Link Pulse. The pulse will be transmitted if either
a packet or a pulse has not been transmitted for 16 ms.
Note that Link Pulses are transmitted when ports are in
Link Test Fail.
Loopback Test Enable
0 Disabled
1 Enabled
Hn
G0G1G2G3
Hn
0 Disabled
1 Enabled
Gn
Transmit Link Pulse Enable
This command allows the QuIET device to detect and
correct the polarity of signals at RXD.
0 Disabled
1 Enabled
Fn
Disable Link Test
Enable Link Test
H0H1H2H3
0E0E1E2E3F0F1F2F3G0G1G2G3H0H1H2H3I J0J1J2J3KSSSSSSS
En
0
1
Jn
Am79C988A
0
1
Full Duplex
Normal
P R E L I M I N A R Y
CMOS/PAUI Mode Selection
Command and Status Default Conditions
This command sets the QuIET interface drivers (PDO,
PDI, PCI) to be driven at normal PAUI signal levels or
CMOS voltage levels. The default is PAUI levels. Refer
to the DC Characteristics table for voltage levels.
K
0
1
CMOS Levels
PAUI Levels
Reset Function
The QuIET device enters the reset state when the reset
pin (RST) is held LOW. All ports, status registers, and
command registers are put into their default state. When
powering up the device, the RST pin should be held
LOW for 150 microseconds (µs). At other times, the RST
pin should be held LOW for a minimum of 4 µs. The
default conditions are detailed below.
Command
Extended Distance
Link Test
Link Pulse Transmit
Correct Polarity
Loopback Test
Transceiver Mode Selection
CMOS/PAUI Mode
Status
Device
Link
Polarity
Jabber
Am79C988A
Default
Disabled
Enabled
Enabled
Disabled
Disabled
Normal
PAUI Mode
Default
QuIET
Fail
Correct
No Error
11
P R E L I M I N A R Y
SYSTEMS APPLICATIONS
10BASE-T Repeaters
10BASE-T ports that can be individually switched between three Ethernet collision domains.
The IMR2/QuIET chipset provides a system solution to
designing 10BASE-T repeaters. Figure 3 shows the
necessary connections between the IMR2 device and
the QuIET device. Although only one QuIET device is
shown for clarity, three QuIET devices are required to
build a 12-port 10BASE-T repeater.
The IMR2 and QuIET devices must share a common
ground plane and a common power plane. Failure to
meet this design requirement may result in false assertion of internal carrier sense or inability to unsquelch in
either PDI (for IMR2) or PDO (for QuIET).
Port Switching
The PAUI ports on the QuIET device can also be connected to standard AUI ports when used with devices
other than the IMR2 chip. Connection to a standard AUI
port is not meant to support a full length AUI cable. The
AUI connection should remain on the same board as
shown in Figure 6.
The IMR2/QuIET chipset supports port switching, which
is the ability to move individual ports to any one of multiple Ethernet backplanes under software control. To implement port switching, each port on the QuIET device
is connected to two or more IMR2 devices in parallel.
Each IMR2 device defines a different logical repeater
and constitutes a separate Ethernet collision domain.
For each port on the QuIET device, only one corresponding port on the IMR2 devices is enabled at any
one time.
Figure 4 shows the IMR2 device-to-QuIET device connections necessary for port switching. Note that only
one QuIET device is shown for clarity. A full implementation would use three QuIET devices to provide 12
12
Connection to Standard AUI Port
Connection to CMOS Circuits
The PAUI ports on the QuIET device can also drive
CMOS loads for other devices, including switches. The
PDO, PDI, and PCI signals connect directly to the
CMOS device. Note that CMOS mode must be
selected in the Management Command Frame.
Am79C988A
P R E L I M I N A R Y
IMR2
PDO0
PDI0
PCI0
QuIET
TP Connector
TXD0+
110 Ω
TXD0-
PDO0
PDI0
PCI0
RXD0+
RXD0- 100 Ω
TP Connector
TXD1+
PDO1
PDI1
PCI1
TXD1-
PDO1
PDI1
PCI1
RXD1+
RXD1-
110 Ω
100 Ω
TP Connector
TXD2+
PDO2
PDI2
PCI2
PDO2
PDI2
PCI2
TXD2-
110 Ω
RXD2+
100 Ω
RXD2TP Connector
PDO3
PDI3
PCI3
TXD3+
TXD3- 110 Ω
PDO3
PDI3
PCI3
RXD3+
RXD3-
100 Ω
AVDD
MCLK
RST
REXT
RST
CLK
13K Ω
Typical
19880B-7
Note: Common mode chokes may be required.
Figure 3. IMR2 Device to QuIET Device Connection
Am79C988A
13
P R E L I M I N A R Y
QuIET
SDATA
Device 2
DIR
CLK
IMR2 Device
SDATA[3]
RST
NC
SDATA[2]
QuIET
SDATA
SDATA[1]
SDATA[0]
DIR[1]
Device 1
DIR
CLK
DIR[0]
MCLK
RST
RST
NC
QuIET
SDATA
Reset
CLK
Device 0
DIR
CLK
RST
19880B-8
Figure 4. IMR2 Device To QuIET Device Serial Interface
Backplane 0
Am79C983
IMR2 0
PDO
PDI
PCI
PDO
PDI
PCI
PDO
PDI
PCI
PDO
PDI
PCI
PDO
PDI
PCI
PDO
PDI
PCI
PDO
PDI
PCI
PDO
PDI
PCI
C
SDATA
9
SDATA[0]
DIR[1]
DIR
Backplane 1
TX
A
m
7
9
RX
TX
RX
TX
RX
TX
RX
Port 0
Port 1
Port 2
Port 3
8
8
PDO
PDI
PCI
Am79C983
PDO
PDI
PCI
IMR2 1
PDO
PDI
PCI
PDO
PDI
PCI
Backplane 2
PDO
PDI
PCI
Am79C983
PDO
PDI
PCI
IMR2 2
PDO
PDI
PCI
PDO
PDI
PCI
19880B-9
Figure 5. Port Switching
14
Am79C988A
P R E L I M I N A R Y
0.1 µF
1:1
DO+
PDO
78 Ω
12 KΩ
DO-
0.1 µF
10 KΩ
1:1
AUI
Port
DI+
PDI
200 Ω
10 KΩ
DI-
0.1 µF
1:1
CI+
200 Ω
QuIET
Device
10 KΩ
PCI
10 KΩ
CI-
19880B-10
Figure 6. AUI to PAUI Connections
Am79C988A
15
P R E L I M I N A R Y
ABSOLUTE MAXIMUM RATINGS
OPERATING RANGES
Storage Temperature. . . . . . . . . . . . . –65°C to +150°C
Commercial (C) Devices
Ambient Temperature Under Bias. . . . . . . . . 0 to 70°C
Supply Voltage referenced to
AVSS or DVSS (AVDD, DVDD) . . . . . . . . . . . . . .–0.3 to +6V
Temperature (TA) . . . . . . . . . . . . . . . . . .0°C to + 70° C
Supply Voltages (VDD). . . . . . . . . . . . . . . . . +5 V ±5%
Operating ranges define those limits between which the
functionality of the device is guaranteed.
Stresses above those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent device failure. Functionality
at or above these limits is not implied. Exposure to Absolute
Maximum Ratings for extended periods may affect device reliability. Programming conditions may differ.
DC CHARACTERISTICS over operating ranges unless otherwise specified
Parameter
Symbol
Digital I/O
VIL
VIH
VOL
VOH
IIH
IIL
Parameter Description
Input LOW Voltage
Input HIGH Voltage
Output LOW Voltage
Output HIGH Voltage
Input Leakage Current HIGH (DIR,
SDATA, CLK, RST)
Input Leakage Current LOW (DIR,
SDATA, CLK, TEST)
Input Leakage Current HIGH (TEST)
Input Leakage Current LOW (RST)
IILDH
IILDL
PAUI Ports
VPOH
Output HIGH Voltage
Test Conditions
Min
DVSS = 0.0 V
IOL=4.0 mA
IOH =-0.4 mA
0<VIN<DVDD
-0.5
2.0
2.4
-
0V<VIN<DVDD
-
-10
µA
0<VIN<DVDD
0V<VIN<DVDD
-
500
-500
µA
µA
0.8
DVDD +0.5
0.4
10
Unit
V
V
V
V
µA
PAUI Mode
VDD/2 + 0.45
-
V
VPOL
Output LOW Voltage
PAUI Mode
-
VDD/2 - 0.45
V
VPIH
Input HIGH Voltage
PAUI Mode
VDD/2 + 0.45
-
V
VPIL
Input LOW Voltage
PAUI Mode
-
VDD/2 - 0.45
V
IPILH
Input Leakage Current HIGH
AVDD = MAX
-
10
µA
IPILL
Input Leakage Current LOW
AVDD = MAX
-
-10
VPASQ
PDO Squelch (the value PDO must go to
before internal PDO carrier sense can be
turned on)
Twisted Pair Ports
IIRXD
Input Current at RXD±
RRXD
RXD Differential Input Resistance
VTIVB
RXD±, Open Circuit Input Voltage
(Bias)
VTIDV
Differential Mode Input Voltage Range
(RXD)
VTSQ+
RXD Positive Squelch Threshold
(Peak)
VTSQRXD Negative Squelch Threshold
(Peak)
VTHS+
RXD Post-Squelch Positive Threshold
(Peak)
VTHSRXD Post-Squelch Negative Threshold
(Peak)
16
Max
VDD/2 - 0.400 VDD/2 - 0.175
µA
mV
AVSS<VIN<AVDD
(Note 1)
IIN = 0 mA
-500
10
AVDD-3.0
500
AVDD-1.5
µA
kΩ
V
AVDD = 5.0 V
-3.1
3.1
V
Sinusoid 5 MHz <f< 10 MHz
300
520
mV
Sinusoid 5 MHz <f< 10 MHz
-520
-300
mV
Sinusoid 5 MHz <f< 10 MHz
120
293
mV
Sinusoid 5 MHz <f< 10 MHz
-293
-120
mV
Am79C988A
P R E L I M I N A R Y
Parameter
Symbol
VLTSQ+
Parameter Description
RXD Positive Squelch Threshold Extended Distance Mode
Test Conditions
Sinusoid 5 MHz <f< 10 MHz
Min
180
Max
312
Unit
mV
VLTSQ-
RXD Positive Squelch Threshold Extended Distance Mode
Sinusoid 5 MHz <f< 10 MHz
-312
-180
mV
VLTHS+
RXD Post-Squelch Positive Threshold
Extended Distance Mode
Sinusoid 5 MHz <f< 10 MHz
80
175
mV
VLTHS-
RXD Post-Squelch Negative Threshold
Extended Distance Mode
Sinusoid 5 MHz <f< 10 MHz
-175
-80
mV
VRXDTH
VTXI
RXD Switching Threshold
TXD± Differential Output Voltage Imbalance
TXD± Idle Output Current
(Note 1)
-60
-40
+60
+40
mV
mV
DV DD = 5V
(Note 2)
-2
2
µA
-
380
mA
-
120
mA
ITXOFF
Power Supply Current
IDDTX
Power Supply Current (All 4 ports TransF = 20 MHz VDD = VMAX
mitting Including TXD current)
(Uses Twisted Pair Switching
Test Current)
IDDI
Power Supply Current Idle
F= 20 MHz VDD =VMAX
Note:
1. CMOS Mode on PAUI signals is guaranteed by design and is compatible with normal CMOS levels present on other QuIET
device pins.
Am79C988A
17
P R E L I M I N A R Y
SWITCHING CHARACTERISTICS over operating ranges unless otherwise specified
Parameter
Symbol
Parameter Description
Clock and Reset Timing
tCLK
CLK Clock Period
tCLKH
CLK Clock High
tCLKL
CLK Clock Low
tCLKR
CLK Rise Time
tCLKF
CLK Fall Time
tRST
Reset Pulse Width (RST pin LOW)
tPRST
Reset Pulse Width at Power Up
Transmit Timing
tPWODO
PDO Pulse Width Accept/ Reject Threshold
tPWKDO
PDO Pulse Width Maintain/Turn-Off
Threshold
Test Conditions
Min
Max
Unit
(Note 1)
49.995
20
20
4
150
50.005
30
30
10
10
-
ns
ns
ns
ns
ns
µs
µs
Input > VASQ (Max)
15
35
ns
(Note 3)
Input > VASQ (Max)
110
200
ns
-
300
200
ns
ns
250
8
75
20
250
1.0
450
24
120
150
750
-
ns
ms
ns
ms
ms
µs
-
300
100
ns
ns
(Note 5)
5
35
ns
(Note 6)
136
200
ns
200
-
400
tRON +100
70
ns
ns
ns
(Note 1)
(Note 1)
(Note 1)
200
-
10
10
5
ns
ns
ns
ns
(Note 1)
(Note 1)
87
40
500
500
117
60
ns
ns
ns
ns
10
10
10
10
-
40
ns
ns
ns
ns
ns
(Note 1)
(Note 1)
(Note 4)
tTON
tTSD
Transmit Start-Up Delay
Transmit Static Propagation Delay (PDO
to TXD)
tTETD
Transmit End of Transmission (for TXD)
tPERLP
Idle Signal Period
tPWLP
Link Pulse Width
tJA
Transmit Jabber Activation Time
tJR
Transmit Jabber Reset Time
tJREC
Transmit Jabber Recovery Time (Minimum time gap between packets to prevent
Jabber activation)
tDODION
PDO to PDI Start-up Delay
tDODISD
PDO to PDI Static Propagation Delay
Receive Timing
tPWORD
RXD Pulse Width Accept/Reject
Threshold
tPWKRD
RXD Pulse Width Maintain/Turn-Off
Threshold
tRON
Receiver Start-up Delay (RXD to PDI)
tRVD
First Validly Timed Bits
tRSD
Receiver Static Propagation Delay (RXD
to PDI)
tRETD
PDI End of Transmission
tRR
PDI, PCI Rise Time
tRF
PDI, PCI Fall Time
tRM
PDI, PCI Rise and Fall Time Mismatch (tRR
- tRF)
Collision Timing
tCON
Collision Turn On Delay
tCOFF
Collision Turn Off Delay
tCPER
Collision Period
tCPW
Collision Output Pulse Width
Serial Interface Timing
tSDSU
CLK to DIR Setup Time
tSDHD
DIR Hold Time
tSSSU
CLK to SDATA Setup Time
tSSHD
CLK to SDATA Hold Time
tSSDO
CLK to Output Delay
18
(Note 7)
(Note 1)
(Note 7)
(Note 7)
(Note 1)
(Note 7)
(Note 7)
(Note 7)
(Note 7)
Am79C988A
P R E L I M I N A R Y
Parameter
Symbol
tSSDOZ
tSDS
tDDS
Parameter Description
Clock to High Impedance Output
DIR going HIGH to SDATA Input Valid
DIR going LOW to SDATA Output Valid
Test Conditions
(Note 7)
(Note 7)
Min
-50
100
Max
40
100
150
Unit
ns
ns
ns
Notes:
1. Parameter is not tested.
2. Uses switching test load.
3. PDO pulses narrower than tPWODO (min) will be rejected; PDO pulses wider than tPWODO (max) will turn internal PDO carrier
sense on.
4. PDO pulses narrower than tPWKDO (min) will maintain internal PDO carrier sense on; PDO pulses longer than tPWKDO (max)
will turn internal PDO carrier sense off.
5. RXD pulses narrower than tPWORD (min) will be rejected; RXD pulses longer than tPWORD (max) will turn internal RXD carrier
sense on.
6. RXD pulses narrower than tPWKRD (min) will maintain internal RXD carrier sense; RXD pulses longer than tPWKRD (max) will
turn internal RXD carrier sense off.
7. Parameter tested functionally.
Am79C988A
19
P R E L I M I N A R Y
KEY TO SWITCHING WAVEFORMS
WAVEFORM
INPUTS
OUTPUTS
Must be
Steady
Will be
Steady
May
Change
from H to L
Will be
Changing
from H to L
May
Change
from L to H
Will be
Changing
from L to H
Don’t Care,
Any Change
Permitted
Changing,
State
Unknown
Does Not
Apply
Center
Line is HighImpedance
“Off” State
KS00010
SWITCHING WAVEFORMS
tCLKR
tCLKF
tCLK
tCLKH
tCLKL
19880B-11
Figure 7. Clock (CLK) Timing
RST
tRST
tPRST
19880B-12
Figure 8. Reset Pulse
20
Am79C988A
P R E L I M I N A R Y
SWITCHING WAVEFORMS
tPWODO
tPWKDO
tPWKDO
PDO
tTSD
tTSD
TXD+
tTSD
tTON
tTETD
TXD-
tDODION
tDODISD
PDI
19880B-13
Figure 9. Transmit Signals
tPWORD
tPWKRD
tPWKRD
VTHS+
RXD
VTHStRON
tRR
PDI
tRETD
tRSD
tRF
19880B-14
Figure 10. Receive Signals
PDO
RXD
tCON
tCOFF
PCI
tCPER
tCPW
19880B-15
Figure 11. Collision Signals
Am79C988A
21
P R E L I M I N A R Y
SWITCHING WAVEFORMS
tPWLP
tPERLP
19880B-16
Figure 12. Transmit Link Beat Pulse
50%
0V
PDO
0V
TXD
50%
PCI
tJA
0V
tJR
19880B-17
Figure 13. Jabber Function
22
Am79C988A
P R E L I M I N A R Y
SWITCHING WAVEFORMS
CLK
tSDSU
DIR
SDATA
DIR
SDATA
{
{
tSSHD
tSSSU
E1
-0
L2
L3
tSSDO
tSSDO
tSDHD
DIR
{
SDATA
-1
DIR
SDATA
{
M2
M3
19880B-18
Figure 14. Serial Interface Waveforms
DIR
TSDS
TDDS
(min)
(max)
TDDS
SDATA
19880B-19
Figure 15. Serial Interface SDATA Transmit and Start Receive
Am79C988A
23
P R E L I M I N A R Y
SWITCHING TEST CIRCUITS
VDD
R
Test Point
Test Pin
100pF
330*
VSS
R = 330 for PAUI
1kΩ for SDATA
*Not used for SDATA
19880B-20
Figure 16. Switching Test Circuit
TXD+
TP
110 Ω
TXD-
TP
19880B-21
Figure 17. Twisted Pair Switching Test Circuit
24
Am79C988A
P R E L I M I N A R Y
PHYSICAL DIMENSIONS*
PL 044
44-Pin Plastic Leaded Chip Carrier (Measured in inches)
.685
.695
.042
.056
.650
.656
.062
.083
Pin 1 I.D.
.685
.695
.650
.656
.500 .590
REF .630
.013
.021
.026
.032
.009
.015
.050 REF
TOP VIEW
.090
.120
.165
.180
SEATING PLANE
SIDE VIEW
16-038-SQ
PL 044
EC80
11.3.97 lv
REVISION SUMMARY
This revision (B) reflects changes to Figures 3, 6, and
17. Changes have also been made to the Ordering Information page, and the DC Characteristics and Switching Characteristics tables. No other technical changes
have been made.
Trademarks
Copyright © 1997 Advanced Micro Devices, Inc. All rights reserved.
AMD, the AMD logo, and combinations thereof, and QuIET, IMR2, and PAUI are trademarks of Advanced Micro Devices, Inc.
Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
Am79C988A
25