ONSEMI NBSG53ABAR2

NBSG53A
2.5V/3.3VSiGe Selectable
Differential Clock and Data
D Flip−Flop/Clock Divider
with Reset and OLS*
The NBSG53A is a multi−function differential D flip−flop (DFF) or
fixed divide by two (DIV/2) clock generator. This is a part of the
GigaComm™ family of high performance Silicon Germanium
products. A strappable control pin is provided to select between the
two functions. The device is housed in a low profile 4x4 mm 16−pin
Flip−Chip BGA (FCBGA) or a 3x3 mm 16 pin QFN package.
The NBSG53A is a device with data, clock, OLS*, reset, and select
inputs. Differential inputs incorporate internal 50 W termination
resistors and accept NECL (Negative ECL), PECL (Positive ECL),
LVCMOS/LVTTL, CML, or LVDS. The OLS* input is used to
program the peak−to−peak output amplitude between 0 and 800 mV
in five discrete steps. The RESET and SELECT inputs are
single−ended and can be driven with either LVECL or
LVCMOS/LVTTL input levels.
Data is transferred to the outputs on the positive edge of the clock.
The differential clock inputs of the NBSG53A allow the device to also
be used as a negative edge triggered device.
Features
• Maximum Input Clock Frequency (DFF) > 8 GHz Typical
(See Figures 4, 6, 8, 10, and 11)
• Maximum Input Clock Frequency (DIV/2) > 10 GHz Typical
•
•
•
•
•
•
•
(See Figures 5, 7, 9, 10, and 11)
210 ps Typical Propagation Delay (OLS = FLOAT)
http://onsemi.com
MARKING
DIAGRAM**
SG
53A
LYW
FCBGA−16
BA SUFFIX
CASE 489
ÇÇ
ÇÇ
16
1
1
QFN−16
MN SUFFIX
CASE 485G
SG
53A
ALYWG
G
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
G
= Pb−Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
45 ps Typical Rise and Fall Times (OLS = FLOAT)
DIV/2 Mode (Active with Select Low)
DFF Mode (Active with Select High)
ORDERING INFORMATION
Selectable Swing PECL Output with Operating Range: VCC = 2.375 V
to 3.465 V with VEE = 0 V
Selectable Swing NECL Output with NECL Inputs with
Operating Range: VCC = 0 V with VEE = −2.375 V to −3.465 V
Selectable Output Level (0 V, 200 mV, 400 mV, 600 mV, or 800 mV
Peak−to−Peak Output)
50 W Internal Input Termination Resistors on all Differential Inputs
See detailed ordering and shipping information in the package
dimensions section on page 16 of this data sheet.
•
• Pb−Free Packages are Available
*Output Level Select
© Semiconductor Components Industries, LLC, 2006
July, 2006 − Rev. 8
1
Publication Order Number:
NBSG53A/D
NBSG53A
1
A
2
VTD
B
D
VTCLK
CLK
3
D
VCC
4
VCC
R
SEL OLS
16
15
14
Exposed Pad
(EP)
13
VTD
VTCLK
1
CLK
2
12
VEE
11
Q
Q
NBSG53A
C
VTCLK
CLK
VCC
D
R
VEE
SEL
Q
CLK
3
10
Q
VTCLK
4
9
VCC
OLS
Figure 1. BGA−16 Pinout (Top View)
5
6
7
8
VTD
D
D
VTD
Figure 2. QFN−16 Pinout (Top View)
Table 1. Pin Description
Pin
BGA
QFN
Name
I/O
C2
1
VTCLK
−
C1
2
CLK
ECL, CML,
LVCMOS,
LVDS, LVTTL
Input
Inverted Differential Input.
B1
3
CLK
ECL, CML,
LVCMOS,
LVDS, LVTTL
Input
Noninverted Differential Input.
B2
4
VTCLK
−
Internal 50 W Termination Pin. See Table 4.
A1
5
VTD
−
Internal 50 W termination pin. See Table 4.
A2
6
D
ECL, CML,
LVCMOS,
LVDS, LVTTL
Input
Inverted Differential Input.
A3
7
D
ECL, CML,
LVCMOS,
LVDS, LVTTL
Input
Noninverted Differential Input.
Description
Internal 50 W Termination Pin. See Table 4.
A4
8
VTD
−
Internal 50 W Termination Pin. See Table 4.
D1,B3
9,16
VCC
−
Positive Supply Voltage
B4
10
Q
RSECL Output
NonInverted Differential Output. Typically Terminated with 50 W Resistor to
VTT = VCC − 2 V.
C4
11
Q
RSECL Output
Inverted Differential Output. Typically Terminated with 50 W Resistor to
VTT = VCC − 2 V.
C3
12
VEE
−
D4
13
OLS*
Input
D3
14
SEL
LVECL,
LVCMOS,
LVTTL Input
Select Logic Input. Internal 75 kW to VEE.
D2
15
R
LVECL,
LVCMOS,
LVTTL Input
Reset D Flip−Flop. Internal 75 kW to VEE.
N/A
−
EP
Negative Supply Voltage
Input Pin for the Output Level Select (OLS). See Table 2.
Exposed Pad. (Note 1)
1. All VCC and VEE pins must be externally connected to Power Supply to guarantee proper operation. The thermally exposed pad (EP) on
package bottom (see case drawing) must be attached to a heat−sinking conduit.
2. In the differential configuration when the input termination pins (VTD, VTD, VTCLK, VTCLK) are connected to a common termination voltage, and if no signal is applied then the device will be susceptible to self−oscillation.
3. When an output level of 400 mV is desired and VCC − VEE > 3.0 V, 2KW resistor should be connected from OLS pin to VEE.
http://onsemi.com
2
NBSG53A
VCC
OLS
VTD
50 W
2
2
D
D
50 W
2
VTD
D
Flip−Flop
(DFF)
R
Q
1
Q
2
0
Q
2
2
Q
D
Flip−Flop
(DIV/2)
VTCLK
50 W
2
CLK
R
CLK
50 W
VTCLK
R
SEL
75 kW
75 kW
VEE
Figure 3. Simplified Logic Diagram
Table 2. OUTPUT LEVEL SELECT (OLS)
OLS
Q/Q VPP
Table 3. TRUTH TABLE
OLS Sensitivity
R
SEL
D
CLK
Q
Function
VCC
800 mV
OLS − 75 mV
H
x
x
x
L
Reset
VCC − 0.4 V
200 mV
OLS $ 150 mV
L
H
L
Z
L
DFF
VCC − 0.8 V
600 mV
OLS $ 100 mV
L
H
H
Z
H
DFF
VCC − 1.2 V
0
OLS $ 75 mV
L
L
x
Z
Q
DIV/2
VEE (Note 4)
400 mV
OLS + 100 mV
Float
600 mV
N/A
Z = LOW to HIGH Transition
4. When an output level of 400 mV is desired and
VCC − VEE > 3.0 V, 2.0 kW resistor should be connected from
OLS to VEE.
Table 4. INTERFACING OPTIONS
INTERFACING OPTIONS
CONNECTIONS
CML
Connect VTCLK, VTD and VTCLK, VTD to VCC
LVDS
Connect VTCLK, VTD and VTCLK, VTD Together
AC−COUPLED
Bias VTCLK, VTD and VTCLK, VTD Inputs within Common Mode Range (VIHCMR)
RSECL, PECL, NECL
Standard ECL Termination Techniques
LVTTL, LVCMOS
An External Voltage (VTHR) should be Applied to the Unused Complementary Differential Input. Nominal
VTHR is 1.5 V for LVTTL and VCC/2 for LVCMOS Inputs. This Voltage must be within the VTHR Specification.
http://onsemi.com
3
NBSG53A
Table 5. ATTRIBUTES
Characteristics
Value
Positive Operating Voltage Range for VCC (VEE = 0 V)
2.375 V to 3.465 V
Negative Operating Voltage Range for VEE (VCC = 0 V)
−2.375 V to −3.465 V
Internal Input Pulldown Resistor (R, SEL)
ESD Protection
75 kW
Human Body Model
Machine Model
Charged Device Model
> 1.5 kV
> 50 V
> 4 kV
16−FCBGA
16−QFN
Level 3
Level 1
Moisture Sensitivity (Note 5)
Flammability Rating
UL 94 V−0 @ 0.125 in
Oxygen Index
28 to 34
Transistor Count
482
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
5. For additional information, refer to Application Note AND8003/D.
Table 6. MAXIMUM RATINGS
Rating
Units
VCC
Symbol
Positive Power Supply
Parameter
VEE = 0 V
Condition 1
3.6
V
VEE
Negative Power Supply
VCC = 0 V
−3.6
V
VI
Positive Input
Negative Input
VEE = 0 V
VCC = 0 V
3.6
−3.6
V
V
VINPP
Differential Input Voltage
2.8
|VCC − VEE|
V
V
IIN
Input Current Through RT (50 W Resistor)
Static
Surge
45
80
mA
mA
IOUT
Output Current
Continuous
Surge
25
50
mA
mA
TA
Operating Temperature Range
16 FCBGA
16 QFN
−40 to +70
−40 to +85
°C
Tstg
Storage Temperature Range
−65 to +150
°C
qJA
Thermal Resistance (Junction−to−Ambient)
(Note 6)
0 LFPM
500 LFPM
0 LFPM
500 LFPM
16 FCBGA
16 FCBGA
16 QFN
16 QFN
108
86
41.6
35.2
°C/W
°C/W
°C/W
°C/W
qJC
Thermal Resistance (Junction−to−Case)
2S2P (Note 6)
2S2P (Note 7)
16 FCBGA
16 QFN
5.0
4.0
°C/W
°C/W
Tsol
Wave Solder
< 15 sec
< 3 sec @ 248°C
< 3 sec @ 260°C
225
265
265
°C
|D − D|
Pb (BGA)
Pb (QFN)
Pb−Free (QFN)
Condition 2
VI v VCC
VI w VEE
VCC − VEE w 2.8 V
VCC − VEE < 2.8 V
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
6. JEDEC standard 51−6, multilayer board − 2S2P (2 signal, 2 power).
7. JEDEC standard multilayer board − 2S2P (2 signal, 2 power) with 8 filled thermal vias under exposed pad.
http://onsemi.com
4
NBSG53A
Table 7. DC CHARACTERISTICS, INPUT WITH PECL OUTPUT VCC = 2.5 V; VEE = 0 V (Note 8)
−40°C
Symbol
Characteristic
25°C
70°C(BGA)/85°C(QFN)**
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
33
45
57
33
45
57
33
45
57
mA
mV
IEE
Negative Power Supply Current
VOH
Output HIGH Voltage (Note 9)
1460
1510
1560
1490
1540
1590
1515
1565
1615
VOL
Output LOW Voltage (Note 9)
(OLS = VCC)
(OLS = VCC − 0.4 V)
(OLS = VCC − 0.8 V, OLS = FLOAT)
(OLS = VCC − 1.2 V)
(OLS = VEE)
555
1235
775
1455
1005
705
1295
895
1505
1095
855
1385
1015
1585
1215
595
1270
810
1490
1040
745
1330
930
1540
1130
895
1420
1050
1620
1250
625
1295
840
1510
1065
775
1355
960
1560
1155
925
1445
1080
1640
1275
670
125
510
0
325
800
215
615
5
415
660
120
505
0
320
795
210
610
0
410
655
120
500
0
320
790
210
605
5
410
VOUTPP
mV
Output Voltage Amplitude
(OLS = VCC)
(OLS = VCC − 0.4 V)
(OLS = VCC − 0.8 V, OLS = FLOAT)
(OLS = VCC − 1.2 V)
(OLS = VEE)
mV
VIH
Input HIGH Voltage (Single−Ended)
(Notes 11 and 13)
CLK, CLK, D, D
VEE +
1275
VCC −
1000*
VCC
VEE +
1275
VCC −
1000*
VCC
VEE +
1275
VCC−
1000*
VCC
mV
VIL
Input LOW Voltage (Single−Ended)
(Notes 12 and 13)
CLK, CLK, D, D
VEE
VCC−
1400*
VIH−
150
VEE
VCC−
1400*
VIH−
150
VEE
VCC−
1400*
VIH−
150
mV
VIH
Input High Voltage (Single−Ended)
R, SEL
1290
VCC
1355
VCC
1415
VCC
Input Low Voltage (Single−Ended)
R, SEL
VEE
890
VEE
955
VEE
1015
VTHR
Input Threshold Voltage (Single−Ended)
(Note 13)
VEE+
1125
VCC−
75
VEE+
1125
VCC−
75
VEE+
1125
VCC−
75
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 10)
1.2
2.5
1.2
2.5
1.2
2.5
V
RTIN
Internal Input Termination Resistor
45
50
55
45
50
55
45
50
55
W
IIH
Input HIGH Current (@VIH)
R, SEL
CLK, CLK, D, D
35
5
100
50
35
5
100
50
35
5
100
50
mA
IIL
Input LOW Current (@VIL)
R, SEL
CLK, CLK, D, D
20
5
100
50
20
5
100
50
20
5
100
50
mA
VIL
mV
mV
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
8. Input and output parameters vary 1:1 with VCC. VEE can vary +0.125 V to −0.965 V.
9. All outputs loaded with 50 W to VCC − 2.0 V.
10. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
11. VIH cannot exceed VCC. |VIH − VTHR| < 2600 mV.
12. VIL always w VEE. |VIL − VTHR| < 2600 mV.
13. VTHR is the voltage applied to one input when running in single−ended mode.
*Typicals used for testing purposes.
**The device packaged in FCBGA−16 have maximum ambient temperature specification of 70°C and devices packaged in QFN−16 have
maximum ambient temperature specification of 85°C.
http://onsemi.com
5
NBSG53A
Table 8. DC CHARACTERISTICS, INPUT WITH PECL OUTPUT VCC = 3.3 V; VEE = 0 V (Note 14)
−40°C
Symbol
Characteristic
25°C
70°C(BGA)/85°C(QFN)***
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
IEE
Negative Power Supply Current
35
47
59
35
47
59
35
47
59
mA
VOH
Output HIGH Voltage (Note 15)
2260
2310
2360
2290
2340
2390
2315
2365
2415
mV
VOL
Output LOW Voltage (Note 15)
(OLS = VCC)
(OLS = VCC − 0.4 V)
(OLS = VCC − 0.8 V, OLS = FLOAT)
(OLS = VCC − 1.2 V)
**(OLS = VEE)
1320
2030
1550
2260
1785
1470
2090
1670
2310
1875
1620
2180
1790
2390
1995
1360
2065
1585
2290
1820
1510
2125
1705
2340
1910
1660
2215
1825
2420
2030
1390
2090
1615
2315
1850
1540
2150
1735
2365
1940
1690
2240
1855
2445
2060
705
130
535
0
345
815
220
640
0
435
695
125
530
0
340
805
215
635
0
430
690
125
525
0
335
800
215
630
0
425
VOUTPP
mV
Output Amplitude Voltage
(OLS = VCC)
(OLS = VCC − 0.4 V)
(OLS = VCC − 0.8 V, OLS = FLOAT)
(OLS = VCC − 1.2 V)
**(OLS = VEE)
mV
VIH
Input HIGH Voltage (Single−Ended)
(Notes 17 and 19)
CLK, CLK, D, D
VEE +
1275
VCC −
1000*
VCC
VEE +
1275
VCC −
1000*
VCC
VEE +
1275
VCC −
1000*
VCC
mV
VIL
Input LOW Voltage (Single−Ended)
(Notes 18 and 19)
CLK, CLK, D, D
VIH−
2600
VCC−
1400*
VIH−
150
VIH−
2600
VCC−
1400*
VIH−
150
VIH−
2600
VCC−
1400*
VIH−
150
mV
VIH
Input High Voltage (Single−Ended)
R, SEL
2090
VCC
2155
VCC
2215
VCC
Input Low Voltage (Single−Ended)
R, SEL
VEE
1690
VEE
1755
VEE
1815
VEE+
1125
VCC−
75
VEE+
1125
VCC−
75
VEE+
1125
VCC−
75
mV
3.3
1.2
3.3
1.2
3.3
V
50
55
45
50
55
45
50
55
W
VIL
mV
mV
VTHR
Input Threshold Voltage
(Single−Ended) (Note 19)
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 16)
1.2
RTIN
Internal Input Termination Resistor
45
IIH
Input HIGH Current (@VIH)
R, SEL
CLK, CLK, D, D
35
5
100
50
35
5
100
50
35
5
100
50
mA
IIL
Input LOW Current (@VIL)
R, SEL
CLK, CLK, D, D
20
5
100
50
20
5
100
50
20
5
100
50
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification
limit values are applied individually under normal operating conditions and not valid simultaneously.
14. Input and output parameters vary 1:1 with VCC. VEE can vary +0.925 V to −0.165 V.
15. All outputs loaded with 50 W to VCC − 2.0 V.
16. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
17. VIH cannot exceed VCC. |VIH − VTHR| < 2600 mV.
18. VIL always w VEE. |VIL − VTHR| < 2600 mV.
19. VTHR is the voltage applied to one input when running in single−ended mode.
*Typicals used for testing purposes.
**When an output level of 400 mV is desired and VCC − VEE > 3.0 V, a 2 kW resistor should be connected from OLS to VEE.
***The device packaged in FCBGA−16 have maximum ambient temperature specification of 70°C and devices packaged in QFN−16 have
maximum ambient temperature specification of 85°C.
http://onsemi.com
6
NBSG53A
Table 9. DC CHARACTERISTICS, NECL INPUT WITH NECL OUTPUT
VCC = 0 V; VEE = −3.465 V to −2.375 V (Note 20)
−40°C
Symbol
Characteristic
25°C
70°C(BGA)/85°C(QFN)***
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
IEE
Negative Power Supply Current
35
47
59
35
47
59
35
47
59
mA
VOH
Output HIGH Voltage (Note 21)
−1040
−990
−940
−1010
−960
−910
−985
−935
−885
mV
VOL
Output LOW Voltage (Note 21)
−3.465 V v VEE v −3.0 V
(OLS = VCC)
(OLS = VCC − 0.4 V)
(OLS = VCC − 0.8 V, OLS =FLOAT)
(OLS = VCC − 1.2 V)
**(OLS = VEE)
−3.0 V < VEE v −2.375 V
(OLS = VCC)
(OLS = VCC − 0.4 V)
(OLS = VCC − 0.8 V, OLS =FLOAT)
(OLS = VCC − 1.2 V)
(OLS = VEE)
VOUTPP
Output Voltage Amplitude
−3.465 V v VEE v −3.0 V
(OLS = VCC)
(OLS = VCC − 0.4 V)
(OLS = VCC − 0.8 V,
OLS = FLOAT)
(OLS = VCC − 1.2 V)
**(OLS = VEE)
−3.0 V < VEE v −2.375 V
(OLS = VCC)
(OLS = VCC − 0.4 V)
(OLS = VCC − 0.8 V, OLS
=FLOAT)
(OLS = VCC − 1.2 V)
(OLS = VEE)
mV
−1980
−1270
−1750
−1040
−1515
−1830
−1210
−1630
−990
−1425
−1680
−1120
−1510
−910
−1305
−1940
−1235
−1715
−1010
−1480
−1790
−1175
−1595
−960
−1390
−1640
−1085
−1475
−880
−1270
−1910
−1210
−1685
−985
−1450
−1760
−1150
−1565
−935
−1360
−1610
−1060
−1445
−855
−1240
−1945
−1265
−1725
−1045
−1495
−1795
−1205
−1605
−995
−1405
−1645
−1115
−1485
−915
−1285
−1905
−1230
−1690
−1010
−1460
−1755
−1170
−1570
−960
−1370
−1605
−1080
−1450
−880
−1250
−1875
−1205
−1660
−990
−1435
−1725
−1145
−1540
−940
−1345
−1575
−1055
−1420
−860
−1225
mV
705
130
535
0
345
815
220
640
0
435
695
125
530
0
340
805
215
635
0
430
690
125
525
0
335
800
215
630
0
425
670
125
510
0
325
800
215
615
5
415
660
120
505
0
320
795
210
610
0
410
655
120
500
0
320
790
210
605
5
410
VIH
Input HIGH Voltage (Single−Ended)
(Notes 23 and 25) CLK, CLK, D, D
VEE +
1275
VCC −
1000*
VCC
VEE +
1275
VCC −
1000*
VCC
VEE +
1275
VCC −
1000*
VCC
mV
VIL
Input LOW Voltage (Single−Ended)
(Notes 24 and 25) CLK, CLK, D, D
VIH−
2600
VCC−
1400*
VIH−
150
VIH−
2600
VCC−
1400*
VIH−
150
VIH−
2600
VCC−
1400*
VIH−
150
mV
VIH
Input High Voltage
(Single−Ended)
mV
R, SEL
VIL
VTHR
−1210
VCC
−1145
VCC
−1085
VCC
Input Low Voltage (Single−Ended)
R, SEL
VEE
−1610
VEE
−1545
VEE
−1485
Input Threshold Voltage
(Single−Ended) (Note 25)
VEE+
1125
VCC−
75
VEE+
1125
VCC−
75
VEE+
1125
VCC−
75
mV
mV
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification
limit values are applied individually under normal operating conditions and not valid simultaneously.
20. Input and output parameters vary 1:1 with VCC.
21. All outputs loaded with 50 W to VCC − 2.0 V.
22. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
23. VIH cannot exceed VCC. |VIH − VTHR| < 2600 mV.
24. VIL always w VEE. |VIL − VTHR| < 2600 mV.
25. VTHR is the voltage applied to one input when running in single−ended mode.
*Typicals used for testing purposes.
**When an output level of 400 mV is desired and VCC − VEE > 3.0 V, a 2 kW resistor should be connected from OLS to VEE.
***The device packaged in FCBGA−16 have maximum ambient temperature specification of 70°C and devices packaged in QFN−16 have
maximum ambient temperature specification of 85°C.
http://onsemi.com
7
NBSG53A
Table 9. DC CHARACTERISTICS, NECL INPUT WITH NECL OUTPUT
VCC = 0 V; VEE = −3.465 V to −2.375 V (Note 20) (continued)
−40°C
Symbol
Characteristic
VIHCMR
Input HIGH Voltage Common
Mode Range
(Differential Configuration)
(Note 22)
RTIN
Internal Input Termination Resistor
IIH
Input HIGH Current (@VIH)
R, SEL
CLK, CLK, D, D
IIL
Min
VEE + 1.2
45
Max
0.0
50
55
35
5
Min
Typ
VEE + 1.2
45
70°C(BGA)/85°C(QFN)***
Max
0.0
Min
Typ
Max
Unit
0.0
V
50
55
W
VEE + 1.2
50
55
100
50
35
5
100
50
35
5
100
50
45
20
5
100
50
20
5
100
50
20
5
100
50
900
300
100
−300
300
100
5
−100
900
300
100
−300
300
100
5
−100
900
300
100
−300
300
100
5
−100
−1500
−600
−1500
−600
−1500
−600
−1000
−400
−1000
−400
−1000
−400
mA
mA
Input LOW Current (@VIL)
R, SEL
CLK, CLK, D, D
IOLS
Typ
25°C
OLS Input Current (See Figure
12)
(OLS = VCC)
(OLS = VCC − 0.4 V)
(OLS = VCC − 0.8 V, OLS =
FLOAT)
(OLS = VCC − 1.2 V)
−3.465 V v VEE v −3.0 V
*(OLS = VEE)
−3.0 V < VEE v −2.375 V
(OLS = VEE)
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification
limit values are applied individually under normal operating conditions and not valid simultaneously.
20. Input and output parameters vary 1:1 with VCC.
21. All outputs loaded with 50 W to VCC − 2.0 V.
22. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
23. VIH cannot exceed VCC. |VIH − VTHR| < 2600 mV.
24. VIL always w VEE. |VIL − VTHR| < 2600 mV.
25. VTHR is the voltage applied to one input when running in single−ended mode.
*Typicals used for testing purposes.
**When an output level of 400 mV is desired and VCC − VEE > 3.0 V, a 2 kW resistor should be connected from OLS to VEE.
***The device packaged in FCBGA−16 have maximum ambient temperature specification of 70°C and devices packaged in QFN−16 have
maximum ambient temperature specification of 85°C.
http://onsemi.com
8
NBSG53A
Table 10. AC CHARACTERISTICS for FCBGA−16
VCC = 0 V; VEE = −3.465 V to −2.375 V or VCC = 2.375 V to 3.465 V; VEE = 0 V
−40°C
Symbol
fmax
tPLH,
tPHL
Min
Characteristic
Maximum Frequency
(See Figures 4, 6, 8, 10, and 11)
(See Figures 5, 7, 9, 10, and 11)
(Note 26)
Typ
25°C
Max
Min
Typ
70°C
Max
Min
Typ
Max
Unit
GHz
DFF
8
8
8
DIV/2
10
10
10
Propagation Delay to Output Differential
CLK→Q, Q
(OLS = VCC)
(OLS = VCC − 0.4 V)
(OLS = VCC − 0.8 V, OLS = FLOAT)
**(OLS = VEE)
160
150
155
155
210
200
205
205
260
250
255
255
160
155
160
160
215
205
210
210
270
255
260
260
165
160
160
160
220
210
215
215
275
260
270
270
SEL→Q, Q
(OLS = VCC)
(OLS = VCC − 0.4 V)
(OLS = VCC − 0.8 V, OLS = FLOAT)
**(OLS = VEE)
165
160
160
160
220
210
215
210
275
260
270
260
170
160
165
160
225
210
220
215
280
260
275
270
170
160
165
165
225
210
220
220
280
260
275
275
R→Q, Q
(OLS = VCC) DIV/2
(OLS = VCC) DFF
(OLS = VCC − 0.4 V) DIV/2
(OLS = VCC − 0.4 V) DFF
(OLS = VCC −0.8 V, OLS = FLOAT) DIV/2
(OLS = VCC − 0.8 V, OLS = FLOAT) DFF
**(OLS = VEE) DIV/2
**(OLS = VEE) DFF
220
200
215
195
220
200
215
195
295
270
285
260
290
265
285
260
370
340
355
325
360
330
355
325
225
205
220
200
220
200
220
200
300
275
290
265
295
270
290
265
375
345
360
330
370
340
360
330
225
205
220
200
220
200
220
200
300
275
290
265
295
270
290
265
375
345
360
330
370
340
360
330
5
20
5
20
5
20
0.5
1.5
0.5
1.5
0.5
1.5
tSKEW
Duty Cycle Skew (Notes 27 and 29) DFF
tJITTER
RMS Random Clock Jitter
ps
ps
ps
fin v 8 GHz
(See Figures 4 and 6) (Note 26)
Peak−to−Peak Data Dependent Jitter
fin = 8 Gb/s
VINPP
Input Voltage Swing/Sensitivity
(Differential Configuration) (Note 28)
tr
tf
Output Rise/Fall Times (20% − 80%)
@ 1 GHz
Q, Q
(OLS = VCC)
(OLS = VCC − 0.4 V)
(OLS = VCC − 0.8 V, OLS = FLOAT)
**(OLS = VEE)
TBD
75
2600
75
2600
75
2600
mV
ps
30
20
25
25
50
40
45
45
65
60
65
65
30
20
25
25
50
40
45
45
65
60
65
65
30
20
25
25
50
40
45
45
65
60
65
65
ts
Setup Time
D→CLK
30
14
30
10
30
13
ps
th
Hold Time
D→CLK
25
12
25
7
25
9
ps
trr
Reset Recovery
DFF, DIV/2
40
9
40
12
40
10
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
26. Measured using a 500 mV source, 50% duty cycle clock source. Repetitive 1010 input data pattern. All outputs loaded with 50 W to
VCC − 2.0 V. Input edge rates is 40 ps (20% − 80%).
27. See Figure 14. tSKEW = |tPLH − tPHL| for a nominal 50% differential clock input waveform.
28. VINPP (MAX) cannot exceed VCC − VEE (Applicable only when VCC − VEE < 2600 mV).
29. See Figure 10. Duty Cycle % vs. Frequency.
**When an output level of 400 mV is desired and VCC − VEE > 3.0 V, a 2 kW resistor should be connected from OLS to VEE.
http://onsemi.com
9
NBSG53A
Table 11. AC CHARACTERISTICS for QFN−16
VCC = 0 V; VEE = −3.465 V to −2.375 V or VCC = 2.375 V to 3.465 V; VEE = 0 V
−40°C
Symbol
fmax
Min
Characteristic
Maximum Frequency
(See Figures 4, 6, 8, 10, and 11)
(See Figures 5, 7, 9, 10, and 11)
(Note 30)
Typ
25°C
Max
Min
Typ
85°C
Max
Min
Typ
Max
Unit
GHz
DFF
8
8
8
DIV/2
10
10
10
tPLH,
tPHL
Propagation Delay to Output Differential
(Note 34)
CLK→Q, Q
SEL→Q, Q
R→Q, Q DIN/2
DFF
tSKEW
Duty Cycle Skew (Notes 31 and 33) DFF
tJITTER
RMS Random Clock Jitter
ps
150
160
215
195
215
190
280
270
285
280
375
345
5
0.5
150
160
215
195
215
190
280
270
285
280
375
345
20
5
1
0.5
150
160
215
195
215
190
280
270
285
280
375
345
20
5
20
1
0.5
1
ps
ps
fin v 8 GHz
(See Figures 4 and 6) (Note 30)
Peak−to−Peak Data Dependent Jitter
fin = 8 Gb/s
VINPP
Input Voltage Swing/Sensitivity
(Differential Configuration) (Note 32)
tr
tf
Output Rise/Fall Times (20% − 80%)
@ 1 GHz
Q, Q
(OLS = VCC)
(OLS = VCC − 0.4 V)
(OLS = VCC − 0.8 V, OLS = FLOAT)
**(OLS = VEE)
TBD
75
TBD
2600
75
TBD
2600
75
2600
mV
ps
28
15
25
20
40
40
35
35
65
65
65
65
28
15
25
20
40
40
35
35
65
65
65
65
28
15
25
20
40
40
35
35
65
65
65
65
ts
Setup Time
D→CLK
30
14
30
10
30
13
ps
th
Hold Time
D→CLK
25
12
25
7
25
0
ps
trr
Reset Recovery
DFF, DIV/2
40
9
40
12
40
10
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
30. Measured using a 500 mV source, 50% duty cycle clock source. Repetitive 1010 input data pattern. All outputs loaded with 50 W to
VCC − 2.0 V. Input edge rates is 40 ps (20% − 80%).
31. See Figure 14. tSKEW = |tPLH − tPHL| for a nominal 50% differential clock input waveform.
32. VINPP (MAX) cannot exceed VCC − VEE (Applicable only when VCC − VEE < 2600 mV).
33. See Figure 10. Duty Cycle % vs. Frequency.
34. For all OLS Configuration.
**When an output level of 400 mV is desired and VCC − VEE > 3.0 V, a 2 kW resistor should be connected from OLS to VEE.
***The device packaged in FCBGA−16 have maximum ambient temperature specification of 70°C and devices packaged in QFN−16 have
maximum ambient temperature specification of 85°C.
http://onsemi.com
10
NBSG53A
900
9
OLS = VCC
700
8
7
OLS = VCC − 0.8 V, OLS = FLOAT
600
500
6
*OLS = VEE
5
400
300
4
OLS = VCC − 0.4 V
3
200
JITTER OUT ps (RMS)
OUTPUT VOLTAGE AMPLITUDE
800
2
100
1
RMS JITTER
0
0
1
2
3
4
5
6
7
8
9
10
11
0
12
INPUT FREQUENCY (GHz)
Figure 4. Output Voltage Amplitude (VOUTPP) / RMS Jitter vs.
Input Frequency (fin) for DFF Mode (VCC − VEE = 3.3 V @ 255C; Repetitive 1010 Input Data Pattern)
900
OUTPUT VOLTAGE AMPLITUDE
OLS = VCC
800
700
OLS = VCC − 0.8 V, OLS = FLOAT
600
500
*OLS = VEE
400
300
OLS = VCC − 0.4 V
200
100
0
0
1
2
3
4
5
6
7
8
9
10
11
12
INPUT FREQUENCY (GHz)
Figure 5. Output Voltage Amplitude (VOUTPP) / RMS Jitter vs.
Input Frequency (fin) for DIV/2 Mode (VCC − VEE = 3.3 V @ 255C)
*When an output level of 400 mV is desired and VCC − VEE > 3.0 V, a 2 kW resistor should be connected from OLS to VEE.
http://onsemi.com
11
NBSG53A
900
700
8
7
OLS = VCC − 0.8 V, OLS = FLOAT
600
500
6
5
*OLS = VEE
400
300
4
OLS = VCC − 0.4 V
3
200
JITTER OUT ps (RMS)
OUTPUT VOLTAGE AMPLITUDE
800
9
OLS = VCC
2
100
1
RMS JITTER
0
0
1
2
3
4
5
6
7
8
9
10
11
0
12
INPUT FREQUENCY (GHz)
Figure 6. Output Voltage Amplitude (VOUTPP) / RMS Jitter vs.
Input Frequency (fin) for DFF Mode (VCC − VEE = 2.5 V @ 255C; Repetitive 1010 Input Data Pattern)
900
OUTPUT VOLTAGE AMPLITUDE
800
700
OLS = VCC
*OLS = VCC − 0.8 V, OLS = FLOAT
600
500
OLS = VEE
400
300
OLS = VCC − 0.4 V
200
100
0
0
1
2
3
4
5
6
7
8
9
10
11
12
INPUT FREQUENCY (GHz)
Figure 7. Output Voltage Amplitude (VOUTPP) / RMS Jitter vs.
Input Frequency (fin) for DIV/2 Mode (VCC − VEE = 2.5 V @ 255C)
*When an output level of 400 mV is desired and VCC − VEE > 3.0 V, a 2 kW resistor should be connected from OLS to VEE.
http://onsemi.com
12
NBSG53A
1200
VOH (Q)
1100
1000
VOH/VOL (mV)
900
VOH (Q)
800
700
600
VOL (Q)
500
400
300
VOL (Q)
200
100
0
0
1
2
3
4
5
6
7
8
9
10
11
12
INPUT FREQUENCY (GHz)
Figure 8. VOH/VOL (Q/Q) vs. Input Frequency (fin) for DFF Mode
(VCC − VEE = 3.3 V @ 255C and OLS = VCC − 0.8 V, OLS = FLOAT)
1200
VOH (Q)
1100
1000
VOH/VOL (mV)
900
VOH (Q)
800
700
600
VOL (Q)
500
400
300
VOL (Q)
200
100
0
0
1
2
3
4
5
6
7
8
9
10
11
12
INPUT FREQUENCY (GHz)
Figure 9. VOH/VOL (Q/Q) vs. Input Frequency (fin) for DIV/2 Mode
(VCC − VEE = 3.3 V @ 255C and OLS = VCC − 0.8 V, OLS = FLOAT)
http://onsemi.com
13
NBSG53A
100
90
DUTY CYCLE (%)
80
70
DIV/2 Mode
60
50
DFF Mode
40
30
20
10
0
0
1
2
3
4
5
6
7
8
9
10
11
12
11
12
INPUT FREQUENCY (GHz)
Figure 10. Duty Cycle % vs. Input Frequency (fin)
(VCC − VEE = 3.3 V @ 255C)
100
90
DUTY CYCLE (%)
80
70
DIV/2 Mode
60
50
DFF Mode
40
30
20
10
0
0
1
2
3
4
5
6
7
8
9
10
INPUT FREQUENCY (GHz)
Figure 11. Duty Cycle % vs. Input Frequency (fin)
(VCC − VEE = 2.5 V @ 705C)
http://onsemi.com
14
NBSG53A
300
200
100
IOLS (mA)
0
−100
−200
−300
−400
−500
−600
−700
VCC
VCC − 400
VCC − 800
VCC − 1200
VEE
VOLS (mV)
Figure 12. Typical OLS Input Current vs. OLS Input Voltage
(VCC − VEE = 3.3 V @ 255C)
1000
VCC − 75
800
Voutpp (mV)
VCC − 700
VCC − 900
600
VEE + 100
400
VCC − 250
VCC − 550
200
VCC − 1125
VCC − 1275
0
VCC
VCC − 400
VCC − 800
VCC − 1200
OLS (mV)
Figure 13. OLS Operating Area
http://onsemi.com
15
VEE
NBSG53A
CLK
VINPP = VIH(CLK) − VIL(CLK)
CLK
Q
VOUTPP = VOH(Q) − VOL(Q)
Q
tPHL
tPLH
Figure 14. AC Reference Measurement
Q
Zo = 50 W
D
Receiver
Device
Driver
Device
Q
Zo = 50 W
D
50 W
50 W
VTT
VTT = VCC − 2.0 V
Figure 15. Typical Termination for Output Driver and Device Evaluation
(Refer to Application Note AND8020/D − Termination of ECL Logic Devices)
ORDERING INFORMATION
Package Type
Shipping †
NBSG53ABA
4x4 mm
FCBGA−16
100 Units / Tray (Contact Sales Representative)
NBSG53ABAR2
4x4 mm
FCBGA−16
100 / Tape & Reel
3x3 mm
QFN−16
123 Units / Rail
NBSG53AMNG
3x3 mm
QFN−16
(Pb−Free)
123 Units / Rail
NBSG53AMNR2
3x3 mm
QFN−16
3000 / Tape & Reel
3x3 mm
QFN−16
(Pb−Free)
3000 / Tape & Reel
Device
NBSG53AMN
NBSG53AMNR2G
Board
Description
NBSG53ABAEVB
NBSG53ABA Evaluation Board
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
http://onsemi.com
16
NBSG53A
PACKAGE DIMENSIONS
FCBGA−16
BA SUFFIX
PLASTIC 4 X 4 (mm) BGA FLIP CHIP PACKAGE
CASE 489−01
ISSUE O
LASER MARK FOR PIN 1
IDENTIFICATION IN
THIS AREA
−X−
D
M
−Y−
K
E
M
0.20
3X
e
4
3
2
FEDUCIAL FOR PIN A1
IDENTIFICATION IN THIS AREA
1
A
3
B
b
16 X
C
D
S
VIEW M−M
0.15
M
Z X Y
0.08
M
Z
5
0.15 Z
A
A2
A1
16 X
4
−Z−
0.10 Z
DETAIL K
ROTATED 90 _ CLOCKWISE
http://onsemi.com
17
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3. DIMENSION b IS MEASURED AT THE MAXIMUM
SOLDER BALL DIAMETER, PARALLEL TO DATUM
PLANE Z.
4. DATUM Z (SEATING PLANE) IS DEFINED BY THE
SPHERICAL CROWNS OF THE SOLDER BALLS.
5. PARALLELISM MEASUREMENT SHALL EXCLUDE
ANY EFFECT OF MARK ON TOP SURFACE OF
PACKAGE.
DIM
A
A1
A2
b
D
E
e
S
MILLIMETERS
MIN
MAX
1.40 MAX
0.25
0.35
1.20 REF
0.30
0.50
4.00 BSC
4.00 BSC
1.00 BSC
0.50 BSC
NBSG53A
PACKAGE DIMENSIONS
16 PIN QFN
CASE 485G−01
ISSUE C
PIN 1
LOCATION
ÇÇ
ÇÇ
ÇÇ
D
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.25 AND 0.30 MM FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
5. Lmax CONDITION CAN NOT VIOLATE 0.2 MM
MINIMUM SPACING BETWEEN LEAD TIP
AND FLAG
A
B
E
DIM
A
A1
A3
b
D
D2
E
E2
e
K
L
0.15 C
TOP VIEW
0.15 C
(A3)
0.10 C
MILLIMETERS
MIN
MAX
0.80
1.00
0.00
0.05
0.20 REF
0.18
0.30
3.00 BSC
1.65
1.85
3.00 BSC
1.65
1.85
0.50 BSC
0.18 TYP
0.30
0.50
A
16 X
0.08 C
SIDE VIEW
SOLDERING FOOTPRINT*
SEATING
PLANE
A1
C
0.575
0.022
D2
16X
5
EXPOSED PAD
8
4
9
K
12
1
16
16X
e
13
0.50
0.02
b
0.10 C A B
1.50
0.059
3.25
0.128
E2
0.05 C
EXPOSED PAD
e
L
NOTE 5
16X
3.25
0.128
0.30
0.012
BOTTOM VIEW
0.30
0.012
SCALE 10:1
NOTE 3
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and solderin
details, please download the ON Semiconductor Soldering an
Mounting Techniques Reference Manual, SOLDERRM/D.
GigaComm is a trademark of Semiconductor Components Industries, LLC.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: [email protected]
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5773−3850
http://onsemi.com
18
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your local
Sales Representative
NBSG53A/D