VGA Port Companion Circuit PACVGA200 Features • • • • • • • • • Single chip solution for the VGA port interface Includes ESD protection, level shifting, and RGB termination Seven channels of ESD protection for all VGA port connector pins meeting IEC-61000-4-2 Level-4 ESD requirements (±8kV contact discharge) Very low loading capacitance from ESD protection diodes on VIDEO lines, 4pF typical 75Ω termination resistors for VIDEO lines (matched to 1% typ.) TTL to CMOS level-translating buffers with power down mode for HSYNC and VSYNC lines Bi-directional level shifting N-channel FETs provided for DDC_CLK & DDC_DATA channels Compact 24-pin QSOP package Lead-free version available Applications • • Notebook computers with VGA port Desktop PCs with VGA port Product Description The PACVGA200 incorporates seven channels of ESD protection for all signal lines commonly found in a VGA port. ESD protection is implemented with current steering diodes designed to safely handle the high surge currents encountered with IEC-61000-4-2 Level-4 ESD Protection (±8kV contact discharge). When a channel is subjected to an electrostatic discharge, the ESD current pulse is diverted via the protection diodes into either the positive supply rail or ground where it may be safely dissipated. Separate positive supply rails are provided for the VIDEO, DDC and SYNC channels to facilitate interfacing with low voltage Video Controller ICs and provide design flexibility in multi-supply-voltage environments. ©2010 SCILLC. All rights reserved. May 2010 Rev. 2 Two non-inverting drivers provide buffering for the HSYNC and VSYNC signals from the Video Controller IC (SYNC_IN1, SYNC_IN2). These buffers accept TTL input levels and convert them to CMOS output levels that swing between Ground and VCC4 . These drivers have nominal 60 Ω output impedance (RS) to match the characteristic impedance of the HSYNC & VSYNC lines of the video cables typically used in PC applications. Two N-channel FETs provide the level shifting function required when the DDC controller is operated at a lower supply voltage than the monitor. Three 75 Ω termination resistors suitable for terminating the video signals from the video DAC are also provided. These resistors have separate input pins to allow insertion of additional EMI filtering, if required, between the termination point and the ESD protection diodes. These resistors are matched to better than 2% for excellent signal level matching for the R/G/B signals. When the PWR_UP input is driven LOW, the SYNC inputs can be floated without causing the SYNC buffers to draw any current from the VCC4 supply. When the PWR_UP input is LOW, the SYNC outputs are driven LOW. An internal diode (D1 in schematic on previous page) is also provided so that VCC3 can be derived from VCC4, if desired, by connecting VCC3 to V_BIAS. In applications where VCC4 may be powered down, diode D1 blocks any DC current paths from the DDC_OUT pins back to the powered down VCC4 rail via the top ESD protection diodes. The PACVGA200 device is housed in a 24-pin QSOP package and is available with optional lead-free finishing. Publication Order Number: PACVGA200/D PACVGA200 Simplified Electrical Schematic VCC 1 VCC 2 2 12 VIDEO_2 VIDEO_3 3 DDC_IN1 4 5 14 16 15 TERM_2 TERM_3 GNDA 23 SYNC_OUT1 SD1 RB GNDD GNDD 11 GNDD 6 PWR_UP VCC 2 8 75 9 75 10 75 RC VCC 3 GNDD TERM_1 20 RS 1 19 SYNC_IN1 DDC_OUT1 GNDD GNDD VCC 4 D1 13 RC GNDD VIDEO_1 V_BIAS VCC 3 DDC_IN2 GNDD RC GNDD VCC 4 GNDD 1 17 18 SYNC_OUT2 DDC_OUT2 SYNC_IN2 21 24 GNDD 7 22 RS GNDD GNDD GNDA GNDD To p View V CC4 1 24 SD2 V CC1 2 23 SD1 VIDEO_1 3 22 SYNC_OUT2 VIDEO_2 4 21 SYNC_IN2 VIDEO_3 5 20 SYNC_OUT1 GNDD 6 19 SYNC_IN1 GNDA 7 18 DDC_OUT2 TERM_1 8 17 DDC_IN2 TERM_2 9 16 DDC_IN1 TERM_3 10 15 DDC_OUT1 PWR_UP 11 14 VCC 3 V CC2 12 13 V_BIAS 24-pin QSOP Rev. 2 | Page 2 of 10 | www.onsemi.com SD2 PACVGA200 Ordering Information PART NUMBERING INFORMATION Lead-free Finish Pins Package Ordering Part Number1 Part Marking 24 QSOP-24 PACVGA200QR PACVGA200QR Note 1: Parts are shipped in Tape & Reel form unless otherwise specified. PIN DESCRIPTIONS LEAD(s) NAME DESCRIPTION 1 VCC4 Positive voltage supply pin. This is an isolated VCC pin for the SYNC_1, SYNC_2, SD1 and SD2 circuits. 2 VCC1 Positive voltage supply pin. This is an isolated VCC pin for the VIDEO_1, VIDEO_2 and VIDEO_3 ESD circuits. 3-5 VIDEO_1, VIDEO_2, VIDEO_3 RGB Video Protection Channels. These pins tie to the RGB video lines (for example, the Blue signal) between the VGA controller device and the video connector. 6 GNDD Digital Ground reference supply pin. 7 GNDA Ground reference supply pin for TERM_1, TERM_2 and TERM_3 pins. 8-10 TERM_1, TERM_2, TERM_3 11 PWR_UP 12 VCC2 13 V_BIAS 14 VCC3 15 DDC_OUT1 DDC Signal Output 1. Connects to the connector side of one of the DDC signals (for example, the bidirectional DDC_Data serial line). 16 DDC_IN1 DDC Signal Input 1. Connects to the VGA Controller side of one of the DDC signals (for example, the bidirectional DDC_Data serial line). 17 DDC_IN2 DDC Signal Input 2. Connects to the VGA Controller side of one of the DDC signals (for example, the bidirectional DDC_Clk). RGB Video Termination Channels. These pins tie to the RGB video lines (for example, the Blue signal) providing a 75Ω termination to GNDA for the given video channel. Sync Signal Output 1. Ties to the video connector side of one of the sync lines (for example the Horizontal Sync signal). Positive voltage supply pin. This is an isolated VCC pin for the DDC_IN1 and DDC_IN2 input circuits. Defines the logic one level for the DDC_OUTn outputs. Used to derive VCC3 from VCC4 input. Positive voltage supply pin. This is an isolated VCC pin for the DDC_OUT1 and DDC_OUT2 ESD protection circuits. Rev. 2 | Page 3 of 10 | www.onsemi.com PACVGA200 LEAD(s) NAME DESCRIPTION 18 DDC_OUT2 DDC Signal Output 2. Connects to the connector side of one of the DDC signals (for example, the bidirectional DDC_Clk). 19 SYNC_IN1 Sync Signal Buffer Input 1. Connects to the VGA Controller side of one of the sync lines (for example, the Horizontal Sync signal). 20 SYNC_OUT1 21 SYNC_IN2 22 SYNC_OUT2 Sync Signal Buffer Output 2. Connects to the video connector side of one of the sync lines (for example the Vertical Sync signal). 23 SD1 Sync Signal Filter 1. Connects to the video connector side of one of the sync lines (for example the Vertical Sync signal). 24 SD2 Sync Signal Filter 2. Connects to the video connector side of one of the sync lines (for example the Horizontal Sync signal). Sync Signal Buffer Output 1. Connects to the video connector side of one of the sync lines (for example the Horizontal Sync signal). Sync Signal Buffer Input 2. Connects to the VGA Controller side of one of the sync lines (for example, the Vertical Sync signal). Specifications ABSOLUTE MAXIMUM RATINGS PARAMETER RATING UNITS [GND - 0.5] to +6.0 V 100 μA -65 to +150 °C (GND - 0.5) to (VCC1 + 0.5) -6.0, +6.0 (GND - 0.5) to (VCC2 + 0.5) (GND - 0.5) to (VCC3 + 0.5) (GND - 0.5) to (VCC4 + 0.5) V V V V V 1000 mW PARAMETER RATING UNITS Operating Temperature Range 0 to +70 °C VCC1,VCC2,VCC3, and VCC4 Supply Voltage Diode D1 Forward DC Current Storage Temperature Range DC Voltage at Inputs VIDEO_1, VIDEO_2, VIDEO_3 TERM_1, TERM_2, TERM_3 DDC_IN1, DDC_IN2 DDC_OUT1, DDC_OUT2 SYNC_IN1, SYNC_IN2 Package Power Rating STANDARD OPERATING CONDITIONS Rev. 2 | Page 4 of 10 | www.onsemi.com PACVGA200 ELECTRICAL OPERATING CHARACTERISTICS (SEE NOTE 1) SYMBOL PARAMETER CONDITIONS ICC1 VCC1 Supply Current ICC2, ICC3 ICC4 MIN TYP MAX UNITS VCC1 = 5.0V, VIDEO inputs at VCC1 or GND level 10 μA VCC2 & VCC3 Supply Current VCC2 = VCC3 = 5.0V 10 μA VCC4 Supply Current VCC4 = 5.0V; SYNC inputs at GND or VCC4 level; PWR-UP pin at VCC4; SYNC outputs unloaded 10 μA VCC4 = 5.0V; SYNC inputs at 3.0V; PWR-UP pin at VCC4; SYNC outputs unloaded 200 μA VCC4 = 5.0V; PWR-UP input at GND; SYNC outputs unloaded VBIAS RT VBIAS Open Circuit Voltage 10 No external current drawn from VBIAS pin Video Termination Resistance VCC4-0.8 71.25 RT Resistance Matching VIH Logic High Input Voltage VCC4 = 5.0V; See Note 2 VIL Logic Low Input Voltage VCC4 = 5.0V; See Note 2 VOH Logic High Output Voltage IOH = -4mA, VCC4 = 5.0V; See Note 2 VOL Logic Low Output Voltage IOL = 4mA, VCC4 = 5.0V; See Note 2 ROH Output Resistance See Note 2 ROL RB,RP μA V 75 78.75 Ω 1 2 % 2.0 V 0.8 V 4.5 4.8 V 0.18 0.32 V 50 125 Ω 45 80 Ω Resistor Value PWR_UP = VCC3 = 5.0V 0.5 1.0 2.0 MΩ RC VCC2 Pull-down Resistor Value VCC2 = 3.0V 0.5 1.5 3.0 MΩ IN Input Current VIDEO inputs HSYNC, VSYNC inputs VCC1= 5.0V; VIN = VCC1 or GND VCC4 = 5.0V; VIN = VCC4 or GND +1 +1 μA μA Off-state Leakage Current, Level-shifting NFET (VCC2 - VDDC_IN) < 0.4V; VDDC_OUT = VCC2 (VCC2 - VDDC_OUT) < 0.4V; VDDC_IN = VCC2 10 10 μA μA IOFF Rev. 2 | Page 5 of 10 | www.onsemi.com PACVGA200 SYMBOL PARAMETER CONDITIONS VON Voltage drop across level shifting NFET when turned ON VCC2= 2.5V; VS = GND; IDS = 3mA CIN Input Capacitance VIDEO_1,VIDEO_2 & VIDEO_3 inputs VCC1 = 5.0V; VIN = 2.5V; measured at 1MHz VCC1 = 2.5V; VIN = 1.25V; measured at 1MHz MIN 3.0 3.0 TYP MAX UNITS 0.15 V 4.0 4.5 5.0 5.6 pF pF tPLH SYNC Drivers L => H Propagation Delay CL = 50pF; VCC=5.0V,Input tR and tF < 5ns 8.0 12.0 ns tPHL SYNC Drivers H => L Propagation Delay CL = 50pF; VCC=5.0V; Input tR and tF < 5ns 8.0 12.0 ns tR, tF SYNC Drivers Output Rise & Fall Times CL = 50pF; VCC=5.0V; Input tR and tF < 5ns (measured 10% - 90%) 5.0 7.0 10.0 ns VESD ESD Withstand Voltage VCC1 = VCC3 = VCC4 = 5V; Note 3 ±8 kV Note 1: All parameters specified over standard operating conditions unless otherwise noted. Note 2: This parameter applies only to the HSYNC and VSYNC channels. HSYNC and VSYNC have 8mA drivers with RS added in series to terminate transmission line. Note 3: Per the IEC-61000-4-2 International ESD Standard, Level 4 contact discharge method. VCC1, VCC3 and VCC4 must be bypassed to GND via a low impedance ground plane with a 0.2uF, low inductance, chip ceramic capacitor at each supply pin. ESD pulse is applied between the applicable pins and GND. ESD pulse can be positive or negative with respect to GND. Applicable pins are: VIDEO_1, VIDEO_2, VIDEO_3, SYNC_OUT1, SD1, SYNC_OUT2, SD2, DDC_OUT1 and DDC_OUT2. All other pins are ESD protected to the industry standard 2kV per the Human Body Model (MIL-STD-883, Method 3015). Rev. 2 | Page 6 of 10 | www.onsemi.com PACVGA200 Test Circuit Information Average Current through VCC4 (ICC4) The circuit in Figure 1 was used to characterize ICC4 current as SYNC_IN signal frequency varies. A square wave signal was connected to the input of one of the SYNC buffers (i.e. pin 19 or pin 21). The frequency of this signal was varied between 0 and 100 kHz. The risetime and falltime was kept constant at 10ns. Three different values of C1 were used: 0pF, 50pF and 100pF. The results are plotted in Figure 2. VCC 4 +5V ICC 4 3.3V SYNC_IN SYNC_OUT 0V C1 Figure 1. Sync Buffer ICC4 Test Circuit Figure 2. ICC4 vs. SYNC_IN Frequency Performance Data Rev. 2 | Page 7 of 10 | www.onsemi.com PACVGA200 Application Information Figure 3. Typical Connection Diagram A resistor may be necessary between the VCC3 pin and ground if protection against a stream of ESD pulses is required while the PACVGA200 is in the power-down state. The value of this resistor should be chosen such that the extra charge deposited into the VCC3 bypass capacitor by each ESD pulse will be discharged before the next ESD pulse occurs. The maximum ESD repetition rate specified by the IEC-61000-4-2 standard is one pulse per second. When the PACVGA200 is in the power-up state, an internal discharge resistor is connected to ground via an FET switch for this purpose. For the same reason, VCC1 and VCC4 may also require bypass capacitor discharging resistors to ground if there are no other components in the system to provide a discharge path to ground. GNDA, the reference voltage for the 75Ω resistors is not connected internally to GNDD and should ideally be connected to the ground of the video DAC IC. Rev. 2 | Page 8 of 10 | www.onsemi.com PACVGA200 Mechanical Details QSOP Mechanical Specifications: PACVGA200 devices are packaged in 24-pin QSOP packages. Dimensions are presented below. For complete information on the QSOP-24 package, see the California Micro Devices QSOP Package Information document. PACKAGE DIMENSIONS Package QSOP (JEDEC name is SSOP) Pins 24 Millimeters Inches Dimensions Min Max Min Max A 1.35 1.75 0.053 0.069 A1 0.10 0.25 0.004 0.010 B 0.20 0.30 0.008 0.012 C 0.18 0.25 0.007 0.010 D 8.56 8.73 0.337 0.344 E 3.81 3.98 0.150 0.157 e 0.64 BSC 0.025 BSC H 5.79 6.19 0.228 0.244 L 0.40 1.27 0.016 0.050 # per tube 55 pcs* # per tape and reel 2500 pcs Package Dimensions for QSOP-24 Controlling dimension: inches * This is an approximate number which may vary. Rev. 2 | Page 9 of 10 | www.onsemi.com PACVGA200 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. 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This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: [email protected] N. American Technical Support: 800-282-9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81-3-5773-3850 Rev. 2 | Page 10 of 10 | www.onsemi.com ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative