PRELIMINARY CM2006 VGA Port Companion Circuit For Monitors Features Product Description • The CM2006 connects between the VGA or DVI-I port connector and the internal analog or digital flat panel controller logic. The CM2006 incorporates ESD protection for all signals, level shifting for the DDC signals and buffering for the SYNC signals. ESD protection for the video, DDC and SYNC lines is implemented with low-capacitance current steering diodes. • • • • • • • • Includes ESD protection, level-shifting, buffering and sync impedance matching VESA VSIS Version 1 Revision 2 Compatible Interface Supports Optional NAVI Signalling requirements 7 channels of ESD protection for all VGA port connector pins meeting IEC-61000-4-2 Level 4 ESD requirements (±8kV contact discharge) Very low loading capacitance from ESD protection diodes on VIDEO lines, 3pF maximum Schmitt triggered input buffers for HSYNC and VSYNC lines Bi-directional level shifting N-channel FETs provided for DDC_CLK & DDC_DATA channels Backdrive protection on all lines Compact 16-lead QSOP package All connector interface pins are designed to safely handle the high current spikes specified by IEC-61000-4-2 Level 4 (±8kV contact discharge). The ESD protection for the DDC, SYNC and VIDEO signal pins is designed to prevent "back current" when the device is powered down while connected to a video source that is powered up. Separate positive supply rails are provided for the VIDEO / SYNC signals and DDC signals to facilitate interfacing with low voltage video controller ICs and microcontrollers to provide design flexibility in multisupply-voltage environments. Applications • VGA and DVI-I ports in: - Monitors - Set Top Boxes Two Schmitt-Triggered non-inverting buffers redrive and condition the HSYNC and VSYNC signals from the video Connector (SYNC1, SYNC2). These buffers accept VESA VSIS compliant TTL input signals and convert them to CMOS output levels that swing between Ground and VCC. (cont’d next page) Simplified Electrical Schematic VCC_DDC VCC BYP 1 8 11 7 VIDEO_1 VIDEO_2 VIDEO_3 GND DDC_IN1 DDC_IN2 ENABLE SYNC_IN1 SYNC_IN2 10 DDC_OUT1 DDC_OUT2 3 4 RT RT 5 6 16 9 14 GND SYNC_OUT2 SYNC_OUT1 12 2 13 15 © 2006 California Micro Devices Corp. All rights reserved. 02/21/06 490 N. McCarthy Blvd., Milpitas, CA 95035-5112 ● Tel: 408.263.3214 ● Fax: 408.263.7846 ● www.cmd.com 1 PRELIMINARY CM2006 Product Description (cont’d) Two N-channel MOSFETs provide the level shifting function required when the DDC controller or EDID EEPROM is operated at a lower supply voltage than the monitor. The gate terminals for these MOSFETS (VCC_DDC) should be connected to the supply rail (typically 3.3V, 2.5V etc.) that supplies power to the transceivers of the DDC controller. PACKAGE / PINOUT DIAGRAM Top View VCC 1 16 SYNC_OUT2 ENABLE 2 15 SYNC_IN2 VIDEO_1 3 14 SYNC_OUT1 VIDEO_2 4 13 SYNC_IN1 VIDEO_3 5 12 DDC_IN2 GND 6 11 DDC_OUT2 VCC_DDC 7 10 DDC_OUT1 BYP 8 9 DDC_IN1 16 Pin QSOP Note: This drawing is not to scale. PIN DESCRIPTIONS LEAD(s) NAME 1 VCC DESCRIPTION This is a supply input for the SYNC_1 and SYNC_2 level shifters, video protection and the DDC circuits. 2 ENABLE Active high enable. Disables the Sync buffer outputs when low. 3 VIDEO_1 Video signal ESD protection channel. This pin is typically tied one of the video lines between the controller device and the video connector. 4 VIDEO_2 Video signal ESD protection channel. This pin is typically tied one of the video lines between the controller device and the video connector. 5 VIDEO_3 Video signal ESD protection channel. This pin is typically tied one of the video lines between the controller device and the video connector. 6 GND 7 VCC_DDC 8 BYP 9 DDC_IN1 10 DDC_OUT1 11 DDC_OUT DDC signal output. Connects to the monitor DDC logic. 12 DDC_IN2 DDC signal input. Connects to the video connector side of one of the DDC lines 13 SYNC_IN1 14 SYNC_OUT1 15 SYNC_IN2 16 SYNC_OUT2 Ground reference supply pin. This is an isolated supply input for the DDC_1 and DDC_2 level-shifting N-FET gates. An external 0.22uF bypass capacitor is required on this pin. DDC signal input. Connects to the video connector side of one of the DDC lines.signal output. DDC signal output. Connects to the monitor DDC logic. Sync signal buffer input. Connects to the video connector side of one of the sync lines. Sync signal buffer output. Connects to the monitor SYNC logic. Sync signal buffer input. Connects to the video connector side of one of the sync lines. Sync signal buffer output. Connects to the monitor SYNC logic. © 2006 California Micro Devices Corp. All rights reserved. 2 490 N. McCarthy Blvd., Milpitas, CA 95035-5112 ● Tel: 408.263.3214 ● Fax: 408.263.7846 ● www.cmd.com 02/21/06 PRELIMINARY CM2006 Ordering Information PART NUMBERING INFORMATION Standard Finish Lead-free Finish Pins Package Ordering Part Number1 Part Marking Ordering Part Number1 Part Marking 16 QSOP CM2006-02QS CM2006-02QS CM2006-02QR CM2006-02QR Note 1: Parts are shipped in Tape & Reel form unless otherwise specified. Specifications ABSOLUTE MAXIMUM RATINGS PARAMETER RATING UNITS [GND - 0.5] to +6.0 V [GND - 0.5] to [VCC + 0.5] [GND - 0.5] to 6.0 [GND - 0.5] to 6.0 [GND - 0.5] to [VCC + 0.5] V V V V Operating Temperature Range -40 to +85 °C Storage Temperature Range -40 to +150 °C 500 mW RATING UNITS -40 to +85 °C 5 V VCC_DDC and VCC Supply Voltage Inputs DC Voltage at Inputs VIDEO_1, VIDEO_2, VIDEO_3 DDC_IN1, DDC_IN2 DDC_OUT1, DDC_OUT2 SYNC_IN1, SYNC_IN2, ENABLE Package Power Rating (TA=25°C) STANDARD OPERATING CONDITIONS PARAMETER Operating Temperature Range VCC © 2006 California Micro Devices Corp. All rights reserved. 02/21/06 490 N. McCarthy Blvd., Milpitas, CA 95035-5112 ● Tel: 408.263.3214 ● Fax: 408.263.7846 ● www.cmd.com 3 PRELIMINARY CM2006 Specifications ELECTRICAL OPERATING CHARACTERISTICS (SEE NOTE 1) SYMBOL ICC_DDC ICC PARAMETER CONDITIONS VCC_DDC Supply Current VCC_DDC = 5.0V MIN TYP 10 μA VCC Supply Current VCC = 5V; SYNC inputs at GND or VCC; SYNC outputs unloaded 1 mA 2.0 mA 1.0 V VCC = 5V; SYNC inputs at 3.0V; SYNC outputs unloaded VF ESD Diode Forward Voltage IF = 10mA VIH Logic High Input Voltage VCC = 5.0V; Note 2 VIL 2.0 Logic Low Input Voltage VCC = 5.0V; Note 2 VHYS Hysteresis Voltage VCC = 5.0V; Note 2 VOH Logic High Output Voltage IOH = 0mA, VCC = 5.0V; Note 2 VOL Logic Low Output Voltage IOL = 0mA, VCC = 5.0V; Note 2 SYNC Driver Output Resistance VCC = 5.0V; SYNC Inputs at GND or 3.0V Input Current VIDEO Inputs ROUT IIN SYNC_IN1, SYNC_IN2 Inputs IOFF Level Shifting N-MOSFET "OFF" State Leakage Current Voltage Drop Across Level-shifting N-MOSFET when "ON" CIN_VID VIDEO Input Capacitance V 0.5 400 V mV 4.0 V 0.15 V 24 Ω VCC = 5.0V; VIN = VCC or GND ±10 μA VCC = 5.0V; VIN = VCC or GND ±10 μA (VCC_DDC - VDDC_IN) < 0.4V; VDDC_OUT = VCC_DDC 10 μA 10 μA 7 15 (VCC_DDC - VDDC_OUT) < 0.4V; VDDC_IN = VCC_DDC IBACKDRIVE Current conducted from input pins when Vcc VCC < VINPUT_PIN ; Note 6 is powered down. VON MAX UNITS μA 10 VCC_DDC = 2.5V; VS = GND; IDS = 3mA; 0.18 V VCC = 5.0V; VIN = 2.5V; f = 1MHz; Note 4 3 pF VCC = 2.5V; VIN = 1.25V; f = 1MHz; Note 4 3.5 pF tPLH SYNC Driver L => H Propagation Delay CL = 50pF; VCC = 5.0V; Input tR and tF < 5ns 12 ns tPHL SYNC Driver H => L Propagation Delay CL = 50pF; VCC = 5.0V; Input tR and tF < 5ns 12 ns tR, tF SYNC Driver Output Rise & Fall Times CL = 50pF; VCC = 5.0V; Input tR and tF < 5ns VESD1 ESD Withstand Voltage, Sync_out pins only VCC = 5V; Notes 3, 4, & 5 ±2 kV VESD ESD Withstand Voltage VCC = 5V; Notes 3, 4, & 6 ±8 kV 3 ns Note 1: All parameters specified over standard operating conditions unless otherwise noted Note 2: These parameters apply only to the SYNC drivers. Note that ROUT = RT + RBUFFER. Note 3: Per the IEC-61000-4-2 International ESD Standard, Level 4 contact discharge method. BYP and VCC must be bypassed to GND via a low impedance ground plane with a 0.22μF, low inductance, chip ceramic capacitor at each supply pin. ESD pulse is applied between the applicable pins and GND. ESD pulses can be positive or negative with respect to GND. Applicable pins are: VIDEO_1, VIDEO_2, VIDEO_3, SYNC_IN1, SYNC_IN2, DDC_IN1 and DDC_IN2. All pins are ESD protected to the industry standard ±2kV Human Body Model (MIL-STD-883, Method 3015). Note 4: This parameter is guaranteed by design and characterization. Note 5: This specification applies to the SYNC_OUT pins only. Note 6: Applicable pins are: VIDEO_1, VIDEO_2, VIDEO_3, SYNC_IN1, SYNC_IN2, DDC_IN1 and DDC_IN2. © 2006 California Micro Devices Corp. All rights reserved. 4 490 N. McCarthy Blvd., Milpitas, CA 95035-5112 ● Tel: 408.263.3214 ● Fax: 408.263.7846 ● www.cmd.com 02/21/06 PRELIMINARY CM2006 Application Information VCC_5V Optional EMI Filters VSYNC HSYNC C11 FB4 C12 C9 FB3 C10 0.22uF VSYNC ENABLE HSYNC VCC SYNC_IN1 SYNC_OUT1 DDCA_CLK DDCA_DATA C7 C5 FB2 FB1 C8 C6 SYNC_IN2 SYNC_OUT2 R R DDC_IN1 DDC_OUT1 DDC_CLK DDC_IN2 DDC_OUT2 DDC_DATA CM2006 RED_VIDEO VF** GREEN_VIDEO VF** VIDEO_2 BLUE_VIDEO VF** VIDEO_3 VIDEO_1 BYP RED 0.22uF GREEN BLUE VCC_DDC ** VIDEO Filters. 75 VCC_GPIO Video Port Connector 75 75 Figure 1. Typical Application Connection Diagram NOTES 1 The CM2006 should be placed as close to the VGA or DVI-I connector as possible. 2 The ESD protection channels VIDEO_1, VIDEO_2, VIDEO_3 may be used interchangeably between the R, G, B signals. 3 If differential video signal routing is used, the RED, BLUE, and GREEN signal lines should be terminated with external 37.5 ohm resistors. 4 "VF" are external video filters for the RGB signals. 5 Supply bypass capacitors C1 and C2 must be placed immediately adjacent to the corresponding Vcc pins. Connections to the Vcc pins and ground plane must be made with minimal length copper traces (preferably less than 5mm) for best ESD protection. 6 The bypass capacitor for the BYP pin has been omitted in this diagram. This results in a reduction in the maximum ESD withstand voltage at the DDC_OUT pins from ±8kV to ±2kV. If 8kV ESD protection is required, a 0.22μF ceramic bypass capacitor should be connected between BYP and ground. 7 The SYNC buffers may be used interchangeably between HSYNC and VSYNC. 8 The EMI filters at the SYNC_OUT and DDC_OUT pins (C5 to C12, and Ferrite Beads FB1 to FB4) are for reference only. The component values and filter configuration may be changed to suit the application. 9 The DDC level shifters DDC_IN, DDC_OUT, may be used interchangeably between DDCA_CLK and DDCA_DATA. 10 R1, R2 are optional. They may be used, if required, to pull the DDC_CLK and DDC_DATA lines to VCC_5V when no monitor is connected to the VGA connector. If used, it should be noted that "back current" may flow between the DDC pins and VCC_5V via these resistors when VCC_5V is powered down. © 2006 California Micro Devices Corp. All rights reserved. 02/21/06 490 N. McCarthy Blvd., Milpitas, CA 95035-5112 ● Tel: 408.263.3214 ● Fax: 408.263.7846 ● www.cmd.com 5 PRELIMINARY CM2006 Mechanical Details QSOP Mechanical Specifications Mechanical Package Diagrams CM2006 devices are packaged in 16-pin QSOP packages. Dimensions are presented below. For complete information on the QSOP-16 package, see the California Micro Devices QSOP Package Information document. TOP VIEW D 16 15 14 13 12 11 10 9 PACKAGE DIMENSIONS Package Pins Dimensions H QSOP (JEDEC name is SSOP) 16 Millimeters Inches Min Max Min Max A 1.35 1.75 0.053 0.069 A1 0.10 0.25 0.004 0.010 B 0.20 0.30 0.008 0.012 C 0.18 0.25 0.007 0.010 D 4.80 5.00 0.189 0.197 E 3.81 3.98 0.150 0.157 e E Pin 1 Marking 0.64 BSC 1 2 3 4 5 6 7 8 SIDE VIEW A A1 SEATING PLANE B e 0.025 BSC H 5.79 6.19 0.228 0.244 L 0.40 1.27 0.016 0.050 # per tube 100 pcs* # per tape and reel 2500 pcs END VIEW C Controlling dimension: inches L * This is an approximate number which may vary. Package Dimensions for QSOP-16 © 2006 California Micro Devices Corp. All rights reserved. 6 490 N. McCarthy Blvd., Milpitas, CA 95035-5112 ● Tel: 408.263.3214 ● Fax: 408.263.7846 ● www.cmd.com 02/21/06