CM2009 VGA Port Companion Circuit Features Product Description • The CM2009 connects between a video graphics controller embedded in a PC, graphics adapter card or set top box and the VGA or DVI-I port connector. The CM2009 incorporates ESD protection for all signals, level shifting for the DDC signals and buffering for the SYNC signals. ESD protection for the video, DDC and SYNC lines is implemented with low-capacitance current steering diodes. • • • • • • • Includes ESD protection, level-shifting, buffering and sync impedance matching 7 channels of ESD protection for all VGA port connector pins meeting IEC-61000-4-2 Level 4 ESD requirements (±8kV contact discharge) Very low loading capacitance from ESD protection diodes on VIDEO lines, 4pF maximum 5V drivers for HSYNC and VSYNC lines Integrated impedance matching resistors on sync lines Bi-directional level shifting N-channel FETs provided for DDC_CLK & DDC_DATA channels Backdrive protection on DDC lines Compact 16-lead QSOP package Applications • All ESD diodes are designed to safely handle the high current spikes specified by IEC-61000-4-2 Level 4 (±8KV contact discharge if CBYP is present, ±4KV if not). The ESD protection for the DDC signal pins are designed to prevent "back current" when the device is powered down while connected to a monitor that is powered up. Separate positive supply rails are provided for the VIDEO, DDC and SYNC channels to facilitate interfacing with low voltage video controller ICs to provide design flexibility in multi-supply-voltage environments. VGA and DVI-I ports in: - Desktop and Notebook PCs - Graphics Cards - Set Top Boxes (cont’d next page) Simplified Electrical Schematic 9 VCC_VIDEO 2 12 VCC_DDC 7 VIDEO_1 VIDEO_2 VIDEO_3 GND VCC_SYNC BYP 8 1 3 4 5 RT 6 RT 16 14 DDC_IN1 DDC_IN2 SYNC_IN1 SYNC_IN2 DDC_OUT1 DDC_OUT2 10 GND SYNC_OUT2 SYNC_OUT1 11 13 15 © 2004 California Micro Devices Corp. All rights reserved. 08/12/04 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 ▲ Tel: 408.263.3214 ▲ Fax: 408.263.7846 ▲ www.calmicro.com 1 CM2009 Product Description (cont’d) Two non-inverting drivers provide buffering for the HSYNC and VSYNC signals from the video controller IC (SYNC1, SYNC2). These buffers accept TTL input levels and convert them to CMOS output levels that swing between Ground and VCC_SYNC, which is typically 5V. Additionally, each driver has a series termination resistor (RT) connected to the SYNC_OUT pin, eliminating the external termination resistors typically required for the HSYNC and VSYNC lines of the video cable. There are three versions with different values of RT to allow termination at typically 65Ω (CM2009-00) or 55Ω (CM2009-01) or 15Ω (CM2009-02). The 15Ω (CM2009-02) version will typically require two external resistors which can be chosen to exactly match the characteristic impedance of the SYNC lines of the video cable. Two N-channel MOSFETs provide the level shifting function required when the DDC controller is operated at a lower supply voltage than the monitor. The gate terminals for these MOSFETS (VCC_DDC) should be connected to the supply rail (typically 3.3V) that supplies power to the transceivers of the DDC controller. PACKAGE / PINOUT DIAGRAM Top View VCC_SYNC 1 16 SYNC_OUT2 VCC_VIDEO 2 15 SYNC_IN2 VIDEO_1 3 14 SYNC_OUT1 VIDEO_2 4 13 SYNC_IN1 VIDEO_3 5 12 DDC_OUT2 GND 6 11 DDC_IN2 VCC_DDC 7 10 DDC_IN1 BYP 8 9 DDC_OUT1 16 Pin QSOP Note: This drawing is not to scale. Ordering Information PART NUMBERING INFORMATION Standard Finish Lead-free Finish ROUT Pins Package Ordering Part Number1 Part Marking Ordering Part Number1 65Ω 16 QSOP CM2009-00QS CM2009-00QS CM2009-00QR CM2009-00QR 55Ω 16 QSOP CM2009-01QS CM2009-01QS CM2009-01QR CM2009-01QR 15Ω 16 QSOP CM2009-02QS CM2009-02QS CM2009-02QR CM2009-02QR Part Marking Note 1: Parts are shipped in Tape & Reel form unless otherwise specified. © 2004 California Micro Devices Corp. All rights reserved. 2 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 ▲ Tel: 408.263.3214 ▲ Fax: 408.263.7846 ▲ www.calmicro.com 08/12/04 CM2009 Pin Description PIN DESCRIPTIONS LEAD(s) NAME 1 VCC_SYNC DESCRIPTION This is an isolated supply input for the SYNC_1 and SYNC_2 level shifters and their associated ESD protection circuits. 2 VCC_VIDEO This is a supply pin specifically for the VIDEO_1, VIDEO_2 and VIDEO_3 ESD protection circuits. 3 VIDEO_1 Video signal ESD protection channel. This pin is typically tied one of the video lines between the VGA controller device and the video connector. 4 VIDEO_2 Video signal ESD protection channel. This pin is typically tied one of the video lines between the VGA controller device and the video connector. 5 VIDEO_3 Video signal ESD protection channel. This pin is typically tied one of the video lines between the VGA controller device and the video connector. 6 GND 7 VCC_DDC 8 BYP 9 DDC_OUT1 10 DDC_IN1 DDC signal input. Connects to the VGA controller side of one of the sync lines. 11 DDC_IN2 DDC signal input. Connects to the VGA controller side of one of the sync lines. 12 DDC_OUT2 DDC signal output. Connects to the video connector side of one of the sync lines. 13 SYNC_IN1 Sync signal buffer input. Connects to the VGA controller side of one of the sync lines. 14 SYNC_OUT1 15 SYNC_IN2 16 SYNC_OUT2 Ground reference supply pin. This is an isolated supply input for the DDC_1 and DDC_2 level-shifting N-FET gates. This input is used to connect an external 0.2uF bypass capacitor to the DDC circuits, resulting in an increased ESD withstand voltage rating for these circuits (±8kV with vs. ±4kV without). DDC signal output. Connects to the video connector side of one of the sync lines. Sync signal buffer output. Connects to the video connector side of one of the sync lines. Sync signal buffer input. Connects to the VGA controller side of one of the sync lines. Sync signal buffer output. Connects to the video connector side of one of the sync lines. Specifications ABSOLUTE MAXIMUM RATINGS PARAMETER RATING UNITS [GND - 0.5] to +6.0 V 10 mA [GND - 0.5] to [VCC_VIDEO + 0.5] [GND - 0.5] to 6.0 [GND - 0.5] to 6.0 [GND - 0.5] to [VCC_SYNC + 0.5] V V V V Operating Temperature Range -40 to +85 °C Storage Temperature Range -40 to +150 °C 500 mW VCC_VIDEO,VCC_DDC and VCC_SYNC Supply Voltage Inputs ESD Diode Forward Current (one diode conducting at a time) DC Voltage at Inputs VIDEO_1, VIDEO_2, VIDEO_3 DDC_IN1, DDC_IN2 DDC_OUT1, DDC_OUT2 SYNC_IN1, SYNC_IN2 Package Power Rating (TA=25°C) © 2004 California Micro Devices Corp. All rights reserved. 08/12/04 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 ▲ Tel: 408.263.3214 ▲ Fax: 408.263.7846 ▲ www.calmicro.com 3 CM2009 Specifications (cont’d) ELECTRICAL OPERATING CHARACTERISTICS (SEE NOTE 1) SYMBOL PARAMETER ICC_VIDEO VCC_VIDEO Supply Current CONDITIONS MIN TYP MAX UNITS VCC_VIDEO = 5.0V; VIDEO inputs at VCC_VIDEO or GND 10 µA ICC_DDC VCC_DDC Supply Current VCC_DDC = 5.0V 10 µA ICC_SYNC VCC_SYNC Supply Current VCC_SYNC = 5V; SYNC inputs at GND or VCC_SYNC; SYNC outputs unloaded 50 µA VCC_SYNC = 5V; SYNC inputs at 3.0V; SYNC outputs unloaded 2.0 mA 1.0 V VF ESD Diode Forward Voltage IF = 10mA VIH Logic High Input Voltage VCC_SYNC = 5.0V; Note 2 2.0 V VIL Logic Low Input Voltage VCC_SYNC = 5.0V; Note 2 VOH Logic High Output Voltage IOH = 0mA, VCC_SYNC = 5.0V; Note 2 VOL Logic Low Output Voltage IOL = 0mA, VCC_SYNC = 5.0V; Note 2 ROUT SYNC Driver Output Resistance (CM2009-00 only) VCC_SYNC = 5.0V; SYNC Inputs at GND or 3.0V 65 Ω ROUT SYNC Driver Output Resistance (CM2009-01 only) VCC_SYNC = 5.0V; SYNC Inputs at GND or 3.0V 55 Ω ROUT SYNC Driver Output Resistance (CM2009-02 only) VCC_SYNC = 5.0V; SYNC Inputs at GND or 3.0V; Note 5 15 Ω VOH-02 Logic High Output Voltage (CM2009-02 only) IOH = 24mA; VCC_SYNC = 5.0V; Note 2 VOL-02 Logic Low Output Voltage (CM2009-02 only) IOL = 24mA; VCC_SYNC = 5.0V; Note 2 IIN Input Current VIDEO Inputs SYNC_IN1, SYNC_IN2 Inputs IOFF Level Shifting N-MOSFET "OFF" State Leakage Current VON Voltage Drop Across Level-shifting N-MOSFET when "ON" CIN_VID VIDEO Input Capacitance V 0.15 V V 2.0 V 0.8 V VCC_VIDEO = 5.0V; VIN = VCC_VIDEO or GND ±1 µA VCC_SYNC = 5.0V; VIN = VCC_SYNC or GND ±1 µA (VCC_DDC - VDDC_IN) ≤ 0.4V; VDDC_OUT = VCC_DDC 10 µA 10 µA 0.18 V (VCC_DDC - VDDC_OUT) ≤ 0.4V; VDDC_IN = VCC_DDC VCC_DDC = 2.5V; VS = GND; IDS = 3mA; VCC_VIDEO = 5.0V; VIN = 2.5V; ƒ = 1MHz; Note 4 4 pF VCC_VIDEO = 2.5V; VIN = 1.25V; ƒ = 1MHz; Note 4 4.5 pF CL = 50pF; VCC = 5.0V; Input tR and tF ≤ 5ns 12 ns 12 ns tPLH SYNC Driver L => H Propagation Delay tPHL SYNC Driver H => L Propagation Delay CL = 50pF; VCC = 5.0V; Input tR and tF ≤ 5ns tR, tF SYNC Driver Output Rise & Fall Times CL = 50pF; VCC = 5.0V; Input tR and tF ≤ 5ns ESD Withstand Voltage VCC_VIDEO = VCC_SYNC = 5V; Notes 3, 4 & 5 VESD 0.6 4.85 4 ±8 ns kV Note 1: All parameters specified over standard operating conditions unless otherwise noted. Note 2: These parameters apply only to the SYNC drivers. Note that ROUT = RT + RBUFFER. Note 3: Per the IEC-61000-4-2 International ESD Standard, Level 4 contact discharge method. BYP, VCC_VIDEO and VCC_SYNC must be bypassed to GND via a low impedance ground plane with a 0.2µF, low inductance, chip ceramic capacitor at each supply pin. ESD pulse is applied between the applicable pins and GND. ESD pulses can be positive or negative with respect to GND. Applicable pins are: VIDEO_1, VIDEO_2, VIDEO_3, SYNC_OUT1, SYNC_OUT2, DDC_OUT1 and DDC_OUT2. All other pins are ESD protected to the industry standard ±2kV Human Body Model (MIL-STD-883, Method 3015). The bypass capacitor at the BYP pin may optionally be omitted, in which case the max. ESD withstand voltage for the DDC_OUT1 and DDC_OUT2 pins is reduced to ±4kV. Note 4: This parameter is guaranteed by design and characterization. Note 5: The SYNC_OUT pins on the CM2009-02 are guaranteed for 2kV HBM ESD protection. © 2004 California Micro Devices Corp. All rights reserved. 4 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 ▲ Tel: 408.263.3214 ▲ Fax: 408.263.7846 ▲ www.calmicro.com 08/12/04 CM2009 Application Information HSYNC VSYNC R1 100k R2 100k VCC_5V VCCA_DAC VCC_SYNC VCC_VIDEO C2 0.2uF SYNC_OUT2 C11 VSYNC_OUT C12 SYNC_GND SYNC_OUT1 C1 0.2uF FB4 SYNC_IN2 HSYNC_OUT C9 FB3 C10 C7 FB2 C8 SYNC_IN1 DDC_OUT2 RED DDC_IN2 GREEN DDC_IN1 BLUE DIG_GND DDC_CLK DDC_OUT1 C5 ** VIDEO Filters. See Note 4 VCCGPIO FB1 C6 CM2009 VF** 75 VF** 75 VF** 75 DDC_DATA Optional EMI Filters VIDEO_1 RED_VIDEO VIDEO_2 GREEN_VIDEO VIDEO_3 BLUE_VIDEO RED_GND VCC_DDC GREEN_GND BLUE_GND Video Port Connector DDCA_CLK DDCA_DATA Figure 1. Typical Application Connection Diagram NOTES 1 The CM2009 should be placed as close to the VGA or DVI-I connector as possible. 2 The ESD protection channels VIDEO_1, VIDEO_2, VIDEO_3 may be used interchangeably between the R, G, B signals. 3 If differential video signal routing is used, the RED, BLUE, and GREEN signal lines should be terminated with external 37.5 resistors. 4 "VF" are external video filters for the RGB signals. 5 Supply bypass capacitors C1 and C2 must be placed immediately adjacent to the corresponding Vcc pins. Connections to the Vcc pins and ground plane must be made with minimal length copper traces (preferably less than 5mm) for best ESD protection. 6 The bypass capacitor for the BYP pin has been omitted in this diagram. This results in a reduction in the maximum ESD withstand voltage at the DDC_OUT pins from ±8kV to ±4kV. If 8kV ESD protection is required, a 0.2µF ceramic bypass capacitor should be connected between BYP and ground. 7 The SYNC buffers may be used interchangeably between HSYNC and VSYNC. 8 The EMI filters at the SYNC_OUT and DDC_OUT pins (C5 to C12, and Ferrite Beads FB1 to FB4) are for reference only. The component values and filter configuration may be changed to suit the application. 9 The DDC level shifters DDC_IN, DDC_OUT, may be used interchangeably between DDCA_CLK and DDCA_DATA. 10 R1, R2 are optional. They may be used, if required, to pull the DDC_CLK and DDC_DATA lines to VCC_5V when no monitor is connected to the VGA connector. If used, it should be noted that "back current" may flow between the DDC pins and VCC_5V via these resistors when VCC_5V is powered down. 11 For optimal ESD performance with the CM2009-02, an additional clamp device (such as the CMD PACDN042) should be placed on HSYNC/VSYNC lines between the external matching resistor and the VGA connector. © 2004 California Micro Devices Corp. All rights reserved. 08/12/04 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 ▲ Tel: 408.263.3214 ▲ Fax: 408.263.7846 ▲ www.calmicro.com 5 CM2009 Mechanical Details QSOP Mechanical Specifications CM2009 devices are packaged in 16-pin QSOP packages. Dimensions are presented below. Mechanical Package Diagrams For complete information on the QSOP-16 package, see the California Micro Devices QSOP Package Information document. TOP VIEW D 16 15 14 13 12 11 10 9 PACKAGE DIMENSIONS Package Pins Dimensions H QSOP (JEDEC name is SSOP) 16 Millimeters Inches Min Max Min Max A 1.35 1.75 0.053 0.069 A1 0.10 0.25 0.004 0.010 B 0.20 0.30 0.008 0.012 C 0.18 0.25 0.007 0.010 D 4.80 5.00 0.189 0.197 E 3.81 3.98 0.150 0.157 e E Pin 1 Marking 0.64 BSC 1 2 3 4 5 6 7 8 SIDE VIEW A A1 SEATING PLANE B e 0.025 BSC H 5.79 6.19 0.228 0.244 L 0.40 1.27 0.016 0.050 # per tube 100 pcs* # per tape and reel 2500 pcs Controlling dimension: inches END VIEW C L * This is an approximate number which may vary. Package Dimensions for QSOP-16 © 2004 California Micro Devices Corp. All rights reserved. 6 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 ▲ Tel: 408.263.3214 ▲ Fax: 408.263.7846 ▲ www.calmicro.com 08/12/04