PACVGA100/101 VGA Port ESD Protection and Termination Network Features Product Description • • +15 kV ESD protection per channel, connector • +8 kV contact, 15 kV air discharge ESD protection • • per channel, connector side (IEC 61000-4-2 Level 4 standard) Low loading capacitance—4.5pF typical 16-pin QSOP package The PACVGA100/101 functions as a transmission line termination and ESD protection device for video applications. It provides 75 ohm parallel terminations for video R, G, and B lines and series terminations for the Horizontal Sync, Vertical Sync and the two DDC lines which serve as Plug and Play logic signals. In addition, all interface lines provide Level 4 ESD protection per the IEC 61000-4-2 contact discharge specification. The PACVGA100 provides internal pull-up resistors (R3) for the two DDC lines whereas the PACVGA101 omits these internal pull-ups so that different pull-up resistor values can be added externally. Seven channel ESD protection side (HBM) Applications • • • • ESD protection and termination resistors for VGA (video) port interfaces Desktop PCs Notebook computers LCD monitors Simplified Electrical Schematic Typical Application Circuit VCC R G B R1 R2 VCC Red Grn Blue H-Sync V-Sync 7 9 DDC_Data DDC_Clk 11 14 8 16 PACVGA100/101 Video Controller 1 2 3 5 4 CBYPASS 0.2uF Video Connector R1, R2 required only for VGA101 (See Note 1) 6 10 H-Sync V-Sync 12 15 DDC_Data DDC_Clk 13 Note 1: For best ESD protection, minimize R/G/B trace lengths between the PACVGA100/101 device and the video connector. R1 = 75Ω, R2 = 33Ω R3 = 2.2KΩ (for PACVGA100 only) * R3 omitted for PACVGA101 © 2002 California Micro Devices Corp. All rights reserved. 02/14/02 215 Topaz Street, Milpitas, California 95035 ▲ Tel: (408) 263-3214 ▲ Fax: (408) 263-7846 ▲ www.calmicro.com 1 PACVGA100/101 PACKAGE / PINOUT DIAGRAM Top View VCC 1 16 VCC RGB1 2 15 DDC2_CONN RGB2 3 14 DDC2_CTLR VSS 4 13 VSS RGB3 5 12 DDC1_CONN SYNC1_CONN 6 11 DDC1_CTLR SYNC1_CTLR 7 10 SYNC2_CONN VCC 8 9 SYNC2_CTLR 16-pin QSOP Note: This drawing is not to scale. PIN DESCRIPTIONS LEAD(s) NAME DESCRIPTION 1, 8, 16 VCC 2 RGB1 RGB Video Protection Channel 1. Ties to one of the RGB video lines (for example, the Red signal) between the VGA controller device and the video connector. 3 RGB2 RGB Video Protection Channel 2. Ties to one of the RGB video lines (for example, the Blue signal) between the VGA controller device and the video connector. 4, 13 VSS 5 RGB3 6 SYNC1_CONN Sync Signal Output 1. Ties to the video connector side of one of the sync lines (for example the Horizontal Sync signal). 7 SYNC1_CTLR Sync Signal Input 1. Connects to the VGA Controller side of one of the sync lines (for example, the Horizontal Sync signal). 9 SYNC2_CTLR Sync Signal Input 2. Connects to the VGA Controller side of one of the sync lines (for example, the Vertical Sync signal). 10 SYNC2_CONN Sync Signal Output 2. Connects to the video connector side of one of the sync lines (for example, the Vertical Sync signal). 11 DDC1_CTLR DDC Signal Input 1. Connects to the VGA Controller side of one of the DDC signals (for example, the bidirectional DDC_Data serial line). 12 DDC1_CONN DDC Signal Output 1. Connects to the connector side of one of the DDC signals (for example, the bidirectional DDC_Data serial line). 14 DDC2_CTLR DDC Signal Input 2. Connects to the VGA Controller side of one of the DDC signals (for example, the bidirectional DDC_Clk). 15 DDC2_CONN DDC Signal Output 2. Connects to the connector side of one of the DDC signals (for example, the bidirectional DDC_Clk). Positive voltage supply pins. Ground reference supply pin. RGB Video Protection Channel 3. Ties to one of the RGB video lines (for example, the Green signal) between the VGA controller device and the video connector. © 2002 California Micro Devices Corp. All rights reserved. 2 215 Topaz Street, Milpitas, California 95035 ▲ Tel: (408) 263-3214 ▲ Fax: (408) 263-7846 ▲ www.calmicro.com 02/14/02 PACVGA100/101 Ordering Information PART NUMBERING INFORMATION Pins Package Ordering Part Number1 Part Marking 16 QSOP PACVGA100 PACVGA100Q 16 QSOP PACVGA101 PACVGA101Q Note 1: Parts are shipped in Tape & Reel form unless otherwise specified. Specifications ABSOLUTE MAXIMUM RATINGS PARAMETER RATING UNITS Supply Voltage (VCC - VSS) 6.0 V Diode Forward DC Current (Note 1) 20 mA Operating Temperature Range -40 to +85 °C Storage Temperature Range -65 to +150 °C (V SS - 0.5) to (VCC + 0.5) V 800 mW RATING UNITS Operating Temperature Range -40 to +85 °C Operating Supply Voltage (VCC- VSS) PACVGA100 PACVGA101 5.0 3.3 to 5.0 V V DC Voltage at any channel input Package Power Rating Note 1: Only one diode conducting at a time. STANDARD OPERATING CONDITIONS PARAMETER © 2002 California Micro Devices Corp. All rights reserved. 02/14/02 215 Topaz Street, Milpitas, California 95035 ▲ Tel: (408) 263-3214 ▲ Fax: (408) 263-7846 ▲ www.calmicro.com 3 PACVGA100/101 Specifications (cont’d) ELECTRICAL OPERATING CHARACTERISTICS1 SYMBOL TOLR TCR VF PARAMETER MAX UNITS Resistor Absolute Tolerance R/G/B Termination Resistor (R1) Series Termination Resistor (R2) DDC Pull-up Resistor (R3) +5 +5 +10 % % % Temperature Coefficient of Resistance (TCR) +200 ppm/°C 0.95 V Diode Forward Voltage IF = 20mA Diode Reverse Breakdown Voltage Top Diode (Cathode connected to VCC) Bottom Diode (Anode connected to VSS) VRB ILEAK MIN Channel Input Capacitance at pins 2, 3, 5, 6, 10, 12 & 15 VESD ESD Protection 1) Peak Discharge Voltage at pins 2, 3, 5, 6 10, 12 & 15, in system a) Human Body Model, MIL-STD-883, Method 3015 b) Contact discharge per IEC 61000-4-2 2) Peak Discharge Voltage at pins 7, 9, 11 & 14 a) Human Body Model, MIL-STD-883, Method 3015 Channel Clamp Voltage at pins 2, 3, 5, 6, 10, 12 & 15 Positive Transients Negative Transients Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: TYP 0.65 17.0 25.0 Channel Leakage Current CIN VCP CONDITIONS @ 1 MHz, VP=5V, V N=0V, VIN=2.5V; Note 2 applies V V +0.1 +1.0 µA 4.5 6 pF Note 3 Notes 2,4 +15 kV Notes 2,5 +8 kV Note 6 Notes 2,4 +4 kV @15kV ESD HBM; Notes 2 & 4 VP + 13.0 VN - 13.0 V V All parameters specified at TA=25°C unless otherwise noted. These parameters guaranteed by design and characterization. From I/O pins to VP or VN only; VP bypassed to VN with 0.2µF ceramic capacitor. Human Body Model per MIL-STD-883, Method 3015, CDischarge = 100pF, R Discharge = 1.5KΩ, VP = 5.0V, VN grounded. Standard IEC 61000-4-2 with CDischarge = 150pF, RDischarge = 330Ω, VP = 5.0V, VN grounded. These pins are not directly connected to the VGA connector and therefore are not subject to direct ESD strikes. © 2002 California Micro Devices Corp. All rights reserved. 4 215 Topaz Street, Milpitas, California 95035 ▲ Tel: (408) 263-3214 ▲ Fax: (408) 263-7846 ▲ www.calmicro.com 02/14/02 PACVGA100/101 Mechanical Details QSOP Mechanical Specifications PACVGA100/101 devices are packaged in 16-pin QSOP packages. Dimensions are presented below. Mechanical Package Diagrams For complete information on the QSOP-16 package, see the California Micro Devices QSOP Package Information document. TOP VIEW D 16 15 14 13 12 11 10 9 PACKAGE DIMENSIONS Package QSOP (JEDEC name is SSOP) Pins Dimensions E Pin 1 Marking 16 Millimeters Inches Min Max Min Max A 1.35 1.75 0.053 0.069 A1 0.10 0.25 0.004 0.010 B 0.20 0.30 0.008 0.012 C 0.18 0.25 0.007 0.010 D 4.80 5.00 0.189 0.197 E 3.81 3.98 0.150 0.157 e H 0.64 BSC 1 2 3 4 5 6 7 8 SIDE VIEW A A1 SEATING PLANE B e 0.025 BSC H 5.79 6.19 0.228 0.244 L 0.40 1.27 0.016 0.050 # per tube 100 pieces* # per tape and reel 2500 pieces END VIEW C Controlling dimension: inches L * This is an approximate number which may vary. Package Dimensions for QSOP-16 © 2002 California Micro Devices Corp. All rights reserved. 02/14/02 215 Topaz Street, Milpitas, California 95035 ▲ Tel: (408) 263-3214 ▲ Fax: (408) 263-7846 ▲ www.calmicro.com 5