ONSEMI NTD3813NT4G

NTD3813N
Power MOSFET
16 V, 51 A, Single N-Channel, DPAK/IPAK
Features
•Low RDS(on) to Minimize Conduction Losses
•Low Capacitance to Minimize Driver Losses
•Optimized Gate Charge to Minimize Switching Losses
•Three Package Variations for Design Flexibility
•These are Pb-Free Devices
http://onsemi.com
V(BR)DSS
RDS(ON) MAX
ID MAX
8.75 mW @ 10 V
16 V
51 A
Applications
14.5 mW @ 4.5 V
•DC-DC Converters
•High Side Switching
D
MAXIMUM RATINGS (TJ = 25°C unless otherwise stated)
Value
Unit
VDSS
16
V
VGS
±16
V
ID
13.8
A
Continuous Drain
Current RqJA
(Note 1)
TA = 25°C
Power Dissipation
RqJA (Note 1)
TA = 25°C
PD
2.6
W
Continuous Drain
Current RqJA
(Note 2)
TA = 25°C
ID
9.6
A
Steady
State
10.7
TA = 85°C
1 2
7.4
1.2
W
Continuous Drain
Current RqJC
(Note 1)
TC = 25°C
ID
51
A
Power Dissipation
RqJC (Note 1)
TC = 25°C
PD
34.9
W
TA = 25°C
IDM
114
A
TA = 25°C
IDmaxPkg
35
A
TJ,
TSTG
-55 to
+175
°C
tp=10ms
Current Limited by Package
Operating Junction and Storage
Temperature
Source Current (Body Diode)
39
IS
29
A
Drain to Source dV/dt
dV/dt
6
V/ns
Single Pulse Drain-to-Source Avalanche
Energy (TJ = 25°C, VDD = 50 V, VGS = 10 V,
IL = 10 Apk, L = 0.3 mH, RG = 25 W)
EAS
15
mJ
Lead Temperature for Soldering Purposes
(1/8” from case for 10 s)
TL
1
3
PD
TC = 85°C
4
4
4
TA = 25°C
Pulsed Drain
Current
S
N-CHANNEL MOSFET
°C
260
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
CASE 369AA
DPAK
(Bent Lead)
STYLE 2
2 3
1
2
3
CASE 369AC
CASE 369D
3 IPAK
IPAK
(Straight Lead) (Straight Lead
DPAK)
MARKING DIAGRAMS
& PIN ASSIGNMENTS
4
Drain
4
Drain
4
Drain
YWW
38
13NG
Power Dissipation
RqJA (Note 2)
TA = 85°C
G
YWW
38
13NG
Gate-to-Source Voltage
Symbol
YWW
38
13NG
Parameter
Drain-to-Source Voltage
2
1 2 3
1 Drain 3
Gate Source Gate Drain Source 1 2 3
Gate Drain Source
Y
WW
3813N
G
= Year
= Work Week
= Device Code
= Pb-Free Package
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
© Semiconductor Components Industries, LLC, 2007
December, 2007 - Rev. 0
1
Publication Order Number:
NTD3813N/D
NTD3813N
THERMAL RESISTANCE MAXIMUM RATINGS
Symbol
Value
Unit
Junction-to-Case (Drain)
Parameter
RqJC
4.3
°C/W
Junction-to-TAB (Drain)
RqJC-TAB
3.6
Junction-to-Ambient – Steady State (Note 1)
RqJA
58
Junction-to-Ambient – Steady State (Note 2)
RqJA
121
1. Surface-mounted on FR4 board using 1 sq-in pad, 1 oz Cu.
2. Surface-mounted on FR4 board using the minimum recommended pad size.
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise specified)
Symbol
Test Condition
Min
Drain-to-Source Breakdown Voltage
V(BR)DSS
VGS = 0 V, ID = 250 mA
16
Drain-to-Source Breakdown Voltage
Temperature Coefficient
V(BR)DSS/
TJ
Parameter
Typ
Max
Unit
OFF CHARACTERISTICS
Zero Gate Voltage Drain Current
Gate-to-Source Leakage Current
IDSS
V
16.8
VGS = 0 V,
VDS = 16 V
mV/°C
TJ = 25°C
1.0
TJ = 125°C
10
IGSS
VDS = 0 V, VGS = ±16 V
VGS(TH)
VGS = VDS, ID = 250 mA
mA
±100
nA
2.5
V
ON CHARACTERISTICS (Note 3)
Gate Threshold Voltage
Negative Threshold Temperature
Coefficient
VGS(TH)/TJ
Drain-to-Source On Resistance
RDS(on)
Forward Transconductance
gFS
1.5
5.3
mV/°C
VGS = 10 V
ID = 15 A
7.2
8.75
VGS = 4.5 V
ID = 15 A
11
14.5
VDS = 1.5 V, ID = 15 A
40
mW
S
CHARGES AND CAPACITANCES
Input Capacitance
CISS
Output Capacitance
COSS
Reverse Transfer Capacitance
CRSS
191
Total Gate Charge
QG(TOT)
8.5
Threshold Gate Charge
QG(TH)
Gate-to-Source Charge
Gate-to-Drain Charge
Total Gate Charge
QGS
963
VGS = 0 V, f = 1.0 MHz, VDS = 12 V
pF
12.8
0.93
VGS = 4.5 V, VDS = 12 V, ID = 15 A
QGD
QG(TOT)
338
3.1
nC
3.8
VGS = 10 V, VDS = 12 V, ID = 15 A
16.7
nC
SWITCHING CHARACTERISTICS (Note 4)
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
td(ON)
tr
td(OFF)
12
VGS = 4.5 V, VDS = 12 V,
ID = 15 A, RG = 3.0 W
38
14
tf
5.0
td(ON)
8.0
tr
td(OFF)
VGS = 10 V, VDS = 12 V,
ID = 15 A, RG = 3.0 W
tf
33
20
8.0
3. Pulse Test: pulse width v 300 ms, duty cycle v 2%.
4. Switching characteristics are independent of operating junction temperatures.
5. Assume standoff of 110 mm.
http://onsemi.com
2
ns
ns
NTD3813N
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise specified)
Parameter
Symbol
Test Condition
Min
Typ
Max
TJ = 25°C
0.88
1.2
TJ = 125°C
0.76
Unit
DRAIN-SOURCE DIODE CHARACTERISTICS
Forward Diode Voltage
Reverse Recovery Time
Charge Time
Discharge Time
Reverse Recovery Charge
VSD
VGS = 0 V,
IS = 15 A
tRR
ta
tb
V
14.4
VGS = 0 V, dIS/dt = 100 A/ms,
IS = 15 A
6.8
ns
7.6
QRR
3.7
nC
Source Inductance
LS
2.49
nH
Drain Inductance, DPAK
LD
0.0164
Drain Inductance, IPAK (Note 5)
LD
PACKAGE PARASITIC VALUES
TA = 25°C
1.88
Gate Inductance
LG
3.46
Gate Resistance
RG
0.4
3. Pulse Test: pulse width v 300 ms, duty cycle v 2%.
4. Switching characteristics are independent of operating junction temperatures.
5. Assume standoff of 110 mm.
http://onsemi.com
3
W
NTD3813N
TYPICAL PERFORMANCE CURVES
45
45
ID, DRAIN CURRENT (AMPS)
40
4.5 V
35
3.8 V
3.6 V
30
25
3.4 V
20
15
3.2 V
10
3.0 V
2.8 V
5
0
0.5
1
1.5
2.5
2
3
20
15
TJ = 125°C
10
TJ = 25°C
5
TJ = -55°C
1
2
3
4
5
Figure 2. Transfer Characteristics
0.06
0.05
0.04
0.03
0.02
0.01
4
5
6
8
7
9
10
0.018
TJ = 25°C
0.016
VGS = 4.5 V
0.014
0.012
0.010
VGS = 10 V
0.008
0.006
0.004
5
10
15
20
25
30
35
40
VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)
ID, DRAIN CURRENT (AMPS)
Figure 3. On-Resistance vs. Gate-to-Source
Voltage
Figure 4. On-Resistance vs. Drain Current and
Gate Voltage
1.6
10000
VGS = 0 V
ID = 15 A
VGS = 10 V
IDSS, LEAKAGE (nA)
RDS(on), DRAIN-TO-SOURCE RESISTANCE
(NORMALIZED)
25
Figure 1. On-Region Characteristics
0.07
1.4
30
VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)
ID = 15 A
TJ = 25°C
3
35
VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
0.08
0
VDS ≥ 10 V
40
0
RDS(on), DRAIN-TO-SOURCE RESISTANCE (W)
0
RDS(on), DRAIN-TO-SOURCE RESISTANCE (W)
TJ = 25°C
4V
ID, DRAIN CURRENT (AMPS)
10 V
1.2
1.0
TJ = 175°C
1000
TJ = 125°C
100
0.8
0.6
-50
10
-25
0
25
50
75
100
125
150
175
5
7
9
11
13
15
TJ, JUNCTION TEMPERATURE (°C)
VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
Figure 5. On-Resistance Variation with
Temperature
Figure 6. Drain-to-Source Leakage Current
vs. Drain Voltage
http://onsemi.com
4
NTD3813N
1400
1300
1200
1100
1000
900
800
700
600
500
400
300
200
100
0
0
VGS , GATE-TO-SOURCE VOLTAGE (VOLTS)
C, CAPACITANCE (pF)
TYPICAL PERFORMANCE CURVES
VGS = 0 V
TJ = 25°C
Ciss
Coss
Crss
2
4
6
8
10
12
14
16
DRAIN-TO-SOURCE VOLTAGE (VOLTS)
10
QT
8
6
IS, SOURCE CURRENT (AMPS)
VDD = 12 V
ID = 15 A
VGS = 10 V
t, TIME (ns)
100
tr
td(off)
td(on)
tf
10
RG, GATE RESISTANCE (OHMS)
2
ID = 15 A
TJ = 25°C
0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
QG, TOTAL GATE CHARGE (nC)
100
15
14 VGS = 0 V
13 T = 25°C
J
12
11
10
9
8
7
6
5
4
3
2
1
0
0.4
0.5
100 ms
1
1 ms
10 ms
dc
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
0.1
0.1
1
10
100
VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
EAS, SINGLE PULSE DRAIN-TO-SOURCE
AVALANCHE ENERGY (mJ)
I D, DRAIN CURRENT (AMPS)
10 ms
VGS = 20 V
SINGLE PULSE
TC = 25°C
0.7
0.8
1.0
0.9
Figure 10. Diode Forward Voltage vs. Current
1000
10
0.6
VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS)
Figure 9. Resistive Switching Time
Variation vs. Gate Resistance
100
Q2
Figure 8. Gate-To-Source and Drain-To-Source
Voltage vs. Total Charge
1000
1
1
Q1
4
Figure 7. Capacitance Variation
10
VGS
15
ID = 10 A
12.5
10
7.5
5.0
2.5
0
25
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
50
75
100
125
150
TJ, JUNCTION TEMPERATURE (°C)
Figure 12. Maximum Avalanche Energy vs.
Starting Junction Temperature
http://onsemi.com
5
175
NTD3813N
ORDERING INFORMATION
Package
Shipping†
NTD3813NT4G
DPAK
(Pb-Free)
2500 / Tape & Reel
NTD3813N-1G
IPAK
(Pb-Free)
75 Units / Rail
NTD3813N-35G
IPAK Trimmed Lead
(3.5 " 0.15 mm)
(Pb-Free)
75 Units / Rail
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
http://onsemi.com
6
NTD3813N
PACKAGE DIMENSIONS
DPAK (SINGLE GAUGE)
CASE 369AA-01
ISSUE A
-TC
B
V
NOTES:
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
SEATING
PLANE
E
R
4
Z
A
S
1
2
DIM
A
B
C
D
E
F
H
J
L
R
S
U
V
Z
H
3
U
F
J
L
D
STYLE 2:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
2 PL
0.13 (0.005)
M
INCHES
MIN
MAX
0.235 0.245
0.250 0.265
0.086 0.094
0.025 0.035
0.018 0.024
0.030 0.045
0.386 0.410
0.018 0.023
0.090 BSC
0.180 0.215
0.024 0.040
0.020
--0.035 0.050
0.155
---
T
SOLDERING FOOTPRINT*
6.20
0.244
2.58
0.101
5.80
0.228
3.0
0.118
1.6
0.063
6.172
0.243
SCALE 3:1
mm Ǔ
ǒinches
*For additional information on our Pb-Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
http://onsemi.com
7
MILLIMETERS
MIN
MAX
5.97
6.22
6.35
6.73
2.19
2.38
0.63
0.89
0.46
0.61
0.77
1.14
9.80 10.40
0.46
0.58
2.29 BSC
4.57
5.45
0.60
1.01
0.51
--0.89
1.27
3.93
---
NTD3813N
PACKAGE DIMENSIONS
3 IPAK, STRAIGHT LEAD
CASE 369AC-01
ISSUE O
B
V
NOTES:
1.. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2.. CONTROLLING DIMENSION: INCH.
3. SEATING PLANE IS ON TOP OF
DAMBAR POSITION.
4. DIMENSION A DOES NOT INCLUDE
DAMBAR POSITION OR MOLD GATE.
C
E
R
DIM
A
B
C
D
E
F
G
H
J
K
R
V
W
A
SEATING PLANE
K
W
F
J
G
H
D
3 PL
0.13 (0.005) W
INCHES
MIN
MAX
0.235 0.245
0.250 0.265
0.086 0.094
0.027 0.035
0.018 0.023
0.037 0.043
0.090 BSC
0.034 0.040
0.018 0.023
0.134 0.142
0.180 0.215
0.035 0.050
0.000 0.010
MILLIMETERS
MIN
MAX
5.97
6.22
6.35
6.73
2.19
2.38
0.69
0.88
0.46
0.58
0.94
1.09
2.29 BSC
0.87
1.01
0.46
0.58
3.40
3.60
4.57
5.46
0.89
1.27
0.000
0.25
IPAK (STRAIGHT LEAD DPAK)
CASE 369D-01
ISSUE B
C
B
V
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
E
R
4
Z
A
S
1
2
3
-TSEATING
PLANE
K
J
F
H
D
G
DIM
A
B
C
D
E
F
G
H
J
K
R
S
V
Z
INCHES
MIN
MAX
0.235 0.245
0.250 0.265
0.086 0.094
0.027 0.035
0.018 0.023
0.037 0.045
0.090 BSC
0.034 0.040
0.018 0.023
0.350 0.380
0.180 0.215
0.025 0.040
0.035 0.050
0.155
---
MILLIMETERS
MIN
MAX
5.97
6.35
6.35
6.73
2.19
2.38
0.69
0.88
0.46
0.58
0.94
1.14
2.29 BSC
0.87
1.01
0.46
0.58
8.89
9.65
4.45
5.45
0.63
1.01
0.89
1.27
3.93
---
3 PL
0.13 (0.005)
M
STYLE 2:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
T
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada
Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada
Email: [email protected]
N. American Technical Support: 800-282-9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81-3-5773-3850
http://onsemi.com
8
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your local
Sales Representative
NTD3813N/D