NCP1380 Quasi-Resonant Current-Mode Controller for High-Power Universal Off-Line Supplies The NCP1380 hosts a high−performance circuitry aimed to powering quasi−resonant converters. Capitalizing on a proprietary valley−lockout system, the controller shifts gears and reduces the switching frequency as the power loading becomes lighter. This results in a stable operation despite switching events always occurring in the drain−source valley. This system works down to the 4th valley and toggles to a variable frequency mode beyond, ensuring an excellent standby power performance. To improve the safety in overload situations, the controller includes an Over Power Protection (OPP) circuit which clamps the delivered power at high−line. Safety−wise, a fixed internal timer relies on the feedback voltage to detect a fault. Once the timer elapses, the controller stops and stays latched for option A and C or enters auto−recovery mode for option B and D. Particularly well suited for adapter applications, the controller features a pin to implement either a combined overvoltage / overtemperature protection (Version A and B) or a combined brown−out/overvoltage protection (Version C and D). Features • Quasi−Resonant Peak Current−Mode Control Operation • Valley Switching Operation with Valley−Lockout for Noise−Immune Operation • Frequency Foldback at Light Load to Improve the Light Load • • • • • • • • • • • • Efficiency Adjustable Over Power Protection Auto−Recovery or Latched Internal Output Short−Circuit Protection Fixed Internal 80 ms Timer for Short−Circuit Protection Combined Overvoltage and Overtemperature Protection (A and B Versions) Combined Overvoltage Protection and Brown−Out (C and D Versions) +500 mA / −800 mA Peak Current Source/Sink Capability Internal Temperature Shutdown Direct Optocoupler Connection Extended VCC Range Operation Up to 28 V Extremely Low No−Load Standby Power SO−8 Package These Devices are Pb−Free and are RoHS Compliant http://onsemi.com QUASI−RESONANT PWM CONTROLLER FOR HIGH POWER AC−DC WALL ADAPTERS MARKING DIAGRAMS 8 SOIC−8 D SUFFIX CASE 751 8 1 1 1380X X A L Y W G 1380X ALYWX G = Specific Device Code = Device Option (A, B, C, or D) = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package PIN CONNECTIONS ZCD 1 8 CT FB 2 7 FAULT CS 3 6 VCC GND 4 5 DRV ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 25 of this data sheet. Typical Applications • High Power ac−dc Converters for TVs, Set−Top Boxes etc. • Offline Adapters for Notebooks © Semiconductor Components Industries, LLC, 2009 December, 2009 − Rev. 1 1 Publication Order Number: NCP1380/D NCP1380 TYPICAL APPLICATION EXAMPLE HV−Bulk Vout GND NCP1380 A/B 8 ZCD / OPP 1 2 7 3 4 6 OVP / OTP 5 GND Figure 1. Typical Application Schematic for A and B Versions HV−Bulk Vout GND NCP1380 C/D ZCD / OPP1 8 2 7 3 6 4 5 BO / OVP Figure 2. Typical Application Schematic for C and D Versions http://onsemi.com 2 GND NCP1380 PIN FUNCTION DESCRIPTION Pin N5 Pin Name Function Pin Description 1 ZCD Zero Crossing Detection Connected to the auxiliary winding, this pin detects the core reset event. Also, injecting a negative voltage smaller than 0.3 V on this pin will perform over power protection. Adjust the over power protection 2 FB Feedback pin Hooking an optocoupler collector to this pin will allow regulation. 3 CS Current sense This pin monitors the primary peak. 4 GND − 5 DRV Driver output 6 VCC Supplies the controller 7 Fault Over voltage and Over temperature protection (A and B versions) Pulling this pin down with an NTC or up with a zener diode allows to latch the controller. Over−voltage and Brown−out protection (C and D versions) This pin observes the HV rail and protects the circuit in case of low main conditions. It also offers a way to latch the circuit in case of over voltage event. 8 CT The controller ground The driver’s output to an external MOSFET This pin is connected to an external auxiliary voltage. Timing capacitor A capacitor connected to this pin acts as the timing capacitor in foldback mode. NCP1380 OPTIONS OTP OVP NCP1380 / A Yes Yes NCP1380 / B Yes Yes Brown−Out Auto−Recovery Overcurrent Protection Latched Overcurrent Protection Yes Yes NCP1380 / C Yes Yes NCP1380 / D Yes Yes http://onsemi.com 3 Yes Yes NCP1380 INTERNAL CIRCUIT ARCHITECTURE VDD BO r eset VCC latch V CC management VDD VDD aux fa ul t Rpullup VCCstop gr a nd reset FB L OGI C BL OCK clamp VDD ICt DRV Ct + DRV gr a nd reset ga te − Ct s e tpoi nt R Q Q Ct Discharge Cs S top + 10 V ESD DRV GN D A: l a tc he d de ma g − Vth S 3 ms blanking Q Q La ux Up IpFlag TIM ER Down Reset P W Mr eset R SS end 40 ms Ti me Out /4 gr a nd reset The 40 ms Time Out is active only during s oft−s ta r t − SS end VOVP noi s e de l a y 5 ms Ti me Out Ipeak(VCO) = 17.5% VILIMIT + ZCD S PWMreset LEB 1 Fa ul t + IpFlag noi s e de l a y OPP − Rsense + VILIMIT + SS end VOTP − Soft-start SS end Soft−s ta rt e nd ? the n 1 else 0 CsS top + LEB 2 LEB 2 is shorter than LEB 1 VCC IOTP(REF) − CS VDD − VC S(stop) Figure 3. Internal Circuit Architecture for Versions A and B http://onsemi.com 4 NCP1380 VDD BO reset latch VDD VDD aux VCC V CC management fa ul t R pul l up VCCstop gr a nd reset FB LOGIC BLOCK VDD clamp ICt DRV Ct DRV + gr a nd reset ga te − Ct se tpoint R Q QS Ct discharge ZCD + 10 V ESD DRV C: l a tc he d de ma g − GN D CsS top Vth S 3 ms blanking La ux SS end Up TIMER Down Res et R 40 ms Time Out /4 Q Q nois e de la y 5 ms Time Out Ipeak(VCO) = 17.5% VILIMIT + VOVP − LEB 1 + Rsense VCC − P W Mreset CS VDD IpFlag IBO OPP VILIMIT LEB 2 is shorter than LEB 1 noi s e de l a y + − Soft-start SS end LEB 2 P W Mreset gr a nd reset The 40 ms Time Out is active only during s oft−s ta r t SS end I pFl a g VBO + − Soft−s ta r t e nd ? the n 1 else 0 CsS top BO r es et Rclamp Vclamp + − VCS ( st op) Figure 4. Internal Circuit Architecture for Versions C and D http://onsemi.com 5 OVP/BO HV NCP1380 MAXIMUM RATINGS TABLE Value Unit VCC(MAX) ICC(MAX) Symbol Maximum Power Supply voltage, VCC pin, continuous voltage Maximum current for VCC pin −0.3 to 28 $30 V mA VDRV(MAX) IDRV(MAX) Maximum driver pin voltage, DRV pin, continuous voltage Maximum current for DRV pin −0.3 to 20 $1000 V mA Maximum voltage on low power pins (except pins DRV and VCC) Current range for low power pins (except pins ZCD, DRV and VCC) −0.3 to 10 $10 V mA +3 / −2 mA Thermal Resistance Junction−to−Air 120 °C/W Maximum Junction Temperature 150 °C Operating Temperature Range −40 to +125 °C Storage Temperature Range −60 to +150 °C ESD Capability, HBM model (Note 1) 4 kV ESD Capability, CDM model (Note 1) 2 kV VMAX IMAX IZCD(MAX) RqJA TJ(MAX) Rating Maximum current for ZCD pin Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. This device series contains ESD protection and exceeds the following tests: Human Body Model 4000 V per Mil−Std−883, Method 3015. Charged Device Model 2000 V per JEDEC Standard JESD22−C101D 2. This device contains latchup protection and exceeds 100 mA per JEDEC Standard JESD78. ELECTRICAL CHARACTERISTICS (Unless otherwise noted: For typical values TJ = 25°C, VCC = 12 V, VZCD = 0 V, VFB = 3 V, VCS = 0 V, Vfault = 1.5 V, CT = 680 pF) For min/max values TJ = −40°C to +125°C, Max TJ = 150°C, VCC = 12 V) Condition Symbol Min Typ Max Unit 16 8.3 7.2 6.2 6 17 9 8.0 7.2 7 18 9.4 9.2 8.2 8 − − 5 20 − − ms − 10 20 mA SUPPLY SECTION − STARTUP AND SUPPLY CIRCUITS VCC(on) VCC(off) VCC(HYS) VCC(latch) VCC(reset) Supply Voltage Startup Threshold Minimum Operating Voltage Hysteresis VCC(on) − VCC(off) Clamped VCC when latched−off Internal logic reset tVCC(off) tVCC(reset) VCC(off) noise filter VCC(reset) noise filter VCC increasing VCC decreasing VCC decreasing, ICC = 30 mA V ICC(start) Startup current FB pin open VCC = VCC(on) − 0.5 V ICC(disch) Current that discharges VCC when the controller gets latched VCC = 12 V 3.0 4.0 5.0 mA ICC(latch) Current into VCC that keeps the controller latched (Note 3) VCC = VCC(latch) 30 − − mA VCC > VCC(off) Fsw = 10 kHz CDRV = 1 nF, FSW = 65 kHz CDRV = 1 nF, VFB = 1.25 V − − − − 1.7 1.7 2.65 2.0 2.0 2.0 3.0 − ICC1 ICC2 ICC3A ICC3B Supply Current Device Disabled/Fault (Note 3) B, C, and D only Device Enabled/No output load on pin 5 Device Switching (FSW = 65 kHz) Device Switching VCO mode mA CURRENT COMPARATOR − CURRENT SENSE 3. 4. 5. 6. 7. VILIM Current Sense Voltage Threshold VFB = 4 V, VCS increasing 0.76 0.8 0.84 V tLEB Leading Edge Blanking Duration for VILIM Minimum on time minus tILIM 210 275 330 ns Ibias Input Bias Current (Note 3) DRV high −2 − 2 mA Guaranteed by design. The peak current setpoint goes down as the load decreases. It is frozen below Ipeak(VCO) (Ipeak = cst) If negative voltage in excess to −300 mV is applied to ZCD pin, the current setpoint decrease is no longer guaranteed to be linear Minimum value for TJ = 125°C NTC with R110 = 8.8 kW. http://onsemi.com 6 NCP1380 ELECTRICAL CHARACTERISTICS (Unless otherwise noted: For typical values TJ = 25°C, VCC = 12 V, VZCD = 0 V, VFB = 3 V, VCS = 0 V, Vfault = 1.5 V, CT = 680 pF) For min/max values TJ = −40°C to +125°C, Max TJ = 150°C, VCC = 12 V) Symbol Condition Min Typ Max Unit Propagation Delay VCS > VILIM to DRV turn−off − 125 175 ns Ipeak(VCO) Percentage of maximum peak current level at which VCO takes over (Note 4) VFB = 0.4 V, VCS increasing 15.4 17.5 19.6 % VOPP(MAX) Setpoint decrease for VZCD = −300 mV (Note 5) VZCD = −300 mV, VFB = 4 V, VCS increasing 35 37.5 40 % 1.125 1.200 1.275 V − 120 − ns CURRENT COMPARATOR − CURRENT SENSE tILIM VCS(stop) tBCS Threshold for immediate fault protection activation Leading Edge Blanking Duration for VCS(stop) DRIVE OUTPUT − GATE DRIVE RSNK RSRC Drive Resistance DRV Sink DRV Source VDRV = 10 V VDRV = 2 V − − 12.5 20 − − ISNK ISRC Drive current capability DRV Sink DRV Source VDRV = 10 V VDRV = 2 V − − 800 500 − − W mA tr Rise Time (10% to 90%) CDRV = 1 nF, VDRV from 0 to 12 V − 40 75 ns tf Fall Time (90% to 10%) CDRV = 1 nF, VDRV from 0 to 12 V − 25 60 ns VDRV(low) DRV Low Voltage VCC = VCC(off) + 0.2 V CDRV = 1 nF, RDRV = 33 kW 8.4 9.1 − V VDRV(high) DRV High Voltage (Note 6) VCC = VCC(MAX) CDRV = 1 nF 10.5 13.0 15.5 V DEMAGNETIZATION INPUT − ZERO VOLTAGE DETECTION CIRCUIT VZCD(TH) ZCD threshold voltage VZCD decreasing 35 55 90 mV VZCD(HYS) ZCD hysteresis VZCD increasing 15 35 55 mV VCH VCL Input clamp voltage High state Low state Ipin1 = 3.0 mA Ipin1 = −2.0 mA 8 −0.9 10 −0.7 12 −0.3 tDEM Propagation Delay − 150 250 ns CPAR Internal input capacitance tBLANK Blanking delay after on−time toutSS tout Timeout after last demag transition RZCD(pdown) VZCD decreasing from 4 V to −0.3 V During soft−start After the end of soft−start Pulldown resistor (Note 3) V − 10 − pF 2.30 3.15 4.00 ms 28 5.0 41 5.9 54 6.7 ms 140 320 500 kW 5.15 5.40 5.65 V 18 20 22 mA − − 90 mV TIMING CAPACITOR VCT(MAX) ICT VCT(MIN) CT 3. 4. 5. 6. 7. Maximum voltage on CT pin VFB < VFB(TH) Source current VCT = 0 V Minimum voltage on CT pin, discharge switch activated Recommended timing capacitor value 220 Guaranteed by design. The peak current setpoint goes down as the load decreases. It is frozen below Ipeak(VCO) (Ipeak = cst) If negative voltage in excess to −300 mV is applied to ZCD pin, the current setpoint decrease is no longer guaranteed to be linear Minimum value for TJ = 125°C NTC with R110 = 8.8 kW. http://onsemi.com 7 pF NCP1380 ELECTRICAL CHARACTERISTICS (Unless otherwise noted: For typical values TJ = 25°C, VCC = 12 V, VZCD = 0 V, VFB = 3 V, VCS = 0 V, Vfault = 1.5 V, CT = 680 pF) For min/max values TJ = −40°C to +125°C, Max TJ = 150°C, VCC = 12 V) Symbol Condition Min Typ Max Unit Internal pullup resistor 15 18 22 kW Pin FB to current setpoint division ratio 3.8 4.0 4.2 FB pin threshold under which CT is clamped to VCT(MAX) 0.26 0.3 0.34 VFB decreases 1.316 1.4 1.484 VFB decreases 1.128 1.2 1.272 VFB decreases 0.846 0.9 0.954 VFB decreases 0.732 0.8 0.828 FEEDBACK SECTION RFB(pullup) Iratio VFB(TH) V VHVCOD Valley threshold FB voltage where 1st valley ends and 2nd valley starts FB voltage where 2nd valley ends and 3rd valley starts FB voltage where 3rd valley ends and 4th valley starts FB voltage where 4th valley ends and VCO starts VHVCOI FB voltage where VCO ends and 4th valley starts VFB increases 1.316 1.4 1.484 VH4I FB voltage where 4th valley ends and 3rd valley starts FB voltage where 3rd valley ends and 2nd valley starts FB voltage where 2nd valley ends and 1st valley starts VFB increases 1.504 1.6 1.696 VFB increases 1.692 1.8 1.908 VFB increases 1.880 2.0 2.120 140 − 170 °C − 40 − °C VH2D VH3D VH4D VH3I VH2I V FAULT PROTECTION (ALL VERSIONS) TSHDN TSHDN(HYS) tOVLD tSSTART RFault(clamp) VOVP tlatch(delay) Thermal Shutdown Device switching (FSW around 65 kHz) Thermal Shutdown Hysteresis Overload Timer VFB = 4 V, VCS > VILIM 75 85 95 ms Soft−start duration VFB = 4 V, VCS ramping up, measured from 1st DRV pulse to VCS(peak) = 90% of VILIM 2.8 3.8 4.8 ms 1.3 1.55 1.8 kW 2.35 2.5 2.65 V 22.5 30 37.5 ms 85 91 97 mA Clamp series resistor Fault detection level for OVP VFault increasing Delay before latch confirmation FAULT PROTECTION A & B VERSIONS IOTP(REF) VOTP VFault(clamp) Reference current for direct connection of an NTC (Note 7) VFault = VOTP + 0.2 V Fault detection level for OTP VFault decreasing 0.744 0.8 0.856 V Clamped voltage (Fault pin left open) Fault pin open 1.13 1.35 1.57 V 0.744 0.8 0.856 V 9 10 11 mA 22.5 30 37.5 ms 1.0 1.2 1.4 V FAULT PROTECTION C & D VERSIONS VBO Brown−Out level VFault decreasing IBO Sourced hysteresis current VFault > VBO VFault = VBO + 0.2 V tBO(delay) VFault(clamp) 3. 4. 5. 6. 7. Delay before entering and exiting Brown−out Clamped voltage (Fault pin left open) Fault pin open Guaranteed by design. The peak current setpoint goes down as the load decreases. It is frozen below Ipeak(VCO) (Ipeak = cst) If negative voltage in excess to −300 mV is applied to ZCD pin, the current setpoint decrease is no longer guaranteed to be linear Minimum value for TJ = 125°C NTC with R110 = 8.8 kW. http://onsemi.com 8 NCP1380 9.00 17.25 8.95 17.20 8.90 VCC(off), (V) VCC(on), (V) 17.30 17.15 17.10 8.80 8.75 17.05 17.00 −40 8.85 −20 0 20 40 60 80 100 TJ, JUNCTION TEMPERATURE (°C) 8.70 −40 120 1.80 2.70 1.70 2.60 ICC3A, (mA) ICC2, (mA) 2.80 1.60 1.50 1.40 40 60 80 100 120 2.50 2.40 2.30 −20 0 20 40 60 80 100 TJ, JUNCTION TEMPERATURE (°C) 2.20 −40 120 Figure 7. ICC2 vs. Junction Temperature 2.40 10.0 2.30 9.5 2.20 9.0 2.10 8.5 2.00 1.90 1.70 6.5 20 40 60 80 100 120 7.5 7.0 0 0 20 40 60 80 100 TJ, JUNCTION TEMPERATURE (°C) 8.0 1.80 −20 −20 Figure 8. ICC3A vs. Junction Temperature ICC(start), (mA) ICC3B, (mA) 20 Figure 6. VCC(off) vs. Junction Temperature 1.90 1.60 −40 0 TJ, JUNCTION TEMPERATURE (°C) Figure 5. VCC(on) vs. Junction Temperature 1.30 −40 −20 6.0 −40 120 TJ, JUNCTION TEMPERATURE (°C) −20 0 20 40 60 80 100 TJ, JUNCTION TEMPERATURE (°C) Figure 9. ICC3B vs. Junction Temperature 120 Figure 10. ICC(start) vs. Junction Temperature http://onsemi.com 9 810 330 805 310 800 290 TLEB, (ns) VILIM, (mV) NCP1380 795 790 785 270 250 230 780 −40 −20 0 20 40 60 80 100 210 −40 120 −20 TJ, JUNCTION TEMPERATURE (°C) 0 20 40 60 80 100 120 TJ, JUNCTION TEMPERATURE (°C) Figure 11. VILIM vs. Junction Temperature Figure 12. TLEB vs. Junction Temperature 1.265 39.0 1.245 38.5 VCS(stop), (V) VOPP(max), (%) 1.225 1.205 1.185 1.165 38.0 37.5 37.0 36.5 1.145 1.125 −40 −20 0 20 40 60 80 100 36.0 −40 120 −20 0 20 40 60 80 100 120 TJ, JUNCTION TEMPERATURE (°C) Figure 13. VCS(stop) vs. Junction Temperature Figure 14. VOPP(MAX) vs. Junction Temperature 9.4 14.5 14.0 9.3 9.2 VDRV(high), (V) VDRV(low), (V) 13.5 9.1 9.0 13.0 12.5 12.0 11.5 8.9 11.0 8.8 −40 −20 0 20 40 60 80 100 10.5 120 −40 TJ, JUNCTION TEMPERATURE (°C) −20 0 20 40 60 80 100 TJ, JUNCTION TEMPERATURE (°C) Figure 15. VDRV(low) vs. Junction Temperature 120 Figure 16. VDRV(high) vs. Junction Temperature http://onsemi.com 10 NCP1380 55 85 50 45 VZCD(hys), (V) VZCD(th), (V) 75 65 55 40 35 30 25 45 20 35 −40 −20 0 20 40 60 80 100 15 120 −40 −20 TJ, JUNCTION TEMPERATURE (°C) Figure 17. VZCD(th) vs. Junction Temperature 20 40 60 80 100 120 Figure 18. VZCD(hys) vs. Junction Temperature 3.50 49.0 3.40 47.0 45.0 3.30 ToutSS, (ms) TBLANK, (ms) 0 TJ, JUNCTION TEMPERATURE (°C) 3.20 3.10 43.0 41.0 39.0 3.0 37.0 2.90 −40 −20 0 20 40 60 80 100 35.0 120 −40 −20 0 20 40 60 80 100 120 TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C) Figure 19. TBLANK vs. Junction Temperature Figure 20. ToutSS vs. Junction Temperature 6.6 810 6.4 805 800 6.0 VOTP, (mV) Tout, (ms) 6.2 5.8 5.6 795 790 5.4 785 5.2 5.0 −40 −20 0 20 40 60 80 100 TJ, JUNCTION TEMPERATURE (°C) 780 120 −40 Figure 21. Tout vs. Junction Temperature −20 0 20 40 60 80 100 TJ, JUNCTION TEMPERATURE (°C) Figure 22. VOTP vs. Junction Temperature http://onsemi.com 11 120 810 91.0 805 90.0 800 VBO, (mV) 92.0 89.0 88.0 87.0 86.0 −40 795 790 785 −20 0 20 40 60 80 100 780 120 −40 −20 TJ, JUNCTION TEMPERATURE (°C) 0 20 10.2 10.0 9.8 9.6 9.4 −20 60 80 100 Figure 24. VBO vs. Junction Temperature 10.4 9.2 −40 40 TJ, JUNCTION TEMPERATURE (°C) Figure 23. IOTP vs. Junction Temperature IBO, (mA) IOTP, (mA) NCP1380 0 20 40 60 80 100 TJ, JUNCTION TEMPERATURE (°C) Figure 25. IBO vs. Junction Temperature http://onsemi.com 12 120 120 NCP1380 APPLICATION INFORMATION • Fault input (A and B versions): By combining a dual The NCP1380 implements a standard current−mode architecture operating in quasi−resonant mode. Due to a proprietary circuitry, the controller prevents valley−jumping instability and steadily locks out in selected valley as the power demand goes down. Once the fourth valley is reached, the controller continues to reduce the frequency further down, offering excellent efficiency over a wide operating range. Thanks to a fault timer combined to an OPP circuitry, the controller is able to efficiently limit the output power at high−line. • Quasi−Resonance Current−mode operation: implementing quasi−resonance operation in peak current−mode control, the NCP1380 optimizes the efficiency by switching in the valley of the MOSFET drain−source voltage. Thanks to a proprietary circuitry, the controller locks−out in a selected valley and remains locked until the output loading significantly changes. When the load becomes lighter, the controller jumps into the next valley. It can go down to the 4th valley if necessary. Beyond this point, the controller reduces its switching frequency by freezing the peak current setpoint. During quasi−resonance operation, in case of very damped valleys, a 5.5 ms timer emulates the missing valleys. • Frequency reduction in light−load conditions: when the 4th valley is left, the controller reduces the switching frequency which naturally improves the standby power by a reduction of all switching losses. • Overpower protection (OPP): When the voltage on ZCD pin swings in flyback polarity, a direct image if the input voltage is applied on ZCD pin. We can thus reduce the peak current depending of VZCD during the on−time. • Internal soft−start: A soft−start precludes the main power switch from being stressed upon startup. Its duration is fixed and equal to 4 ms. • • threshold on the Fault pin, the controller allows the direct connection of an NTC to ground plus a zener diode to a monitored voltage. In case the pin is brought below the OTP threshold by the NTC or above the OVP threshold by the zener diode, the circuit permanently latches−off and VCC is clamped to 7.2 V. Fault input (C and D versions): The C and D versions of NCP1380 include a brown−out circuit which safely stops the controller in case the input voltage is too low. Restart occurs via a complete startup sequence (latch reset and soft−start). During normal operation, the voltage on this pin is clamped to Vclamp to give enough room for OVP detection. If the voltage on this pin increases above 2.5 V, the part latches−off. Short−circuit protection: Short−circuit and especially over−load protections are difficult to implement when a strong leakage inductance between auxiliary and power windings affects the transformer (where the auxiliary winding level does not properly collapse in presence of an output short). Here, when the internal 0.8 V maximum peak current limit is activated, the timer starts counting up. If the fault disappears, the timer counts down. If the timer reaches completion while the error flag is still present, the controller stops the pulses. This protection is latched on A and C version (the user must unplug and re−plug the power supply to restart the controller) and auto−recovery on B and D versions (if the fault disappears, the SMPS automatically resumes operation). In addition, all versions feature a winding short−circuit protection, that senses the CS signal and stops the controller if VCS reaches 1.5 x VILIM (after a reduced LEB of tBCS). This additional comparator is enabled only during the main LEB duration tLEB, for noise immunity reason. NCP1380 OPERATING MODES NCP1380 has two operating mode: quasi−resonant operation and VCO operation for the frequency foldback. The operating mode is fixed by the FB voltage as portrayed by Figure 26: • Quasi−resonant operation occurs for FB voltage higher than 0.8 V (FB decreasing) or higher than 1.4 V (FB increasing) which correspond to high output power and medium output power. The peak current is variable and is set by the FB voltage divided by 4. • Frequency foldback or VCO mode occurs for FB voltage lower than 0.8 V (FB decreasing) or lower than 1.4 V (FB increasing). This corresponds to low output power. During VCO mode, the peak current decreases down to 17.5% of its maximum value and is then frozen. The switching frequency is variable and decreases as the output load decreases. The switching frequency is set by the end of charge of the capacitor connected to the CT pin. This capacitor is charged with a constant current source and the capacitor voltage is compared to an internal threshold fixed by FB voltage. When this capacitor voltage reaches the threshold the capacitor is rapidly discharged down to 0 V and a new period start. http://onsemi.com 13 NCP1380 Figure 26. Operating Valley According to FB Voltage VALLEY DETECTION AND SELECTION The valley detection is done by monitoring the voltage of the auxiliary winding of the transformer. A valley is detected when the voltage on pin 1 crosses down the 55 mV internal threshold. When a valley is detected, an internal counter is incremented. The operating valley (1st, 2nd, 3rd or 4th) is determined by the FB voltage as shown by Figure 26. VDD VDD Rpullup FB V FB LOGIC BLOCK V FBth VDD S ICt Ct Q + − R Ct setpoint Tim e Out Ct Discharge ZCD + de m a g 10 V ES D DRV DRV Q − Vth leakage blanking 3 us puls e La ux Figure 27. Valley Detection Circuit http://onsemi.com 14 CS comparator NCP1380 necessary output power. This allows achieving very low standby power consumption. The Figure 28 shows a simulation case where the output current of a 19 V, 60 W adapter decreases from 2.8 A to 0.1 A. No instability is seen during the valley transitions (Figures 29, 30, 31 and 32) As the output load decreases (FB voltage decreases), the valleys are incremented from the first to the fourth. When the fourth valley is reached, if FB voltage further decreases below 0.8 V, the controller enters VCO mode. During VCO operation, the peak current continues to decrease until it reaches 17.5% of the maximum peak current: the switching frequency expands to deliver the Figure 28. Output Load is Decreased from 2.8 A Down to 100 mA at 120 Vdc Input Voltage http://onsemi.com 15 NCP1380 Figure 29. Zoom 1: 1st to 2nd Valley Transition Figure 30. Zoom 2: 2nd to 3rd Valley Transition http://onsemi.com 16 NCP1380 Figure 31. Zoom 3: 3rd to 4th Valley Transition Figure 32. Zoom 4: 4th Valley to VCO Mode Transition Time Out introduced by the Over Power Compensation diode (Figure 40), the voltage on the ZCD pin is very low and the ZCD comparator might be unable to detect the valleys. In this condition, setting the DRV Latch with the 5.5 ms time−out can lead to a continuous conduction mode operation (CCM) at the beginning of the soft−start. This CCM operation only last a few cycles until the voltage on ZCD pin becomes high enough to be detected by the ZCD comparator. To avoid this, the time−out duration is extended to 40 ms during the soft−start in order to ensure that the transformer is fully demagnetized before the MOSFET is turned−on. In case of extremely damped free oscillations, the ZCD comparator can be unable to detect the valleys. To avoid such situation, NCP1380 integrates a Time Out function that acts as a substitute clock for the decimal counter inside the logic bloc. The controller thus continues its normal operation. To avoid having a too big step in frequency, the time out duration is set to 5.5 ms. Figures 34 and 35 detail the time out operation. The NCP1380 also features an extended time out during the soft−start. Indeed, at startup, the output voltage reflected on the auxiliary winding is low. Because of the voltage drop http://onsemi.com 17 NCP1380 VDD ZC D + demag − 10 V ES D LOGI C BL OCK Vth leakage blanking 3 us pulse TimeOut DRV SS e nd 5.5 us time out SS e nd 40 us time out Figure 33. Time Out Circuit Figure 34. Time Out Case n51: the 3rd Valley is Missing http://onsemi.com 18 NCP1380 Figure 35. Time Out Case n52: the 3rd and 4th Valley are Missing VCO MODE OR FREQUENCY FOLDBACK VCO operation occurs for FB voltage lower than 0.8 V (FB decreasing), or lower than 1.4 V (FB increasing). This corresponds to low output power. During VCO operation, the peak current is fixed to 17.5% of his maximum value and the frequency is variable and expands as the output power decreases. The frequency is set by the end of charge of the capacitor connected to the CT pin. This capacitor is charged with a constant current source and its voltage is compared to an internal threshold (VFBth) fixed by FB voltage (see Figure 27). When this capacitor voltage reaches the threshold, the capacitor is rapidly discharged down to 0 V and a new period start. The internal threshold is inversely proportional to FB voltage. The relationship between VFB and VFBth is given by Equation 1. V FBth + 6.5 * (10ń3)V FB (eq. 1) When VFB is lower than 0.3 V, VCT is clamped to VCT(MAX) which is typically 5.5 V. Figure 36 shows the VCO mode at works. Figure 36. In VCO Mode, as the Power Output Decreases, the Frequency Expands http://onsemi.com 19 NCP1380 SHORT−CIRCUIT OR OVERLOAD MODE Figure 37 shows the implementation of the fault timer. S Q Vd d DRV au x Q R VCC VCC management latch fau l t CsStop CS LEB1 R sen se + ZCD/OPP PW Mr eset − FB/4 Down Up TIMER IpFlag OPP Reset + V IL IM IT A&C: Latched − SS en d Soft −s t art end ? t hen 1 else 0 Soft−start Laux LEB2 + VC C sto p grand reset S Q Q CsStop R − grand reset V CS(stop) Figure 37. Overload Detection Schematic On A and C versions, when the timers finishes counting 80 ms, the circuit goes in latch mode (Figure 39): the DRV pulses stop and VCC is pulled down to VCC(latch) which is 7.2 V typically. The circuit un−latches when the current circulating in VCC pin drops below ICC(latch). In parallel to the cycle−by−cycle sensing of the CS pin, another comparator with a reduced LEB (tBCS) and a threshold of 1.2 V is able to sense winding short−circuit and immediately shut down the controller. Depending on the version, this additional protection is either latched or auto−recovery, according to the overload protection behavior. When the current in the MOSFET is higher than VILIM / Rsense, “Max Ip” comparator trips and the digital timer starts counting: the timer count is incremented each 10 ms. When the current comes back within safe limits, “Max Ip” comparator becomes silent and the timer count down: the timer count is decremented each 10 ms. In normal overload conditions the timer reaches its completion when it has counted up 8 times 10 ms. On B and D version, when the timers reaches its completion, the circuit enter auto−recovery mode: the circuit stops all operations and VCC decreases via the circuit own consumption (ICC1). When VCC reaches VCC(off), the circuit goes in startup mode and restart switching. (see Figure 38) This ensures a low duty−cycle burst operation in fault mode. http://onsemi.com 20 NCP1380 Figure 38. Auto−Recovery Short−Circuit Protection on B and D Versions Figure 39. Latched Short−Circuit Protection on A and C Versions http://onsemi.com 21 NCP1380 OVER POWER COMPENSATION the input voltage. As the auxiliary winding is already connected to ZCD pin for the valley detection, by selecting the right values for Ropu and Ropl, we can easily perform over power compensation. The over power compensation is achieved by monitoring the signal on ZCD pin (pin 1). Indeed, a negative voltage applied on this pin directly affects the internal voltage reference setting the maximum peak current (Figure 40). When the power MOSFET is turned−on, the auxiliary winding voltage becomes a negative voltage proportional to Rz cd Ropu CS ZCD/OPP IpFlag OPP 1 ESD protection Ropl Au x V IL IMIT + Demag − Vt h leakage blanking Tblank DRV Figure 40. Over Power Compensation Circuit To ensure optimal zero−crossing detection, a diode is needed to bypass Ropu during the off−time. If we apply the resistor divider law on the pin 1 during the on−time, we obtain the following relationship: R ZCD ) R opu R opl +* N p,auxV in * V OPP V OPP Design example: Vaux = 18 V Vd = 0.6 V Np,aux = 0.18 If we want at least 8 V on ZCD pin, we have: (eq. 2) R ZCD R opl Where: Np,aux is the auxiliary to primary turn ration: Np,aux = Naux / Np Vin is the DC input voltage VOPP is the negative OPP voltage By selecting a value for Ropl, we can easily deduce Ropu using Equation 2. While selecting the value for Ropl, we must be careful not choosing a too low value for this resistor in order to have enough voltage for zero−crossing detection during the off−time. We recommend having at least 8 V on ZCD pin, the maximum voltage being 10 V. During the off−time, ZCD pin voltage can be expressed as follows: V ZCD + R opl R ZCD ) R opl ǒV aux * V dǓ R opl + V aux * V d * V ZCD V ZCD V aux * V d * V ZCD V ZCD (eq. 5) 18 * 0.6 * 8 + [ 1.2 8 We can choose: RZCD = 1 kW and Ropl = 1 kW. For the over power compensation, we need to decrease the peak current by 37.5% at high line (370 Vdc). The corresponding OPP voltage is: V OPP + 0.375 V ILIM + −300 mV (eq. 6) Using Equation 2, we have: R ZCD ) R opu R opt +* + (eq. 3) N p,auxV lin * V OPP −0.18 V OPP 370 * (−0.3) (−0.3) (eq. 7) + 221 Thus, We can thus deduce the relationship between Ropl and RZCD: R ZCD + R opu + 221 Ropl * R ZCD + 221 (eq. 4) http://onsemi.com 22 1k * 1k + 220 kW (eq. 8) NCP1380 OVERVOLTAGE / OVERTEMPERATURE DETECTION (A AND B VERSIONS) Overvoltage and overtemperature detection is achieved by reading the voltage on pin 7 (See Figure 41). VCC V OVP VDD nois e de lay − Dz I OTP(REF) + OVPcomp Fa ult 7 S Q Rc l a mp Clamp − Latch Q + NTC nois e de lay R OT Pc o mp Vclam p V OTP grand reset SS end Figure 41. OVP/OTP Circuitry The IOTP(REF) current (91 mA typ.) biases the Negative Temperature Coefficient sensor (NTC), naturally imposing a dc voltage on the OTP pin. An internal clamp limit the pin 7 voltage to 1.2 V when the NTC resistance is high (For example, at 25°C, RNTC > 100 kW). When the temperature increases, the NTC’s resistance reduces bringing the pin 7 voltage down until it reaches a typical value of 0.8 V: the comparator trips and latches−off the controller (see Figure 42). In case of overvoltage, the zener diode starts to conduct and inject current inside the internal clamp resistor Rclamp thus causing the pin 7 voltage to increase. When this voltage reaches the OVP threshold (2.5 V typ), the controller is latched−off: all the DRV pulses stops and VCC is pulled−down to VCC(latch) (7.2 V typ). The circuit un−latches when the current circulating in VCC pin drops below ICC(latch), thus the user must unplug and replug the power supply. Figure 42. Overvoltage and Overtemperature Chronograms http://onsemi.com 23 NCP1380 OVERVOLTAGE PROTECTION / BROWN−OUT (C AND D VERSIONS) The C and D versions of NCP1380 combine brown−out and overvoltage detection on pin 7. HV−Bulk noi s e de l a y VCC + S Dz S Q VOVP Rbou DRV Q − Q La tc h Q OVP/BO R 7 VDD R IBO Rbol noi s e de l a y gr a nd reset − + CS c omp Clamp Rc l a mp BO reset Vclamp VBO Figure 43. Brown−out and Overvoltage Protection when VCC reaches VCC(on) (Figure 44): this ensures a clean startup sequence with soft−start. The hysteresis for the brown−out function is implemented with a high side current source sinking 10 mA when the brown−out comparator is high (Vbulk > Vbulk(on)) In order to protect the power supply against low input voltage condition, the pin 7 permanently monitors a fraction of the bulk voltage through a voltage divider. When this image of bulk voltage is below the VBO threshold, the controller stops switching. When the bulk voltage comes back within safe limits, the circuit will restart pulsing only Figure 44. Brown−out Operating Chronograms Rclamp thus causing pin 7 voltage to increase. When this voltage reaches VOVP, the controller latches−off and stays latched until the user cycles down the power supply (Figure 45). In order to avoid having a too high voltage on pin 7 if the bulk voltage is high, an internal clamp limits the voltage. In case of overvoltage, the zener diode will start to conduct and inject current inside the internal clamp resistor http://onsemi.com 24 NCP1380 Figure 45. Operating Chronograms in Case of Overvoltage The following equations show how to calculate the brownout resistors. R bol + First of all, select the bulk voltage value at which the controller must start switching (Vbulk(on)) and the bulk voltage for shutdown (Vbulk(off)). Then use the following equation to calculate Rbou and Rbol. ǒ V BO V bulk(on) * V bulkǒoffǓ R bou + I BOǒV bulk(on) * V BOǓ R bolǒV bulk(on) * V BOǓ Ǔ (eq. 9) (eq. 10) V BO ORDERING INFORMATION Package Shipping† NCP1380ADR2G SOIC−8 (Pb−Free) 2500 / Tape & Reel NCP1380BDR2G SOIC−8 (Pb−Free) 2500 / Tape & Reel NCP1380CDR2G SOIC−8 (Pb−Free) 2500 / Tape & Reel NCP1380DDR2G SOIC−8 (Pb−Free) 2500 / Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 25 NCP1380 PACKAGE DIMENSIONS SOIC−8 NB CASE 751−07 ISSUE AJ −X− NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW STANDARD IS 751−07. A 8 5 S B 0.25 (0.010) M Y M 1 4 −Y− K G C N DIM A B C D G H J K M N S X 45 _ SEATING PLANE −Z− 0.10 (0.004) H D 0.25 (0.010) M Z Y S X M J S MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0 _ 8 _ 0.010 0.020 0.228 0.244 SOLDERING FOOTPRINT* 1.52 0.060 7.0 0.275 4.0 0.155 0.6 0.024 1.270 0.050 SCALE 6:1 mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. The products described herein (NCP1380), may be covered by one or more of the following U.S. patents; 6,362,067; 5,073,850. There may be other patents pending. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. 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