AMIS-42770 Dual High Speed CAN Transceiver General Description Controller Area Network (CAN) is a serial communication protocol, which supports distributed real−time control and multiplexing with high safety level. Typical applications of CAN−based networks can be found in automotive and industrial environments. The AMIS−42770 Dual−CAN transceiver is the interface between up to two physical bus lines and the protocol controller and will be used for serial data interchange between different electronic units at more than one bus line. It can be used for both 12 V and 24 V systems. The circuit consists of following blocks: • Two differential line transmitters • Two differential line receivers • Interface to the CAN protocol handler • Interface to expand the number of CAN busses • Logic block including repeater function and the feedback suppression • Thermal shutdown circuit (TSD) Due to the wide common−mode voltage range of the receiver inputs, the AMIS−42770 is able to reach outstanding levels of electromagnetic susceptibility (EMS). Similarly, extremely low electromagnetic emission (EME) is achieved by the excellent matching of the output signals. http://onsemi.com SOIC 20 IC SUFFIX CASE 751AQ ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet. Key Features • Fully Compatible with the ISO 11898−2 Standard • Certified “Authentication on CAN Transceiver Conformance (d1.1)” • Wide Range of Bus Communication Speed (up to 1 Mbit/s in Function of the Bus Topology) • Allows Low Transmit Data Rate in Networks Exceeding 1 km • Ideally Suited for 12 V and 24 V Industrial and Automotive Applications • Low EME: Common−mode−choke is No Longer Required • Differential Receiver with Wide Common−mode Range (±35 V) for High EMS • No Disturbance of the Bus Lines with an Un−powered Node • Prolonged Dominant Time−out Function Allowing Communication • • • • Speeds Down to 1 kbit/s Thermal Protection Bus Pins Protected against Transients Short Circuit Proof to Supply Voltage and Ground This is a Pb−Free Device* *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. © Semiconductor Components Industries, LLC, 2009 January, 2009 − Rev. 3 1 Publication Order Number: AMIS−42770/D AMIS−42770 ORDERING INFORMATION Part Number Package Shipping Configuration Temperature Range AMIS42770ICAW1G SOIC−20 300 GREEN Tube/Tray −40°C to 125°C AMIS42770ICAW1RG SOIC−20 300 GREEN Tape & Reel −40°C to 125°C Table 1. TECHNICAL CHARACTERISTICS Symbol Parameter Conditions Min. Max. Unit VCANHx DC voltage at pin CANH1/2 0 < VCC < 5.25 V; no time limit −45 +45 V VCANLx DC voltage at pin CANL1/2 0 < VCC < 5.25 V; no time limit −45 +45 V Differential bus output voltage in dominant state 42.5 W < RLT < 60 W 1.5 3 V CM−range Input common−mode range for comparator Guaranteed differential receiver threshold and leakage current −35 +35 V VCM−peak Common−Mode peak See Figures 10 and 11 (Note 1) −1000 +1000 mV VCM−step Common−Mode step See Figures 10 and 11 (Note 1) −250 +250 mV Vo(dif)(bus_dom) 1. The parameters VCM−peak and VCM−step guarantee low EME. VCC 12 POR Thermal shutdown Driver control Timer Ri(cm) VCC/2 − + COMP VCC Ri(cm) VCC Logic Unit 10 3 VREF ENB1 Text Ri(cm) VCC/2 + − COMP VCC 4 7 Tx0 Rx0 9 Rint Figure 1. Block Diagram http://onsemi.com 2 18 Timer VCC 8 19 Driver control Feedback Suppression CANL1 AMIS−42770 13 14 Feedback Suppression CANH1 2 x timer clock 2 ENB2 Ri(cm) 5 6 15 16 17 GND CANH2 CANL2 AMIS−42770 TYPICAL APPLICATION Application Description AMIS−42770 is especially designed to provide the link between a CAN controller (protocol IC) and two physical busses. It is able to operate in three different modes: • Dual CAN • A CAN−bus extender • A CAN−bus repeater Application Schematics VBAT CAN BUS 1 5 V−reg CAN BUS 2 CD 100 nF VCC EN1 EN2 Rx0 Tx0 Text Rint 10 Vref 8 13 CANH1 12 2 14 7 AMIS−42770 4 19 CANL1 CANH2 3 9 5 18 6 15 16 17 RLT 60 W CANL2 RLT 60 W GND Figure 2. Application Diagram CAN−bus Repeater CAN BUS 1 VBAT 5 V−reg CD 100 nF CD 100 nF VCC VCC EN1 EN2 Rx0 mC CAN controller Tx0 Text Rint 10 Vref 8 13 CANH1 12 2 14 7 AMIS−42770 4 19 CANL1 CANH2 3 9 5 18 6 15 16 17 CANL2 GND GND Figure 3. Application Diagram Dual−CAN http://onsemi.com 3 RLT 60 W RLT 60 W CAN BUS 2 AMIS−42770 CAN BUS 1 VBAT 5 V−reg CD 100 nF CD 100 nF VCC Vref VCC EN1 EN2 10 Tx0 CAN controller 8 13 CANH1 12 2 Rx0 mC CAN BUS 2 Text Rint 14 7 AMIS−42770 4 19 CANL1 CANH2 3 9 5 18 6 15 16 17 RLT 60 W CANL2 RLT 60 W GND GND isolated +5 Dual OptoCoupler CAN BUS 3 CD 100 nF Vref VCC EN1 EN2 Rx0 Tx0 Text Rint 10 8 13 CANH1 12 2 14 7 CANL1 AMIS−42770 4 CANH2 19 3 9 5 6 15 16 17 18 RLT 60 W CANL2 RLT 60 W GND Figure 4. Application Diagram CAN−bus Extender 1 20 NC EN2 2 19 CANH2 Text 3 18 CANL2 Tx0 4 17 GND GND 5 GND 6 Rx0 7 Vref1 8 13 CANH1 Rint 9 12 VCC EN1 10 11 NC AMIS−42770 NC 16 GND 15 GND 14 CANL1 Figure 5. Pin Out (top view) http://onsemi.com 4 CAN BUS 4 AMIS−42770 Table 2. PIN DESCRIPTION Pin Name Description 1 NC 2 ENB2 3 Text Multi−system transmitter Input; internal pull−up 4 Tx0 Transmitter input; internal pull−up 5 GND Ground connection (Note 2) 6 GND Ground connection (Note 2) 7 Rx0 Receiver output 8 VREF1 9 Rint 10 ENB1 11 NC 12 VCC 13 CANH1 CANH transceiver I/O bus system 1 14 CANL1 CANL transceiver I/O bus system 1 15 GND Ground connection (Note 2) 16 GND Ground connection (Note 2) 17 GND Ground connection (Note 2) 18 CANL2 CANL transceiver I/O bus system 2 19 CANH2 CANH transceiver I/O bus system 2 20 NC Not connected Enable input, bus system 2; internal pull−up Reference voltage Multi−system receiver output Enable input, bus system 1; internal pull−up Not connected Positive supply voltage Not connected 2. In order to ensure the chip performance, all these pins need to be connected to GND on the PCB. FUNCTIONAL DESCRIPTION AMIS−42770 can be also used for only one bus system. If the connections for the second bus system are simply left open it serves as a single transceiver for an electronic unit. For correct operation, it is necessary to terminate the open bus by the proper termination resistor. Overall Functional Description AMIS−42770 is specially designed to provide the link between the protocol IC (CAN controller) and two physical bus lines. Data interchange between those two bus lines is realized via the logic unit inside the chip. To provide an independent switch−off of the transceiver units for both bus systems by a third device (e.g. the °C), enable−inputs for the corresponding driving and receiving sections are provided. As long as both lines are enabled, they appear as one logical bus to all nodes connected to either of them. The bus lines can have two logical states, dominant or recessive. A bus is in the recessive state when the driving sections of all transceivers connected to the bus are passive. The differential voltage between the two wires is approximately zero. If at least one driver is active, the bus changes into the dominant state. This state is represented by a differential voltage greater than a minimum threshold and therefore by a current flow through the terminating resistors of the bus line. The recessive state is overwritten by the dominant state. In case a fault (like short circuit) is present on one of the bus lines, it remains limited to that bus line where it occurs. Data interchange from the protocol IC to the other bus system and on this bus system itself can be continued. Logic Unit and CAN Controller Interface The logic unit inside AMIS−42770 provides data transfer from/to the digital interface to/from the two busses and from one bus to the other bus. The detailed function of the logic unit is described in Table 3. All digital input pins, including ENBx, have an internal pull−up resistor to ensure a recessive state when the input is not connected or is accidentally interrupted. A dominant state on the bus line is represented by a low−level at the digital interface; a recessive state is represented by a high−level. Dominant state received on any bus (if enabled) causes a dominant state on both busses, pin Rint and pin Rx0. Dominant signal on any of the input pins Tx0 and Text causes transmission of dominant on both bus lines (if enabled). Digital inputs Tx0 and Text are used for connecting the internal logic’s of several IC’s to obtain versions with more than two bus outputs (see Figure 4). They have also a direct logical link to pins Rx0 and Rint independently on the EN1x pins – dominant on Tx0 is directly transferred to both Rx0 and Rint pins, dominant on Text is only transferred to Rx0. http://onsemi.com 5 AMIS−42770 Transmitters The driver control circuit ensures that the drivers are switched on and off with a controlled slope to limit EME. The driver control circuit will control itself by the thermal protection circuit, the timer circuit and the logic unit. The enable signal ENBx allows the transmitter to be switched off by a third device (e.g. the °C). In the disabled state (ENBx = high) the corresponding transmitter behaves as in the recessive state. The transceiver includes two transmitters, one for each bus line, and a driver control circuit. Each transmitter is implemented as a push and a pull driver. The drivers will be active if the transmission of a dominant bit is required. During the transmission of a recessive bit all drivers are passive. The transmitters have a built−in current limiting circuit that protects the driver stages from damage caused by accidental short circuit to either positive supply voltage or to ground. Additionally a thermal protection circuit is integrated. Table 3. FUNCTION OF THE LOGIC UNIT (bold letters describe input signals) EN1B EN2B TX0 TEXT Bus 1 State Bus 2 State RX0 RINT 0 0 0 0 dominant dominant 0 0 0 0 0 1 dominant dominant 0 0 0 0 1 0 dominant dominant 0 1 0 0 1 1 recessive recessive 1 1 0 0 1 1 dominant (Note 3) dominant 0 0 0 0 1 1 dominant dominant (Note 3) 0 0 0 1 0 0 dominant recessive 0 0 0 1 0 1 dominant recessive 0 0 0 1 1 0 dominant recessive 0 1 0 1 1 1 recessive recessive 1 1 0 1 1 1 dominant (Note 3) recessive 0 0 0 1 1 1 recessive dominant (Note 3) 1 1 1 0 0 0 recessive dominant 0 0 1 0 0 1 recessive dominant 0 0 1 0 1 0 recessive dominant 0 1 1 0 1 1 recessive recessive 1 1 1 0 1 1 dominant (Note 3) recessive 1 1 1 0 1 1 recessive dominant (Note 3) 0 0 1 1 0 0 recessive recessive 0 0 1 1 0 1 recessive recessive 0 0 1 1 1 0 recessive recessive 0 1 1 1 1 1 recessive recessive 1 1 1 1 1 1 dominant (Note 3) recessive 1 1 1 1 1 1 recessive dominant (Note 3) 1 1 3. Dominant detected by the corresponding receiver. Receivers recessive state and does not depend on the bus voltage. In the enabled state the receiver signal sent to the logic unit is identical to the comparator output signal. Two bus receiving sections sense the states of the bus lines. Each receiver section consists of an input filter and a fast and accurate comparator. The aim of the input filter is to improve the immunity against high−frequency disturbances and also to convert the voltage at the bus lines CANHx and CANLx, which can vary from –12 V to +12 V, to voltages in the range 0 to 5 V, which can be applied to the comparators. The output signal of the comparators is gated by the ENBx signal. In the disabled state (ENBX = high), the output signal of the comparator will be replaced by a permanently Time−out Counter To avoid that the transceiver drives a permanent dominant state on either of the bus lines (blocking all communication), time−out function is implemented. Signals on pins Tx0 and Text as well as both bus receivers are connected to the logic unit through independent timers. If the input of the timer stays dominant for longer than 25 ms (see parameter tdom), it is replaced by a recessive signal on the timer output. http://onsemi.com 6 AMIS−42770 Feedback Suppression exceeds thermal shutdown level. Because the transmitters dissipate most of the total power, the transmitters will be switched off only to reduce power dissipation and IC temperature. All other IC functions continue to operate. The logic unit described in Table 3 constantly ensures that dominant symbols on one bus line are transmitted to the other bus line without imposing any priority on either of the lines. This feature would lead to an “interlock” state with permanent dominant signal transmitted to both bus lines, if no extra measure is taken. Therefore feedback suppression is included inside the logic unit of the transceiver. This block masks−out reception on that bus line, on which a dominant is actively transmitted. The reception becomes active again only with certain delay after the dominant transmission on this line is finished. A fault like a short circuit is limited to that bus line where it occurs; hence data interchange from the protocol IC to the other bus system is not affected. When the voltage at the bus lines is going out of the normal operating range (−12 V to +12 V), the receiver is not allowed to erroneously detect a dominant state. Power−on−Reset (POR) Short Circuits Fault Behavior A current−limiting circuit protects the transmitter output stage from damage caused by an accidental short−circuit to either positive or negative supply voltage, although power dissipation increases during this fault condition. The pins CANHx and CANLx are protected from automotive electrical transients (according to “ISO 7637”). While Vcc voltage is below the POR level, the POR circuit makes sure that: • The counters are kept in the reset mode and stable state without current consumption • Inputs are disabled (don’t care) • Outputs are high impedant; only Rx0 = high−level • Analog blocks are in power down • Oscillator not running and in power down • CANHx and CANLx are recessive • VREF output high impedant for POR not released ELECTRICAL CHARACTERISTICS Definitions All voltages are referenced to GND. Positive currents flow into the IC. Sinking current means that the current is flowing into the pin. Sourcing current means that the current is flowing out of the pin. Over Temperature Detection A thermal protection circuit is integrated to prevent the transceiver from damage if the junction temperature Table 4. ABSOLUTE MAXIMUM RATINGS Symbol VCC Parameter Conditions Supply voltage VCANHx DC voltage at pin CANH1/2 0 < VCC < 5.25 V; no time limit VCANLx DC voltage at pin CANL1/2 0 < VCC < 5.25 V; no time limit VdigIO DC voltage at digital IO pins (EN1B, EN2B, Rint, Rx0, Text, Tx0) VREF DC voltage at pin VREF Min. Max. Unit −0.3 +7 V −45 +45 V −45 +45 V −0.3 VCC + 0.3 V −0.3 VCC + 0.3 V Vtran(CANHx) Transient voltage at pin CANH1/2 (Note 4) −150 +150 V Vtran(CANLx) Transient voltage at pin CANL1/2 (Note 4) −150 +150 V ESD voltage at CANH1/2 and CANL1/2 pins (Note 5) (Note 7) −4 −500 +4 +500 kV V ESD voltage at all other pins (Note 5) (Note 7) −2 −250 +2 +250 kV V Static latch−up at all pins (Note 6) Vesd(CANLx/CANHx) Vesd Latch−up 100 mA Tstg Storage temperature −55 +155 °C Tamb Ambient temperature −40 +125 °C Tjunc Maximum junction temperature −40 +150 °C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 4. Applied transient waveforms in accordance with “ISO 7637 part 3”, test pulses 1, 2, 3a, and 3b (see Figure 6) 5. Standardized human body model (HBM) ESD pulses in accordance to MIL883 method 3015. Supply pin 8 is ±2 kV. 6. Static latch−up immunity: static latch−up protection level when tested according to EIA/JESD78. 7. Standardized charged device model ESD pulses when tested according to EOS/ESD DS5.3−1993. http://onsemi.com 7 AMIS−42770 Table 5. THERMAL CHARACTERISTICS Symbol Parameter Conditions Value Unit Rth(vj−a) Thermal resistance from junction to ambient in SO20 package In free air 85 K/W Rth(vj−s) Thermal resistance from junction to substrate of bare die In free air 45 K/W DC CHARACTERISTICS Table 6. DC AND TIMING CHARACTERISTICS (VCC = 4.75 to 5.25 V; Tjunc = −40 to +150°C; RLT = 60 W unless specified otherwise.) Parameter Conditions ICC Supply current, no loads on digital outputs, both busses enabled Dominant transmitted Recessive transmitted PORL_VCC Power−on−reset level on VCC Symbol Min. Typ. Max. Unit 45 137.5 19.5 mA 4.7 V SUPPLY (pin VCC) 2.2 DIGITAL INPUTS (Tx0, Text, EN1B, EN2B) VIH High−level input voltage 0.7 x VCC − VCC V VIL Low−level input voltage −0.3 − 0.3 x VCC V IIH High−level input current VIN = VCC −5 0 +5 mA IIL Low−level input current VIN = 0 V −75 −200 −350 mA Ci Input capacitance Not tested − 5 10 pF DIGITAL OUTPUTS (pin Rx0, Rint) Ioh High−level output current Vo = 0.7 x VCC −5 −10 −15 mA Iol Low−level output current Vo = 0.3 x VCC 5 10 15 mA Reference output voltage −50 mA < IVREF < +50 mA 0.45 x VCC 0.50 x VCC 0.55 x VCC V Reference output voltage for full common mode range −35 V <VCANHx < +35 V; −35 V <VCANLx < +35 V 0.40 x VCC 0.50 x VCC 0.60 x VCC V REFERENCE VOLTAGE OUTPUT (pin VREF1) VREF VREF_CM BUS LINES (pins CANH1/2 and CANL1/2) Vo(reces)(CANHx) Recessive bus voltage at pin CANH1/2 VTx0 = VCC; no load 2.0 2.5 3.0 V Vo(reces)(CANLx) Recessive bus voltage at pin CANL1/2 VTx0 = VCC; no load 2.0 2.5 3.0 V Io(reces) (CANHx) Recessive output current at pin CANH1/2 −35 V < VCANHx < +35 V; 0 V < VCC < 5.25 V −2.5 − +2.5 mA Io(reces) (CANLx) Recessive output current at pin CANL1/2 −35 V < VCANLx < +35 V; 0 V < VCC < 5.25 V −2.5 − +2.5 mA Vo(dom) (CANHx) Dominant output voltage at pin CANH1/2 VTx0 = 0 V 3.0 3.6 4.25 V Vo(dom) (CANLx) Dominant output voltage at pin CANL1/2 VTx0 = 0 V 0. 5 1.4 1.75 V Vo(dif) (bus) Differential bus output voltage (VCANHx − VCANLx) VTx0 = 0 V; dominant; 42.5 W < RLT < 60 W 1.5 2.25 3.0 V VTxD = VCC; recessive; no load −120 0 +50 mV Io(sc) (CANHx) Short circuit output current at pin CANH1/2 VCANHx = 0 V;VTx0 = 0 V −45 −70 −120 mA Io(sc) (CANLx) Short circuit output current at pin CANL1/2 VCANLx = 36 V; VTx0 = 0 V 45 70 120 mA http://onsemi.com 8 AMIS−42770 Table 6. DC AND TIMING CHARACTERISTICS (VCC = 4.75 to 5.25 V; Tjunc = −40 to +150°C; RLT = 60 W unless specified otherwise.) Symbol Parameter Conditions Min. Typ. Max. Unit BUS LINES (pins CANH1/2 and CANL1/2) Vi(dif)(th) Differential receiver threshold voltage −5 V < VCANLx < +12 V; −5 V < VCANHx < +12 V; see Figure 7 0.5 0.7 0.9 V Vihcm(dif) (th) Differential receiver threshold voltage for high common− mode −35 V < VCANLx < +35 V; −35 V < VCANHx < +35 V; see Figure 7 0.3 0.7 1.05 V Differential receiver input voltage hysteresis −35 V < VCANL < +35 V; −35 V < VCANH < +35 V; see Figure 7 50 70 100 mV Vi(dif) (hys) Ri(cm)(CANHx) Common−mode input resistance at pin CANH1/2 15 26 37 KW Ri(cm) (CANLx) Common−mode input resistance at pin CANL1/2 15 26 37 KW −3 0 +3 % 25 50 75 KW Ri(cm)(m) Ri(dif) Matching between pin CANH1/2 and pin CANL1/2 common− mode input resistance VCANHx = VCANLx Differential input resistance Ci(CANHx) Input capacitance at pin CANH1/2 VTx0 = VCC; not tested 7.5 20 pF Ci(CANLx) Input capacitance at pin CANL1/2 VTx0 = VCC; not tested 7.5 20 pF Differential input capacitance VTx0 = VCC; not tested 3.75 10 pF Ci(dif) ILI(CANHx) Input leakage current at pin CANH1/2 VCC < PORL_VCC; −5.25 V < VCANHx < 5.25 V −350 170 350 mA ILI(CANLx) Input leakage current at pin CANL1/2 VCC < PORL_VCC; −5.25 V < VCANLx < 5.25 V −350 170 350 mA VCM−peak Common−mode peak during transition from dom → rec or rec → dom See Figure 11 −1000 1000 mV VCM−step Difference in common−mode between dominant and recessive state See Figure 11 −250 250 mV THERMAL SHUTDOWN Tj(sd) Shutdown junction temperature 150 °C TIMING CHARACTERISTICS (see Figures 8 and 9) td(Tx−BUSon) Delay Tx0/Text to bus active 40 85 120 ns td(Tx−BUSoff) Delay Tx0/Text to bus inactive 30 60 115 ns td(BUSon−RX) Delay bus active to Rx0/Rint 25 55 115 ns td(BUSoff−RX) Delay bus inactive to Rx0/Rint 65 100 145 ns 100 200 ns 4 10 35 ns 15 25 45 ms 300 ns td(ENxB) Delay from EN1B to bus active/inactive td(Tx−Rx) Delay from Tx0 to Rx0/Rint and from Text to Rx0 (direct logical path) tdom td(FBS) 15 pF on the digital output Time out counter interval Delay for feedback suppression release 5+ td(BUSon−RX) http://onsemi.com 9 AMIS−42770 Measurement Set−ups and Definitions Schematics are given for single CAN transceiver. +5V 100 nF VCC Vref 8 13 CANH1 12 Text 1 nF Transient Generator 3 Rint 14 9 AMIS−42770 Tx0 19 CANL1 CANH2 1 nF 4 Rx0 7 10 18 17 16 15 6 5 2 CANL2 GND EN1 EN2 Figure 6. Test Circuit for Automotive Transients VRxD High Low Hysteresis 0,9 0,5 Vi(dif)(hys) Figure 7. Hysteresis of the Receiver +5 V 100 nF Vref VCC 12 Text Rint 8 13 CANH1 RLT 3 14 9 AMIS−42770 Tx0 19 CANL1 7 10 EN1 2 17 16 15 6 18 5 RLT CANL2 60 W GND EN2 Figure 8. Test Circuit for Timing Characteristics http://onsemi.com 10 CLT 100 pF CANH2 4 Rx0 60 W CLT 100 pF AMIS−42770 Tx0 Text 0,7 VCC 0,3 VCC VCANHx−BUS VCANHx VDIFF = VCANHx − VCANLx VCANLx dominant 5V 0,9 V 0V 0,9 V 0,5 V 0,5 V tPD(H) 0,3 VCC td(Tx−Rx) 0,7 VCC 0,3 VCC td(Tx−Rx) td(Tx−BUSoff) td(Tx−BUSon) td(BUSon−Rx) td(BUSoff−Rx) Figure 9. Timing Diagram for AC Characteristics +5 V 100 nF Vref VCC Rint 10 nF 3 Active Probe 14 9 AMIS−42770 Tx0 19 CANL1 7 10 EN1 2 17 16 15 EN2 6 18 5 6.2 kW CANH2 30 W 4 Rx0 6.2 kW 8 13 CANH1 12 Text Gen recessive 0,7 VCC Rx0 Rint Spectrum Anayzer 30 W CANL2 47 nF GND Figure 10. Basic Test Set−up for Electromagnetic Measurement http://onsemi.com 11 AMIS−42770 CANHx CANLx recessive VCM−peak VCM−peak VCM = 0.5* (VCANHx + VCANLx) VCM−peak Figure 11. Common−mode Voltage Peaks (see Measurement Set−up Figure 10) Company or Product Inquiries For more information about ON Semiconductor’s products or services visit our Web site at http://www.onsemi.com. http://onsemi.com 12 AMIS−42770 PACKAGE DIMENSIONS SOIC 20 W CASE 751AQ−01 ISSUE O ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. 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This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: [email protected] N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81−3−5773−3850 http://onsemi.com 13 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative AMIS−42770/D