INTEGRATED CIRCUITS NOTICE PLEASE SEE THE P87C552 DATA SHEET FOR NEW DESIGN-INS 87C552 80C51 8-bit microcontroller 8K/256 OTP, 8 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O Product specification Supersedes data of 1998 Jan 19 IC20 Data Handbook 1998 May 01 Philips Semiconductors Product specification 80C51 8-bit microcontroller 87C552 8K/256 OTP, 8 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O DESCRIPTION The 87C552 Single-Chip 8-Bit Microcontroller is manufactured in an advanced CMOS process and is a derivative of the 80C51 microcontroller family. The 87C552 has the same instruction set as the 80C51. Three versions of the derivative exist: • 83C552—8k bytes mask programmable ROM • 80C552—ROMless version of the 83C552 • 87C552—8k bytes EPROM The 87C552 contains a 8k × 8 a volatile 256 × 8 read/write data memory, five 8-bit I/O ports, one 8-bit input port, two 16-bit timer/event counters (identical to the timers of the 80C51), an additional 16-bit timer coupled to capture and compare latches, a 15-source, two-priority-level, nested interrupt structure, an 8-input ADC, a dual DAC pulse width modulated interface, two serial interfaces (UART and I2C-bus), a “watchdog” timer and on-chip oscillator and timing circuits. For systems that require extra capability, the 87C552 can be expanded using standard TTL compatible memories and logic. FEATURES • 80C51 central processing unit • 8k × 8 EPROM expandable externally to 64k bytes • An additional 16-bit timer/counter coupled to four capture registers and three compare registers • Two standard 16-bit timer/counters • 256 × 8 RAM, expandable externally to 64k bytes • Capable of producing eight synchronized, timed outputs • A 10-bit ADC with eight multiplexed analog inputs • Two 8-bit resolution, pulse width modulation outputs • Five 8-bit I/O ports plus one 8-bit input port shared with analog In addition, the 87C552 has two software selectable modes of power reduction—idle mode and power-down mode. The idle mode freezes the CPU while allowing the RAM, timers, serial ports, and interrupt system to continue functioning. The power-down mode saves the RAM contents but freezes the oscillator, causing all other chip functions to be inoperative. inputs The device also functions as an arithmetic processor having facilities for both binary and BCD arithmetic plus bit-handling capabilities. The instruction set consists of over 100 instructions: 49 one-byte, 45 two-byte, and 17 three-byte. With a 16MHz crystal, 58% of the instructions are executed in 0.75µs and 40% in 1.5µs. Multiply and divide instructions require 3µs. • I2C-bus serial I/O port with byte oriented master and slave functions • Full-duplex UART compatible with the standard 80C51 • On-chip watchdog timer • 16MHz speed • Extended temperature ranges • OTP package available ORDERING INFORMATION EPROM TEMPERATURE °C AND PACKAGE FREQ MHz DRAWING NUMBER S87C552-4A68 0 to +70, Plastic Leaded Chip Carrier 16 SOT188-3 S87C552-4BA 0 to +70, Plastic Quad Flat Pack 16 SOT318-2 S87C552-5A68 –40 to +85, Plastic Leaded Chip Carrier 16 SOT188-3 NOTE: 1. For ROM and ROMless see data sheet 80C552/83C552 1998 May 01 2 853-1690 19336 Philips Semiconductors Product specification 80C51 8-bit microcontroller 87C552 8K/256 OTP, 8 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O BLOCK DIAGRAM T0 T1 3 INT0 3 INT1 3 PWM0 VDD 3 PWM1 AVSS AVREF ADC0-7 SDA – + VSS AVDD STADC 5 SCL 1 1 XTAL1 T0, T1 TWO 16-BIT TIMER/EVENT COUNTERS XTAL2 PROGRAM MEMORY 8k x 8 EPROM CPU EA ALE DUAL PWM SERIAL I2C PORT ADC 80C51 CORE EXCLUDING ROM/RAM PSEN 3 DATA MEMORY 256 x 8 RAM WR 8-BIT INTERNAL BUS 3 RD 16 0 AD0-7 PARALLEL I/O PORTS AND EXTERNAL BUS 2 SERIAL UART PORT FOUR 16-BIT CAPTURE LATCHES 8-BIT PORT A8-15 3 P0 P1 P2 P3 TxD 3 RxD 1 P5 P4 CT0I-CT3I ALTERNATE FUNCTION OF PORT 0 3 ALTERNATE FUNCTION OF PORT 3 1 ALTERNATE FUNCTION OF PORT 1 4 ALTERNATE FUNCTION OF PORT 4 2 ALTERNATE FUNCTION OF PORT 2 5 ALTERNATE FUNCTION OF PORT 5 0 T2 16-BIT TIMER/ EVENT COUNTERS 1 16 1 T2 RT2 T2 16-BIT COMPARATORS WITH REGISTERS COMPARATOR OUTPUT SELECTION T3 WATCHDOG TIMER 4 CMSR0-CMSR5 CMT0, CMT1 RST EW SU00211 1998 May 01 3 Philips Semiconductors Product specification 80C51 8-bit microcontroller 87C552 8K/256 OTP, 8 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O LOGIC SYMBOL PIN CONFIGURATIONS VSS VDD 9 XTAL1 XTAL2 EA/VPP ALE/PROG PSEN AVSS AVDD AVref+ AVref– STADC PWM0 PWM1 1 61 PORT 0 10 60 PLASTIC LEADED CHIP CARRIER LOW ORDER ADDRESS AND DATA BUS 26 PORT 1 CT0I CT1I CT2I CT3I T2 RT2 SCL SDA PORT 2 PORT 5 ADC0-7 27 Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 HIGH ORDER ADDRESS AND DATA BUS PORT 3 PORT 4 CMSR0-5 CMT0 CMT1 RST EW 44 RxD/DATA TxD/CLOCK INT0 INT1 T0 T1 WR RD SU00210 Pin 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 Function P5.0/ADC0 VDD STADC PWM0 PWM1 EW P4.0/CMSR0 P4.1/CMSR1 P4.2/CMSR2 P4.3/CMSR3 P4.4/CMSR4 P4.5/CMSR5 P4.6/CMT0 P4.7/CMT1 RST P1.0/CT0I P1.1/CT1I P1.2/CT2I P1.3/CT3I P1.4/T2 P1.5/RT2 P1.6/SCL P1.7/SDA 43 Function P3.0/RxD P3.1/TxD P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 P3.6/WR P3.7/RD NC NC XTAL2 XTAL1 VSS VSS NC P2.0/A08 P2.1/A09 P2.2/A10 P2.3/A11 P2.4/A12 P2.5/A13 P2.6/A14 P2.7/A15 Pin 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 Function PSEN ALE/PROG EA/VPP P0.7/AD7 P0.6/AD6 P0.5/AD5 P0.4/AD4 P0.3/AD3 P0.2/AD2 P0.1/AD1 P0.0/AD0 AVref– AVref+ AVSS AVDD P5.7/ADC7 P5.6/ADC6 P5.5/ADC5 P5.4/ADC4 P5.3/ADC3 P5.2/ADC2 P5.1/ADC1 SU00208 PLASTIC QUAD FLAT PACK PIN FUNCTIONS 80 65 1 64 PQFP 24 41 25 40 Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Function P4.1/CMSR1 P4.2/CMSR2 NC P4.3/CMSR3 P4.4/CMSR4 P4.5/CMSR5 Pin 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 P4.6/CMT0 P4.7/CMT1 RST P1.0/CT0I P1.1/CT1I P1.2/CT2I P1.3/CT3I P1.4/T2 P1.5/RT2 P1.6/SCL P1.7/SDA P3.0/RxD P3.1/TxD P3.2/INT0 NC = Not Connected IC = Internally Connected (do not use) 1998 May 01 4 Function NC NC P3.3/INT1 P3.4/T0 P3.5/T1 P3.6/WR P3.7/RD NC NC NC XTAL2 XTAL1 IC VSS VSS VSS NC P2.0/A08 P2.1/A09 P2.2/A10 Pin 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 Function P2.3/A11 P2.4/A12 NC NC P2.5/A13 P2.6/A14 P2.7/A15 PSEN ALE/PROG EA/VPP P0.7/AD7 P0.6/AD6 P0.5/AD5 P0.4/AD4 P0.3/AD3 P0.2/AD2 P0.1/AD1 P0.0/AD0 AVref– AVref+ Pin 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 Function AVSS NC AVDD P5.7/ADC7 P5.6/ADC6 P5.5/ADC5 P5.4/ADC4 P5.3/ADC3 P5.2/ADC2 P5.1/ADC1 P5.0/ADC0 VDD IC STADC PWM0 PWM1 EW NC NC P4.0/CMSR0 SU00209 Philips Semiconductors Product specification 80C51 8-bit microcontroller 8K/256 OTP, 8 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O 87C552 PIN DESCRIPTION PIN NO. MNEMONIC PLCC QFP TYPE VDD 2 72 I Digital Power Supply: +5V power supply pin during normal operation, idle and power-down mode. STADC 3 74 I Start ADC Operation: Input starting analog to digital conversion (ADC operation can also be started by software). PWM0 4 75 O Pulse Width Modulation: Output 0. PWM1 5 76 O Pulse Width Modulation: Output 1. EW 6 77 I Enable Watchdog Timer: Enable for T3 watchdog timer and disable power-down mode. P0.0-P0.7 57-50 58-51 I/O Port 0: Port 0 is an 8-bit open-drain bidirectional I/O port. Port 0 pins that have 1s written to them float and can be used as high-impedance inputs. Port 0 is also the multiplexed low-order address and data bus during accesses to external program and data memory. In this application it uses strong internal pull-ups when emitting 1s. Port 0 is also used to input the code byte during programming and to output the code byte during verification. P1.0-P1.7 16-23 16-21 22-23 16-19 20 21 22 23 10-17 10-15 16-17 10-13 14 15 16 17 I/O I/O I/O I I I I/O I/O Port 1: 8-bit I/O port. Alternate functions include: (P1.0-P1.5): Quasi-bidirectional port pins. (P1.6, P1.7): Open drain port pins. CT0I-CT3I (P1.0-P1.3): Capture timer input signals for timer T2. T2 (P1.4): T2 event input. RT2 (P1.5): T2 timer reset signal. Rising edge triggered. SCL (P1.6): Serial port clock line I2C-bus. SDA (P1.7): Serial port data line I2C-bus. Port 1 is also used to input the lower order address byte during EPROM programming and verification. A0 is on P1.0, etc. P2.0-P2.7 39-46 38-42, 45-47 I/O Port 2: 8-bit quasi-bidirectional I/O port. Alternate function: High-order address byte for external memory (A08-A15). Port 2 is also used to input the upper order address during EPROM programming and verification. A8 is on P2.0, A9 on P2.1, through A12 on P2.4. P3.0-P3.7 24-31 18-20, 23-27 18 19 20 23 24 25 26 27 I/O Port 3: 8-bit quasi-bidirectional I/O port. Alternate functions include: 80, 1-2 4-8 80, 1-2 4-6 7, 8 I/O Port 4: 8-bit quasi-bidirectional I/O port. Alternate functions include: O CMSR0-CMSR5 (P4.0-P4.5): Timer T2 compare and set/reset outputs on a match with timer T2. CMT0, CMT1 (P4.6, P4.7): Timer T2 compare and toggle outputs on a match with timer T2. 68-62, 1 71-64, I RST 15 9 I/O Reset: Input to reset the 87C552. It also provides a reset pulse as output when timer T3 overflows. XTAL1 35 32 I Crystal Input 1: Input to the inverting amplifier that forms the oscillator, and input to the internal clock generator. Receives the external clock signal when an external oscillator is used. XTAL2 34 31 O Crystal Input 2: Output of the inverting amplifier that forms the oscillator. Left open-circuit when an external clock is used. 36, 37 34-36 I Digital ground. 47 48 O Program Store Enable: Active-low read strobe to external program memory. 24 25 26 27 28 29 30 31 P4.0-P4.7 7-14 7-12 13, 14 P5.0-P5.7 VSS PSEN 1998 May 01 NAME AND FUNCTION RxD(P3.0): Serial input port. TxD (P3.1): Serial output port. INT0 (P3.2): External interrupt. INT1 (P3.3): External interrupt. T0 (P3.4): Timer 0 external input. T1 (P3.5): Timer 1 external input. WR (P3.6): External data memory write strobe. RD (P3.7): External data memory read strobe. O Port 5: 8-bit input port. ADC0-ADC7 (P5.0-P5.7): Alternate function: Eight input channels to ADC. 5 Philips Semiconductors Product specification 80C51 8-bit microcontroller 87C552 8K/256 OTP, 8 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O PIN DESCRIPTION (Continued) PIN NO. MNEMONIC PLCC QFP TYPE NAME AND FUNCTION ALE/PROG 48 49 O Address Latch Enable: Latches the low byte of the address during accesses to external memory. It is activated every six oscillator periods. During an external data memory access, one ALE pulse is skipped. ALE can drive up to eight LS TTL inputs and handles CMOS inputs without an external pull-up. This pin is also the program pulse input (PROG) during EPROM programming. EA/VPP 49 50 I External Access: When EA is held at TTL level high, the CPU executes out of the internal program ROM provided the program counter is less than 8192. When EA is held at TTL low level, the CPU executes out of external program memory. EA is not allowed to float. This pin also receives the 12.75V programming supply voltage (VPP) during EPROM programming. AVREF– 58 59 I Analog to Digital Conversion Reference Resistor: Low-end. AVREF+ 59 60 I Analog to Digital Conversion Reference Resistor: High-end. AVSS 60 61 I Analog Ground AVDD 61 63 I Analog Power Supply NOTE: 1. To avoid “latch-up” effect at power-on, the voltage on any pin at any time must not be higher or lower than VDD + 0.5V or VSS – 0.5V, respectively. OSCILLATOR CHARACTERISTICS IDLE MODE XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier. The pins can be configured for use as an on-chip oscillator, as shown in the logic symbol. In the idle mode, the CPU puts itself to sleep while some of the on-chip peripherals stay active. The instruction to invoke the idle mode is the last instruction executed in the normal operating mode before the idle mode is activated. The CPU contents, the on-chip RAM, and all of the special function registers remain intact during this mode. The idle mode can be terminated either by any enabled interrupt (at which time the process is picked up at the interrupt service routine and continued), or by a hardware reset which starts the processor in the same manner as a power-on reset. To drive the device from an external clock source, XTAL1 should be driven while XTAL2 is left unconnected. There are no requirements on the duty cycle of the external clock signal, because the input to the internal clock circuitry is through a divide-by-two flip-flop. However, minimum and maximum high and low times specified in the data sheet must be observed. POWER-DOWN MODE RESET In the power-down mode, the oscillator is stopped and the instruction to invoke power-down is the last instruction executed. Only the contents of the on-chip RAM are preserved. A hardware reset is the only way to terminate the power-down mode. The control bits for the reduced power modes are in the special function register PCON. Table 1 shows the state of the I/O ports during low current operating modes. A reset is accomplished by holding the RST pin high for at least two machine cycles (24 oscillator periods), while the oscillator is running. To insure a good power-on reset, the RST pin must be high long enough to allow the oscillator time to start up (normally a few milliseconds) plus two machine cycles. At power-on, the voltage on VDD and RST must come up at the same time for a proper start-up. Table 1. External Pin Status During Idle and Power-Down Modes PROGRAM MEMORY ALE PSEN PORT 0 PORT 1 PORT 2 PORT 3 PORT 4 PWM0/ PWM1 Idle Internal 1 1 Data Data Data Data Data High Idle External 1 1 Float Data Address Data Data High Power-down Internal 0 0 Data Data Data Data Data High Power-down External 0 0 Float Data Data Data Data High MODE 1998 May 01 6 Philips Semiconductors Product specification 80C51 8-bit microcontroller 87C552 8K/256 OTP, 8 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O Serial Control Register (S1CON) – See Table 2 S1CON (D8H) CR2 ENS1 STA STO SI AA CR1 CR0 Bits CR0, CR1 and CR2 determine the serial clock frequency that is generated in the master mode of operation. Table 2. Serial Clock Rates BIT FREQUENCY (kHz) AT fOSC CR2 CR1 CR0 6MHz 12MHz 16MHz fOSC DIVIDED BY 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 23 27 31.25 37 6.25 50 100 0.25 < 62.5 0 to 225 47 54 62.5 75 12.5 100 200 0.5 < 62.5 0 to 224 62.5 71 83.3 100 17 133 1 267 1 0.67 < 56 0 to 223 256 224 192 160 960 120 60 96 × (256 – (reload value Timer 1)) Timer 1 in Mode 2. NOTE: 1. These frequencies exceed the upper limit of 100kHz of the I2C-bus specification and cannot be used in an I2C-bus application. ABSOLUTE MAXIMUM RATINGS1, 2, 3 RATING UNIT Storage temperature range –65 to +150 °C Voltage on EA/VPP to VSS –0.5 to +13 V Voltage on any other pin to VSS –0.5 to +6.5 V Input, output DC current on any single I/O pin 5.0 mA Power dissipation (based on package heat transfer limitations, not device power consumption) 1.0 W PARAMETER NOTES: 1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any conditions other than those described in the AC and DC Electrical Characteristics section of this specification is not implied. 2. This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maxima. 3. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless otherwise noted. DEVICE SPECIFICATIONS SUPPLY VOLTAGE (V) TYPE FREQUENCY (MHz) MIN MAX MIN MAX TEMPERATURE RANGE (°C) P87C552-4 4.5 5.5 3.5 16 0 to +70 P87C552-5 4.5 5.5 3.5 16 –40 to +85 1998 May 01 7 Philips Semiconductors Product specification 80C51 8-bit microcontroller 87C552 8K/256 OTP, 8 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O DC ELECTRICAL CHARACTERISTICS VSS, AVSS = 0V SYMBOL PARAMETER IDD Supply current operating: PCA8XC552-5-16 IID Idle mode: 87C552 IPD Power-down current: TEST CONDITIONS 87C552 LIMITS MIN MAX UNIT See notes 1 and 2 fOSC = 16MHz 40 mA See notes 1 and 3 fOSC = 16MHz 7 mA See notes 1 and 4; 2V < VPD < VDD max 50 µA Inputs VIL Input low voltage, except EA, P1.6, P1.7 –0.5 0.2VDD–0.1 V VIL1 Input low voltage to EA –0.5 0.2VDD–0.3 V P1.7/SDA5 VIL2 Input low voltage to P1.6/SCL, VIH Input high voltage, except XTAL1, RST –0.5 0.3VDD V 0.2VDD+0.9 VDD+0.5 V VIH1 VIH2 Input high voltage, XTAL1, RST 0.7VDD VDD+0.5 V Input high voltage, P1.6/SCL, P1.7/SDA5 0.7VDD 6.0 V IIL Logical 0 input current, ports 1, 2, 3, 4, except P1.6, P1.7 ITL Logical 1-to-0 transition current, ports 1, 2, 3, 4, except P1.6, P1.7 VIN = 0.45V –50 µA See note 6 –650 µA ±IIL1 Input leakage current, port 0, EA, STADC, EW 0.45V < VI < VDD 10 µA ±IIL2 Input leakage current, P1.6/SCL, P1.7/SDA 0V < VI < 6V 0V < VDD < 5.5V 10 µA ±IIL3 Input leakage current, port 5 0.45V < VI < VDD 1 µA IOL = 1.6mA7 0.45 V 3.2mA7 0.45 V 0.4 V Outputs VOL Output low voltage, ports 1, 2, 3, 4, except P1.6, P1.7 VOL1 Output low voltage, port 0, ALE, PSEN, PWM0, PWM1 IOL = VOL2 Output low voltage, P1.6/SCL, P1.7/SDA IOL = 3.0mA7 VOH Output high voltage, ports 1, 2, 3, 4, except P1.6/SCL, P1.7/SDA VOH1 Output high voltage (port 0 in external bus mode, ALE, PSEN, PWM0, PWM1)8 VOH2 Output high voltage (RST) RRST Internal reset pull-down resistor CIO Pin capacitance –IOH = 60µA –IOH = 25µA –IOH = 10µA 2.4 0.75VDD 0.9VDD V V V –IOH = 400µA –IOH = 150µA –IOH = 40µA 2.4 0.75VDD 0.9VDD V V V –IOH = 400µA –IOH = 120µA 2.4 0.8VDD V V 50 Test freq = 1MHz, Tamb = 25°C 150 kΩ 10 pF 5.5 V 1.2 mA 50 µA 50 µA Analog Inputs AVDD Analog supply voltage: 87C5529 AVDD = VDD±0.2V AIDD Analog supply current: operating: Port 5 = 0 to AVDD AIID Idle mode: 87C552 AIPD 1998 May 01 Power-down mode: 87C552 4.5 2V < AVPD < AVDD max 8 Philips Semiconductors Product specification 80C51 8-bit microcontroller 87C552 8K/256 OTP, 8 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O DC ELECTRICAL CHARACTERISTICS (Continued) TEST SYMBOL PARAMETER CONDITIONS LIMITS MIN MAX UNIT AVDD+0.2 V AVDD+0.2 V V 50 kΩ 15 pF Analog Inputs (Continued) AVIN Analog input voltage AVSS–0.2 AVREF Reference voltage: AVREF– AVREF+ AVSS–0.2 RREF Resistance between AVREF+ and AVREF– CIA Analog input capacitance 10 tADS Sampling time 8tCY µs tADC Conversion time (including sampling time) 50tCY µs DLe Differential non-linearity10, 11, 12 ±1 LSB ILe Integral non-linearity10, 13 ±2 LSB error10, 14 OSe Offset Ge Gain error10, 15 error10, 16 Ae Absolute voltage MCTC Channel to channel matching 517 ±2 LSB ±0.4 % ±3 LSB ±1 LSB Ct Crosstalk between inputs of port 0–100kHz –60 dB NOTES FOR DC ELECTRICAL CHARACTERISTICS: 1. See Figures 10 through 15 for IDD test conditions. 2. The operating supply current is measured with all output pins disconnected; XTAL1 driven with tr = tf = 10ns; VIL = VSS + 0.5V; VIH = VDD – 0.5V; XTAL2 not connected; EA = RST = Port 0 = EW = VDD; STADC = VSS. 3. The idle mode supply current is measured with all output pins disconnected; XTAL1 driven with tr = tf = 10ns; VIL = VSS + 0.5V; VIH = VDD – 0.5V; XTAL2 not connected; Port 0 = EW = VDD; EA = RST = STADC = VSS. 4. The power-down current is measured with all output pins disconnected; XTAL2 not connected; Port 0 = EW = VDD; EA = RST = STADC = XTAL1 = VSS. 5. The input threshold voltage of P1.6 and P1.7 (SIO1) meets the I2C specification, so an input voltage below 1.5V will be recognized as a logic 0 while an input voltage above 3.0V will be recognized as a logic 1. 6. Pins of ports 1 (except P1.6, P1.7), 2, 3, and 4 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its maximum value when VIN is approximately 2V. 7. Capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the VOLs of ALE and ports 1 and 3. The noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operations. In the worst cases (capacitive loading > 100pF), the noise pulse on the ALE pin may exceed 0.8V. In such cases, it may be desirable to qualify ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input. IOL can exceed these conditions provided that no single output sinks more than 5mA and no more than two outputs exceed the test conditions. 8. Capacitive loading on ports 0 and 2 may cause the VOH on ALE and PSEN to momentarily fall below the 0.9VDD specification when the address bits are stabilizing. 9. The following condition must not be exceeded: VDD – 0.2V < AVDD < VDD + 0.2V. 10. Conditions: AVREF– = 0V; AVDD = 5.0V. Measurement by continuous conversion of AVIN = –20mV to 5.12V in steps of 0.5mV, derivating parameters from collected conversion results of ADC. AVREF+ (87C552) = 4.977V. ADC is monotonic with no missing codes. 11. The differential non-linearity (DLe) is the difference between the actual step width and the ideal step width. (See Figure 1.) 12. The ADC is monotonic; there are no missing codes. 13. The integral non-linearity (ILe) is the peak difference between the center of the steps of the actual and the ideal transfer curve after appropriate adjustment of gain and offset error. (See Figure 1.) 14. The offset error (OSe) is the absolute difference between the straight line which fits the actual transfer curve (after removing gain error), and a straight line which fits the ideal transfer curve. (See Figure 1.) 15. The gain error (Ge) is the relative difference in percent between the straight line fitting the actual transfer curve (after removing offset error), and the straight line which fits the ideal transfer curve. Gain error is constant at every point on the transfer curve. (See Figure 1.) 16. The absolute voltage error (Ae) is the maximum difference between the center of the steps of the actual transfer curve of the non-calibrated ADC and the ideal transfer curve. 17. This should be considered when both analog and digital signals are simultaneously input to port 5. 1998 May 01 9 Philips Semiconductors Product specification 80C51 8-bit microcontroller 87C552 8K/256 OTP, 8 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O Offset error OSe Gain error Ge 1023 1022 1021 1020 1019 1018 (2) 7 (1) Code Out 6 5 (5) 4 (4) 3 (3) 2 1 1 LSB (ideal) 0 1 2 3 4 5 6 7 1018 1019 1020 1021 1022 1023 1024 AVIN (LSBideal) Offset error OSe 1 LSB = AVREF+ – AVREF– 1024 (1) Example of an actual transfer curve. (2) The ideal transfer curve. (3) Differential non-linearity (DLe). (4) Integral non-linearity (ILe). (5) Center of a step of the actual transfer curve. SU00212 Figure 1. ADC Conversion Characteristic 1998 May 01 10 Philips Semiconductors Product specification 80C51 8-bit microcontroller 87C552 8K/256 OTP, 8 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O AC ELECTRICAL CHARACTERISTICS1, 2 12MHz CLOCK SYMBOL FIGURE PARAMETER MIN MAX 16MHz CLOCK MIN MAX VARIABLE CLOCK MIN MAX UNIT 3.5 16 MHz 1/tCLCL 2 Oscillator frequency tLHLL 2 ALE pulse width 127 tAVLL 2 Address valid to ALE low tLLAX 2 Address hold after ALE low tLLIV 2 ALE low to valid instruction in tLLPL 2 ALE low to PSEN low 43 23 tCLCL–40 tPLPH 2 PSEN pulse width 205 143 3tCLCL–45 tPLIV 2 PSEN low to valid instruction in tPXIX 2 Input instruction hold after PSEN tPXIZ 2 Input instruction float after PSEN 59 38 tCLCL–25 ns tAVIV 2 Address to valid instruction in 312 208 5tCLCL–105 ns tPLAZ 2 PSEN low to address float 10 10 10 ns tAVLL 3, 4 Address valid to ALE low 43 23 tCLCL–40 ns tRLRH 3 RD pulse width 400 275 6tCLCL–100 ns tWLWH 3 WR pulse width 400 275 6tCLCL–100 tRLDV 3 RD low to valid data in tRHDX 3 Data hold after RD tRHDZ 3 Data float after RD 97 55 2tCLCL–70 ns tLLDV 3 ALE low to valid data in 517 350 8tCLCL–150 ns tAVDV 3 Address to valid data in 9tCLCL–165 ns tLLWL 3, 4 ALE low to RD or WR low 200 3tCLCL+50 ns tAVWL 3, 4 Address valid to WR low or RD low 203 tQVWX 4 Data valid to WR transition 23 tDW 4 Data before WR 433 tWHQX 4 Data hold after WR 33 13 tRLAZ 4 RD low to address float tWHLH 3, 4 85 2tCLCL–40 ns 28 8 tCLCL–55 ns 48 28 tCLCL–35 234 150 145 0 83 0 ns 4tCLCL–100 ns ns ns 3tCLCL–105 0 ns ns Data Memory 252 0 148 0 585 300 43 238 120 123 3tCLCL–50 ns ns 4tCLCL–130 ns 3 tCLCL–60 ns 288 7tCLCL–150 ns tCLCL–50 ns 0 RD or WR high to ALE high 0 398 138 ns 5tCLCL–165 0 23 103 tCLCL–40 0 ns tCLCL+40 ns External Clock tCHCX 5 High time3 20 20 20 tCLCX 5 Low time3 20 20 20 tCLCH 5 Rise time3 tCHCL 5 Fall time3 ns ns 20 20 20 ns 20 20 20 ns Serial Timing – Shift Register Mode4 (Test Conditions: Tamb = 0°C to +70°C; VSS = 0V; Load Capaciatnce = 80pF) tXLXL 6 Serial port clock cycle time 1.0 0.75 12tCLCL µs tQVXH 6 Output data setup to clock rising edge 700 492 10tCLCL–133 ns tXHQX 6 Output data hold after clock rising edge 50 8 2tCLCL–117 ns tXHDX 6 Input data hold after clock rising edge 0 0 0 tXHDV 6 Clock rising edge to input data valid 700 492 NOTES: 1. Parameters are valid over operating temperature range unless otherwise specified. 2. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF. 3. tCLCL = 1/fOSC = one oscillator clock period. tCLCL = 83.3ns at fOSC = 12MHz. tCLCL = 62.5ns at fOSC = 16MHz. 4. These values are characterized but not 100% production tested. 1998 May 01 11 ns 10tCLCL–133 ns Philips Semiconductors Product specification 80C51 8-bit microcontroller 87C552 8K/256 OTP, 8 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O AC ELECTRICAL CHARACTERISTICS (Continued) SYMBOL PARAMETER INPUT OUTPUT I2C Interface (Refer to Figure 9)5 tHD;STA START condition hold time ≥ 14 tCLCL > 4.0µs 1 tLOW SCL low time ≥ 16 tCLCL > 4.7µs 1 tHIGH SCL high time ≥ 14 tCLCL > 4.0µs 1 tRC SCL rise time ≤ 1µs –2 tFC SCL fall time ≤ 0.3µs < 0.3µs 3 tSU;DAT1 Data set-up time ≥ 250ns > 20 tCLCL – tRD tSU;DAT2 SDA set-up time (before rep. START cond.) ≥ 250ns > 1µs 1 tSU;DAT3 SDA set-up time (before STOP cond.) ≥ 250ns > 8 tCLCL tHD;DAT Data hold time ≥ 0ns > 8 tCLCL – tFC tSU;STA Repeated START set-up time ≥ 14 tCLCL > 4.7µs 1 tSU;STO STOP condition set-up time ≥ 14 tCLCL > 4.0µs 1 tBUF Bus free time ≥ 14 tCLCL > 4.7µs 1 tRD SDA rise time ≤ 1µs –2 tFD SDA fall time ≤ 0.3µs < 0.3µs 3 NOTES: 1. At 100 kbit/s. At other bit rates this value is inversely proportional to the bit-rate of 100 kbit/s. 2. Determined by the external bus-line capacitance and the external bus-line pull-resistor, this must be < 1µs. 3. Spikes on the SDA and SCL lines with a duration of less than 3 tCLCL will be filtered out. Maximum capacitance on bus-lines SDA and SCL = 400pF. 4. tCLCL = 1/fOSC = one oscillator clock period at pin XTAL1. For 62ns (42s) < tCLCL < 285ns (16MHz (24Hz) > fOSC > 3.5MHz) the SI01 interface meets the I2C-bus specification for bit-rates up to 100 kbit/s. 5. These values are guaranteed but not 100% production tested. 1998 May 01 12 Philips Semiconductors Product specification 80C51 8-bit microcontroller 87C552 8K/256 OTP, 8 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O EXPLANATION OF THE AC SYMBOLS P – PSEN Q – Output data R – RD signal t – Time V – Valid W – WR signal X – No longer a valid logic level Z – Float Examples: tAVLL = Time for address valid to ALE low. tLLPL = Time for ALE low to PSEN low. Each timing symbol has five characters. The first character is always ‘t’ (= time). The other characters, depending on their positions, indicate the name of a signal or the logical status of that signal. The designations are: A – Address C – Clock D – Input data H – Logic level high I – Instruction (program memory contents) L – Logic level low, or ALE tLHLL ALE tAVLL tLLPL tPLPH tLLIV tPLIV PSEN tLLAX A0–A7 PORT 0 tPXIZ tPLAZ tPXIX A0–A7 INSTR IN tAVIV PORT 2 A0–A15 A8–A15 SU00006 Figure 2. External Program Memory Read Cycle ALE tWHLH PSEN tLLDV tLLWL tRLRH RD tAVLL tLLAX tRLAZ PORT 0 tRHDZ tRLDV tRHDX A0–A7 FROM RI OR DPL DATA IN A0–A7 FROM PCL INSTR IN tAVWL tAVDV PORT 2 P2.0–P2.7 OR A8–A15 FROM DPH A0–A15 FROM PCH SU00007 Figure 3. External Data Memory Read Cycle 1998 May 01 13 Philips Semiconductors Product specification 80C51 8-bit microcontroller 87C552 8K/256 OTP, 8 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O ALE tWHLH PSEN tWLWH tLLWL WR tLLAX tAVLL tWHQX tQVWX tDW A0–A7 FROM RI OR DPL PORT 0 DATA OUT A0–A7 FROM PCL INSTR IN tAVWL PORT 2 P2.0–P2.7 OR A8–A15 FROM DPH A8–A15 FROM PCH SU00213 Figure 4. External Data Memory Write Cycle tr tHIGH VIH1 VIH1 0.8V tf VIH1 0.8V VIH1 0.8V 0.8V tLOW tCLCL SU00214 Figure 5. External Clock Drive XTAL1 INSTRUCTION 0 1 2 3 4 5 6 7 8 ALE tXLXL CLOCK tXHQX tQVXH OUTPUT DATA 0 1 WRITE TO SBUF 2 3 4 5 6 7 tXHDX tXHDV SET TI INPUT DATA VALID VALID VALID VALID VALID VALID VALID VALID CLEAR RI SET RI SU00027 Figure 6. Shift Register Mode Timing 1998 May 01 14 Philips Semiconductors Product specification 80C51 8-bit microcontroller 87C552 8K/256 OTP, 8 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O 2.4V 2.0V 2.0V Test Points 0.8V 0.8V 0.45V NOTE: AC inputs during testing are driven at 2.4V for a logic ‘1’ and 0.45V for a logic ‘0’. Timing measurements are made at 2.0V for a logic ‘1’ and 0.8V for a logic ‘0’. SU00215 Figure 7. AC Testing Input/Output Float 2.4V 2.4V 0.45V 2.0V 2.0V 0.8V 0.8V 0.45V NOTE: The float state is defined as the point at which a port 0 pin sinks 3.2mA or sources 400µA at the voltage test levels. SU00216 Figure 8. AC Testing Input, Float Waveform repeated START condition START or repeated START condition START condition tSU;STA STOP condition tRD 0.7 VCC SDA (INPUT/OUTPUT) 0.3 VCC tBUF tFD tRC tFC tSU;STO 0.7 VCC SCL (INPUT/OUTPUT) 0.3 VCC tSU;DAT3 tHD;STA tLOW tHIGH tSU;DAT1 tHD;DAT tSU;DAT2 SU00107A Figure 9. Timing SIO1 (I2C) Interface 1998 May 01 15 Philips Semiconductors Product specification 80C51 8-bit microcontroller 87C552 8K/256 OTP, 8 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O 50 (1) 40 30 (2) IDD mA 20 (3) 10 (4) 0 NOTE: These values are valid only within the frequency specifications of the device under test. 4 0 8 12 16 f (MHz) (1) (2) (3) (4) Maximum operating mode; VDD = 6V Maximum operating mode; VDD = 4V Maximum idle mode; VDD = 6V Maximum idle mode; VDD = 4V SU00217 Figure 10. 16MHz Version Supply Current (IDD) as a Function of Frequency at XTAL1 (fOSC) VDD VDD IDD P1.6 P1.7 VDD VDD VDD P0 RST EA STADC (NC) XTAL2 CLOCK SIGNAL XTAL1 EW AVSS VSS AVref– SU00218 Figure 11. IDD Test Condition, Active Mode All other pins are disconnected1 1. Active Mode: a. The following pins must be forced to VDD: EA, RST, Port 0, and EW. b. The following pins must be forced to VSS: STADC, AVss, and AVref–. c. Ports 1.6 and 1.7 should be connected to VDD through resistors of sufficiently high value such that the sink current into these pins cannot exceed the IOL1 spec of these pins. d. The following pins must be disconnected: XTAL2 and all pins not specified above. 1998 May 01 16 Philips Semiconductors Product specification 80C51 8-bit microcontroller 87C552 8K/256 OTP, 8 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O VDD VDD IDD P1.6 P1.7 VDD RST VDD STADC P0 (NC) XTAL2 CLOCK SIGNAL XTAL1 EW EA AVSS VSS AVref– SU00219 Figure 12. IDD Test Condition, Idle Mode All other pins are disconnected2 2. Idle Mode: a. The following pins must be forced to VDD: Port 0 and EW. b. The following pins must be forced to VSS: RST, STADC, AVss,, AVref–, and EA. c. Ports 1.6 and 1.7 should be connected to VDD through resistors of sufficiently high value such that the sink current into these pins cannot exceed the IOL1 spec of these pins. These pins must not have logic 0 written to them prior to this measurement. d. The following pins must be disconnected: XTAL2 and all pins not specified above. VDD–0.5 0.7VDD 0.5V 0.2VDD–0.1 tCHCL tCHCX tCLCH tCLCX tCLCL SU00220 Figure 13. Clock Signal Waveform for IDD Tests in Active and Idle Modes tCLCH = tCHCL = 5ns VDD VDD IDD P1.6 P1.7 VDD VDD RST STADC P0 (NC) EW XTAL2 EA XTAL1 AVSS VSS AVref– SU00221 Figure 14. IDD Test Condition, Power Down Mode All other pins are disconnected. VDD = 2V to 5.5V3 3. Power Down Mode: a. The following pins must be forced to VDD: Port 0 and EW. b. The following pins must be forced to VSS: RST, STADC, XTAL1, AVss,, AVref–, and EA. c. Ports 1.6 and 1.7 should be connected to VDD through resistors of sufficiently high value such that the sink current into these pins cannot exceed the IOL1 spec of these pins. These pins must not have logic 0 written to them prior to this measurement. d. The following pins must be disconnected: XTAL2 and all pins not specified above. 1998 May 01 17 Philips Semiconductors Product specification 80C51 8-bit microcontroller 87C552 8K/256 OTP, 8 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O programmed, further programming of the code memory and encryption table is disabled. However, the other lock bit can still be programmed. EPROM CHARACTERISTICS The 87C552 is programmed by using a modified Quick-Pulse Programming algorithm. It differs from older methods in the value used for VPP (programming supply voltage) and in the width and number of the ALE/PROG pulses. Note that the EA/VPP pin must not be allowed to go above the maximum specified VPP level for any amount of time. Even a narrow glitch above that voltage can cause permanent damage to the device. The VPP source should be well regulated and free of glitches and overshoot. The 87C552 contains two signature bytes that can be read and used by an EPROM programming system to identify the device. The signature bytes identify the device as an 87C552 manufactured by Philips. Program Verification Table 3 shows the logic levels for reading the signature byte, and for programming the program memory, the encryption table, and the lock bits. The circuit configuration and waveforms for quick-pulse programming are shown in Figures 15 and 16. Figure 17 shows the circuit configuration for normal program memory verification. If lock bit 2 has not been programmed, the on-chip program memory can be read out for program verification. The address of the program memory locations to be red is applied to ports 1 and 2 as shown in Figure 17. The other pins are held at the “Verify Code Data” levels indicated in Table 3. The contents of the address location will be emitted on port 0. External pull-ups are required on port 0 for this operation. Quick-Pulse Programming The setup for microcontroller quick-pulse programming is shown in Figure 15. Note that the 87C552 is running with a 4 to 6MHz oscillator. The reason the oscillator needs to be running is that the device is executing internal address and program data transfers. If the encryption table has been programmed, the data presented at port 0 will be the exclusive NOR of the program byte with one of the encryption bytes. The user will have to know the encryption table contents in order to correctly decode the verification data. The encryption table itself cannot be read out. The address of the EPROM location to be programmed is applied to ports 1 and 2, as shown in Figure 15. The code byte to be programmed into that location is applied to port 0. RST, PSEN, and pins of ports 2 and 3 specified in Table 3 are held at the “Program Code Data” levels indicated in Table 3. The ALE/PROG is pulsed low 25 times as shown in Figure 16. Reading the Signature Bytes The signature bytes are read by the same procedure as a normal verification of locations 030H and 031H, except that P3.6 and P3.7 need to be pulled to a logic low. The values are: (030H) = 15H indicates manufactured by Philips Components (031H) = 94H indicates 87C552 To program the encryption table, repeat the 25-pulse programming sequence for addresses 0 through 1FH, using the “Pgm Encryption Table” levels. Do not forget that after the encryption table is programmed, verification cycles will produce only encrypted data. Program/Verify Algorithms Any algorithm in agreement with the conditions listed in Table 3, and which satisfies the timing specifications, is suitable. To program the lock bits, repeat the 25-pulse programming sequence using the “Pgm Lock Bit” levels. After one lock bit is Table 3. EPROM Programming Modes MODE RST PSEN ALE/PROG EA/VPP P2.7 P2.6 P3.7 P3.6 Read signature 1 0 Program code data 1 0 1 1 0 0 0 0 0* VPP 1 0 1 1 Verify code data 1 0 Pgm encryption table 1 0 1 1 0 0 1 1 0* VPP 1 0 1 0 Pgm lock bit 1 1 0 0* VPP 1 1 1 1 Pgm lock bit 2 1 0 0* VPP 1 1 0 0 NOTES: 1. 0 = Valid low for that pin; 1 = valid high for that pin. 2. VPP = 12.75V ±0.25V. 3. VDD = 5V ±10% during programming and verification. * ALE/PROG receives 25 programming pulses while VPP is held at 12.75V. Each programming pulse is low for 100µs (±10µs) and high for a minimum of 10µs. Trademark phrase of Intel Corporation. 1998 May 01 18 Philips Semiconductors Product specification 80C51 8-bit microcontroller 87C552 8K/256 OTP, 8 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O +5V VDD A0-A7 P0 P1 1 RST EA/VPP 1 P3.6 ALE/PROG 1 P3.7 87C552 XTAL2 4-6MHz XTAL1 PGM DATA +12.75V 25 100µs PULSES TO GROUND PSEN 0 P2.7 1 P2.6 0 A8-A12 P2.0-P2.4 VSS SU00222 Figure 15. Programming Configuration 25 PULSES 1 ALE/PROG: 0 10µs MIN 1 ALE/PROG: 100µs+10 0 SU00018 Figure 16. PROG Waveform +5V VDD A0-A7 P0 P1 1 RST EA/VPP 1 P3.6 ALE/PROG 1 P3.7 87C552 XTAL2 4-6MHz XTAL1 PSEN PGM DATA 1 1 0 P2.7 0 ENABLE P2.6 0 P2.0-P2.4 A8-A12 VSS SU00223 Figure 17. Program Verification 1998 May 01 19 Philips Semiconductors Product specification 80C51 8-bit microcontroller 87C552 8K/256 OTP, 8 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O EPROM PROGRAMMING AND VERIFICATION CHARACTERISTICS Tamb = 21°C to +27°C, VDD = 5V±10%, VSS = 0V SYMBOL PARAMETER MIN MAX 12.5 13.0 V 50 mA 6 MHz VPP Programming supply voltage IPP Programming supply current 1/tCLCL Oscillator frequency tAVGL Address setup to PROG low 48tCLCL tGHAX Address hold after PROG 48tCLCL tDVGL Data setup to PROG low 48tCLCL tGHDX Data hold after PROG 48tCLCL tEHSH P2.7 (ENABLE) high to VPP 48tCLCL tSHGL VPP setup to PROG low 10 tGHSL VPP hold after PROG 10 tGLGH PROG width 90 tAVQV Address to data valid tELQZ ENABLE low to data valid tEHQZ Data float after ENABLE 0 tGHGL PROG high to PROG low 10 P1.0–P1.7 P2.0–P2.4 4 UNIT µs µs µs 110 48tCLCL 48tCLCL 48tCLCL µs PROGRAMMING* VERIFICATION* ADDRESS ADDRESS tAVQV DATA IN PORT 0 DATA OUT tDVGL tAVGL tGHDX tGHAX ALE/PROG tGLGH tSHGL tGHGL tGHSL LOGIC 1 LOGIC 1 EA/VPP LOGIC 0 tEHSH tELQV tEHQZ P2.7 ENABLE SU00020 * FOR PROGRAMMING VERIFICATION SEE FIGURE 17. FOR VERIFICATION CONDITIONS SEE TABLE 3. Figure 18. EPROM Programming and Verification Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the components in the I2C system provided the system conforms to the I2C specifications defined by Philips. This specification can be ordered using the code 9398 393 40011. 1998 May 01 20 Philips Semiconductors Product specification 80C51 8-bit microcontroller 8K/256 OTP, 8 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O PLCC68: plastic leaded chip carrier; 68 leads; pedestal 1998 May 01 21 87C552 SOT188-3 Philips Semiconductors Product specification 80C51 8-bit microcontroller 8K/256 OTP, 8 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O QFP80: plastic quad flat package; 80 leads (lead length 1.95 mm); body 14 x 20 x 2.8 mm 1998 May 01 22 87C552 SOT318-2 Philips Semiconductors Product specification 80C51 8-bit microcontroller 8K/256 OTP, 8 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O NOTES 1998 May 01 23 87C552 Philips Semiconductors Product specification 80C51 8-bit microcontroller 8K/256 OTP, 8 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O 87C552 Data sheet status Data sheet status Product status Definition [1] Objective specification Development This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. Preliminary specification Qualification This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. Product specification Production This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. [1] Please consult the most recently issued datasheet before initiating or completing a design. Definitions Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 Date of release: 05-98 Document order number: 1998 May 01 24 9397 750 05367