NCS7101 1.8 Volt Rail−to−Rail Operational Amplifier The NCS7101 operational amplifier provides rail−to−rail operation on both the input and output. The output can swing within 50 mV of each rail. This rail−to−rail operation enables the user to make full use of the entire supply voltage range available. It is designed to work at very low supply voltages (1.8 V and ground), yet can operate with a supply of up to 10 V and ground. The NCS7101 is available in the space saving SOT−23−5 package with two industry standard pinouts. Features http://onsemi.com LOW VOLTAGE RAIL−TO−RAIL OPERATIONAL AMPLIFIER • Low Voltage, Single Supply Operation (1.8 V and Ground to 10 V • • • • • • • • • and Ground) 1.0 pA Input Bias Current Unity Gain Bandwidth of 1.0 MHz at 5.0 V, 0.9 MHz at 1.8 V Output Voltage Swings Within 50 mV of Both Rails @ 1.8 V No Phase Reversal on the Output for Over−Driven Input Signals Input Offset Trimmed to 1.0 mV Low Supply Current (ID = 1.0 mA) Works Down to Two Discharged NiCd Battery Cells ESD Protected Inputs Up to 2.0 kV Pb−Free Packages are Available Typical Applications • • • • • Dual NiCd/NiMH Cell Powered Systems Portable Communication Devices Low Voltage Active Filters Power Supply Monitor and Control Interface to DSP Rail to Rail Input CASE 483 SOT−23−5 SN SUFFIX 5 1 MARKING DIAGRAM x = C for SN1 D for SN2 AAx AYWG A = Assembly Location G Y = Year W = Work Week 1 G = Pb−Free Package (Note: Microdot may be in either location) 5 PIN CONNECTIONS VOUT 1 VCC Non−Inverting Input 2 5 VEE 4 Inverting Input + − 3 Style 1 Pin Out (SN1T1) Rail to Rail Output VOUT 1 VEE Non−Inverting Input 2 5 VCC 4 Inverting Input + − 3 Style 2 Pin Out (SN2T1) 1.8 V to 10 V + − ORDERING INFORMATION This device contains 68 active transistors. Figure 1. Typical Application Shipping † Device Package NCS7101SN1T1 SOT−23−5 NCS7101SN1T1G SOT−23−5 (Pb−Free) 3000 Tape & Reel (7 inch Reel) SOT−23−5 NCS7101SN2T1 NCS7101SN2T1G SOT−23−5 (Pb−Free) †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. © Semiconductor Components Industries, LLC, 2006 February, 2006 − Rev. 3 1 Publication Order Number: NCS7101/D NCS7101 MAXIMUM RATINGS Rating Symbol Value Unit VS 10 V Input Differential Voltage Range (Note 1) VIDR VEE − 300 mV to 10 V V Input Common Mode Voltage Range (Note 1) VICR VEE − 300 mV to 10 V V Output Short Circuit Duration (Note 2) tSC Indefinite sec Junction Temperature TJ 150 °C Power Dissipation and Thermal Characteristics SOT−23−5 Package Thermal Resistance, Junction−to−Air Power Dissipation @ TA = 70°C RqJA PD 220 364 °C/W mW Storage Temperature Range Tstg −65 to 150 °C VESD 2000 V Supply Voltage (VCC to VEE) ESD Protection at any Pin Human Body Model (Note 3) 1. Either or both inputs should not exceed the range of VEE − 300 mV to VEE + 10 V. 2. Maximum package power dissipation limits must be observed to ensure that the maximum junction temperature is not exceeded. TJ = TA + (PDRqJA) 3. ESD data available upon request. DC ELECTRICAL CHARACTERISTICS (VCC = 2.5 V, VEE = −2.5 V, VCM = VO = 0, RL to GND, TA = 25°C, unless otherwise noted.) Characteristics Symbol Input Offset Voltage VCC = 0.9 V, VEE = −0.9 V TA = 25°C TA = −40°C to 85°C VCC = 2.5 V, VEE = −2.5 V TA = 25°C TA = −40°C to 85°C VCC = 5.0 V, VEE = −5.0 V TA = 25°C TA = −40°C to 85°C Min Typ Max VIO Unit mV −7.0 −9.0 0.6 − 7.0 9.0 −7.0 −9.0 0.6 − 7.0 9.0 −7.0 −9.0 0.6 − 7.0 9.0 DVIO/DT − 8.0 − mV/°C Input Bias Current (VCC = 1.8 V to 10 V) |IIB| − 1.0 − pA Common Mode Input Voltage Range VICR VEE − VCC V Large Signal Voltage Gain VCC = 5.0 V, VEE = −5.0 V RL = 10 kW RL = 2.0 kW AVOL Output Voltage Swing, High (VID = "0.2 V) VCC = 0.9 V, VEE = −0.9 V (TA = 25°C) RL = 10 k RL = 2.0 k TA = −40°C to 85°C RL = 10 k RL = 2.0 k VCC = 2.5 V, VEE = −2.5 V (TA = 25°C) RL = 600 RL = 2.0 k TA = −40°C to 85°C RL = 600 RL = 2.0 k VCC = 5.0 V, VEE = −5.0 V (TA = 25°C) RL = 600 RL = 2.0 k TA = −40°C to 85°C RL = 600 RL = 2.0 k VOH Input Offset Voltage Temperature Coefficient (RS = 50) TA = −40°C to 105°C kV/V 16 16 http://onsemi.com 2 50 30 − − V 0.85 0.80 0.88 0.82 − − 0.85 0.79 − − − − 2.10 2.35 2.21 2.44 − − 2.00 2.40 − − − − 4.40 4.80 4.60 4.88 − − 4.40 4.80 − − − − NCS7101 DC ELECTRICAL CHARACTERISTICS (continued) (VCC = 2.5 V, VEE = −2.5 V, VCM = VO = 0, RL to GND, TA = 25°C, unless otherwise noted.) Characteristics Symbol Output Voltage Swing, Low (VID = "0.2 V) VCC = 0.9 V, VEE = −0.9 V (TA = 25°C) RL = 10 k RL = 2.0 k TA = −40°C to 85°C RL = 10 k RL = 2.0 k VCC = 2.5 V, VEE = −2.5 V (TA = 25°C) RL = 600 RL = 2.0 k TA = −40°C to 85°C RL = 600 RL = 2.0 k VCC = 5.0 V, VEE = −5.0 V (TA = 25°C) RL = 600 RL = 2.0 k TA = −40°C to 85°C RL = 600 RL = 2.0 k Min Typ Max VOL Common Mode Rejection Ratio Vin = 0 to 10 V Vin = 0 to 5.0 V CMRR Power Supply Rejection Ratio VCC/VEE = 10 V/Ground, DVS = 2.5 V PSRR Output Short Circuit Current (Vin Diff = "1.0 V) VCC = +0.9 V, VEE = −0.9 V Source Sink VCC = +2.5 V, VEE = −2.5 V Source Sink VCC = 5.0 V, VEE = −5.0 V Source Sink ISC Power Supply Current (VO = 0 V) VCC = +0.9 V, VEE = −0.9 V TA = 25°C TA = −40°C to 85°C VCC = +2.5 V, VEE = −2.5 V TA = 25°C TA = −40°C to 85°C VCC = 5.0 V, VEE = −5.0 V TA = 25°C TA = −40°C to 85°C ID http://onsemi.com 3 Unit V − − −0.88 −0.82 −0.85 −0.80 − − − − −0.85 −0.78 − − −2.22 −2.38 −2.10 −2.35 − − − − −2.00 −2.30 − − −4.66 −4.88 −4.40 −4.80 − − − − −4.35 −4.80 65 60 − − − − 65 − − dB dB mA − − 3.0 −3.0 − − 20 −60 25 −25 60 −20 50 −140 72 −72 140 −50 mA − − 0.97 − 1.20 1.30 − − 1.05 − 1.30 1.40 − − 1.13 − 1.40 1.50 NCS7101 AC ELECTRICAL CHARACTERISTICS (VCC = 2.5 V, VEE = −2.5 V, VCM = VO = 0, RL to GND, TA = 25°C, unless otherwise noted.) Characteristics Symbol Min Typ Max Unit SR 0.7 1.2 3.0 V/ms Gain Bandwidth Product (VCC = 10 V) GBW 0.5 1.0 3.0 MHz Gain Margin (RL = 10 k, CL = 5.0 pF) Am − 6.5 − dB Phase Margin (RL = 10 k, CL = 5.0 pF) φm − 60 − Deg Power Bandwidth (VO = 4.0 Vpp, RL = 2.0 kW, THD v 1.0%) BWP − 130 − kHz Total Harmonic Distortion (VO = 4.0 Vpp, RL = 2.0 kW, AV = 1.0) f = 1.0 kHz f = 10 kHz THD − − 0.02 0.2 − − Slew Rate (VO = −2.0 to 2.0 V, RL = 2.0 kW, AV = 1.0) % Differential Input Resistance (VCM = 0 V) Rin − u1.0 − tera W Differential Input Capacitance (VCM = 0 V) Cin − 2.0 − pF Equivalent Input Noise Voltage (Freq = 1.0 kHz) en − 140 − nV/√Hz http://onsemi.com 4 Vsat, OUTPUT SATURATION VOLTAGE (V) Vsat, OUTPUT SATURATION VOLTAGE (mV) NCS7101 0 VCC −0.4 −400 High State Output Sourcing Current −800 −1200 VS = ±2.5 V RL = to GND TA = 25°C −1.2 Low State Output Sinking Current 400 VEE 0 100 1.0 k 10 k 100 k 1.0 M VCC VS = ±2.5 V RL = to GND TA = 25°C −0.8 1200 800 0 High State Output Sourcing Current Low State Output Sinking Current 1.2 0.8 VEE 0.4 0 0 2.0 4.0 6.0 8.0 10 12 RL, LOAD RESISTANCE (W) IL, LOAD CURRENT (mA) Figure 2. Output Saturation Voltage versus Load Resistance Figure 3. Output Saturation Voltage versus Load Current VS = ±5.0 V RL = 100 k TA = 25°C GAIN 100 10 1.0 VS = ±2.5 V RL = ∞ CL = 0 AV = 1.0 0.1 AVOL, GAIN (dB) IIB, INPUT CURRENT (pA) 100 80 60 −60 PHASE −100 20 −140 0 25 50 75 100 125 1.0 10 100 1.0 k 10 k 100 k 1.0 M −180 10 M TA, AMBIENT TEMPERATURE (°C) f, FREQUENCY (Hz) Figure 4. Input Bias Current versus Temperature Figure 5. Gain and Phase versus Frequency 500 mV/div VS = ±2.5 V VO = 4.0 VPP RL = 10 k CL = 10 pF AV = 1.0 TA = 25°C 50 mV/div −20 40 0 0 0 f, EXCESS PHASE (°) 1000 VS = ±2.5 V VO = 4.0 VPP RL = 10 k CL = 10 pF AV = 1.0 TA = 25°C t, time (500 ns/Div) t, time (1.0 ms/Div) Figure 6. Transient Response Figure 7. Slew Rate http://onsemi.com 5 CMR, COMMON MODE REJECTION (dB) NCS7101 RL = 10 k AV = 1.0 TA = 25°C 12 VS = ±5.0 V 10 8.0 6.0 VS = ±2.5 V 4.0 VS = ±0.9 V 2.0 0 PSR, POWER SUPPLY REJECTION (dB) 1.0 k 10 k 100 k 90 VS = ±2.5 V RL = ∞ TA = 25°C AV = 1.0 80 70 60 50 40 30 20 10 0 −10 10 1.0 k 10 k 100 k 1.0 M 10 M f, FREQUENCY (Hz) Figure 8. Output Voltage versus Frequency Figure 9. Common Mode Rejection versus Frequency 90 80 VS = ±2.5 V RL = ∞ TA = 25°C AV = 1.0 PSR+ 70 60 50 PSR− 40 30 20 10 0 −10 100 1.0 k 10 k 100 k 1.0 M 10 M f, FREQUENCY (Hz) 140 Output Pulsed Test at 3% Duty Cycle 120 100 −40°C 80 25°C 60 85°C 40 20 0 0 ±1.0 ±2.0 ±3.0 ±4.0 ±5.0 VS, SUPPLY VOLTAGE (V) Figure 11. Output Short Circuit Sinking Current versus Supply Voltage Figure 10. Power Supply Rejection versus Frequency 140 1.4 Output Pulsed Test at 3% Duty Cycle 120 |ID|, SUPPLY CURRENT (mA) |ISC|, OUTPUT SHORT CIRCUIT CURRENT (mA) 100 f, FREQUENCY (Hz) 100 10 100 1.0 M |ISC|, OUTPUT SHORT CIRCUIT CURRENT (mA) Vout, OUTPUT VOLTAGE (VPP) 14 −40°C 100 25°C 80 60 85°C 40 20 85°C 1.2 1.0 25°C 0.8 −40°C 0.6 0.4 RL = ∞ AV = 1.0 Vin = 0 V 0.2 0 0 0 ±1.0 ±2.0 ±3.0 ±4.0 ±5.0 0 ±1.0 ±2.0 ±3.0 ±4.0 VS, SUPPLY VOLTAGE (V) VS, SUPPLY VOLTAGE (V) Figure 12. Output Short Circuit Sourcing Current versus Supply Voltage Figure 13. Supply Current versus Supply Voltage with No Load http://onsemi.com 6 ±5.0 THD, TOTAL HARMONIC DISTORTION (%) 10 AV = 1000 1.0 AV = 100 AV = 10 0.1 VS = ±2.5 V Vout = 4.0 VPP RL = 2 k TA = 25°C 0.01 AV = 1.0 0.001 10 100 1.0 k 10 k 100 k AV = 100 0.1 VS = ±5.0 V Vout = 8.0 VPP RL = 2 k TA = 25°C AV = 10 0.01 AV = 1.0 0.001 10 100 1.0 k 100 k 10 k Figure 14. Total Harmonic Distortion versus Frequency with 5.0 V Supply Figure 15. Total Harmonic Distortion versus Frequency with 10 V Supply 1.0 AV = 1000 0.1 AV = 100 VS = ±2.5 V Vout = 4.0 VPP RL = 10 k TA = 25°C AV = 10 0.01 AV = 1.0 0.001 10 100 1.0 k 10 k 100 k THD, TOTAL HARMONIC DISTORTION (%) f, FREQUENCY (Hz) 10 1.0 AV = 1000 0.1 AV = 100 0.01 VS = ±5.0 V Vout = 8.0 VPP RL = 10 k TA = 25°C AV = 10 AV = 1.0 0.001 10 100 1.0 k 10 k 100 k f, FREQUENCY (Hz) f, FREQUENCY (Hz) Figure 16. Total Harmonic Distortion versus Frequency with 5.0 V Supply Figure 17. Total Harmonic Distortion versus Frequency with 10 V Supply 1.6 +Slew Rate, VS = ±2.5 V SR, SLEW RATE (V/ms) AV = 1000 1.0 f, FREQUENCY (Hz) 10 1.2 −Slew Rate, VS = ±2.5 V RL = 10 k CL = 10 pF AV = 1.0 TA = 25°C 0.8 0.4 +Slew Rate, VS = ±0.9 V 0 −50 10 GBW, GAIN BANDWIDTH PRODUCT (MHz) THD, TOTAL HARMONIC DISTORTION (%) THD, TOTAL HARMONIC DISTORTION (%) NCS7101 −Slew Rate, VS = ±0.9 V −25 0 25 50 75 100 125 3.0 VS = ±2.5 V RL = 10 k CL = 5.3 pF 2.0 1.0 0 −50 −25 0 25 50 75 100 TA, AMBIENT TEMPERATURE (°C) TA, AMBIENT TEMPERATURE (°C) Figure 18. Slew Rate versus Temperature (Avg.) Figure 19. Gain Bandwidth Product versus Temperature http://onsemi.com 7 125 NCS7101 −100 10 −140 0 −180 −220 VS = ±0.9 V VS = ±2.5 V −20 Φ, EXCESS PHASE (°) 20 −10 −260 10 k 100 k 1.0 M 10 M 40 30 20 20 Gain Margin 10 0 −50 −25 0 50 75 0 125 100 Figure 21. Gain and Phase Margin versus Temperature 70 40 Gain Margin 20 VS = ±2.5 V RL = 10 k CL = 5.0 pF TA = 25°C 0 −40 100 1.0 k 10 k 100 k 70 VS = ±2.5 V RL = 10 k AV = 100 TA = 25°C 60 AV, GAIN MARGIN (dB) 80 40 Phase Margin 50 60 50 40 40 30 30 20 20 Gain Margin −20 10 −40 1.0M 0 10 1.0 0 1000 100 10 CL, CAPACITIVE LOAD (pF) Rt, DIFFERENTIAL SOURCE RESISTANCE (W) Figure 22. Gain and Phase Margin versus Differential Source Resistance Figure 23. Gain and Phase Margin versus Output Load Capacitance 80 12 Phase Margin 70 10 Am, GAIN MARGIN (dB) Vout, OUTPUT VOLTAGE (VPP) 25 Figure 20. Voltage Gain and Phase versus Frequency 60 10 30 TA, AMBIENT TEMPERATURE (°C) 60 −20 40 f, FREQUENCY (Hz) Phase Margin 0 50 10 100 20 60 VS = ±2.5 V RL = 10 k CL = 10 pF 50 100 M 100 80 70 60 −300 −30 Am, GAIN MARGIN (dB) −60 80 Phase Margin 70 Am, GAIN MARGIN (dB) 30 −20 Φm, PHASE MARGIN (°) AV, GAIN (dB) 40 80 8.0 6.0 RL = 10 k AV = 100 TA = 25°C Split Supplies 4.0 2.0 60 AV = 100 RL = 10 k CL = 0 TA = 25°C 50 40 30 20 Gain Margin 10 0 0 0 2.0 4.0 6.0 8.0 10 0 ±1.0 ±2.0 ±3.0 ±4.0 VCC − VEE, SUPPLY VOLTAGE (V) VS, SUPPLY VOLTAGE (V) Figure 24. Output Voltage Swing versus Supply Voltage Figure 25. Gain and Phase Margin versus Supply Voltage http://onsemi.com 8 Φm, PHASE MARGIN (°) 20 RL = 10 k AV = 100 TA = 25°C Φm, PHASE MARGIN (°) 50 ±5.0 NCS7101 20 VIO, INPUT OFFSET VOLTAGE (mV) AVOL, OPEN LOOP GAIN (dB) 120 110 100 90 RL = 10 k CL = 0 TA = 25°C 80 70 60 0 ±1.0 ±2.0 ±3.0 ±4.0 VS = ±2.5 V RL = ∞ CL = 0 AV = 1.0 TA = 25°C 15 10 5 0 −5 −10 −15 −20 −3.0 ±5.0 −2.0 VS, SUPPLY VOLTAGE (V) 2.0 3.0 6.0 VS = ±0.9 V RL = ∞ CL = 0 AV = 1.0 TA = 25°C VCM, COMMON MODE INPUT VOLTAGE RANGE (V) VIO, INPUT OFFSET VOLTAGE (mV) 5 1.0 Figure 27. Input Offset Voltage versus Common Mode Input Voltage Range, VS = +2.5 V 20 10 0 VCM, COMMON VOLTAGE RANGE (V) Figure 26. Open Loop Voltage Gain versus Supply Voltage (Split Supplies) 15 −1.0 0 −5 −10 −15 −20 −1.0 −0.8 −0.6 −0.4 −0.2 0 0.2 0.4 0.6 0.8 4.0 2.0 DVIO = 5.0 mV RL = ∞ CL = 0 AV = 1.0 TA = 25°C 0 −2.0 −4.0 −6.0 ±0.5 ±1.0 1.0 VCM, COMMON MODE INPUT VOLTAGE (V) ±2.0 ±3.0 ±4.0 ±5.0 VS, SUPPLY VOLTAGE (V) Figure 28. Input Offset Voltage versus Common Mode Input Voltage Range, VS = +0.9 V Figure 29. Common−Mode Input Voltage Range versus Power Supply Voltage http://onsemi.com 9 NCS7101 APPLICATION INFORMATION AND OPERATING DESCRIPTION Cfb GENERAL INFORMATION The NCS7101 is a rail−to−rail input, rail−to−rail output operational amplifier that features guaranteed 1.8 volt operation. This feature is achieved with the use of a modified analog CMOS process that allows the implementation of depletion MOSFET devices. The amplifier has a 1.0 MHz gain bandwidth product, 1.2 V/ms slew rate and is operational over a power supply range less than 1.8 V to as high as 10 V. Rfb Rin Input Cin Output Cin = Input and printed circuit board capacitance Figure 30. Input Capacitance Pole Cancellation Inputs The input topology of this device series is unconventional when compared to most low voltage operational amplifiers. It consists of an N−channel depletion mode differential transistor pair that drives a folded cascode stage and current mirror. This configuration extends the input common mode voltage range to encompass the VEE and VCC power supply rails, even when powered from a combined total of less than 1.8 volts. Figures 27 and 28 show the input common mode voltage range versus power supply voltage. The differential input stage is laser trimmed in order to minimize offset voltage. The N−channel depletion mode MOSFET input stage exhibits an extremely low input bias current of less than 40 pA. The input bias current versus temperature is shown in Figure 4. Either one or both inputs can be biased as low as VEE minus 300 mV to as high as 10 V without causing damage to the device. If the input common mode voltage range is exceeded, the output will not display a phase reversal but it may latch in the appropriate high or low state. The device can then be reset by removing and reapplying power. If the maximum input positive or negative voltage ratings are to be exceeded, a series resistor must be used to limit the input current to less than 2.0 mA. The ultra low input bias current of the NCS7101 allows the use of extremely high value source and feedback resistor without reducing the amplifier’s gain accuracy. These high value resistors, in conjunction with the device input and printed circuit board parasitic capacitances Cin, will add an additional pole to the single pole amplifier shown in Figure 30. If low enough in frequency, this additional pole can reduce the phase margin and significantly increase the output settling time. The effects of Cin, can be canceled by placing a zero into the feedback loop. This is accomplished with the addition of capacitor Cfb. An approximate value for Cfb can be calculated by: Cfb + − + Output The output stage consists of complementary P and N channel devices connected to provide rail−to−rail output drive. With a 2.0 k load, the output can swing within 100 mV of either rail. It is also capable of supplying over 95 mA when powered from 10 V and 3.0 mA when powered from 1.8 V. When connected as a unity gain follower, the NCS7101 can directly drive capacitive loads in excess of 390 pF at room temperature without oscillating but with significantly reduced phase margin. The unity gain follower configuration exhibits the highest bandwidth and is most prone to oscillations when driving a high value capacitive load. The capacitive load in combination with the amplifier’s output impedance, creates a phase lag that can result in an under−damped pulse response or a continuous oscillation. Figure 32 shows the effect of driving a large capacitive load in a voltage follower type of setup. When driving capacitive loads exceeding 390 pF, it is recommended to place a low value isolation resistor between the output of the op amp and the load, as shown in Figure 31. The series resistor isolates the capacitive load from the output and enhances the phase margin. Refer to Figure 33. Larger values of R will result in a cleaner output waveform but excessively large values will degrade the large signal rise and fall time and reduce the output’s amplitude. Depending upon the capacitor characteristics, the isolation resistor value will typically be between 50 to 500 ohms. The output drive capability for resistive and capacitive loads is shown in Figures 2, 3, and 23. Input Rin Cin Rfb + − R Output CL Isolation resistor R = 50 to 500 Figure 31. Capacitance Load Isolation Note that the lowest phase margin is observed at cold temperature and low supply voltage. http://onsemi.com 10 NCS7101 Figure 32. Small Signal Transient Response with Large Capacitive Load Figure 33. Small Signal Transient Response with Large Capacitive Load and Isolation Resistor. http://onsemi.com 11 NCS7101 RT 470 k VCC Output Voltage 0 VCC CT 1.0 nF Timing Capacitor Voltage − 0.67 VCC 0.33 VCC fO = 1.5 kHz + The non−inverting input threshold levels are set so that the capacitor voltage oscillates between 1/3 and 2/3 of VCC. This requires the resistors R1a, R1b and R2 to be of equal value. The following formula can be used to approximate the output frequency. R1a 470 k 0.9 V R2 470 k R1b 470 k 1 f + O 1.39 R TC T Figure 34. Square Wave Oscillator cww D1 1N4148 10 k VCC Output Voltage 0 1.0 M D2 1N4148 10 k Timing Capacitor Voltage 0.67 VCC 0.33 VCC cw Clock−wise, Low Duty Cycle VCC CT 1.0 nF VCC Output Voltage − 0 fO + Timing Capacitor Voltage R1a 470 k 0.67 VCC 0.33 VCC Counter−Clock−wise, High Duty Cycle VCC R1b 470 k R2 470 k The timing capacitor CT will charge through diode D2 and discharge through diode D1, allowing a variable duty cycle. The pulse width of the signal can be programmed by adjusting the value of the trimpot. The capacitor voltage will oscillate between 1/3 and 2/3 of VCC, since all the resistors at the non−inverting input are of equal value. Figure 35. Variable Duty Cycle Pulse Generator R1 1.0 M 2.5 V R3 1.0 k + Cin 10 mF ≈ − 10,000 mF −2.5 V R Ceff. + 1 Cin R3 R2 1.0 M Figure 36. Positive Capacitance Multiplier http://onsemi.com 12 NCS7101 Af Cf 400 pF Rf 100 k fL 0.9 V R2 10 k 1 f + [ 200 Hz L 2pR C 1 1 − VO + Vin C1 80 nF fH 1 f + [ 4.0 kHz H 2pRC f f R1 10 k −0.9 V R A + 1 ) f + 11 f R2 Figure 37. Voice Band Filter Vsupply VCC Vin + I − V in + sink R sense Rsense Figure 38. High Compliance Current Sink Is VL 5.0 V 1.0 W Rsense RL R3 1.0 k R4 R1 1.0 k + − 1.0 k VO R5 Is VO 1.00 A 67.93 mV 0.50 A 78.67 mV 2.4 k For best performance, use low tolerance resistors. R2 3.3 k Figure 39. High Side Current Sense http://onsemi.com 13 NCS7101 k R2 VCC k R1 + iL + VO − VS , Note that iL is independent of RL R1 R1 VS R2 RL iL Figure 40. Current Source R1 VCC iS − VO + VO = −iS R1 Figure 41. Current to Voltage Converter VCC i=0 − VS + RL VO iL R1 iR1 + iL + iR1 Figure 42. Voltage to Current Converter http://onsemi.com 14 V VR1 + S R1 R1 NCS7101 R2 ƪ VCC R1 V1 − V2 + ƫƪ ƫ R4 R2 R VO + V2 ) 1 * V1 2 R3 ) R4 R1 R1 VO If R1 = R3, and R2 = R4, the equation simplifies to: R3 R VO + (V2 * V1) 2 R1 R4 Figure 43. Differential Amplifier R4 R1 V2 V1 VCC R2 − R3 VO + V2 ƪ V V V VO + * R2 1 ) 2 ) 3 R1 R2 R3 ƫ To minimize input offset current take: R5 = R1 // R2 // R3 // R4 R5 Figure 44. Summing Amplifier http://onsemi.com 15 NCS7101 PACKAGE DIMENSIONS SOT−23−5 / TSOP−5, SC59−5 CASE 483−02 ISSUE E NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH THICKNESS. MINIMUM LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE MATERIAL. 4. A AND B DIMENSIONS DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR GATE BURRS. D S 5 4 1 2 3 B L G J C 0.05 (0.002) H M K MILLIMETERS MIN MAX 2.90 3.10 1.30 1.70 0.90 1.10 0.25 0.50 0.85 1.05 0.013 0.100 0.10 0.26 0.20 0.60 1.25 1.55 0_ 10 _ 2.50 3.00 DIM A B C D G H J K L M S A INCHES MIN MAX 0.1142 0.1220 0.0512 0.0669 0.0354 0.0433 0.0098 0.0197 0.0335 0.0413 0.0005 0.0040 0.0040 0.0102 0.0079 0.0236 0.0493 0.0610 0_ 10 _ 0.0985 0.1181 SOLDERING FOOTPRINT* 0.95 0.037 1.9 0.074 2.4 0.094 1.0 0.039 0.7 0.028 SCALE 10:1 mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: N. American Technical Support: 800−282−9855 Toll Free Literature Distribution Center for ON Semiconductor USA/Canada P.O. Box 61312, Phoenix, Arizona 85082−1312 USA Phone: 480−829−7710 or 800−344−3860 Toll Free USA/Canada Japan: ON Semiconductor, Japan Customer Focus Center 2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051 Fax: 480−829−7709 or 800−344−3867 Toll Free USA/Canada Phone: 81−3−5773−3850 Email: [email protected] http://onsemi.com 16 ON Semiconductor Website: http://onsemi.com Order Literature: http://www.onsemi.com/litorder For additional information, please contact your local Sales Representative. NCS7101/D