MCR8SD, MCR8SM, MCR8SN Preferred Device Sensitive Gate Silicon Controlled Rectifiers Reverse Blocking Thyristors Designed primarily for half-wave ac control applications, such as motor controls, heating controls, and power supplies; or wherever half−wave, silicon gate−controlled devices are needed. http://onsemi.com SCRs 8 AMPERES RMS 400 thru 800 VOLTS Features • Sensitive Gate Allows Triggering by Microcontrollers and other • • • • • • • • Logic Circuits Blocking Voltage to 800 Volts On−State Current Rating of 8 Amperes RMS at 80°C High Surge Current Capability − 80 Amperes Rugged, Economical TO−220AB Package Glass Passivated Junctions for Reliability and Uniformity Minimum and Maximum Values of IGT, VGT and IH Specified for Ease of Design Immunity to dv/dt − 5 V/msec Minimum at 110°C Pb−Free Packages are Available* G A MARKING DIAGRAM AY WW MCR8SxG AKA MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) Rating Symbol Peak Repetitive Off−State Voltage (Note 1) (TJ = −40 to 110°C, Sine Wave, 50 to 60 Hz, Gate Open) MCR8SD MCR8SM MCR8SN VDRM, VRRM On-State RMS Current (180° Conduction Angles; TC = 80°C) IT(RMS) 8.0 A Peak Non-Repetitive Surge Current (1/2 Cycle, Sine Wave, 60 Hz, TJ = 110°C) ITSM 80 A Circuit Fusing Consideration (t = 8.33 ms) I2t 26.5 A2sec Forward Peak Gate Power (Pulse Width ≤ 1.0 ms, TC = 80°C) Forward Average Gate Power (t = 8.3 ms, TC = 80°C) Value Unit V PG(AV) 5.0 W 0.5 W Forward Peak Gate Current (Pulse Width ≤ 1.0 ms, TC = 80°C) IGM 2.0 A Operating Junction Temperature Range TJ −40 to 110 °C Storage Temperature Range Tstg −40 to 150 °C Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1. VDRM and VRRM for all types can be applied on a continuous basis. Ratings apply for zero or negative gate voltage; positive gate voltage shall not be applied concurrent with negative potential on the anode. Blocking voltages shall not be tested with a constant current source such that the voltage ratings of the devices are exceeded. *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. © Semiconductor Components Industries, LLC, 2005 December, 2005 − Rev. 3 1 2 TO−220AB CASE 221A−09 STYLE 3 3 A Y WW x G AKA 400 600 800 PGM 1 K = Assembly Location = Year = Work Week = D, M, or N = Pb−Free Package = Diode Polarity PIN ASSIGNMENT 1 Cathode 2 Anode 3 Gate 4 Anode ORDERING INFORMATION Package Shipping MCR8SD Device TO−220AB 50 Units / Rail MCR8SDG TO−220AB (Pb−Free) 50 Units / Rail MCR8SM TO−220AB 50 Units / Rail MCR8SMG TO−220AB (Pb−Free) 50 Units / Rail MCR8SN TO−220AB 50 Units / Rail MCR8SNG TO−220AB (Pb−Free) 50 Units / Rail Preferred devices are recommended choices for future use and best overall value. Publication Order Number: MCR8S/D MCR8SD, MCR8SM, MCR8SN THERMAL CHARACTERISTICS Characteristic Thermal Resistance, Junction−to−Case Junction−to−Ambient Maximum Lead Temperature for Soldering Purposes 1/8″ from Case for 10 Seconds Symbol Value Unit RqJC RqJA 2.2 62.5 °C/W TL 260 °C ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) Characteristic Symbol Min Typ Max − − − − 10 500 Unit OFF CHARACTERISTICS Peak Repetitive Forward or Reverse Blocking Current (Note 3) (VD = Rated VDRM and VRRM; RGK = 1 kW) TJ = 25°C TJ = 110°C IDRM, IRRM mA ON CHARACTERISTICS Peak Forward On−State Voltage (Note 2) (ITM = 16 A) VTM − − 1.8 V Gate Trigger Current (Continuous dc) (Note 4) (VD = 12 V; RL = 100 W) IGT 5.0 25 200 mA Holding Current (Note 4) (VD = 12 V, Gate Open, Initiating Current = 200 mA) IH − 0.5 6.0 mA Latch Current (Note 4) (VD = 12 V, IG = 200 mA) IL − 0.6 8.0 mA Gate Trigger Voltage (Continuous dc) (Note 4) (VD = 12 V; RL = 100 W) TJ = 25°C TJ = *40°C VGT 0.3 − 0.65 − 1.0 1.5 V Gate Non−Trigger Voltage (VD = 12 V, RL = 100 W) TJ = 110°C VGD 0.2 − − V Critical Rate of Rise of Off−State Voltage (VD = 67% VDRM, RGK = 1 KW, CGK = 0.1 mF, TJ = 110°C) dv/dt 5.0 15 − V/ms Critical Rate of Rise of On−State Current IPK = 50 A, Pw = 40 msec, diG/dt = 1 A/msec, Igt = 10 mA di/dt − − 100 A/ms DYNAMIC CHARACTERISTICS 2. Indicates Pulse Test: Pulse Width v 2.0 ms, Duty Cycle v 2%. 3. RGK = 1000 Ohms included in measurement. 4. Does not include RGK in measurement. http://onsemi.com 2 MCR8SD, MCR8SM, MCR8SN Voltage Current Characteristic of SCR + Current Anode + VTM Symbol Parameter VDRM Peak Repetitive Off State Forward Voltage IDRM Peak Forward Blocking Current VRRM Peak Repetitive Off State Reverse Voltage IRRM Peak Reverse Blocking Current VTM Peak On State Voltage IH Holding Current on state IH IRRM at VRRM + Voltage IDRM at VDRM Reverse Blocking Region (off state) Forward Blocking Region (off state) Reverse Avalanche Region P(AV), AVERAGE POWER DISSIPATION (WATTS) Anode − TC , CASE TEMPERATURE (° C) 110 105 100 95 90 85 dc 80 30° 90° 120° 180° 60° 75 0 1 2 3 4 5 6 7 8 IT(RMS), RMS ON−STATE CURRENT (AMPS) 15 dc 12 9 180° 90° 60° 6 30° 3 0 1 0 2 3 4 5 7 6 8 IT(AV), AVERAGE ON−STATE CURRENT (AMPS) Figure 1. Typical RMS Current Derating Figure 2. On−State Power Dissipation 100 100 TYPICAL @ TJ = 25°C GATE TRIGGER CURRENT (m A) IT, INSTANTANEOUS ON−STATE CURRENT (AMPS) 120° MAXIMUM @ TJ = 110°C 10 MAXIMUM @ TJ = 25°C 1 0.1 0.5 1.0 1.5 2.0 2.5 3.0 90 80 70 60 50 40 30 20 10 0 −40 −25 −10 3.5 5 20 35 50 65 80 95 110 VT, INSTANTANEOUS ON−STATE VOLTAGE (VOLTS) TJ, JUNCTION TEMPERATURE (°C) Figure 3. Typical On−State Characteristics Figure 4. Typical Gate Trigger Current versus Junction Temperature http://onsemi.com 3 VGT, GATE TRIGGER VOLTAGE (VOLTS) MCR8SD, MCR8SM, MCR8SN IH, HOLDING CURRENT (m A) 1000 100 10 1 −40 −25 −10 5 20 35 50 65 80 95 110 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 −40 −25 −10 5 20 35 50 65 80 95 110 TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C) Figure 5. Typical Holding Current versus Junction Temperature Figure 6. Typical Gate Trigger Voltage versus Junction Temperature IL, LATCHING CURRENT (m A) 1000 100 10 1 −40 −25 −10 5 20 35 50 65 80 95 TJ, JUNCTION TEMPERATURE (°C) Figure 7. Typical Latching Current versus Junction Temperature http://onsemi.com 4 110 MCR8SD, MCR8SM, MCR8SN PACKAGE DIMENSIONS TO−220AB CASE 221A−09 ISSUE AA −T− B SEATING PLANE C F T S 4 DIM A B C D F G H J K L N Q R S T U V Z A Q 1 2 3 U H K Z L R V NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION Z DEFINES A ZONE WHERE ALL BODY AND LEAD IRREGULARITIES ARE ALLOWED. J G D N INCHES MIN MAX 0.570 0.620 0.380 0.405 0.160 0.190 0.025 0.035 0.142 0.147 0.095 0.105 0.110 0.155 0.018 0.025 0.500 0.562 0.045 0.060 0.190 0.210 0.100 0.120 0.080 0.110 0.045 0.055 0.235 0.255 0.000 0.050 0.045 −−− −−− 0.080 STYLE 3: PIN 1. 2. 3. 4. MILLIMETERS MIN MAX 14.48 15.75 9.66 10.28 4.07 4.82 0.64 0.88 3.61 3.73 2.42 2.66 2.80 3.93 0.46 0.64 12.70 14.27 1.15 1.52 4.83 5.33 2.54 3.04 2.04 2.79 1.15 1.39 5.97 6.47 0.00 1.27 1.15 −−− −−− 2.04 CATHODE ANODE GATE ANODE ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. 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