ETC NTP35N15/D

NTP35N15
Preferred Device
Product Preview
Power MOSFET
37 Amps, 150 Volts
N–Channel TO–220
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Features
• Source–to–Drain Diode Recovery Time Comparable to a Discrete
37 AMPERES
150 VOLTS
50 mΩ @ VGS = 10 V
Fast Recovery Diode
• Avalanche Energy Specified
• IDSS and RDS(on) Specified at Elevated Temperature
Typical Applications
• PWM Motor Controls
• Power Supplies
• Converters
N–Channel
D
MAXIMUM RATINGS (TC = 25°C unless otherwise noted)
Symbol
Value
Unit
Drain–to–Source Voltage
VDSS
150
Vdc
Drain–to–Source Voltage (RGS = 1.0 MΩ)
VDGR
150
Vdc
Gate–to–Source Voltage
– Continuous
– Non–Repetitive (tp10 ms)
VGS
VGSM
20
40
Rating
Drain Current
– Continuous @ TA 25°C
– Continuous @ TA 100°C
– Pulsed (Note 1.)
PD
178
1.43
W
W/°C
Operating and Storage Temperature Range
TJ, Tstg
–55 to
+150
°C
Single Drain–to–Source Avalanche Energy –
Starting TJ = 25°C
(VDD = 100 Vdc, VGS = 10 Vdc,
IL(pk) = 21.6 A, L = 3.0 mH, RG = 25 Ω)
EAS
700
mJ
Maximum Lead Temperature for Soldering
Purposes, 1/8″ from case for 10 seconds
MARKING DIAGRAM
& PIN ASSIGNMENT
4
Drain
Adc
37
23
111
Thermal Resistance
– Junction–to–Case
– Junction–to–Ambient
S
Vdc
ID
ID
IDM
Total Power Dissipation @ TA = 25°C
Derate above 25°C
G
4
TO–220AB
CASE 221A
STYLE 5
1
NTP35N15
LLYWW
1
Gate
2
3
3
Source
2
Drain
°C/W
RθJC
RθJA
0.7
62.5
TL
260
°C
1. Pulse Test: Pulse Width = 10 µs, Duty Cycle = 2%.
NTP35N15
LL
Y
WW
= Device Code
= Location Code
= Year
= Work Week
ORDERING INFORMATION
Device
NTP35N15
Package
Shipping
TO–220AB
50 Units/Rail
Preferred devices are recommended choices for future use
and best overall value.
This document contains information on a product under development. ON Semiconductor
reserves the right to change or discontinue this product without notice.
 Semiconductor Components Industries, LLC, 2001
June, 2001 – Rev. 0
1
Publication Order Number:
NTP35N15/D
NTP35N15
ELECTRICAL CHARACTERISTICS (TC = 25°C unless otherwise noted)
Characteristic
Symbol
Min
Typ
Max
Unit
150
–
–
240
–
–
–
–
–
–
5.0
50
–
–
±100
2.0
–
2.9
–8.56
4.0
–
–
–
0.042
–
0.050
0.120
–
1.55
1.78
gFS
–
26
–
mhos
Ciss
–
2275
3200
pF
Coss
–
450
650
Crss
–
90
175
td(on)
–
20
35
tr
–
125
225
td(off)
–
90
175
OFF CHARACTERISTICS
Drain–to–Source Breakdown Voltage
(VGS = 0 Vdc, ID = 250 µAdc)
Temperature Coefficient (Positive)
V(BR)DSS
Zero Gate Voltage Collector Current
(VGS = 0 Vdc, VDS = 150 Vdc, TJ = 25°C)
(VGS = 0 Vdc, VDS = 150 Vdc, TJ = 125°C)
IDSS
Gate–Body Leakage Current (VGS = ±20 Vdc, VDS = 0)
IGSS
Vdc
mV/°C
µAdc
nAdc
ON CHARACTERISTICS
Gate Threshold Voltage
VDS = VGS, ID = 250 µAdc)
Temperature Coefficient (Negative)
VGS(th)
Static Drain–to–Source On–State Resistance
(VGS = 10 Vdc, ID = 18.5 Adc)
(VGS = 10 Vdc, ID = 18.5 Adc, TJ = 125°C)
RDS(on)
Drain–to–Source On–Voltage
(VGS = 10 Vdc, ID = 18.5 Adc)
VDS(on)
Forward Transconductance (VDS = 10 Vdc, ID = 18.5 Adc)
Vdc
mV/°C
Ω
Vdc
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance
(VDS = 25 Vd
Vdc, VGS = 0 Vdc,
Vd
f = 1.0 MHz)
Reverse Transfer Capacitance
SWITCHING CHARACTERISTICS (Notes 2. & 3.)
Turn–On Delay Time
Rise Time
Turn–Off Delay Time
(VDD = 120 Vdc, ID = 37 Adc,
VGS = 10 Vdc,
Vdc
RG = 9.1 Ω)
Fall Time
Gate Charge
(VDS = 120 Vdc,
Vd ID = 37 Adc,
Ad
VGS = 10 Vdc)
ns
tf
–
120
210
Qtot
–
70
100
Qgs
–
14
–
Qgd
–
32
–
VSD
–
–
1.00
0.88
1.5
–
Vdc
trr
–
170
–
ns
ta
–
112
–
tb
–
58
–
QRR
–
1.14
–
nC
BODY–DRAIN DIODE RATINGS (Note 2.)
Forward On–Voltage
(IS = 37 Adc, VGS = 0 Vdc)
(IS = 37 Adc, VGS = 0 Vdc, TJ = 125°C)
Reverse Recovery Time
(IS = 37 Adc,
Ad VGS = 0 Vdc,
Vd
dIS/dt = 100 A/µs)
Reverse Recovery Stored Charge
2. Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2%.
3. Switching characteristics are independent of operating junction temperature.
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2
µC
NTP35N15
60
70
TJ = 25°C
VGS = 10 V
VGS = 5.5 V
VGS = 9 V
50
VGS = 8 V
40
VGS = 7 V
VGS = 5 V
30
VGS = 6 V
20
VDS ≥ 10 V
60
ID, DRAIN CURRENT (AMPS)
ID, DRAIN CURRENT (AMPS)
70
VGS = 4.5 V
10
50
40
TJ = 25°C
30
20
TJ = 100°C
10
VGS = 4 V
0
0
1
2
3
4
5
6
7
8
9
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
TJ = –55°C
0
10
2
RDS(on), DRAIN–TO–SOURCE RESISTANCE ()
0.1
0.055
VDS = 10 V
0.08
TJ = 100°C
0.06
0.04
TJ = 25°C
0.02
TJ = –55°C
0
7
Figure 2. Transfer Characteristics
0
10
20
30
40
50
ID, DRAIN CURRENT (AMPS)
60
70
TJ = 25°C
0.05
VGS = 10 V
0.45
VGS = 15 V
0.40
0.35
0.03
0
Figure 3. On–Resistance versus Drain Current
and Temperature
2.5
2.25
10
20
30
40
50
ID, DRAIN CURRENT (AMPS)
60
70
Figure 4. On–Resistance versus Drain Current
and Gate Voltage
10,000
VGS = 0 V
ID = 18.5 A
VGS = 10 V
TJ = 150°C
2.0
IDSS, LEAKAGE (nA)
RDS(on), DRAIN–TO–SOURCE RESISTANCE (NORMALIZED)
RDS(on), DRAIN–TO–SOURCE RESISTANCE ()
Figure 1. On–Region Characteristics
3
4
5
6
VGS, GATE–TO–SOURCE VOLTAGE (VOLTS)
1.75
1000
1.5
1.25
1.0
0.75
100
TJ = 100°C
0.5
0.25
0
–50
–25
0
25
50
75
100 125
TJ, JUNCTION TEMPERATURE (°C)
10
150
30 40 50 60 70 80 90 100 110 120 130 140 150
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
Figure 5. On–Resistance Variation with
Temperature
Figure 6. Drain–to–Source Leakage Current
versus Voltage
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3
NTP35N15
POWER MOSFET SWITCHING
The capacitance (Ciss) is read from the capacitance curve at
a voltage corresponding to the off–state condition when
calculating td(on) and is read at a voltage corresponding to the
on–state when calculating td(off).
At high switching speeds, parasitic circuit elements
complicate the analysis. The inductance of the MOSFET
source lead, inside the package and in the circuit wiring
which is common to both the drain and gate current paths,
produces a voltage at the source which reduces the gate drive
current. The voltage is determined by Ldi/dt, but since di/dt
is a function of drain current, the mathematical solution is
complex. The MOSFET output capacitance also
complicates the mathematics. And finally, MOSFETs have
finite internal gate resistance which effectively adds to the
resistance of the driving source, but the internal resistance
is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate
resistance (Figure 9) shows how typical switching
performance is affected by the parasitic circuit elements. If
the parasitics were not present, the slope of the curves would
maintain a value of unity regardless of the switching speed.
The circuit used to obtain the data is constructed to minimize
common inductance in the drain and gate circuit loops and
is believed readily achievable with board mounted
components. Most power electronic loads are inductive; the
data in the figure is taken with a resistive load, which
approximates an optimally snubbed inductive load. Power
MOSFETs may be safely operated into an inductive load;
however, snubbing reduces switching losses.
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge
controlled. The lengths of various switching intervals (∆t)
are determined by how fast the FET input capacitance can
be charged by current from the generator.
The published capacitance data is difficult to use for
calculating rise and fall because drain–gate capacitance
varies greatly with applied voltage. Accordingly, gate
charge data is used. In most cases, a satisfactory estimate of
average input current (IG(AV)) can be made from a
rudimentary analysis of the drive circuit so that
t = Q/IG(AV)
During the rise and fall time interval when switching a
resistive load, VGS remains virtually constant at a level
known as the plateau voltage, VSGP. Therefore, rise and fall
times may be approximated by the following:
tr = Q2 x RG/(VGG – VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turn–on and turn–off delay times, gate current is
not constant. The simplest calculation uses appropriate
values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG – VGSP)]
td(off) = RG Ciss In (VGG/VGSP)
6000
C, CAPACITANCE (pF)
5000
VDS = 0 V
VGS = 0 V
TJ = 25°C
Ciss
4000
3000
Crss
Ciss
2000
1000
0
10
Coss
Crss
5
VGS
0
VDS
5
10
15
20
25
GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
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4
12
120
QT
VDS
80
Q1
Q2
60
VGS
40
4
2
0
ID = 37 A
TJ = 25°C
0
10
VDD = 75 V
ID = 37 A
VGS = 10 V
100
8
6
1000
20
30
40
50
QG, TOTAL GATE CHARGE (nC)
60
20
0
70
t, TIME (ns)
10
VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)
NTP35N15
td(off)
100
tr
tf
td(on)
10
1
Figure 8. Gate–To–Source and Drain–To–Source
Voltage versus Total Charge
10
RG, GATE RESISTANCE (OHMS)
100
Figure 9. Resistive Switching Time
Variation versus Gate Resistance
DRAIN–TO–SOURCE DIODE CHARACTERISTICS
40
VGS = 0 V
TJ = 25°C
I S , SOURCE CURRENT (AMPS)
35
30
25
20
15
10
5
0
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS)
1.0
Figure 10. Diode Forward Voltage versus Current
SAFE OPERATING AREA
reliable operation, the stored energy from circuit inductance
dissipated in the transistor while in avalanche must be less
than the rated limit and adjusted for operating conditions
differing from those specified. Although industry practice is
to rate in terms of energy, avalanche energy capability is not
a constant. The energy rating decreases non–linearly with an
increase of peak current in avalanche and peak junction
temperature.
Although many E–FETs can withstand the stress of
drain–to–source avalanche at currents up to rated pulsed
current (IDM), the energy rating is specified at rated
continuous current (ID), in accordance with industry custom.
The energy rating must be derated for temperature as shown
in the accompanying graph (Figure 12). Maximum energy at
currents below rated continuous ID can safely be assumed to
equal the values indicated.
The Forward Biased Safe Operating Area curves define
the maximum simultaneous drain–to–source voltage and
drain current that a transistor can handle safely when it is
forward biased. Curves are based upon maximum peak
junction temperature and a case temperature (TC) of 25°C.
Peak repetitive pulsed power limits are determined by using
the thermal response data in conjunction with the procedures
discussed
in
AN569,
“Transient
Thermal
Resistance–General Data and Its Use.”
Switching between the off–state and the on–state may
traverse any load line provided neither rated peak current
(IDM) nor rated voltage (VDSS) is exceeded and the
transition time (tr,tf) do not exceed 10 µs. In addition the total
power averaged over a complete switching cycle must not
exceed (TJ(MAX) – TC)/(RθJC).
A Power MOSFET designated E–FET can be safely used
in switching circuits with unclamped inductive loads. For
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5
NTP35N15
SAFE OPERATING AREA
VGS = 20 V
SINGLE PULSE
TC = 25°C
100
10 µs
100 µs
10
1 ms
10 ms
1
dc
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
0.1
0.1
r(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE
(NORMALIZED)
EAS, SINGLE PULSE DRAIN-TO-SOURCE
AVALANCHE ENERGY (mJ)
I D , DRAIN CURRENT (AMPS)
1000
10
1.0
100
VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
700
ID = 21.6 A
600
500
400
300
200
100
0
25
1000
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
150
50
75
100
125
TJ, STARTING JUNCTION TEMPERATURE (°C)
Figure 12. Maximum Avalanche Energy versus
Starting Junction Temperature
1.0
D = 0.5
0.2
0.1
0.1
P(pk)
0.05
0.02
t1
0.01
t2
DUTY CYCLE, D = t1/t2
SINGLE PULSE
0.01
0.00001
0.0001
0.001
0.01
t, TIME (µs)
RθJC(t) = r(t) RθJC
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) – TC = P(pk) RθJC(t)
0.1
Figure 13. Thermal Response
di/dt
IS
trr
ta
tb
TIME
0.25 IS
tp
IS
Figure 14. Diode Reverse Recovery Waveform
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6
1.0
10
NTP35N15
PACKAGE DIMENSIONS
TO–220 THREE–LEAD
TO–220AB
CASE 221A–09
ISSUE AA
SEATING
PLANE
–T–
B
C
F
T
S
4
DIM
A
B
C
D
F
G
H
J
K
L
N
Q
R
S
T
U
V
Z
A
Q
1 2 3
U
H
K
Z
L
R
V
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION Z DEFINES A ZONE WHERE ALL
BODY AND LEAD IRREGULARITIES ARE
ALLOWED.
J
G
D
N
INCHES
MIN
MAX
0.570
0.620
0.380
0.405
0.160
0.190
0.025
0.035
0.142
0.147
0.095
0.105
0.110
0.155
0.018
0.025
0.500
0.562
0.045
0.060
0.190
0.210
0.100
0.120
0.080
0.110
0.045
0.055
0.235
0.255
0.000
0.050
0.045
----0.080
STYLE 5:
PIN 1. GATE
2. DRAIN
3 SOURCE
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7
MILLIMETERS
MIN
MAX
14.48
15.75
9.66
10.28
4.07
4.82
0.64
0.88
3.61
3.73
2.42
2.66
2.80
3.93
0.46
0.64
12.70
14.27
1.15
1.52
4.83
5.33
2.54
3.04
2.04
2.79
1.15
1.39
5.97
6.47
0.00
1.27
1.15
----2.04
NTP35N15
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are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes
without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular
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including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or
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NTP35N15/D