NTY100N10 Preferred Device Power MOSFET 123 A, 100 V N−Channel Enhancement−Mode TO264 Package http://onsemi.com Features 123 A, 100 V 9 mW @ VGS = 10 V (Typ) • Source−to−Drain Diode Recovery Time Comparable to a Discrete • • • Fast Recovery Diode Avalanche Energy Specified IDSS and RDS(on) Specified at Elevated Temperature Pb−Free Package is Available* N−Channel D Applications • PWM Motor Control • Power Supplies • Converters G S MAXIMUM RATINGS (TC = 25°C unless otherwise noted) Rating Symbol Value Unit Drain−Source Voltage VDSS 100 V Drain−Gate Voltage (RGS = 1 MW) VDGR 100 V Gate−Source Voltage − Continuous − Non−Repetitive (tp v 10 ms) VGS VGSM $ 20 $ 40 V V Drain Current (Note 1) − Continuous @ TC = 25°C − Pulsed A A ID 123 369 PD 313 2.5 Watts W/°C TJ, Tstg −55 to 150 °C Single Pulse Drain−to−Source Avalanche Energy − Starting TJ = 25°C (VDD = 80 Vdc, VGS = 10 Vdc, Peak IL = 100 Apk, L = 0.1 mH, RG = 25 W) EAS 500 mJ Thermal Resistance RqJC RqJA 0.4 25 °C/W TL 260 °C Total Power Dissipation (Note 1) Derate above 25°C Operating and Storage Temperature Range − Junction to Case − Junction to Ambient Maximum Lead Temperature for Soldering Purposes, 0.125 in from case for 10 seconds IDM MARKING DIAGRAM & PIN ASSIGNMENT 1 NTY100N10 AYYWWG 2 3 TO−264 CASE 340G STYLE 1 A YY WW G 2 D 3 S = Assembly Location = Year = Work Week = Pb−Free Package ORDERING INFORMATION Device NTY100N10 NTY100N10G Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Pulse Test: Pulse Width = 10 ms, Duty−Cycle = 2%. 1 G Package Shipping TO−264 25 Units/Rail TO−264 (Pb−Free) 25 Units/Rail Preferred devices are recommended choices for future use and best overall value. *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. © Semiconductor Components Industries, LLC, 2006 March, 2006 − Rev. 2 1 Publication Order Number: NTY100N10/D NTY100N10 ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) Symbol Characteristic Min Typ Max Unit 100 − − 144 − − Vdc mV/°C − − − − 10 100 − − 2.0 − 3.1 10.6 4.0 − − − 0.009 0.019 0.010 0.021 OFF CHARACTERISTICS Drain−Source Breakdown Voltage (VGS = 0, ID = 250 mA) (Positive Temperature Coefficient) V(BR)DSS Zero Gate Voltage Drain Current (VGS = 0 Vdc, VDS = 100 Vdc, TJ = 25°C) (VGS = 0 Vdc, VDS = 100 Vdc, TJ = 150°C) IDSS Gate−Body Leakage Current (VGS = $20 Vdc, VDS = 0) IGSS 100 mAdc nAdc ON CHARACTERISTICS (Note 2) Gate Threshold Voltage (VDS = VGS, ID = 250 mAdc) (Negative Temperature Coefficient) VGS(th) Static Drain−Source On−State Resistance (VGS = 10 Vdc, ID = 50 Adc) (VGS = 10 Vdc, ID = 50 Adc, 150°C) RDS(on) Drain−Source On−Voltage (VGS = 10 Vdc, ID = 100 Adc) VDS(on) − 0.8 1.0 Vdc Forward Transconductance (VDS = 6 Vdc, ID = 50 Adc) gFS − 73 − Mhos Ciss − 7225 10110 pF Coss − 1800 2540 Crss − 270 540 td(on) − 30 55 Vdc mV/°C W DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance (VDS = 25 Vdc, VGS = 0 Vdc, f = 1 MHz) Reverse Transfer Capacitance SWITCHING CHARACTERISTICS (Notes 2, 3) Turn−On Delay Time Rise Time Turn−Off Delay Time (VDD = 50 Vdc, ID = 100 Adc, VGS = 10 Vdc, RG = 9.1 W) Fall Time Total Gate Charge Gate−Source Charge (VDS = 80 Vdc, ID = 100 Adc, VGS = 10 Vdc) tr − 150 265 td(off) − 340 595 tf − 250 435 QT − 200 350 Q1 − 40 − Q2 − 100 − Q3 − 86 − − − 1.02 0.94 1.1 − trr − 210 − ta − 155 − tb − 55 − QRR − 1.08 − ns nC BODY−DRAIN DIODE RATINGS (Note 2) VSD Forward On−Voltage (IS = 100 Adc, VGS = 0 Vdc) (IS = 100 Adc, VGS = 0 Vdc, TJ = 150°C) Reverse Recovery Time (IS = 100 Adc, VGS = 0 Vdc, dIS/dt = 100 A/ms) Reverse Recovery Stored Charge 2. Indicates Pulse Test: Pulse Width v300 ms max, Duty Cycle = 2%. 3. Switching characteristics are independent of operating junction temperature. http://onsemi.com 2 Vdc ns mC NTY100N10 200 V = 10 V VGS = 9.0 V GS TJ = 25°C VGS = 8.0 V VGS = 6.0 V VGS = 7.0 V 150 VGS = 6.5 V 100 VGS = 5.6 V 50 VGS = 5.0 V ID, DRAIN CURRENT (A) ID, DRAIN CURRENT (A) 200 VDS w 10 V 150 100 50 0 0.018 2 4 6 8 T = 100°C T = 25°C 0.008 0.006 T = −55°C 0.004 0.002 0 50 100 150 200 ID, DRAIN CURRENT (A) 0.0095 10 0.009 VGS = 10 V 0.0085 VGS = 15 V 0.008 0.0075 0 50 100 150 20 ID, DRAIN CURRENT (A) Figure 4. On−Resistance versus Drain Current and Gate Voltage 1000000 ID = 50 A VGS = 10 V VGS = 0 V 100000 IDSS, LEAKAGE (nA) RDS(on), DRAIN−TO−SOURCE RESISTANCE (NORMALIZED) 8 T = 25°C Figure 3. On−Resistance versus Drain Current and Temperature 1.5 1.0 0.5 0 −50 6 Figure 2. On−Region Characteristics 0.01 2.0 4 Figure 1. On−Region Characteristics 0.012 2.5 2 VGS, GATE−TO−SOURCE VOLTAGE (V) 0.014 0 0 VDS, DRAIN−TO−SOURCE VOLTAGE (V) VGS = 10 V 0.016 0 10 RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) RDS(on), DRAIN−TO−SOURCE CURRENT (W) 0 TJ = 25°C TJ = −55°C TJ = 100°C VGS = 4.6 V 10000 TJ = 125°C 1000 TJ = 100°C 100 10 1.0 −25 0 25 50 75 100 125 150 0 TJ, JUNCTION TEMPERATURE (°C) 20 40 60 80 VDS, DRAIN−TO−SOURCE VOLTAGE (V) Figure 5. On−Resistance Variation with Temperature Figure 6. Drain−to−Source Leakage Current versus Voltage http://onsemi.com 3 100 NTY100N10 POWER MOSFET SWITCHING The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off−state condition when calculating td(on) and is read at a voltage corresponding to the on−state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses. Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (Dt) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain−gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG − VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn−on and turn−off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG − VGSP)] td(off) = RG Ciss In (VGG/VGSP) http://onsemi.com 4 NTY100N10 C, CAPACITANCE (pF) 20000 VDS = 0 16000 VGS = 0 TJ = 25°C Ciss 12000 Crss Ciss 8000 4000 0 Coss 10 5 0 Vgs 5 10 15 20 25 Vds Figure 7. Capacitance Variation 100 QT 8.0 VGS VDS Q2 Q1 6.0 80 60 40 4.0 2.0 Q3 0 0 20 IDS =100 A TJ = 25°C 50 100 150 Qg, TOTAL GATE CHARGE (nC) VDS, DRAIN−TO−SOURCE VOLTAGE (V) VGS, GATE−TO−SOURCE VOLTAGE (V) 10 0 200 Figure 8. Gate−to−Source and Drain−to−Source Voltage versus Total Charge 10000 IS, SOURCE CURRENT (A) 1000 t, TIME (nC) 100 VDD = 50 V ID = 100 A VGS = 10 V td(off) tf 100 tr td(on) 10 1.0 1 10 100 VGS = 0 V TJ = 25°C 80 60 40 20 0 0 0.2 0.4 0.6 0.8 RG, GATE RESISTANCE (W) VSD, SOURCE−TO−DRAIN VOLTAGE (V) Figure 9. Resistive Switching Time Variation versus Gate Resistance Figure 10. Diode Forward Voltage versus Current http://onsemi.com 5 1 NTY100N10 SAFE OPERATING AREA reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non−linearly with an increase of peak current in avalanche and peak junction temperature. Although many E−FETs can withstand the stress of drain−to−source avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated. ID, DRAIN CURRENT (A) 1000 RDS(on) Limit 100 Package Limit 10 10 ms 1 100 ms 1 ms 0.1 0.01 VGS = 20 V Single Pulse TC = 25°C 0.1 1 10 ms Thermal Limit 10 dc 100 EAS, SINGLE PULSE DRAIN−TO−SOURCE AVALANCHE ENERGY (mJ) The Forward Biased Safe Operating Area curves define the maximum simultaneous drain−to−source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25°C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, “Transient Thermal Resistance−General Data and Its Use.” Switching between the off−state and the on−state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded and the transition time (tr,tf) do not exceed 10 ms. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) − TC)/(RqJC). A Power MOSFET designated E−FET can be safely used in switching circuits with unclamped inductive loads. For 1000 500 ID = 100 A 400 300 200 100 0 25 50 75 100 125 150 VDS, DRAIN−TO−SOURCE VOLTAGE (V) TJ, STARTING JUNCTION TEMPERATURE (°C) Figure 11. Maximum Rated Forward Bias Safe Operating Area Figure 12. Maximum Avalanche Energy versus Starting Junction Temperature http://onsemi.com 6 NTY100N10 r (t), EFFECTIVE TRANSIENT THERMAL RESISTANC (NORMALIZED) SAFE OPERATING AREA 1 D = 0.5 0.2 0.1 P(pk) 0.05 0.1 0.02 0.01 t1 t2 DUTY CYCLE, D = t1/t2 SINGLE PULSE 0.01 1.0E−05 1.0E−04 1.0E−03 1.0E−02 RqJC(t) = r(t) RqJC D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) − TC = P(pk) RqJC(t) 1.0E−01 t, TIME (s) Figure 13. Thermal Response di/ dt IS trr ta tb TIME 0.25 IS tp IS Figure 14. Diode Reverse Recovery Waveform http://onsemi.com 7 1.0E+00 1.0E+01 NTY100N10 PACKAGE DIMENSIONS TO−3BPL (TO−264) CASE 340G−02 ISSUE J Q 0.25 (0.010) −B− M T B −T− M C E U N DIM A B C D E F G H J K L N P Q R U W A 1 R 2 L 3 P F 2 PL K W G J H D 3 PL 0.25 (0.010) M T B NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. MILLIMETERS MIN MAX 28.0 29.0 19.3 20.3 4.7 5.3 0.93 1.48 1.9 2.1 2.2 2.4 5.45 BSC 2.6 3.0 0.43 0.78 17.6 18.8 11.2 REF 4.35 REF 2.2 2.6 3.1 3.5 2.25 REF 6.3 REF 2.8 3.2 INCHES MIN MAX 1.102 1.142 0.760 0.800 0.185 0.209 0.037 0.058 0.075 0.083 0.087 0.102 0.215 BSC 0.102 0.118 0.017 0.031 0.693 0.740 0.411 REF 0.172 REF 0.087 0.102 0.122 0.137 0.089 REF 0.248 REF 0.110 0.125 STYLE 1: PIN 1. GATE 2. DRAIN 3. SOURCE S ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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