Revised November 1999 74ACT1284 IEEE 1284 Transceiver General Description Features The 74ACT1284 contains four non-inverting bidirectional buffers and three non-inverting buffers with open Drain outputs and high drive capability on the B Ports. It is intended to provide a standard signaling method for a bi-direction parallel peripheral in an Extended Capabilities Port mode (ECP). ■ TTL-compatible inputs The HD (active HIGH) input pin enables the B Ports to switch from open Drain to a high drive totem pole output, capable of sourcing 14 mA on all seven buffers. The DIR input determines the direction of data flow on the bidirectional buffers. DIR (active HIGH) enables data flow from A Ports to B Ports. DIR (active LOW) enables data flow from B Ports to A Ports. ■ Supports IEEE P1284 Level 1 and Level 2 signaling standards for bidirectional parallel communications between personal computers and printing peripherals ■ A Ports have standard 4 mA totem pole outputs ■ Typical input hysteresis of 0.5V ■ B Port high drive source/sink capability of 14 mA ■ Bidirectional non-inverting buffers ■ B Port outputs in High Impedance mode during power down ■ Guaranteed 4000V minimum ESD protection Ordering Code: Order Number Package Number 74ACT1284SC M20B Package Description 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 74ACT1284MSA MSA20 20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide 74ACT1284MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbol Connection Diagram Pin Descriptions Pin Names HD Description High Drive Enable input (Active HIGH) DIR Direction Control Input A1 - A4 Side A Inputs or Outputs B1 - B4 Side B Inputs or Outputs A5 - A7 Side A Inputs B5 - B7 Side B Outputs FACT is a trademark of Fairchild Semiconductor Corporation. © 1999 Fairchild Semiconductor Corporation DS011683 www.fairchildsemi.com 74ACT1284 IEEE 1284 Transceiver June 1996 74ACT1284 Truth Table Inputs Outputs DIR HD L L B1- B4 Data to A1 - A4, and L H B1- B4 Data to A1 - A4, and H L A1 - A7 Data to B1 - B7 (Note 2) H H A1 - A7 Data to B1 - B7 A5 - A7 Data to B5 - B7 (Note 1) A5 - A7 Data to B5 - B7 Note 1: B5 - B7 Open Drain Outputs Note 2: B1 - B7 Open Drain Outputs Logic Diagram www.fairchildsemi.com 2 Recommended Operating Conditions (Note 4) −0.5V to +7.0V Supply Voltage (VCC) Supply Voltage (VCC) DC Input Diode Current (IIK) VI = −0.5V −20 mA VI = VCC + 0.5V +20 mA DC Input Voltage (VI) A Side −0.5V to VCC + 0.5V DC Input Voltage (VI) B Side −2V to +7V 4.7V to 5.5V Input Voltage (VI) 0V to VCC Output Voltage (VO) 0V to VCC −40°C to +85°C Operating Temperature (TA) DC Output Diode Current (IOK) VO = −0.5V −20 mA VO = VCC + 0.5V +20 mA DC Output Voltage (VO) A Side −0.5V to VCC + 0.5V DC Output Voltage (VO) B Side −2V to +7V Note 3: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation of FACT circuits outside databook specifications. DC Output Source ± 50 mA or Sink Current (IO) DC VCC or Ground Current Note 4: Either voltage limit or current limit is sufficient to protect inputs. ± 50 mA per Output Pin (ICC or IGND) −65°C to +150°C Storage Temperature (TSTG) DC Electrical Characteristics Symbol VIH VIL VOH Parameter VCC (V) Guaranteed Limits TA = +25°C TA = 0°C to +70°C TA = −40°C to +85°C Minimum HIGH Level 4.7 2.0 2.0 2.0 Input Voltage 5.5 2.0 2.0 2.0 Maximum LOW Level 4.7 0.8 0.8 0.8 Input Voltage 5.5 0.8 0.8 0.8 Minimum HIGH Level 4.7 4.5 4.5 4.5 Output Voltage VOL Maximum LOW Level Units V V 3.7 3.7 3.7 4.7 2.4 2.4 2.4 4.7 0.2 0.2 0.2 Output Voltage 4.7 0.4 0.4 Maximum Input Leakage Current ICCT Maximum ICC/Input ICC Maximum Quiescent Supply Current IOZ Maximum Output Leakage Current IOFF Maximum B-Side Power Down Leakage Current High Signal Recognized Low Signal VIN = VIL or VIH (Note 5) IOH = −4 mA (An) V IOH = −14 mA (Bn) V VIN = VIL or VIH (Note 5) IOUT = 50 µA (An) IOH = 4 mA (An) 0.4 V IIN Recognized IOUT = −50 µA (An) V 4.7 Conditions IOH = 14 mA (Bn) VI = VCC, GND 5.5 ±0.1 ±1.0 µA 5.5 1.5 1.5 mA VI = VCC − 2.1V (DIR, A5, A6, A7, HD) 5.5 400 400 500 µA VIN = VCC or GND 5.5 ±20 ±20 ±20 µA VO = VCC, GND 0.0 100 100 100 µA VOUT = 5.25V ∆VT Input Hysteresis 5.0 0.4 0.4 0.35 V VT + − VT− RD Maximum Output Impedance 5.0 22 22 24 Ω Bn (Note 6) Minimum Output Impedance 5.0 8 8 6 Ω Bn (Note 6) Note 5: All outputs loaded; thresholds on input associated with output under test. Note 6: This parameter is guaranteed but not tested, characterized only: RD is the measure of the B-Side output impedance with the output in the HIGH state. 3 www.fairchildsemi.com 74ACT1284 Absolute Maximum Ratings(Note 3) 74ACT1284 AC Electrical Characteristics Symbol Parameter TA = +25°C TA = 0°C to +70°C TA = −40°C to +85°C VCC = 4.7V − 5.5V VCC = 4.7V − 5.5V VCC = 4.7V − 5.5V Units Figure Number Min Max Min Max Min Max tPHL A1- A7 to B1 - B7 2.0 20.0 2.0 20.0 2.0 24.0 ns Figure 1 tPLH A1- A7 to B1 - B7 2.0 20.0 2.0 20.0 2.0 24.0 ns Figure 2 tPHL B1 - B4 to A1 - A4 2.0 20.0 2.0 20.0 2.0 24.0 ns Figure 3 tPLH B1 - B4 to A1 - A4 2.0 20.0 2.0 20.0 2.0 24.0 ns Figure 3 tpEnable Output Enable Time 2.0 20.0 2.0 20.0 2.0 24.0 ns Figure 2 2.0 20.0 2.0 20.0 2.0 24.0 ns Figure 2 0.05 0.40 0.05 0.40 0.05 0.40 V/ns 120 ns HD to B1 - B7 tpDisable Output Disable Time HD to B1 - B7 tSKEW Output Slew Rate tPLH B1 - B7 Figure 1 Figure 2 tPHL tr , tf tRISE and tFALL 120 B1 - B7 (Note 7) 120 Note 7: Open Drain Note 8: This parameter is guaranteed but not tested, characterized only. Note: Pulse Generator for all pulses; Rate ≤ 1.0 MHz; AO ≤ 50Ω; tf ≤ 2.5 ns, tr ≤ 2.5 ns. Capacitance Typ Units CIN Symbol Input Capacitance Parameter 4.0 pF VCC = OPEN (HD, DIR A5 - A7) CI/O I/O Pin Capacitance 12.0 pF VCC = 5.0V www.fairchildsemi.com 4 Conditions Figure 4 (Note 8) 74ACT1284 AC Loading and Waveforms tSLEW measures between 10% to 90% on the tPHL Transition FIGURE 1. A to B Direction Test Load and Waveforms tSLEW measures between 10% to 90% on the tPLH Transition FIGURE 2. B Output Test Load and Waveforms FIGURE 3. B to A Direction Test Load and Waveforms for Outputs A1 - A4 FIGURE 4. A to B Direction Test Load and Waveforms for Open Drain B1 - B7 5 www.fairchildsemi.com 74ACT1284 Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide Package Number M20B 20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide Package Number MSA20 www.fairchildsemi.com 6 74ACT1284 IEEE 1284 Transceiver Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC20 Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. 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