Revised October 2001 74LVT16952 • 74LVTH16952 Low Voltage 16-Bit Registered Transceiver with 3-STATE Outputs General Description Features The LVT16952 and LVTH16952 are 16-bit registered transceivers. Two 8-bit back to back registers store data flowing in both directions between two bidirectional buses. Separate clock, clock enable, and output enable signals are provided for each register. ■ Input and output interface capability to systems at 5V VCC The LVTH16952 data inputs include bushold, eliminating the need for external pull-up resistors to hold unused inputs. The registered transceiver is designed for low-voltage (3.3V) VCC applications, but with the capability to provide a TTL interface to a 5V environment. The LVT16952 and LVTH16952 are fabricated with an advanced BiCMOS technology to achieve high speed operation similar to 5V ABT while maintaining low power dissipation. ■ Bushold data inputs eliminate the need for external pull-up resistors to hold unused inputs (74LVTH16952) ■ Live insertion/extraction permitted ■ Power Up/Down high impedance provides glitch-free bus loading ■ Outputs source/sink −32 mA/+64 mA ■ Functionally compatible with the 74 series 16952 ■ Latch-up conforms to JEDEC JED78 ■ ESD performance: Human-body model > 2000V Machine model > 200V Charged-device model > 1000V Ordering Code: Order Number Package Number Package Description 74LVT16952MEA (Preliminary) MS56A 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300" Wide 74LVT16952MTD (Preliminary) MTD56 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide 74LVTH16952MEA MS56A 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300" Wide 74LVTH16952MTD MTD56 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. © 2001 Fairchild Semiconductor Corporation DS500103 www.fairchildsemi.com 74LVT16952 • 74LVTH16952 Low Voltage 16-Bit Registered Transceiver with 3-STATE Outputs January 2000 74LVT16952 • 74LVTH16952 Connection Diagram Pin Descriptions Pin Names Description A0–A16 Data Register A Inputs B-Register 3-STATE Outputs B0–B16 Data Register B Inputs A-Register 3-STATE Outputs CPABn, CPBAn Clock Pulse Inputs CEAn, CEBn Clock Enable OEABn, OEBAn Output Enable Inputs Truth Table (Note 1) Inputs Internal Register Output An CPABn CEAn OEABn Value Bn X X H L NC B0 X X H H NC Z L L L L L H L Z L L H H L H H Z X L X L NC B0 X H X L NC B0 X L X H NC Z X H X H NC Z L L H H H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = Output High Impedance = LOW-to-HIGH Transition. NC = No Change (state established by last valid CP) B0 = State established by last valid CP Note 1: A to B data flow shown; B to A flow control is the same, but used OEBAn, CPBAn and CEBn. www.fairchildsemi.com 2 74LVT16952 • 74LVTH16952 Logic Diagram Note: n for either byte 1 or byte 2. Please note that these diagrams are provided only for the understanding of logic operations and should not be used to estimate propagation delays. 3 www.fairchildsemi.com 74LVT16952 • 74LVTH16952 Absolute Maximum Ratings(Note 2) Symbol Parameter Value Conditions Units VCC Supply Voltage −0.5 to +4.6 VI DC Input Voltage −0.5 to +7.0 VO DC Output Voltage −0.5 to +7.0 Output in 3-STATE −0.5 to +7.0 Output in HIGH or LOW State (Note 3) V V V IIK DC Input Diode Current −50 VI < GND IOK DC Output Diode Current −50 VO < GND IO DC Output Current 64 VO > VCC Output at HIGH State 128 VO > VCC Output at LOW State V mA mA mA ICC DC Supply Current per Supply Pin ±64 mA IGND DC Ground Current per Ground Pin ±128 mA TSTG Storage Temperature −65 to +150 °C Recommended Operating Conditions Symbol Parameter Min Max Units 2.7 3.6 V 0 5.5 V VCC Supply Voltage VI Input Voltage IOH HIGH-Level Output Current −32 IOL LOW-Level Output Current 64 TA Free-Air Operating Temperature ∆t/∆V Input Edge Rate, VIN = 0.8V–2.0V, VCC = 3.0V mA −40 +85 °C 0 10 ns/V Note 2: Absolute Maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum rated conditions is not implied. Note 3: IO Absolute Maximum Rating must be observed. www.fairchildsemi.com 4 Symbol VIK Input Clamp Diode Voltage T A = −40°C to +85°C VCC Parameter (V) Min Max −1.2 2.7 Units VO ≤ 0.1V or VIH Input HIGH Voltage 2.7–3.6 VIL Input LOW Voltage 2.7–3.6 VOH Output HIGH Voltage 2.7–3.6 VCC − 0.2 V IOH = −100 µA 2.7 2.4 V IOH = −8 mA 3.0 2.0 V IOH = −32 mA VOL II(HOLD) Output LOW Voltage Bushold Input Minimum Drive Bushold Input Over-Drive (Note 4) Current to Change State II Input Current IOFF Power Off Leakage Current IPU/PD Power Up/Down 3-STATE V 0.8 VO ≥ VCC − 0.1V 2.7 0.2 V IOL = 100 µA 2.7 0.5 V IOL = 24 mA 3.0 0.4 V IOL = 16 mA 3.0 0.5 V IOL = 32 mA 3.0 0.55 V IOL = 64 mA 75 µA VI = 0.8V −75 µA VI = 2.0V 500 µA (Note 5) µA (Note 6) 3.0 (Note 4) II(OD) 2.0 Conditions II = −18 mA V 3.0 −500 3.6 10 µA VI = 5.5V Control Pins 3.6 ±1 µA VI = 0V or VCC Data Pins 3.6 −5 µA VI = 0V 1 µA VI = VCC ±100 µA 0 0V ≤ VI or VO ≤ 5.5V VO = 0.5V to 3.0V 0–1.5V ±100 µA IOZL 3-STATE Output Leakage Current 3.6 −5 µA VO = 3.0V IOZL 3-STATE Output Leakage Current 3.6 −5 µA VO = 0.0V IOZH 3-STATE Output Leakage Current 3.6 5 µA VO = 0.5V IOZH 3-STATE Output Leakage Current 3.6 5 µA VO = 3.6V Output Current VI = GND or VCC (Note 4) (Note 4) IOZH+ 3-STATE Output Leakage Current 3.6 10 µA VCC < V O ≤ 5.5V ICCH Power Supply Current 3.6 0.19 mA Outputs High ICCL Power Supply Current 3.6 5 mA Outputs Low ICCZ Power Supply Current 3.6 0.19 mA Outputs Disabled ICCZ+ Power Supply Current 3.6 0.19 mA VCC ≤ V O ≤ 5.5V, ∆ICC Increase in Power Supply Current 3.6 0.2 mA One Input at VCC − 0.6V Outputs Disabled (Note 7) Other Inputs at VCC or GND Note 4: Applies to bushold version only (74LVTH16952). Note 5: An external driver must source at least the specified current to switch from LOW-to-HIGH. Note 6: An external driver must sink at least the specified current to switch from HIGH-to-LOW. Note 7: This is the increase in supply current for each input that is at the specified voltage level rather than VCC or GND. Dynamic Switching Characteristics Symbol Parameter (Note 8) TA = 25°C VCC (V) Min Typ Max Units Conditions CL = 50 pF, RL = 500Ω VOLP Quiet Output Maximum Dynamic VOL 3.3 0.8 V (Note 9) VOLV Quiet Output Minimum Dynamic VOL 3.3 −0.8 V (Note 9) Note 8: Characterized in SSOP package. Guaranteed parameter, but not tested. Note 9: Max number of outputs defined as (n). n−1 data inputs are driven 0V to 3V. Output under test held LOW. 5 www.fairchildsemi.com 74LVT16952 • 74LVTH16952 DC Electrical Characteristics 74LVT16952 • 74LVTH16952 AC Electrical Characteristics TA = −40°C to +85°C Symbol CL = 50 pF, RL = 500Ω Parameter VCC = 3.3 ± 0.3V Min fMAX Maximum Clock Frequency 150 tPLH Propagation Delay 1.3 tPHL CPBA or CPAB to A or B tPZH Output Enable Time tPZL OE to A or B tPHZ Output Disable Time tPLZ tW tS Units VCC = 2.7V Max Min Max 150 MHz 4.4 1.3 4.7 1.3 4.8 1.3 5.0 1.0 4.3 1.0 4.9 1.0 4.8 1.0 5.7 2.1 5.7 2.1 6.2 OE to A or B 2.1 5.1 2.1 5.3 Pulse Width, CPAB or CPBA HIGH or LOW 3.3 3.3 Setup Time A or B before CPAB or CPBA 1.7 2.5 CEA or CEB before CPAB or CPBA 2.0 2.8 ns ns ns ns ns tH Hold Time A or B after CPAB or CPBA 0.8 0.0 CEA or CEB after CPAB or CPBA 0.4 0.0 ns tOSLH Output to Output Skew (Note 10) tOSHL 1.0 1.0 1.0 1.0 ns Note 10: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). Capacitance (Note 11) Typical Units CIN Symbol Input Capacitance Parameter VCC = OPEN, VI = 0V or VCC Conditions 4 pF CI/O Input/Output Capacitance VCC = 3.0V, VO = 0V or VCC 8 pF Note 11: Capacitance is measured at frequency f = 1 MHz, per MIL-STD-883, Method 3012. www.fairchildsemi.com 6 74LVT16952 • 74LVTH16952 Physical Dimensions inches (millimeters) unless otherwise noted 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300" Wide Package Number MS56A 7 www.fairchildsemi.com 74LVT16952 • 74LVTH16952 Low Voltage 16-Bit Registered Transceiver with 3-STATE Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Package Number MTD56 Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. 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