TI SN54LS490

SN54LS490, SN74LS490
DUAL 4-BIT DECADE COUNTERS
SDLS125A – OCTOBER 1976 – REVISED JULY 1998
D
D
D
D
1CLK
1CLR
1QA
1SET9
1QB
1QC
1QD
GND
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
VCC
2CLK
2CLR
2QA
2SET9
2QB
2QC
2QD
SN54LS490 . . . FK PACKAGE
(TOP VIEW)
description
1QA
1SET9
NC
1QB
1QC
4
3 2 1 20 19
18
5
17
6
16
7
15
8
14
9 10 11 12 13
2CLR
2QA
NC
2SET9
2QB
1QD
GND
NC
2QD
2QC
Each of these monolithic circuits contains eight
master-slave flip-flops and additional gating to
implement two individual 4-bit decade counters in
a single package. Each decade counter has
individual clock (1CLK, 2CLK), clear (1CLR,
2CLR), and set-to-9 (1SET9, 2SET9) inputs. BCD
count sequences of any length up to
divide-by-100 can be implemented with a single
’LS490 device. Buffering on each output is
provided to significantly reduce susceptibility to
collector commutation. All inputs are diode
clamped to reduce the effects of line ringing. The
counters have parallel outputs from each counter
stage so that submultiples of the input count
frequency are available for system timing signals.
2CLK
D
SN54LS490 . . . J OR W PACKAGE
SN74LS490 . . . D OR N PACKAGE
(TOP VIEW)
Dual Versions of the SN54LS90 and
SN74LS90 Counters
Individual Clock, Direct Clear, and Set-to-9
Inputs for Each Decade Counter
Dual Counters Can Significantly Improve
System Densities as Package Count Can
Be Reduced by 50%
Maximum Count Frequency of
25 MHz . . . 35 MHz Typical
Buffered Outputs Reduce Possibility of
Collector Commutation
Package Options Include Plastic
Small-Outline (D) Packages, Ceramic Flat
(W) Packages, Ceramic Chip Carriers (FK),
and Standard Plastic (N) and Ceramic (J)
DIPs
1CLR
1CLK
NC
V CC
D
NC – No internal connection
The SN54LS490 is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74LS490 is characterized for use in industrial systems operating from 0°C to 70°C.
CLEAR/SET-TO-9 FUNCTION TABLE
(each counter)
INPUTS
CLR
SET9
OUTPUTS
QA
QB
QC
QD
H
L
L
L
L
L
L
H
H
L
L
H
L
L
Count
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  1998, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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1
SN54LS490, SN74LS490
DUAL 4-BIT DECADE COUNTERS
SDLS125A – OCTOBER 1976 – REVISED JULY 1998
BCD COUNT SEQUENCE
(each counter)
COUNT
OUTPUTS
QD
QC
QB
0
L
L
L
QA
L
1
L
L
L
H
2
L
L
H
L
3
L
L
H
H
4
L
H
L
L
5
L
H
L
H
6
L
H
H
L
7
L
H
H
H
8
H
L
L
L
9
H
L
L
H
logic symbol†
CTRDIV10
1CLR
1SET9
1CLK
2
0
CT=0
4
CT=9
1
5
CT
6
+
3
2CLR
2SET9
2CLK
7
13
14
11
12
10
15
9
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the D, J, N, and W packages.
2
3
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1QA
1QB
1QC
1QD
2QA
2QB
2QC
2QD
SN54LS490, SN74LS490
DUAL 4-BIT DECADE COUNTERS
SDLS125A – OCTOBER 1976 – REVISED JULY 1998
schematics of inputs and outputs
EQUIVALENT OF
EACH CLK INPUT
VCC
EQUIVALENT OF
EACH CLR AND SET9 INPUT
VCC
43 kΩ NOM
Input
TYPICAL OF
ALL OUTPUTS
VCC
18 kΩ NOM
120 Ω NOM
Input
Output
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3
SN54LS490, SN74LS490
DUAL 4-BIT DECADE COUNTERS
SDLS125A – OCTOBER 1976 – REVISED JULY 1998
logic diagram (each counter)
4, 12
SET9
S
CLK
1, 15
3, 13
QA
T
R
5, 11
QB
T
R
6, 10
QC
T
R
S
T
R
CLR
2, 14
Pin numbers shown are for the D, J, N, and W packages.
4
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7, 9
QD
SN54LS490, SN74LS490
DUAL 4-BIT DECADE COUNTERS
SDLS125A – OCTOBER 1976 – REVISED JULY 1998
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Clear and set-to-9 voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Clock input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 5.5 V
Package thermal impedance, θJA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. Voltage values are with respect to network ground terminal.
2. The package thermal impedance is calculated in accordance with JESD 51, except for through-hole packages, which use a trace
length of zero.
recommended operating conditions
SN54LS490
SN74LS490
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.75
5
5.25
UNIT
VCC
IOH
Supply voltage
High-level output current
–400
–400
µA
IOL
fcount
Low-level output current
4
8
mA
25
MHz
tw
tsu
Pulse width (any input)
Count frequency
0
Clear or set-to-9 inactive-state setup time
TA
Operating free-air temperature
–55
‡ The arrow (↓) indicates that the falling edge of the clock pulse is used for reference.
POST OFFICE BOX 655303
25
20
25↓‡
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0
20
25↓‡
125
0
V
ns
ns
70
°C
5
SN54LS490, SN74LS490
DUAL 4-BIT DECADE COUNTERS
SDLS125A – OCTOBER 1976 – REVISED JULY 1998
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
TEST CONDITIONS†
PARAMETER
VIH
VIL
High-level input voltage
VIK
Input clamp voltage
VOH
High-level output voltage
VOL
Low level output voltage
Low-level
II
Input current
at maximum
input voltage
IIH
High-level
g
input current
CLK
IIL
Low-level
input current
CLK
IOS§
ICC
SN74LS490
TYP‡
MAX
MIN
2
2
Low-level input voltage
VCC = MIN,
II = –18 mA
VCC = MIN, VIH = 2 V,
VIL = VILmax
2.5
SN74LS490
TYP‡
MAX
MIN
V
0.7
0.8
V
–1.5
–1.5
V
3.4
2.7
3.4
V
VCC = MIN,
VIH = 2 V
V,
VIL = VILmax
IOL = 4 mA
CLR, SET9
VCC = MAX,
VI = 7 V
0.1
0.1
CLK
VCC = MAX,
VI = 5.5 V
0.2
0.2
VCC = MAX
MAX,
VI = 2
2.7
7V
VCC = MAX
MAX,
VI = 0
0.4
4V
CLR, SET9
CLR, SET9
Short-circuit output current
0.25
0.4
0.25
0.4
0.35
0.5
V
IOL = 8 mA
VCC = MAX
VCC = MAX,
UNIT
mA
–20
20
20
100
100
–0.4
–0.4
–1.6
–1.6
–100
–20
–100
µA
mA
mA
Supply current
See Note 3
15
26
15
26
mA
† For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
‡ All typical values are at VCC = 5 V, TA = 25°C.
§ Not more than one output should be shorted at a time, and duration of the short circuit should not exceed one second.
NOTE 3: ICC is measured with all outputs open, both CLR inputs grounded following momentary connection to 4.5 V, and all other inputs
grounded.
switching characteristics, VCC = 5 V, TA = 25°C (see Figures 1 and 2)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
fmax
CLK
QA
tPLH
CL = 15 pF,
pF
RL = 2 kΩ
CLK
QB,
B QD
CL = 15 pF,
pF
RL = 2 kΩ
CLK
QC
CL = 15 pF,
pF
RL = 2 kΩ
CLR
Any
CL = 15 pF,
RL = 2 kΩ
CL = 15 pF,
pF
RL = 2 kΩ
tPHL
tPHL
tPLH
tPHL
6
RL = 2 kΩ
QA
tPHL
tPLH
CL = 15 pF,
CLK
tPHL
tPLH
TEST CONDITIONS
SET9
QA, QD
QB, QC
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MIN
TYP
25
35
MAX
UNIT
MHz
12
20
13
20
24
39
26
39
32
54
36
54
24
39
24
39
20
36
ns
ns
ns
ns
ns
SN54LS490, SN74LS490
DUAL 4-BIT DECADE COUNTERS
SDLS125A – OCTOBER 1976 – REVISED JULY 1998
PARAMETER MEASUREMENT INFORMATION
3V
SET9
1.3 V
1.3 V
0V
tsu
3V
1.3 V
CLR
1.3 V
0V
tw(clock)
tsu
3V
CLK
1.3 V
1.3 V
1.3 V
1.3 V
0V
tPLH
tPLH
(Measure at
tn + 1)
tPHL
tPHL
(Measure at
tn + 2)
VOH
QA
1.3 V
1.3 V
1.3 V
1.3 V
VOL
tPHL
tPLH
(Measure at
tn + 2)
tPHL
tPHL
(Measure at
tn + 4)
tPHL
VOH
QD
1.3 V
1.3 V
1.3 V
1.3 V
VOL
tPHL
tPLH
(Measure at
tn + 4)
tPHL
tPLH
(Measure at
tn + 8)
tPHL
VOH
QC
1.3 V
1.3 V
1.3 V
1.3 V
VOL
tPLH
tPHL
(Measure at
tn + 8)
tPHL
tPHL
(Measure at
tn + 10)
tPHL
VOH
QB
1.3 V
1.3 V
1.3 V
1.3 V
VOL
NOTE A: Input pulses are supplied by a generator having the following characteristics: tr ≤ 15 ns, tf ≤ 6 ns, PRR ≤ 1 MHz, duty cycle = 50%,
ZO ≈ 50 Ω.
Figure 1. Voltage Waveforms
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7
SN54LS490, SN74LS490
DUAL 4-BIT DECADE COUNTERS
SDLS125A – OCTOBER 1976 – REVISED JULY 1998
PARAMETER MEASUREMENT INFORMATION
VCC
Test
Point
VCC
VCC
RL
From Output
Under Test
CL
(see Note A)
From Output
Under Test
RL
S1
From Output
Under Test
CL
(see Note A)
RL
(see Note B)
Test
Point
(see Note B)
5 kΩ
Test
Point
CL
(see Note A)
LOAD CIRCUIT FOR
BI-STATE
TOTEM-POLE OUTPUTS
High-Level
Pulse
1.3 V
S2
LOAD CIRCUIT
FOR OPEN-COLLECTOR OUTPUTS
LOAD CIRCUIT
FOR 3-STATE OUTPUTS
3V
Timing
Input
1.3 V
1.3 V
0V
tw
Low-Level
Pulse
1.3 V
th
tsu
3V
Data
Input
1.3 V
1.3 V
1.3 V
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATIONS
3V
Input
1.3 V
tPHL
tPLH
VOH
1.3 V
tPHL
Out-of-Phase
Output
(see Note F)
1.3 V
1.3 V
Waveform 1
S2 Open
(see Notes C
and F)
VOL
tPLH
VOH
1.3 V
1.3 V
VOL
1.3 V
0V
tPZL
1.3 V
0V
In-Phase
Output
(see Note F)
3V
Output
Control
(low-level
enabling)
tPLZ
[1.5 V
1.3 V
VOL + 0.3 V
tPHZ
Waveform 2
S2 Closed
(see Notes C
and F)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
tPZH
1.3 V
VOH – 0.3 V
[1.5 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
NOTES: A. CL includes probe and jig capacitance.
B. All diodes are 1N3064 or equivalent.
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
D. In the examples above, the phase relationships between inputs and outputs have been chosen arbitrarily.
E. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO ≈ 50 Ω, tr ≤ 15 ns, tf ≤ 6 ns.
F. S1 and S2 are closed for tPLH, tPHL, tPHZ, and tPLZ; S1 is open and S2 is closed for tPZH; S1 is closed and S2 is open for tPZL.
G. The outputs are measured one at a time with one input transition per measurement.
Figure 2. Load Circuits and Voltage Waveforms
8
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