CD54HC160, CD54HC162 BCD SYNCHRONOUS DECADE COUNTERS SCHS301 – JUNE 2000 D D D D D D D D Synchronous Counting and Loading Two Count-Enable Inputs for n-Bit Cascading Asynchronous Reset (CD54HC160) Synchronous Reset (CD54HC162) Look-Ahead Carry for High-Speed Counting Operating Range 2-V to 6-V VCC EPIC (Enhanced-Performance Implanted CMOS) Process Packaged in Ceramic (F) DIPs CD54HC160, CD54HC162 . . . F PACKAGE (TOP VIEW) CLR CLK A B C D ENP GND 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC RCO QA QB QC QD ENT LOAD description These synchronous, presettable counters feature an internal carry look-ahead for application in high-speed counting designs. The CD54HC160 and CD54HC162 are BCD decade counters. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincident with each other when so instructed by the count-enable (ENP, ENT) inputs and internal gating. This mode of operation eliminates the output counting spikes that are normally associated with synchronous (ripple-clock) counters. A buffered clock (CLK) input triggers the four flip-flops on the rising (positive-going) edge of the clock waveform. These counters are fully programmable; that is, they can be preset to any number between 0 and 9. As presetting is synchronous, setting up a low level at the load input disables the counter and causes the outputs to agree with the setup data after the next clock pulse, regardless of the levels of the enable inputs. The clear function for the CD54HC160 is asynchronous. A low level at the clear (CLR) input sets all four of the flip-flop outputs low, regardless of the levels of the CLK, load (LOAD), or enable inputs. The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without additional gating. Instrumental in accomplishing this function are ENP, ENT, and a ripple-carry output (RCO). Both ENP and ENT must be high to count, and ENT is fed forward to enable RCO. Enabling RCO produces a high-level pulse while the count is maximum (9 with QA high). This high-level overflow ripple-carry pulse can be used to enable successive cascaded stages. Transitions at ENP or ENT are allowed, regardless of the level of CLK. These counters feature a fully independent clock circuit. Changes at control inputs (ENP, ENT, or LOAD) that modify the operating mode have no effect on the contents of the counter until clocking occurs. The function of the counter (whether enabled, disabled, loading, or counting) is dictated solely by the conditions meeting the stable setup and hold times. The CD54HC160 and CD54HC162 are supplied in 16-lead hermetic dual-in-line ceramic packages (F suffix), and are characterized for operation over the full military temperature range of –55°C to 125°C. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC is a trademark of Texas Instruments Incorporated. Copyright 2000, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 CD54HC160, CD54HC162 BCD SYNCHRONOUS DECADE COUNTERS SCHS301 – JUNE 2000 logic symbol† CD54HC160 BINARY COUNTER WITH DIRECT CLEAR CLR LOAD ENT ENP CLK A B C D 1 9 10 7 2 3 CTRDIV10 CT=0 M1 M2 3CT=9 15 RCO G3 G4 C5/2,3,4+ [1] 1,5D 4 [2] 5 [4] 6 [8] 14 13 12 11 QA QB QC QD CD54HC162 BINARY COUNTER WITH SYNCHRONOUS CLEAR CLR LOAD ENT ENP CLK A B C D CTRDIV10 5CT=0 1 9 10 7 2 3 4 5 6 M1 M2 3CT=9 15 G4 C5/2,3,4+ 1,5D [1] [2] [4] [8] 14 13 12 11 † These symbols are in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. 2 RCO G3 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 QA QB QC QD CD54HC160, CD54HC162 BCD SYNCHRONOUS DECADE COUNTERS SCHS301 – JUNE 2000 CD54HC160 logic diagram (positive logic)† CLR LOAD ENT 1 9 10 15 ENP 7 RCO CLK 2 C1 14 QA 1D R A 3 C1 13 QB 1D R B 4 C1 12 QC 1D R C 5 C1 11 QD 1D R D 6 † CD54HC162 decade counter is similar; however, the clear is synchronous. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 CD54HC160, CD54HC162 BCD SYNCHRONOUS DECADE COUNTERS SCHS301 – JUNE 2000 logic diagram, each D/T flip-flop (positive logic) ENT Q Q CL p LOAD n n CL p CL CLR† CL p p n n n CL CL p CL CL p n CLR† D CL CLK † Connect to VDD for CD54HC162. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 CL CD54HC160, CD54HC162 BCD SYNCHRONOUS DECADE COUNTERS SCHS301 – JUNE 2000 typical clear, preset, count, and inhibit sequences Illustrated below is the following sequence: 1. Clear outputs to zero (CD54HC160 is asynchronous; CD54HC162 is synchronous) 2. Preset BCD to seven 3. Count to eight, nine, zero, one, two, and three 4. Inhibit CD54HC160, CD54HC162 CLR LOAD A Data Inputs B C D CLK ENP ENT QA QB Outputs QC QD RCO 7 8 9 0 1 2 3 Count Async Clear Inhibit Sync Preset Clear POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 CD54HC160, CD54HC162 BCD SYNCHRONOUS DECADE COUNTERS SCHS301 – JUNE 2000 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < –0.5 V or VI > VCC + 0.5 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Output clamp current, IOK (VO < –0.5 V or VO > VCC + 0.5 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Continuous output current, IO (VO = –0.5 V to VCC + 0.5 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Power dissipation, PD (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 mW Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265°C Lead temperature, unit inserted into a PC board (minimum thickness 1,6 mm, 1/16 inch) with solder contacting lead tips only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. Above 100°C, derate linearly at a factor of 8 mW/°C. recommended operating conditions (see Note 3) VCC VIH Supply voltage VCC = 2 V VCC = 4.5 V High-level input voltage VCC = 6 V VCC = 2 V MIN MAX 2 6 V 1.5 V 3.15 4.2 0.5 VIL Low-level input voltage VI VO Input voltage 0 Output voltage 0 VCC VCC 0 1000 tr, tf Input transition rise or fall times 0 500 0 400 1.35 VCC = 4.5 V VCC = 6 V VCC = 2 V VCC = 4.5 V VCC = 6 V UNIT V 1.8 V V ns TA Operating free-air temperature –55 125 °C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 CD54HC160, CD54HC162 BCD SYNCHRONOUS DECADE COUNTERS SCHS301 – JUNE 2000 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN IOH = –20 mA VOH IOH = –4 mA IOH = –5.2 mA TYP MAX MIN 2V 1.9 1.9 4.5 V 4.4 4.4 6V 5.9 5.9 4.5 V 3.98 3.7 6V 5.48 UNIT MAX V 5.2 2V 0.1 0.1 IOL = 20 mA 4.5 V 0.1 0.1 6V 0.1 0.1 IOL = 4 mA IOL = 5.2 mA 4.5 V 0.26 0.4 6V 0.26 0.4 6V ±0.1 ±1 mA 6V 8 160 mA 10 10 pF VOL II ICC CD54HC160 CD54HC162 TA = 25°C VCC VI = VCC or GND VI = VCC or GND, IO = 0 CIN V timing requirements over recommended operating free-air temperature range, VCC = 2 V (unless otherwise noted) (see Figure 1) TA = 25°C MIN fmax tw tsu th Maximum frequency CLK 6 4 120 100 150 Data (A, B, C, and D) 60 90 ENP, ENT 50 75 LOAD low 60 90 CLR (’162 only) 65 100 CLR high (’160 only) 75 110 Data (A, B, C, and D) 3 3 ENP, ENT 0 0 LOAD low 3 3 CLR low (’160 only) Setup time before CLK↑ ↑ Hold time after CLK↑ ↑ POST OFFICE BOX 655303 MIN 80 CLK low Pulse duration MAX CD54HC160 CD54HC162 • DALLAS, TEXAS 75265 UNIT MAX MHz ns ns ns 7 CD54HC160, CD54HC162 BCD SYNCHRONOUS DECADE COUNTERS SCHS301 – JUNE 2000 timing requirements over recommended operating free-air temperature range, VCC = 4.5 V (unless otherwise noted) (see Figure 1) TA = 25°C MIN fmax Maximum frequency tw Pulse duration tsu th Setup time before CLK↑ ↑ Hold time after CLK↑ ↑ MAX CD54HC160 CD54HC162 MIN CLK 30 20 CLK low 16 24 CLR low (’160 only) 20 30 Data (A, B, C, and D) 12 18 ENP, ENT 10 15 LOAD low 12 18 CLR (’162 only) 13 20 CLR high (’160 only) 15 22 Data (A, B, C, and D) 3 3 ENP, ENT 0 0 LOAD low 3 3 UNIT MAX MHz ns ns ns timing requirements over recommended operating free-air temperature range, VCC = 6 V (unless otherwise noted) (see Figure 1) TA = 25°C MIN fmax tw tsu th 8 Maximum frequency Pulse duration Setup time before CLK↑ ↑ Hold time after CLK↑ ↑ POST OFFICE BOX 655303 MAX CD54HC160 CD54HC162 MIN CLK 35 24 CLK low 14 20 CLR low (’160 only) 17 26 Data (A, B, C, and D) 10 15 ENP, ENT 9 13 LOAD low 10 15 CLR (’162 only) 11 17 CLR high (’160 only) 13 19 Data (A, B, C, and D) 3 3 ENP, ENT 0 0 LOAD low 3 3 • DALLAS, TEXAS 75265 UNIT MAX MHz ns ns ns CD54HC160, CD54HC162 BCD SYNCHRONOUS DECADE COUNTERS SCHS301 – JUNE 2000 switching characteristics over recommended operating free-air temperature range, VCC = 2 V (unless otherwise noted) (see Figure 1) FROM (INPUT) TO (OUTPUT) LOAD CAPACITANCE tPLH tPHL CLK RCO CL = 50 pF tPLH tPHL CLK Q CL = 50 pF tPLH tPHL ENT RCO CL = 50 pF tPHL CLR PARAMETER Q (’160 only) RCO (’160 only) tTLH tTHL TA = 25°C MIN CL = 50 pF CL = 50 pF MAX CD54HC160 CD54HC162 MIN UNIT MAX 185 280 185 280 185 280 185 280 120 180 120 180 210 315 210 315 75 110 75 110 ns ns ns ns ns switching characteristics over recommended operating free-air temperature range, VCC = 4.5 V (unless otherwise noted) (see Figure 1) FROM (INPUT) TO (OUTPUT) LOAD CAPACITANCE tPLH tPHL CLK RCO CL = 50 pF tPLH tPHL CLK Q CL = 50 pF tPLH tPHL ENT RCO CL = 50 pF tPHL CLR PARAMETER Q (’160 only) RCO (’160 only) tTLH tTHL CL = 50 pF CL = 50 pF POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TA = 25°C MIN MAX CD54HC160 CD54HC162 MIN UNIT MAX 37 56 37 56 37 56 37 56 24 36 24 36 42 63 42 63 15 22 15 22 ns ns ns ns ns 9 CD54HC160, CD54HC162 BCD SYNCHRONOUS DECADE COUNTERS SCHS301 – JUNE 2000 switching characteristics over recommended operating free-air temperature range, VCC = 6 V (unless otherwise noted) (see Figure 1) FROM (INPUT) TO (OUTPUT) LOAD CAPACITANCE tPLH tPHL CLK RCO CL = 50 pF tPLH tPHL CLK Q CL = 50 pF tPLH tPHL ENT RCO CL = 50 pF tPHL CLR PARAMETER Q (’160 only) RCO (’160 only) tTLH tTHL 10 CL = 50 pF CL = 50 pF POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TA = 25°C MIN MAX CD54HC160 CD54HC162 MIN UNIT MAX 31 48 31 48 31 48 31 48 20 31 20 31 36 54 36 54 13 19 13 19 ns ns ns ns ns CD54HC160, CD54HC162 BCD SYNCHRONOUS DECADE COUNTERS SCHS301 – JUNE 2000 PARAMETER MEASUREMENT INFORMATION VCC Test Point From Output Under Test PARAMETER S1 ten RL = 1 kΩ tdis CL (see Note A) S2 S1 S2 tPZH Open Closed tPZL Closed Open tPHZ Open Closed tPLZ Closed Open Open Open tpd or tt LOAD CIRCUIT VCC Input 50% VCC 50% VCC tPLH tPHL VCC CLR Input 50% VCC 0V trec 0V In-Phase Output 50% VCC 10% 90% VCC VOH 50% VCC 10% V OL tf 90% tr tPHL Out-of-Phase Output 90% 50% VCC 10% 50% VCC 10% 90% VOH VOL 90% Output Control VCC 50% VCC 50% VCC 0V tr VOLTAGE WAVEFORMS PROPAGATION DELAY AND OUTPUT TRANSITION TIMES 50% 10% 0V VOLTAGE WAVEFORMS RECOVERY TIME tPLH tf Input 50% VCC CLK 90% VCC 50% VCC 10% 0 V tr tf VOLTAGE WAVEFORM INPUT RISE AND FALL TIMES tPZL Output Waveform 1 (See Note B) tPLZ ≈VCC 50% 10% tPZH Output Waveform 2 (See Note B) ≈VCC VOL tPHZ 50% VCC 90% VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES FOR 3-STATE OUTPUTS NOTES: A. CL includes probe and test-fixture capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns. D. The outputs are measured one at a time with one input transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 PACKAGE OPTION ADDENDUM www.ti.com 30-Mar-2005 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty CD54HC160F3A OBSOLETE CDIP J 16 TBD Call TI Call TI CD54HC162F3A OBSOLETE CDIP J 16 TBD Call TI Call TI Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. 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