ETC SN54LS490

SN54LS490, SN74LS490
DUAL 4-BIT DECADE COUNTERS
SDLS125A – OCTOBER 1976 – REVISED JULY 1998
D
D
D
D
1CLK
1CLR
1QA
1SET9
1QB
1QC
1QD
GND
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
VCC
2CLK
2CLR
2QA
2SET9
2QB
2QC
2QD
SN54LS490 . . . FK PACKAGE
(TOP VIEW)
description
1QA
1SET9
NC
1QB
1QC
4
3 2 1 20 19
18
5
17
6
16
7
15
8
14
9 10 11 12 13
2CLR
2QA
NC
2SET9
2QB
1QD
GND
NC
2QD
2QC
Each of these monolithic circuits contains eight
master-slave flip-flops and additional gating to
implement two individual 4-bit decade counters in
a single package. Each decade counter has
individual clock (1CLK, 2CLK), clear (1CLR,
2CLR), and set-to-9 (1SET9, 2SET9) inputs. BCD
count sequences of any length up to
divide-by-100 can be implemented with a single
’LS490 device. Buffering on each output is
provided to significantly reduce susceptibility to
collector commutation. All inputs are diode
clamped to reduce the effects of line ringing. The
counters have parallel outputs from each counter
stage so that submultiples of the input count
frequency are available for system timing signals.
2CLK
D
SN54LS490 . . . J OR W PACKAGE
SN74LS490 . . . D OR N PACKAGE
(TOP VIEW)
Dual Versions of the SN54LS90 and
SN74LS90 Counters
Individual Clock, Direct Clear, and Set-to-9
Inputs for Each Decade Counter
Dual Counters Can Significantly Improve
System Densities as Package Count Can
Be Reduced by 50%
Maximum Count Frequency of
25 MHz . . . 35 MHz Typical
Buffered Outputs Reduce Possibility of
Collector Commutation
Package Options Include Plastic
Small-Outline (D) Packages, Ceramic Flat
(W) Packages, Ceramic Chip Carriers (FK),
and Standard Plastic (N) and Ceramic (J)
DIPs
1CLR
1CLK
NC
V CC
D
NC – No internal connection
The SN54LS490 is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74LS490 is characterized for use in industrial systems operating from 0°C to 70°C.
CLEAR/SET-TO-9 FUNCTION TABLE
(each counter)
INPUTS
CLR
SET9
OUTPUTS
QA
QB
QC
QD
H
L
L
L
L
L
L
H
H
L
L
H
L
L
Count
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  1998, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
SN54LS490, SN74LS490
DUAL 4-BIT DECADE COUNTERS
SDLS125A – OCTOBER 1976 – REVISED JULY 1998
BCD COUNT SEQUENCE
(each counter)
COUNT
OUTPUTS
QD
QC
QB
0
L
L
L
QA
L
1
L
L
L
H
2
L
L
H
L
3
L
L
H
H
4
L
H
L
L
5
L
H
L
H
6
L
H
H
L
7
L
H
H
H
8
H
L
L
L
9
H
L
L
H
logic symbol†
CTRDIV10
1CLR
1SET9
1CLK
2
0
CT=0
4
CT=9
1
5
CT
6
+
3
2CLR
2SET9
2CLK
7
13
14
11
12
10
15
9
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the D, J, N, and W packages.
2
3
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1QA
1QB
1QC
1QD
2QA
2QB
2QC
2QD
SN54LS490, SN74LS490
DUAL 4-BIT DECADE COUNTERS
SDLS125A – OCTOBER 1976 – REVISED JULY 1998
schematics of inputs and outputs
EQUIVALENT OF
EACH CLK INPUT
VCC
EQUIVALENT OF
EACH CLR AND SET9 INPUT
VCC
43 kΩ NOM
Input
TYPICAL OF
ALL OUTPUTS
VCC
18 kΩ NOM
120 Ω NOM
Input
Output
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3
SN54LS490, SN74LS490
DUAL 4-BIT DECADE COUNTERS
SDLS125A – OCTOBER 1976 – REVISED JULY 1998
logic diagram (each counter)
4, 12
SET9
S
CLK
1, 15
3, 13
QA
T
R
5, 11
QB
T
R
6, 10
QC
T
R
S
T
R
CLR
2, 14
Pin numbers shown are for the D, J, N, and W packages.
4
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
7, 9
QD
SN54LS490, SN74LS490
DUAL 4-BIT DECADE COUNTERS
SDLS125A – OCTOBER 1976 – REVISED JULY 1998
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Clear and set-to-9 voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Clock input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 5.5 V
Package thermal impedance, θJA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. Voltage values are with respect to network ground terminal.
2. The package thermal impedance is calculated in accordance with JESD 51, except for through-hole packages, which use a trace
length of zero.
recommended operating conditions
SN54LS490
SN74LS490
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.75
5
5.25
UNIT
VCC
IOH
Supply voltage
High-level output current
–400
–400
µA
IOL
fcount
Low-level output current
4
8
mA
25
MHz
tw
tsu
Pulse width (any input)
Count frequency
0
Clear or set-to-9 inactive-state setup time
TA
Operating free-air temperature
–55
‡ The arrow (↓) indicates that the falling edge of the clock pulse is used for reference.
POST OFFICE BOX 655303
25
20
25↓‡
• DALLAS, TEXAS 75265
0
20
25↓‡
125
0
V
ns
ns
70
°C
5
SN54LS490, SN74LS490
DUAL 4-BIT DECADE COUNTERS
SDLS125A – OCTOBER 1976 – REVISED JULY 1998
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
TEST CONDITIONS†
PARAMETER
VIH
VIL
High-level input voltage
VIK
Input clamp voltage
VOH
High-level output voltage
VOL
Low level output voltage
Low-level
II
Input current
at maximum
input voltage
IIH
High-level
g
input current
CLK
IIL
Low-level
input current
CLK
IOS§
ICC
SN74LS490
TYP‡
MAX
MIN
2
2
Low-level input voltage
VCC = MIN,
II = –18 mA
VCC = MIN, VIH = 2 V,
VIL = VILmax
2.5
SN74LS490
TYP‡
MAX
MIN
V
0.7
0.8
V
–1.5
–1.5
V
3.4
2.7
3.4
V
VCC = MIN,
VIH = 2 V
V,
VIL = VILmax
IOL = 4 mA
CLR, SET9
VCC = MAX,
VI = 7 V
0.1
0.1
CLK
VCC = MAX,
VI = 5.5 V
0.2
0.2
VCC = MAX
MAX,
VI = 2
2.7
7V
VCC = MAX
MAX,
VI = 0
0.4
4V
CLR, SET9
CLR, SET9
Short-circuit output current
0.25
0.4
0.25
0.4
0.35
0.5
V
IOL = 8 mA
VCC = MAX
VCC = MAX,
UNIT
mA
–20
20
20
100
100
–0.4
–0.4
–1.6
–1.6
–100
–20
–100
µA
mA
mA
Supply current
See Note 3
15
26
15
26
mA
† For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
‡ All typical values are at VCC = 5 V, TA = 25°C.
§ Not more than one output should be shorted at a time, and duration of the short circuit should not exceed one second.
NOTE 3: ICC is measured with all outputs open, both CLR inputs grounded following momentary connection to 4.5 V, and all other inputs
grounded.
switching characteristics, VCC = 5 V, TA = 25°C (see Figures 1 and 2)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
fmax
CLK
QA
tPLH
CL = 15 pF,
pF
RL = 2 kΩ
CLK
QB,
B QD
CL = 15 pF,
pF
RL = 2 kΩ
CLK
QC
CL = 15 pF,
pF
RL = 2 kΩ
CLR
Any
CL = 15 pF,
RL = 2 kΩ
CL = 15 pF,
pF
RL = 2 kΩ
tPHL
tPHL
tPLH
tPHL
6
RL = 2 kΩ
QA
tPHL
tPLH
CL = 15 pF,
CLK
tPHL
tPLH
TEST CONDITIONS
SET9
QA, QD
QB, QC
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MIN
TYP
25
35
MAX
UNIT
MHz
12
20
13
20
24
39
26
39
32
54
36
54
24
39
24
39
20
36
ns
ns
ns
ns
ns
SN54LS490, SN74LS490
DUAL 4-BIT DECADE COUNTERS
SDLS125A – OCTOBER 1976 – REVISED JULY 1998
PARAMETER MEASUREMENT INFORMATION
3V
SET9
1.3 V
1.3 V
0V
tsu
3V
1.3 V
CLR
1.3 V
0V
tw(clock)
tsu
3V
CLK
1.3 V
1.3 V
1.3 V
1.3 V
0V
tPLH
tPLH
(Measure at
tn + 1)
tPHL
tPHL
(Measure at
tn + 2)
VOH
QA
1.3 V
1.3 V
1.3 V
1.3 V
VOL
tPHL
tPLH
(Measure at
tn + 2)
tPHL
tPHL
(Measure at
tn + 4)
tPHL
VOH
QD
1.3 V
1.3 V
1.3 V
1.3 V
VOL
tPHL
tPLH
(Measure at
tn + 4)
tPHL
tPLH
(Measure at
tn + 8)
tPHL
VOH
QC
1.3 V
1.3 V
1.3 V
1.3 V
VOL
tPLH
tPHL
(Measure at
tn + 8)
tPHL
tPHL
(Measure at
tn + 10)
tPHL
VOH
QB
1.3 V
1.3 V
1.3 V
1.3 V
VOL
NOTE A: Input pulses are supplied by a generator having the following characteristics: tr ≤ 15 ns, tf ≤ 6 ns, PRR ≤ 1 MHz, duty cycle = 50%,
ZO ≈ 50 Ω.
Figure 1. Voltage Waveforms
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
7
SN54LS490, SN74LS490
DUAL 4-BIT DECADE COUNTERS
SDLS125A – OCTOBER 1976 – REVISED JULY 1998
PARAMETER MEASUREMENT INFORMATION
VCC
Test
Point
VCC
VCC
RL
From Output
Under Test
CL
(see Note A)
From Output
Under Test
RL
S1
From Output
Under Test
CL
(see Note A)
RL
(see Note B)
Test
Point
(see Note B)
5 kΩ
Test
Point
CL
(see Note A)
LOAD CIRCUIT FOR
BI-STATE
TOTEM-POLE OUTPUTS
High-Level
Pulse
1.3 V
S2
LOAD CIRCUIT
FOR OPEN-COLLECTOR OUTPUTS
LOAD CIRCUIT
FOR 3-STATE OUTPUTS
3V
Timing
Input
1.3 V
1.3 V
0V
tw
Low-Level
Pulse
1.3 V
th
tsu
3V
Data
Input
1.3 V
1.3 V
1.3 V
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATIONS
3V
Input
1.3 V
tPHL
tPLH
VOH
1.3 V
tPHL
Out-of-Phase
Output
(see Note F)
1.3 V
1.3 V
Waveform 1
S2 Open
(see Notes C
and F)
VOL
tPLH
VOH
1.3 V
1.3 V
VOL
1.3 V
0V
tPZL
1.3 V
0V
In-Phase
Output
(see Note F)
3V
Output
Control
(low-level
enabling)
tPLZ
[1.5 V
1.3 V
VOL + 0.3 V
tPHZ
Waveform 2
S2 Closed
(see Notes C
and F)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
tPZH
1.3 V
VOH – 0.3 V
[1.5 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
NOTES: A. CL includes probe and jig capacitance.
B. All diodes are 1N3064 or equivalent.
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
D. In the examples above, the phase relationships between inputs and outputs have been chosen arbitrarily.
E. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO ≈ 50 Ω, tr ≤ 15 ns, tf ≤ 6 ns.
F. S1 and S2 are closed for tPLH, tPHL, tPHZ, and tPLZ; S1 is open and S2 is closed for tPZH; S1 is closed and S2 is open for tPZL.
G. The outputs are measured one at a time with one input transition per measurement.
Figure 2. Load Circuits and Voltage Waveforms
8
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright  1998, Texas Instruments Incorporated
54厅4
fAMlllES Of COMPATI8lE nl CIRCUITS
PIN ASSIGNMENTS
主
(主OPVIEWS)
~
品
4-BIT-S lI CE EXPANDABLE CONTROl ElEMENTS
川存先是川
482
j )t JTPUI 三
CASCADABLE TO N-BITS
SN54S 482 (J)
SN74S48 2 (J , N)
See Bipolar Microcomputer Components Data Book , lCC4270
DUAl DECADE COUNTERS
~
10..
OUl
Vcc
C Lt)C IIt C‘筐'‘'‘
h川
提1
109
固
OUT~TS
_ _一-户、--去。.自lc
200
‘
490
CtOC<<.
' a .捉
. T‘ ' 0
. 'Oc句) .
-国-气，.-----'
ClEA掬臼H
PUT
OH。
ooT盹JT‘
SN54490υ ， W)
SN74490 (J , N)
SN54lS490(J , W) SN74l S490(J.N)
See page 7 -520
4-BY4
REGISτER
670
,
FllES
3 -S TATE OUTPUTS
SIMUL TANEOUS READ/WRITE
EXPANDABLE TO 1024 WORDS
0..1 ..
SN54ιS670 (J. W)
See pa伊 7-526
TEXAS INSTRUMENTS
INζORPORATEO
SN74LS670 (J. N)
.•
5-77
南
品种
产
代号
448
~
c.o
晶名
称
STD
ττ"L
HTTL
Lï口，
STTL
四总线收发器 (OC ，三方向传输〉
LS
AS
AI.S
TTL
TTL
TIL
FAST
4000
HC
Hα、
CMQS
AC
ACT 页码
A
(37 7)
A
(378)
449
•
四总线收~器〈嚣，双向传输.原码〉
465
八缓冲嚣(嚣，原码〉
A
A
(379)
466
八缓冲嚣(3S，反码〉
A
A
(379)
467
双四缓冲器(3S，原码〉
A
A
(380)
468
双四缓冲器(3S，反码〉
A
A
(380)
484
BCD-二避制代码转换器
A
(38 1)
485
二迸制-ßCi)代码转换摞
A
(38 1)
4tO
双 4 位十进制计鼓器
518
8 位恒等比校器 (QC)
A
(383)
5J9
8 位恒等比校嚣 (OC)
A
(383)
520
8 位恒等比较辘〈反码.阁属〉
A
521
8 位恒等比较器〈反码.图腾〉
A
522
8 位恒等比较部〈反码， OC)
A
524
8 位可寄存比校器〈可编程，3S， JiO ， OC 输出〉
A
(385)
525
16 位状态可编程计数器/分颜器
A
(386)
526
熔断型可编程 16 位恒等比较器〈反相输入〉
A
(38 7)
527
馆断型可编程 8 位恒等比较器和 4 位比较器〈反栩输出〉
A
(388)
528
熔断型可编程 12 位恒等比较器
A
(389)
533
八 D 型透明锁存嚣
A
A
A
A
A
A
A
(390)
534
八 D 型上升黯触发器(3S.反~I>
A
A
A
A
A
A
A
(39 1)
537
4 线 -10 线详码器/多跻分配器
538
3 线-8 线译码器/多路分配器
A
A
A
.
.
A
(382)
A
A
A
(384)
A
A
(380
(384)
A
(392)
A
(39 4)
XI6
...
lOGIC PRODUCTS
COUNTER
54/74LS490
Dual BCD Decade Ripple Counter
The counters are triggered by the HIGH-toLOW transitlon of the Clock (CP) inputs.
No external connections are required t。
get the full BCD (8421) decade counting
scheme from the counters. The counter
。 utputs are internally connected as clocks
or decoded inputs to succeeding stages.
Since this is a ripple type counter , the outputs do not change synchronously and
should not be used for high speed address
decoding.
户uv-RJV
The '490 is a Dual BCD Decade Ripple
Counter with separate Clock , Master Set ,
and Master Reset inputs to each counter.
The operation of each half of the '490 is
the same as the '90 used in the BCD
decade mode.
TYPICAL SUPPLY CURRENT
(Total)
T·VERFH
-L-MH
SE-''B·-RJW
AHVAM-
15mA
COMMERCIAL RANGES
+70 oC
PACKAGES
DESCRIPTION
AH-M 啊
• Two BCD decade
TYPE
counters
74LS490
• Asynchronous Master Set
(set-to-9)
• Asynchronous 'Master
Reset (clear)
ORDERING CODE
V CC =5V 主 5%;T A =OOCto
MI Ll TARY RANGES
TA = - 55 0 C to + 125 0 C
V CC =5V 主 10%;
N74LS490N
Plastic DIP
Ceramic DIP
S54LS490F
Flatpack
S54LS490W
INPUT AND OUTPUT LOADING AND FAN.OUT TABLE
NOTE
Where
PINS
54/74LS
CP
4LSul
MR , MS
1LSul
0 0-0 3
10LSul
a 54/74LS unit load (LSul) is
20μA
IIH and - O4mA IIL
,
The Master Set (MS) and Master Reset
(MR) are asynchronous active-HIGH inputs. The HIGH MR input overrides the
clock and clears the associated 4 bits of
the counter. The HIGH MS input overrides
the clock and MR inputs and sets the
associated 4 bits to nine (HLLH).
PIN CONFIGURATION
LOGIC SYMBOL (IEEE/IEC)
LOGIC SYMBOL
4,12
MS
1,15
CP
饨'LS41O
唾
,
4-522
MR
Qo
。1
。2
。3
2,14
3,13
5,11
11 ,10
7,9
GVcNcD zPIn 18
-Pln 8
.
'
l OGl C PRODUCTS
541 74LS490
COUNTER
LOGIC DIAGRAM
MODE SELECTION-FUNCTION
TABLE FOA 1/2 THE '490
RESET/SET
tNPUTS
OUTPUTS
乌-LH
MR
H
L
L
H
L
L
H=HIGH voltage level
L =LOW voltage level
X =Don't care
BCD COUNT SEQUENCE
FOA 1/2 THE '490
a'..' .E.‘.,,
,.‘
'。
(3,13)
...
。。
(8,10)
..
1,, i
。2
。
..
.
nu
L
H
L
H
L
H
L
H
L
H
2
3
4
5
() • PIn Number.
vcc ·网n 18
。 NO-Pln
。。
8
6
7
8
9
NOTE
Output QO connected
ABSOιUTE
MAXIMUM AATINGS
Supply voltage
V 'N
Input voltage
L
H
H
L
L
H
H
L
L
。2
Q3
L
L
L
L
H
H
H
H
L
L
L
L
L
L
L
L
L
L
H
H
input CP1'
(Over operating free-alr temperature range unless ~therwlse noted.)
54LS
74LS
7.0
7.0
V
-0.5 to + 7.0
-0.5 to + 7.0
v
mA
PARAMETER
Vcc
10
。'L
I'N
Input current
v。υT
Voltage applied to output In HIGH output state
Ope r'ating free-alr temperature range
NOT-E
V'N IImlted to + 5.5V on CP Input only.
TA
UNtT
- 30 to + 1
- 30 to + 1
- 0.5 to + Vcc
-0.5 to + Vcc
v
- 55 to + 125
o to 70
.C
」
'
RECOMMENDED OPEAATING CONDITIONS
54174LS
PARAMETER
,
v∞
Supply voltage
V 'H
HIGH-Ievel input voltage
V 'L
LOW-Ievel Input voltage
I'K
Input clamp current
10H
HIGH-Ievel output current
IOL
LOW-Ievel output current
~-
TA
ee-alr temperature
。 peratlng fr
一一生一一
OUTPUTS
COUNT
Mln
Nom
Max
MiI
4.5
5.0
5.5
Com'l
4.75
5.0
5.25
2.0
UNIT
v
v
v
v
MiI
+0.7
Com'l
+0.8
V
-18
mA
-4∞
萨A
MII
4
mA
Com'l
8
"、A
MII
Com'l
, 55
。
+125
.C
70
.C
4.523
LOGIC PRODUCTS
,'
COUNTER
541 74LS490
DC ELECTRICAL CHARACTERISTICS (Over recommended operating free.air temperature range unless otherwise noted.)
VOH
Vcc=MIN , V'H=MIN , V'L=MAX ,
10H= MAX
HIGH.level output voltage
VOL
LOW.level output voltage
V'K
Input clamp voltage
Vcc = MIN , V'H = MIN ,
V'L= MAX
10L= MAX
105
Icc
M iI
2.5
3.4
Com'l
2.7
Vcc = MAX
3.4
V
Mil
0.25
0.4
V
Com'l
0.35
0.5
V
74LS
0.25
0.4
V
V
V,= 7.0V
MR , MS inputs
0.1
mA
V,= 5.5V
CP input
0.2
mA
MR , MS inputs
20
μA
Vcc = MAX , V ,= 2.7V
HIGH.level input current
Vcc = MAX , V ， =ωv
LOW.level input current
Short.circuit output
current 3
Supply current 4 (total)
Max
V
Vcc = MIN , 1,= I'K
Input current at maximum
input voltage
I'L
54/74 LS490
Typ 2
-1.5
IOL=4mA
I'H
Mln
TEST CONDITIONS1
PARAMETER
CP input
100
μA
MR , MS inputs
-0.4
付lA
CP input
-1.6
问lA
-100
mA
26
mA
Vcc = MAX
-20
15
Vcc = MAX
NOTE5
1. For conditions shown as M'N or MAX , use the appropriate va'ue specilied under recommended operating conditions lor the applicable type
2. AII typica' values are at VCC =5V , TA=25 C.
3. 105 is tested with VOUT = + 0.5V and VCC =VCC MAX + 0.5V. Not more than one output should be shorted at a time and duration 01 the short circuit should not exceed one
second
4. Measure 'cc with all outputs open , MR inputs grounded lollowing momentary connection to 4.5V , and all other inputs grounded
0
AC CHARACTERISTICS TA=25 C, Vcc =5.0V
0
54LS/74LS
TEs..T CONDITIONS
PARAMETER
f MAX
t pLH
t PHL
t pLH
t pHL
t pLH
t PHL
Waveform 1
CP input count frequency
Propagation delay
CP to 0 0
Propagation delay
CP to 0 1 or 0 3
Propagation delay
CP to O2
Propagation delay , MR to 0
CL = 15pF, RL= 2kO
Mln
Max
35
UNIT
MHz
Waveform 1
20
20
ns
Waveform 1
39
39
n5
Waveform 1
54
54
ns
Waveform 2
39
t pHL
39
Propagation delay
t PLH
Waveforms 2 & 3
36
t PHL
MS to 0
NOTE
Per industry convention , IMAX is the worst case value 01 the maximum device operating Irequency with no constraints on 勺，勺， pulse width or duty cycle
ns
n5
AC SETUP REaUIREMENTS TA=25 C, Vcc =5.0V
0
'
PARAMETER
TEST CONDITIONS
54LS/74LS
Min
Max
UNIT
tw
CP pulse width
Waveform 1
20
ns
tw
MR pulse width
Waveform 2
20
ns
tw
MS
Waveforms 2 & 3
20
ns
trec
Recovery time , MR to CP
Waveform 2
25
ns
trec
Recovery time , MS to CP
Waveforms 2 & 3
25
ns
4.524
pulse 咀dth
,
lOGIC PRODUCTS
54/74LS490
COUNTER
AC WAVEFORMS
MA OA MS
CP
CP
。
。
W8V8form 1
VM • 1. 3V lor 54LS/74LS
Th e number 01 Clock Pul.e. required between the tPHL and tpLH me..urements
can be determined Irom the appropriate Truth Tables
MS
CP
。0.
03
4
W8V8form 3
TEST CIRCUITS AND WAVEFORMS
TEST CIRCUIT FOR 54174 TOTEM.POLE OUTPUTS
INPUT PULSE DEFINITIONS
tw
VCC
AMP(V)
VCC
OV
,
tTLH(t。
AMP(的
o
'
-.
DEFINITIONS
RL
CL
=Load resistor to VCC; see AC CHARACTERISTl CS for value
=Load capacitance includes jig and probe capacitance; see AC CHARACTERIS.
T1 CS for value.
RT = Termination resistance should be equal to ZOUT of Pulse Generators
o Diodes are 1N916, 1N3064, or equivalen t.
tTLH , tTHL Values should be less than or equal to the table ehtries
,
OV
=1.3V lor 54LS/74LS; VM =1.5V for all other TTL families
INPUT PULSE AEOUIAEMENTS
FAMILY
=
"
tw
VM
Amplltude
A.p. "at.
Pul.. Wldth
tTLH
54/74
3.0V
1MHz
织)O ns
7ns
7ns
54LS/74LS
3.0V
1MHz
5∞ ns
15ns
6ns
54S/74S
3.0V
1MHz
500ns
2.5ns I 2.5ns
tTHL
一一一一一
.
4-525
SN54/74LS490
DUAL DECADE COUNTER
The SN54 / 74LS490 contains a pair of high-speed 4-stage ripple counters.
Each half of the SN54 / 74LS490 has individual Clock, Master Reset and Master Set (Preset 9) inputs. Each section counts in the 8, 4, 2, 1 BCD code.
•
•
•
•
Dual Version of SN54 / 74LS490
Individual Asynchronous Clear and Preset to 9 for Each Counter
Count Frequency — Typically 65 MHz
Input Clamp Diodes Limit High-Speed Termination Effects
DUAL DECADE COUNTER
LOW POWER SCHOTTKY
CONNECTION DIAGRAM DIP (TOP VIEW)
J SUFFIX
CERAMIC
CASE 620-09
16
1
PIN NAMES
MS
MR
CP
Q0 – Q3
N SUFFIX
PLASTIC
CASE 648-08
16
1
LOADING (Note a)
Master Set (Set to 9) Input
Master Reset
Clock Input (Active LOW Going Edge)
Counter Outputs (Note b)
HIGH
LOW
0.5 U.L.
0.5 U.L.
1.5 U.L.
10 U.L.
0.25 U.L.
0.25 U.L.
1.5 U.L.
5 (2.5) U.L.
16
1
ORDERING INFORMATION
NOTES:
a) 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW.
b) The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial
(74) Temperature Ranges.
SN54LSXXXJ
SN74LSXXXN
SN74LSXXXD
LOGIC DIAGRAM (ONE HALF SHOWN)
OUTPUTS
Ceramic
Plastic
SOIC
TRUTH TABLE
D SUFFIX
SOIC
CASE 751B-03
FAST AND LS TTL DATA
5-563
COUNT
Q3
Q2
Q1
Q0
0
1
2
L
L
L
L
L
L
L
L
H
L
H
L
3
4
5
L
L
L
L
H
H
H
L
L
H
L
H
6
7
8
9
L
L
H
H
H
H
L
L
H
H
L
L
L
H
L
H
SN54 / 74LS490
GUARANTEED OPERATING RANGES
Symbol
Parameter
Min
Typ
Max
Unit
VCC
Supply Voltage
54
74
4.5
4.75
5.0
5.0
5.5
5.25
V
TA
Operating Ambient Temperature Range
54
74
– 55
0
25
25
125
70
°C
IOH
Output Current — High
54, 74
– 0.4
mA
IOL
Output Current — Low
54
74
4.0
8.0
mA
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Limits
Symbol
Min
Parameter
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
VIK
Input Clamp Diode Voltage
VOH
Output HIGH Voltage
VOL
Output LOW Voltage
IIH
Input HIGH Current
IIL
Input LOW Current
IOS
Short Circuit Current (Note 1)
ICC
Power Supply Current
Typ
Max
Unit
2.0
54
0.7
74
0.8
– 0.65
– 1.5
Test Conditions
V
Guaranteed Input HIGH Voltage for
All Inputs
V
Guaranteed Input LOW Voltage for
All Inputs
V
VCC = MIN, IIN = – 18 mA
54
2.5
3.5
V
74
2.7
3.5
V
VCC = MIN, IOH = MAX, VIN = VIH
or VIL per Truth Table
VCC = VCC MIN,
VIN = VIL or VIH
per Truth Table
54, 74
0.25
0.4
V
IOL = 4.0 mA
74
0.35
0.5
V
IOL = 8.0 mA
20
µA
VCC = MAX, VIN = 2.7 V
0.1
mA
VCC = MAX, VIN = 7.0 V
mA
VCC = MAX, VIN = 0.4 V
– 100
mA
VCC = MAX
26
mA
VCC = MAX
Max
Unit
MS, MR
– 0.4
Clock
–1.6
– 20
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
AC SET-UP REQUIREMENTS (TA = 25°C, VCC = 5.0 V)
Limits
Symbol
Parameter
Min
Typ
tW
Any Pulse Width
20
ns
ts
MR or MS to Setup Time
25
ns
FAST AND LS TTL DATA
5-564
Test Conditions
VCC = 5.0 V
SN54/74LS490
AC CHARACTERISTICS (TA = 25°C)
Limits
Symbol
Parameter
Min
Typ
25
35
fMAX
Maximum Clock Frequency
tPLH
tPHL
Propagation Delay, CP to Q0
12
13
tPLH
tPHL
Propagation Delay, CP to Q1 or Q3
tPLH
tPHL
Unit
Max
Test Conditions
MHz
Figure 1
20
20
ns
Figure 1
24
26
39
39
ns
Figure 3
Propagation Delay, CP to Q2
32
36
54
54
ns
Figure 2
tPHL
Propagation Delay, MR to Output
24
39
ns
Figure 2
tPLH
tPHL
Propagation Delay, MS to Output
24
20
39
36
ns
Figure 2
VCC = 5.0 V,
CL = 15 pF
AC WAVEFORMS
Figure 1
Figure 2
Figure 3
*The number of Clock Pulses required between the tPHL and tPLH measurements can be determined from the Truth Table.
FAST AND LS TTL DATA
5-565
Case 751B-03 D Suffix
16-Pin Plastic
SO-16
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FAST AND LS TTL DATA
5-566
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◊
FAST AND LS TTL DATA
5-567