INTERSIL X3102V28

X3102
®
Data Sheet
December 22, 2004
3 Cell Li-Ion Battery Protection and
Monitor IC
Features
The X3102 is a protection and monitor IC for use in battery
packs consisting of 3 series Lithium-Ion battery cells. The
device provides internal over-charge, over-discharge, and
overcurrent protection circuitry, internal EEPROM memory,
an internal voltage regulator, and internal drive circuitry for
external FET devices that control cell charge, discharge, and
cell voltage balancing.
Over-charge, over-discharge, and overcurrent thresholds
reside in an internal EEPROM memory register and are
selected independently via software using a 3MHz SPI serial
interface. Detection and time-out delays can also be
individually varied using external capacitors.
Using an internal analog multiplexer, the X3102 allows
battery parameters such as cell voltage and current (using a
sense resistor) to be monitored externally by a separate
microcontroller with A/D converter. Software on this
microcontroller implements gas gauge and cell balancing
functionality in software.
The X3102 contains a current sense amplifier. Selectable
gains of 10, 25, 80 and 160 allow an external 10 bit A/D
converter to achieve better resolution than a more expensive
14 bit converter.
An internal 4kbit EEPROM memory featuring IDLock™,
allows the designer to partition and “lock in” written battery
cell/pack data.
The X3102 is housed in a 28 Pin TSSOP package.
FN8246.0
• Software Selectable Protection Levels and Variable
Protect Detection/Release Times
• Integrated FET Drive Circuitry
• Cell Voltage and Current Monitoring
• 0.5% Accurate Voltage Regulator
• Integrated 4kbit EEPROM
• Flexible Power Management with 1µA Sleep Mode
• Cell Balancing Control
Benefit
• Optimize protection for chosen cells to allow
maximum use of pack capacity.
• Reduce component count and cost
• Simplify implementation of gas gauge
• Accurate voltage and current measurements
• Record battery history to optimize gas gauge, track pack
failures and monitor system use
• Reduce power to extend battery life
• Increase battery capacity and improve cycle life battery life
Ordering Information
PART
NUMBER
X3102V28
VCC LIMITS
TEMP. RANGE
(°C)
6V to 24V
-20 to +70
PACKAGE
28 Ld TSSOP
Pinout
X3102 (TSSOP)
TOP VIEW
VCELL1
1
28
VCC
CB1
2
27
RGP
VCELL2
3
26
RGC
CB2
4
25
RGO
VCELL3
5
24
UVP/OCP
CB3
6
23
OVP/LMON
7
22
CS
8
21
SCK
9
20
10
19
11
18
12
17
AS1
UVT
13
16
AS0
OCT
14
15
AO
VSS
NC
VSS
VCS1
VCS2
OVT
1
SO
SI
AS2
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-352-6832 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2004. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
X3102
Functional Diagram
RGP RGC
VCC
CB1
CB2
VCELL3
CB3
UVP/OCP
Over-charge
Over-discharge
Protection
Sense
Circuits
VSS
NC
Protection
Sample Rate
Timer
AS0
AS1
Analog
MUX
VCS1
VCS2
Protection Circuit
Timing Control
& Configuration
OVT
UVT
AS2
AO
Internal Voltage Regulator
Power-On reset &
Status Register
S0
4 kbit
EEPROM
Overcurrent
Protection &
Current Sense
VSS
OVP/LMON
FET Control
Circuitry
5VDC
Regulator
VCELL1
VCELL2
RGO
Configuration
Register
Control
Register
SPI
I/F
SCK
CS
SI
OCT
Pin Names
PIN
SYMBOL
DESCRIPTION
1
VCELL1
Battery cell 1 voltage input. This pin is used to monitor the voltage of this battery cell internally. The voltage of an individual
cell can also be monitored externally at pin AO.
The X3102 monitors 3 battery cells.
2
CB1
Cell balancing FET control output 1. This output is used to switch an external FET in order to perform cell voltage balancing
control. This function can be used to adjust an individual cell voltage (e.g., during cell charging). CB1 can be driven high (Vcc)
or low (Vss) to switch the external FET ON/OFF.
3
VCELL2
Battery cell 2 voltage. This pin is used to monitor the voltage of this battery cell internally. The voltage of an individual cell can
also be monitored externally at pin AO.
The X3102 monitors 3 battery cells.
4
CB2
Cell balancing FET control output 2. This output is used to switch an external FET in order to perform cell voltage balancing
control. This function can be used to adjust individual cell voltages (e.g., during cell charging). CB2 can be driven high (Vcc) or
low (Vss) to switch the external FET ON/OFF.
5
VCELL3
Battery cell 3 voltage. This pin is used to monitor the voltage of each battery cell internally. The voltage of an individual cell
can also be monitored externally at pin AO.
The X3102 monitors 3 battery cells.
6
CB3
Cell balancing FET control output 3. This output is used to switch an external FET in order to perform cell voltage balancing
control. This function can be used to adjust an individual cell voltage (e.g., during cell charging). CB3 can be driven high (Vcc)
or low (Vss) to switch the external FET ON/OFF.
7
VSS
Ground.
8
NC
No Connect.
9
VSS
Ground.
10
VCS1
Current sense voltage pin 1. A sense resistor (RSENSE) is connected between VCS1 and VCS2 (Figure 1). RSENSE has a
resistance in the order of 20mΩ to 100mΩ, and is used to monitor current flowing through the battery terminals, and protect
against overcurrent conditions. The voltage at each end of RSENSE can also be monitored at pin AO.
11
VCS2
Current sense voltage pin 2. A sense resistor (RSENSE) is connected between VCS1 and VCS2 (Figure 1). RSENSE has a
resistance in the order of 20mΩ to 100mΩ, and is used to monitor current flowing through the battery terminals, and protect
against overcurrent conditions. The voltage at each end of RSENSE can also be monitored at pin AO.
12
OVT
Over-charge detect/release time input. This pin is used to control the delay time (TOV) associated with the detection of an
over-charge condition (See section “Over-charge Protection” on page 19).
13
UVT
Over-discharge detect/release time input. This pin is used to control the delay times associated with the detection (TUV) and
release (TUVR) of an over-discharge (undervoltage) condition (See section “Over-discharge Protection” on page 20).
14
OCT
Overcurrent detect/release time input. This pin is used to control the delay times associated with the detection (TOC) and
release (TOCR) of an overcurrent condition (See section “Overcurrent Protection” on page 23).
2
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December 22, 2004
X3102
Pin Names (Continued)
PIN
SYMBOL
DESCRIPTION
15
AO
Analog multiplexer output. The analog output pin is used to externally monitor various battery parameter voltages. The
voltages which can be monitored at AO (See section “Analog Multiplexer Selection” on page 25) are:
– Individual cell voltages
– Voltage across the current sense resistor (RSENSE). This voltage is amplified with a gain set by the user in the control register
(See section “Current Monitor Function” on page 25.)
The analog select pins AS0–AS2 select the desired voltage to be monitored on the AO pin.
16
AS0
Analog output select pin 0. These pins select which voltage is to be multiplexed to the output AO (See section “Sleep Control
(SLP)” on page 17 and section “Current Monitor Function” on page 25)
17
AS1
Analog output select pin 1. These pins select which voltage is to be multiplexed to the output AO (See section “Sleep Control
(SLP)” on page 17 and section “Current Monitor Function” on page 25)
18
AS2
Analog output select pin 2. These pins select which voltage is to be multiplexed to the output AO (See section “Sleep Control
(SLP)” on page 17 and section “Current Monitor Function” on page 25)
19
SI
Serial data input. SI is the serial data input pin. All opcodes, byte addresses, and data to be written to the device are input on
this pin.
20
SO
Serial data output. SO is a push/pull serial data output pin. During a read cycle, data is shifted out on this pin. Data is clocked
out by the falling edge of the serial clock. While CS is HIGH, SO will be in a High Impedance state.
Note: SI and SO may be tied together to form one line (SI/SO). In this case, all serial data communication with the X3102 is
undertaken over one I/O line. This is permitted ONLY if no simultaneous read/write operations occur.
21
SCK
Serial data clock input. The Serial Clock controls the serial bus timing for data input and output. Opcodes, addresses, or data
present on the SI pin are latched on the rising edge of the clock input, while data on the SO pin change after the falling edge
of the clock input.
22
CS
23
Chip select input pin. When CS is HIGH, the device is deselected and the SO output pin is at high impedance. CS LOW
enables the SPI serial bus.
OVP/LMON Over-charge Voltage Protection output/Load Monitor output. This one pin performs two functions depending upon the
present mode of operation of the X3102.
Over-charge Voltage Protection (OVP)
This pin controls the switching of the battery pack charge FET. This power FET is a P-channel device. As such, cell charge is
possible when OVP/LMON=VSS, and cell charge is prohibited when OVP/LMON=VCC. In this configuration the X3102 turns
off the charge voltage when the cells reach the over-charge limit. This prevents damage to the battery cells due to the
application of charging voltage for an extended period of time (See section “Over-charge Protection” on page 19).
Load Monitor (LMON)
In Overcurrent Protection mode, a small test current (7.5µA typ.) is passed out of this pin to sense the load resistance. The
measured load resistance determines whether or not the X3102 returns from an overcurrent protection mode (See section
“Overcurrent Protection” on page 23).
24
UVP/
OCP
Over-discharge protection output/Overcurrent protection output. Pin UVP/OCP controls the battery cell discharge via an
external power FET. This P-channel FET allows cell discharge when UVP/OCP=Vss, and prevents cell discharge when
UVP/OCP=Vcc. The X3102 turns the external power FET off when the X3102 detects either:
Over-discharge Protection (UVP)
In this case, pin 24 is referred to as “Over-discharge (Undervoltage) protection (UVP)” (See section “Over-discharge Protection”
on page 20). UVP/OCP turns off the FET to prevent damage to the battery cells by being discharged to excessively low
voltages.
Overcurrent protection (OCP)
In this case, pin 24 is referred to as “Overcurrent protection (OCP)” (See section “Overcurrent Protection” on page 23).
UVP/OCP turns off the FET to prevent damage to the battery pack caused by excessive current drain (e.g. as in the case of a
surge current resulting from a stalled disk drive).
25
RGO
Voltage regulator output pin. This pin is an input that connects to the collector of an external PNP transistor. The voltage at
this pin is the regulated output voltage, but it also provides the feedback voltage for the regulator and the operating voltage for
the device.
26
RGC
Voltage regulator control pin. This pin connects to the base of an external PNP transistor and controls the transistor turn on.
27
RGP
Voltage regulator protection pin. This pin is an input that connects to the emitter of an external PNP transistor and an external
current limit resistor and provides a current limit voltage.
28
VCC
Power supply. This pin is provides the voltage for FET control, regulator operation, and wake-up circuits.
3
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December 22, 2004
X3102
Absolute Maximum Ratings
Recommended Operating Conditions
Storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . .-55 to 125°C
Operating temperature. . . . . . . . . . . . . . . . . . . . . . . . . . .-40 to 85°C
DC output current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5mA
Lead temperature (soldering 10s) . . . . . . . . . . . . . . . . . . . . . . 300°C
Power supply voltage, VCC . . . . . . . . . . . . . . VSS-0.5 to VSS+27.0V
Cell voltage, VCELL. . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 6.75V
Terminal voltage, VTERM1 (Pins: SCK, SI, SO, CS, AS0, AS1,
AS2, VCS1, VCS2, OVT, UVT, OCT, AO) VSS-0.5 to VRGO + 0.5V
Terminal voltage, VTERM2 (VCELL1) . . . . .VSS-0.5 to VCC + 1.0V
Terminal voltage VTERM3, (all other pins) . .VSS-0.5 to VCC + 0.5V
Commercial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-20°C to +70°C
Supply Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6V to 24V
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
DC Electrical Specifications
Over the recommended operating conditions, unless otherwise specified
SYMBOL
PARAMETER
ILI
ILO
TEST CONDITIONS
MIN
MAX
UNITS
Input leakage current (SCK, SI, CS, ASO, AS1, AS2)
±10
µA
Output leakage current (SO)
±10
µA
VRGO x 0.3
V
VRGO x 0.7 VRGO + 0.3
V
VIL
Input LOW voltage (SCK, SI, CS, AS0, AS1, AS2)
(Note 1)
-0.3
VIH
Input HIGH voltage (SCK, SI, CS, AS0, AS1, AS2)
(Note 1)
VOL1
Output LOW voltage (SO)
IOL = 1.0mA
VOH1
Output HIGH voltage (SO)
IOH = -0.4mA
VOL2
Output LOW voltage
(UVP/OCP, OVP/LMON, CB1-CB4)
IOL = 100µA
VOH2
Output HIGH voltage
(UVP/OCP, OVP/LMON, CB1-CB4)
IOH = -20µA
VOL3
Output LOW voltage (RGC)
IOL = 2mA, RGP = VCC, RGO = 5V
VOH3
Output HIGH voltage (RGC)
IOH = -20µA, RGP = VCC – 4V, RGO = 5V
0.4
V
VRGO – 0.8
V
0.4
V
VCC – 0.4
V
0.4
V
VCC – 4.0
V
NOTE:
1. VIL min. and VIH max. are for reference only and are not 100% tested.
Operating Specifications Over the recommended operating conditions unless otherwise specified
SYMBOL
VRGO
DESCRIPTION
5V regulated voltage
ILMT
5VDC voltage regulator current limit
(Note 3)
CONDITION
MIN
TYP
(Note 2)
MAX
UNIT
5.5
V
On power up or at wake-up
4.5
After self-tuning (@ 10mA VRGO current; 25°C)
4.97
After self-tuning (@ 10mA VRGO current; 0-50°C) (Note 5)
4.95
5.02
After self-tuning (@ 50mA VRGO current) (Note 5)
4.90
5.00
4.99
RLMT = 10Ω
250
5.01
V
mA
Icc1
VCC supply current (1)
Normal operation
85
250
µA
Icc2
VCC supply current (2)
during nonvolatile EEPROM write
1.3
2.5
mA
Icc3
VCC supply current (3)
During EEPROM read SCK = 3.3MHz
0.9
1.2
mA
Icc4
VCC supply current (4)
Sleep mode
1
µA
Icc5
VCC supply current (5)
Monitor mode AN2, AN1, AN0 not equal to 0
600
µA
4
365
FN8246.0
December 22, 2004
X3102
Operating Specifications Over the recommended operating conditions unless otherwise specified (Continued)
SYMBOL
DESCRIPTION
CONDITION
VOV
Cell over-charge protection mode voltage VOV = 4.20V (VOV1, VOV0 = 0,0)
(Note 4) threshold
(Default in Boldface)
MIN
0°C to 50°C
VOV = 4.25V (VOV1, VOV0 = 0,1)
0°C to 50°C
VOV = 4.30V (VOV1, VOV0 = 1,0)
0°C to 50°C
VOV = 4.35V (VOV1, VOV0 = 1,1)
0°C to 50°C
VOVR
TOV
VUV
Cell over-discharge protection mode
(Note 4) (SLEEP) threshold.
(Default in Boldface)
VUVR
TUV
TUVR
4.275
V
4.15
4.25
4.15
4.325
V
4.20
4.30
V
4.2
4.375
V
4.25
4.35
V
4.25
4.425
V
4.30
4.40
V
Cell over-discharge detection time
Cell over-discharge release time
Load resistance overcurrent mode
release condition
5
1
s
2.35
V
VUV = 2.35V (VUV1, VUV0 = 0,1)
2.25
2.45
V
VUV = 2.45V (VUV1, VUV0 = 1,0)
2.35
2.55
V
VUV = 2.55V (VUV1, VUV0 = 1,1)
2.45
2.65
V
VUV +
0.6
V
CUV = 0.1µF
1
s
CUV = 200pF
2
ms
CUV = 0.1µF
7
ms
CUV = 200pF
100
µs
VOC = 0.075V (VOC1, VOC0 = 0,0)
VOC = 0.150V (VOC1, VOC0 = 1,1)
Overcurrent mode release time
V
2.15
0.050
0.100
0°C to 50°C 0.060
0.090
0.075
0.125
0°C to 50°C 0.085
0.115
0.100
0.150
0.110
0.140
0.125
0.175
0°C to 50°C 0.135
0.165
0°C to 50°C
Overcurrent mode detection time
VOV 0.20
VUV = 2.25V (VUV1, VUV0 = 0,0)
VOC = 0.125V (VOC1, VOC0 = 1,0)
ROCR
4.10
COV = 0.1µF
VOC = 0.100V (VOC1, VOC0 = 0,1)
TOCR
UNIT
Cell over-discharge protection mode
release threshold
VOC
Overcurrent mode detection
(Note 4) voltage
(Default in Boldface)
TOC
MAX
Cell over-charge protection mode release
voltage threshold
Cell over-charge detection time
TYP
(Note 2)
V
V
V
V
COC = 0.001µF
10
ms
COC = 200pF
2
ms
COC = 0.001µF
10
ms
COC = 200pF
2
ms
250
kΩ
Releases when OVP/LMON pin > 2.5V
FN8246.0
December 22, 2004
X3102
Operating Specifications Over the recommended operating conditions unless otherwise specified (Continued)
SYMBOL
VCE
MIN
TYP
(Note 2)
MAX
UNIT
VCE = 0.5V (VCE1, VCE0 = 0,0)
0.4
0.5
0.6
V
VCE = 0.8V (VCE1, VCE0 = 0,1)
0.7
0.8
0.9
V
VCE = 1.1V (VCE1, VCE0 = 1,0)
1
1.1
1.2
V
VCE = 1.4V (Vce1, VCE0 = 1,1)
1.3
1.4
1.5
V
(See Wake-up test circuit) 0°C to 50°C
8.5
9.5
11.2
V
7.5
8.8
10.5
V
DESCRIPTION
CONDITION
Cell charge threshold voltage
VSLR
X3102 wake-up voltage (For Vcc above
this voltage, the device wakes up)
VSLP
X3102 sleep voltage (For Vcc above this (See Sleep test circuit) 0°C to 50°C
voltage, the device cannot go to sleep)
NOTES:
2. Typical at 25°C.
3. See Figure 10 on page 21.
4. The default setting is set at the time of shipping, but may be changed by the user via changes in the configuration register.
5. For reference only, this parameter is not 100% tested.
Test Circuits
VCC
VCC
VCC RGP
VCC RGP
VCELL1
VCELL2
VCELL1
RGC
RGO
1V
VRGO
VCELL2
RGC
VRGO
RGO
1V
VCELL3
VCELL3
1V
VCELL4
VCELL4
VSS
VSS
Increase Vcc until VRGO turns on
Decrease Vcc until VRGO turns off
WAKE-UP TEST CIRCUIT
SLEEP TEST CIRCUIT
Power-Up Timing
SYMBOL
PARAMETER
MIN
MAX
UNIT
tPUR
(Note 6)
Power-up to SPI read operation (RDSTAT, EEREAD STAT)
TOC + 2ms
ms
tPUW1
(Note 6)
Power-up to SPI write operation (WREN, WRDI, EEWRITE, WCFIG, SET IDL,
WCNTR)
TOC + 2ms
ms
tPUW2
(Note 6)
Power-up to SPI write operation (WCNTR - bits 10 and 11)
TOV + 200ms
or
TUV + 200ms
(Note 7)
ms
NOTES:
6. tPUR, tPUW1 and tPUW2 are the delays required from the time VCC is stable until a read or write can be initiated. These parameters are not 100%
tested.
7. Whichever is longer.
6
FN8246.0
December 22, 2004
X3102
Capacitance TA = +25°C, f = 1MHz, VRGO = 5V
SYMBOL
PARAMETER
CONDITIONS
MAX
UNITS
VOUT = 0V
8
pF
VIN = 0V
6
pF
COUT (Note 8) Output capacitance (SO)
CIN (Note 8)
Input capacitance (SCK, SI, CS)
NOTE:
8. This parameter is not 100% tested.
Equivalent A.C. Load Circuit
A.C. Test Conditions
5V
Input pulse levels
2061Ω
SO
0.5 – 4.5V
Input rise and fall times
10ns
Input and output timing level
2.5V
30pF
3025Ω
A.C. Characteristics (Over the recommended operating conditions, unless otherwise specified.)
Serial Input Timing
SYMBOL
PARAMETER
MIN
MAX
UNITS
0
3.3
MHz
fSCK
Clock frequency
tCYC
Cycle time
300
ns
tLEAD
CS lead time
150
ns
tLAG
CS lag time
150
ns
tWH
Clock HIGH time
130
ns
tWL
Clock LOW time
130
ns
tSU
Data setup time
20
ns
tH
Data hold time
20
ns
tRI (Note 9)
Data in rise time
2
µs
tFI (Note 9)
Data in fall time
2
µs
tCS
CS deselect time
tWC (Note 10)
Write cycle time
100
ns
5
ms
NOTES:
9. This parameter is not 100% tested.
10. tWC is the time from the rising edge of CS after a valid write sequence has been sent to the end of the self-timed internal nonvolatile write cycle.
Serial Input Timing
tCS
CS
tLEAD
tLAG
SCK
tH
tSU
SI
MSB IN
tRI
tFI
LSB IN
SO
7
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December 22, 2004
X3102
Serial Output Timing
SYMBOL
PARAMETER
MIN
MAX
UNITS
0
3.3
MHz
fSCK
Clock Frequency
tDIS
Output Disable Time
150
ns
Output Valid from Clock LOW
130
ns
tV
tHO
Output Hold Time
tRO (Note 11)
Output Rise Time
50
ns
tFO (Note 11)
Output Fall Time
50
ns
0
ns
NOTE:
11. This parameter is not 100% tested.
Serial Output Timing
CS
tCYC
tWH
tLAG
SCK
tHO
tV
SO
SI
MSB Out
MSB–1 Out
tWL
tDIS
LSB Out
ADDR
LSB In
Symbol Table
WAVEFORM
INPUTS
OUTPUTS
Must be
steady
Will be
steady
May change
from LOW
to HIGH
Will change
from LOW
to HIGH
May change
from HIGH
to LOW
Will change
from HIGH
to LOW
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
N/A
Center Line
is High
Impedance
8
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December 22, 2004
X3102
Analog Output Response Time
SYMBOL
tVSC
tCSGO
tCO
PARAMETER
MIN
TYP
MAX
UNITS
AO Output Stabilization Time (Voltage Source Change)
1.0
ms
AO Output Stabilization Time (Current Sense Gain Change)
1.0
ms
Control Outputs Response Time (UVP/OCP, OVP/MON, CB4, CB3, CB2, CB1, RGC)
1.0
µs
Change in Voltage Source
AS2:AS0
AO
tVSC
tVSC
Change in Current Sense Gain Amplification and Control Bits
CS
SCK
DI
Control Reg
OVPC
CSG1
Bit10
AO
Current Sense
Gain Change
UVP/OCP
OVP/LMON
CB3:CB1
RGC
On
Control
Outputs
Off
Bit9
CSG0
SLP
0
Bit8
Bit7
Bit6
0
x
Bit5
Old Gain
tCSGO
New Gain
tCO
9
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December 22, 2004
X3102
Typical Operating Characteristics
450
150
CURRENT (µA)
CURRENT (µA)
125
100
400
350
75
50
-20
25
300
80
-20
25
FIGURE 1. NORMAL OPERATING CURRENT
FIGURE 2. MONITOR MODE CURRENT
4.40
VOLTAGE (V)
REGULATOR VOLTAGE (V)
5.020
4.35
4.35V
4.30
4.3V
4.25
4.25V
4.20
4.2V
4.15
-25
25
5.000
4.920
4.900
REGULATED VOLTAGE
VOLTAGE (V)
10
50
100
5.000
2.45V
2.35V
2.35
2.25
-25
1
5.020
2.55V
2.45
2.30
VCC = 10.8V to 16V RLIM = 15Ω (ILIM = 200mA)
FIGURE 4. VOLTAGE REGULATOR OUTPUT (TYPICAL)
2.55
2.40
-25°C
4.940
LOAD (mA)
FIGURE 3. OVER CHARGE TRIP VOLTAGE (TYPICAL)
2.50
25°C
4.960
4.880
75
75°C
4.980
TEMPERATURE (°C)
2.60
80
TEMPERATURE
TEMPERATURE
1mA LOAD
4.980
10mA LOAD
4.960
50mA LOAD
4.940
100mA LOAD
4.920
4.900
2.25V
25
TEMPERATURE (°C)
FIGURE 5. OVER DISCHARGE TRIP VOLTAGE (TYPICAL)
10
75
4.880
-25
VCC = 10.8V to 16V RLIM = 15Ω (ILIM = 200mA)
25
75
TEMPERATURE (°C)
FIGURE 6. VOLTAGE REGULATOR OUTPUT (TYPICAL)
FN8246.0
December 22, 2004
X3102
Principles of Operation
The X3102 provides two distinct levels of functionality and
battery cell protection:
First, in Normal mode, the device periodically checks each
cell for an over-charge and over-discharge state, while
continuously watching for a pack overcurrent condition. A
protection mode violation results from an over-charge, overdischarge, or overcurrent state. The thresholds for these
states are selected by the user through software. When one
of these conditions occur, a Discharge FET or a Charge FET
or both FETs are turned off to protect the battery pack. In an
over-discharge condition, the X3102 device goes into a low
power sleep mode to conserve battery power. During sleep,
the voltage regulator turns off, removing power from the
microcontroller to further reduce pack current.
Second, in Monitor mode, a microcontroller with A/D converter
measures battery cell voltage and pack current via pin AO
and the X3102 on-board MUX. The user can thus implement
protection, charge/discharge, cell balancing or gas gauge
software algorithms to suit the specific application and
characteristics of the cells used. While monitoring these
voltages, all protection circuits are on continuously.
In a typical application, the microcontroller is also
programmed to provide an SMBus interface along with the
Smart Battery System interface protocols. These additions
allow an X3102 based module to adhere to the latest
industry battery pack standards.
Typical Application Circuit
The X3102 has been designed to operate correctly when
used as connected in the Typical Application Circuit (See
Figure 7).
The power MOSFET’s Q1 and Q2 are referred to as the
“Discharge FET” and “Charge FET,” respectively. Since
these FETs are p-channel devices, they will be ON when the
gates are at VSS, and OFF when the gates are at VCC. As
their names imply, the discharge FET is used to control cell
discharge, while the charge FET is used to control cell
charge. Diode D1 allows the battery cells to receive charge
even if the Discharge FET is OFF, while diode D2 allows the
cells to discharge even if the charge FET is OFF. D1 and D2
are integral to the Power FETs. It should be noted that the
cells can neither charge nor discharge if both the charge FET
and discharge FET are OFF.
The operation of the voltage regulator is described in section
“Voltage Regulator” on page 26. This regulator provides a
5VDC±0.5% output. The capacitor (C1) connected from
RGO to ground provides some noise filtering on the RGO
output. The recommended value is 0.1µF or less. The value
chosen must allow VRGO to decay to 0.1V in 170ms or less
when the X3102 enters the sleep mode. If the decay is
slower than this, a resistor (R1) can be placed in parallel with
the capacitor.
During an initial turn-on period (TPUR + TOC), VRGO has a
stable, regulated output in the range of 5VDC ± 10% (See
Figure 8). The selection of the microcontroller should take
this into consideration. At the end of this turn on period, the
X3102 “self-tunes” the output of the voltage regulator to
5V±0.5%. As such, VRGO can be used as a reference
voltage for the A/D converter in the microcontroller.
Repeated power up operations, consistently re-apply the
same “tuned” value for VRGO.
Figure 1 shows a battery pack temperature sensor
implemented as a simple resistive voltage divider, utilizing a
thermistor (RT) and resistor (RT’). The voltage VT can be fed
to the A/D input of a microcontroller and used to measure
and monitor the temperature of the battery cells. RT’ should
be chosen with consideration of the dynamic resistance
range of RT as well as the input voltage range of the
microcontroller A/D input. An output of the microcontroller
can be used to turn on the thermistor divider to allow
periodic turn-on of the sensor. This reduces power
consumption since the resistor string is not always drawing
current.
Diode D3 is included to facilitate load monitoring in an
overcurrent protection mode (See section “Overcurrent
Protection” on page 23), while preventing the flow of current
into pin OVP/LMON during normal operation. The
N-Channel transistor turns off this function during the sleep
mode.
Resistor RPU is connected across the gate and drain of the
charge FET (Q2). The discharge FET Q1 is turned off by the
X3102, and hence the voltage at pin OVP/LMON will be (at
maximum) equal to the voltage of the battery terminal, minus
one forward biased diode voltage drop (VP+–VD7). Since the
drain of Q2 is connected to a higher potential (VP+) a pull-up
resistor (RPU) in the order of 1MΩ should be used to ensure
that the charge FET is completely turned OFF when
OVP/LMON = VCC.
Power to the X3102 is applied to pin VCC via diodes D6 and
D7. These diodes allow the device to be powered by the
Li-Ion battery cells in normal operating conditions, and allow
the device to be powered by an external source (such as a
charger) via pin P+ when the battery cells are being
charged. These diodes should have sufficient current and
voltage ratings to handle both cases of battery cell charge
and discharge.
11
FN8246.0
December 22, 2004
D7
D6
BAT54
BAT54
D1
D2
Charge FET
P+
Q2
Q1
RPU
Discharge FET
1M
ILMON
Transistor Recommendations
Q1, Q2 = Si4435
Q3 = 2N3906
Q4 - Q10 = 2N7002
D3
12
Q10
ILMT
3 or 4
Li-Ion cells†
VRGO
Q3
.
RLMT
1µF
28
C1
0.1µF
27
26
25
24
23
B+
VCC
1
RCB
100
RGO
RGC
RGP
UVP/
OCP
Choose R1 and
C1 such that
VRGO goes to
0.1V (or less) in
170ms (or less)
when entering
the Sleep Mode
(at 25°C).
VCELL1
CB1
3
VCELL2
100
RCB
5
RCB
Q8
CS
SCK
CB2
SO
X3102
SI
VCELL3
100
A/D
Ref
0.01µF
6
AS2
VSS
AS1
7
Set High
after power
up to enable
SMBus and
LMON
CPOR
GP
I/O
RT’
GP
I/O
21
20
19
Q4
GP
I/O
Q5
18
CB3
RPOR
Reset
22
0.01µF
4
Q7
VCC
SMBCLK
100
100 SMBDATA
17
16
AS0
8
NC
15
A/D Input
AO
VSS
VCS1
VCS2
10
11
OVT
UVT
OCT
VT
A/D Input
RT
9
COV
B-
12
CUV
13
COC
FETs Q4 and Q5 are needed
only if external pull-ups on
the SMBus lines cause
voltage to appear at the uC
Vcc pin during sleep mode.
14
FN8246.0
December 22, 2004
RSENSE
FIGURE 7. TYPICAL APPLICATION CIRCUIT
P-
X3102
2
µC,
ASIC
OVP/
LMON
0.01µF
Q6
R1
1M
(Optional)
X3102
The capacitors on the VCELL1 to VCELL4 inputs are used in
a first order low pass filter configuration, at the battery cell
voltage monitoring inputs (VCELL1–VCELL4) of the X3102.
This filter is used to block any unwanted interference signals
from being inadvertently injected into the monitor inputs.
These interference signals may result from:
• Transients created at battery contacts when the battery
pack is being connected/disconnected from the charger or
the host.
• Electrostatic discharge (ESD) from something/someone
touching the battery contacts.
• Unfiltered noise that exists in the host device.
• RF signals which are induced into the battery pack from
the surrounding environment.
Such interference can cause the X3102 to operate in an
unpredictable manner, or in extreme cases, damage the
device. As a guide, the capacitor should be in the order of
0.01µF and the resistor, should be in the order of 10KΩ. The
capacitors should be of the ceramic type. In order to
minimize interference, PCB tracks should be made as short
and as wide as possible to reduce their impedance. The
battery cells should also be placed as close to the X3102
monitor inputs as possible.
Resistors RCB and the associated n-channel MOSFET’s
(Q6–Q9) are used for battery cell voltage balancing. The
X3102 provides internal drive circuitry which allows the user
to switch FETs Q6–Q9 ON or OFF via the microcontroller
and SPI port (See section “Cell Voltage Balance Control
(CBC1–CBC3)” on page 17). When any of the these FETs
are switched ON, a current, limited by resistor RCB, flows
across the particular battery cell. In doing so, the user can
control the voltage across each individual battery cell. This is
important when using Li-Ion battery cells since imbalances in
cell voltages can, in time, greatly reduce the usable capacity
of the battery pack. Cell voltage balancing may be
implemented in various ways, but is usually performed
towards the end of cell charging (“Top-of-charge method”).
Values for RCB will vary according to the specific application.
FETs Q4 and Q5 may be required on general purpose I/Os
of the microcontroller that connect outside of the package. In
some cases, without FETs, pull-up resistors external to the
pack force a voltage on the VCC pin of the microcontroller
during a pack sleep condition. This voltage can affect the
proper tuned voltage of the X3102 regulator. These FETs
should be turned-on by the microcontroller. (See Figure 1.)
Power On Sequence
Initial connection of the Li-Ion cells in the battery pack will
not normally power up the battery pack. Instead, the X3102
enters and remains in the SLEEP mode. To exit the SLEEP
mode, after the initial power up sequence, or following any
other SLEEP MODE, a minimum of 8.5V is applied to the
VCC pin, as would be the case during a battery charge
condition. (See Figure 8.)
When VSLR is applied to VCC, the analog select pins (AS2–
AS0) and the SPI communication pins (CS, CLK, SI, SO)
must be low, so the X3102 powers up correctly into the
normal operating mode. This can be done by using a poweron reset circuit.
When entering the normal operating mode, either from initial
power up or following the SLEEP MODE, all bits in the
control register are zero. With UVPC and OVPC bits at zero,
the charge and discharge FETs are off. The microcontroller
must turn these on to activate the pack. The microcontroller
would typically check the voltage and current levels prior to
turning on the FETs via the SPI port. The software should
prevent turning on the FETs throughout an initial
measurement/calibration period. The duration of this period
is TOV + 200ms or TUV + 200ms, whichever is longer.
The internal 4kbit EEPROM memory can be used to store
the cell characteristics for implementing such functions as
gas gauging, battery pack history, charge/discharge cycles,
and minimum/maximum conditions. Battery pack
manufacturing data as well as serial number information can
also be stored in the EEPROM array. An SPI serial bus
provides the communication link to the EEPROM.
A current sense resistor (RSENSE) is used to measure and
monitor the current flowing into/out of the battery terminals,
and is used to protect the pack from overcurrent conditions
(See section “Overcurrent Protection” on page 23). RSENSE
is also used to externally monitor current via a
microcontroller (See section “Current Monitor Function” on
page 25).
13
FN8246.0
December 22, 2004
X3102
TPUR
VSLR
VCC
0V
5V±10% (Stable and Repeatable)
VRGO Tuned to 5V±0.5%
5V
VRGO
0V
2ms (Typ.)
1
Voltage Regulator Output Status
(Internal Signal)
VRGS
0
TOC
1
Overcurrent Detection Status
(Internal Signal)
OCDS
Status Register Bit 0
1 = X3102 in overcurrent Protection Mode
0 = X3102 NOT in overcurrent Protection Mode
0
1 1 = X3102 in overcurrent Protection Mode OR VRGO Not Yet Tuned
0 = X3102 NOT in overcurrent Protection Mode AND VRGO Tuned
VRGS+OCDS
0
TOV+200ms
1
Status Register Bit 2
(SWCEN = 0)
0
CCES+OVDS
1 = VCELL < VCE OR X3102 in Over-charge Protection Mode
0 = VCELL > VCE OR X3102 NOT in Over-charge Protection Mode
1
Status Register Bit 2
(SWCEN = 1)
0
OVDS
1 = X3102 in Over-charge Protection Mode
From
Microcontroller
0 = X3102 NOT in Over-charge Protection Mode
AS2_AS0
TOV+200ms OR TUV+200ms (whichever is longer)
SPI PORT
Any Read or Write Operation, except turnon of FETs can start here.
Charge, Discharge FETs can be
turned on here.
FIGURE 8. POWER UP TIMING (INITIAL POWER UP OR AFTER SLEEP MODE)
14
FN8246.0
December 22, 2004
X3102
Configuration Register
Over-Discharge Settings
The X3102 can be configured for specific user requirements
using the Configuration Register.
VUV1 and VUV0 control the cell over-discharge (under
voltage threshold) level. See section “Over-discharge
Protection” on page 20.
TABLE 1. CONFIGURATION REGISTER FUNCTIONALITY
TABLE 5. OVER-DISCHARGE THRESHOLD SELECTION
BIT(s)
NAME
FUNCTION
0-5
–
6
SWCEN
Switch Cell Charge Enable threshold
function ON/OFF
7
CELLN
Set the number of Li-Ion
battery cells used (3 or 4)
8-9
VCE1–VCE0
Select Cell Charge Enable threshold
10–11
VOC1–VOC0
Select overcurrent threshold
12–13
VUV1–VUV0
Select over-discharge (under voltage)
threshold
14–15
VOV1–VOV0
Select over-charge voltage threshold
CONFIGURATION
REGISTER BITS
(don’t care)
TABLE 2. CONFIGURATION REGISTER - UPPER BYTE
15
14
13
12
11
10
9
8
VOV1
VOV0
VUV1
VUV0
VOC1
VOC0
VCE1
VCE0
Default = 03H
TABLE 3. CONFIGURATION REGISTER - LOWER BYTE
VUV1
VUV0
OPERATION
0
0
VUV = 2.25V
(default)
0
1
VUV = 2.35V
1
0
VUV = 2.45V
1
1
VUV = 2.55V
Overcurrent Settings
VOC1 and VOC0 control the pack overcurrent level. See
section “Overcurrent Protection” on page 23.
TABLE 6. OVERCURRENT THRESHOLD VOLTAGE
SELECTION.
CONFIGURATION REGISTER BITS
VOC1
VOC0
OPERATION
0
0
VOC = 0.075V (Default)
0
1
VOC = 0.100V
7
6
5
4
3
2
1
0
1
0
VOC = 0.125V
CELLN
SWCEN
x
x
x
x
x
x
1
1
VOC = 0.150V
Default = 40H
Cell Charge Enable Settings
Over-Charge Voltage Settings
VOV1 and VOV0 control the cell over-charge level. See
section “Over-charge Protection” on page 19.
TABLE 4. OVER-CHARGE VOLTAGE THRESHOLD SELECTION
CONFIGURATION REGISTER BITS
VCE1, VCE0 and SWCEN control the pack charge enable
function. SWCEN enables or disables a circuit that prevents
charging if the cells are at too low a voltage. VCE1 and
VCE0 select the voltage that is recognized as too low. See
section “Sleep Mode” on page 20.
TABLE 7. CELL CHARGE ENABLE FUNCTION
VOV1
VOV0
OPERATION
0
0
VOV = 4.20V (Default)
0
1
VOV = 4.25V
1
0
VOV = 4.30V
1
1
VOV = 4.35V
CONFIGURATION
REGISTER BIT
SWCEN
OPERATION
0
Charge enable function: ON
1
Charge enable function: OFF
TABLE 8. CELL CHARGING THRESHOLD VOLTAGE
SELECTION.
CONFIGURATION REGISTER BITS
15
VCE1
VCE0
OPERATION
0
0
VCE = 0.5V
0
1
VCE = 0.80V
1
0
VCE = 1.10V
1
1
VCE = 1.40V (Default)
FN8246.0
December 22, 2004
X3102
Cell Number Selection
Power Up
The X3102 is designed to operate with three (3) Li-Ion
battery cells. The CELLN bit of the configuration register
(Table 9) sets the number of cells recognized. For the
X3102, the value for CELLN should always be zero.
Data Recalled
from Shadow
EEPROM to SRAM
Configuration Register
(SRAM=Old Value)
TABLE 9. SELECTION OF NUMBER OF BATTERY CELLS
CONFIGURATION
REGISTER BIT
WCFIG (New Value)
CELLN
Configuration Register
(Sram=New Value)
OPERATION
1
Not used
0
3 Li-Ion battery cells
The configuration register consists of 16 bits of NOVRAM
memory (Table 2, Table 3). This memory features a highspeed static RAM (SRAM) overlaid bit-for-bit with nonvolatile “Shadow” EEPROM. An automatic array recall
operation reloads the contents of the shadow EEPROM into
the SRAM configuration register upon power-up (Figure 9).
WREN
Write
Enable
Data Recalled
from Shadow
EEPROM to SRAM
Lower Byte
EEWRITE
Write to
4kbit EEPROM
Configuration Register
(SRAM=old value)
Recall
Recall
YES
Power Down
Power Up
Configuration Register (SRAM)
Upper Byte
Store
(New Value)
in Shadow
EEPROM
NO
Power Down
Power Up
Shadow EEPROM
FIGURE 9. POWER UP OF CONFIGURATION REGISTER
Data Recalled
from Shadow
EEPROM to SRAM
The configuration register is designed for unlimited write
operations to SRAM, and a minimum of 1,000,000 store
operations to the EEPROM. Data retention is specified to be
greater than 100 years.
It should be noted that the bits of the shadow EEPROM are
for the dedicated use of the configuration register, and are
NOT part of the general purpose 4kbit EEPROM array.
The WCFIG command writes to the configuration register,
see Table 30 and section “X3102 SPI Serial Communication”
on page 27.
After writing to this register using a WCFIG instruction, data
will be stored only in the SRAM of the configuration register.
In order to store data in shadow EEPROM, a WREN
instruction, followed by a EEWRITE to any address of the
4kbit EEPROM memory array must occur, See Figure 10.
This sequence initiates an internal nonvolatile write cycle
which permits data to be stored in the shadow EEPROM
cells. It must be noted that even though a EEWRITE is made
to the general purpose 4kbit EEPROM array, the value and
address to which it is written, is unimportant. If this
procedure is not followed, the configuration register will
power up to the last previously stored values following a
power down sequence.
16
Configuration Register
(SRAM=New Value)
FIGURE 10. WRITING TO CONFIGURATION REGISTER
Control Register
The Control Register is realized as two bytes of volatile RAM
(Table 10, Table 11). This register is written using the
WCNTR instruction, see Table 30 and section “X3102 SPI
Serial Communication” on page 27.
TABLE 10. CONTROL REGISTER - UPPER BYTE
14
14
13
12
11
10
9
8
x
CBC3
CBC2
CBC1
UVPC
OVPC
CSG1
CSG0
TABLE 11. CONTROL REGISTER - LOWER BYTE
7
6
5
4
3
2
1
0
SLP
0
0
x
x
x
x
x
Since the control register is volatile, data will be lost
following a power down and power up sequence. The default
value of the control register on initial power up or when
exiting the SLEEP MODE is 00h (for both upper and lower
FN8246.0
December 22, 2004
X3102
bytes respectively). The functions that can be manipulated
by the Control Register are shown in Table 12.
TABLE 12. CONTROL REGISTER FUNCTIONALITY
BIT(S)
NAME
0–4
–
5, 6
0, 0
Reserved—write 0 to these locations.
7
SLP
Select sleep mode.
8,9
CSG1,
CSG0
Select current sense voltage gain
10
OVPC
11
OVP/LMON and UVP/OCP can be controlled by using the
WCNTR Instruction to set bits OVPC and UVPC in the
Control register (See page 17).
TABLE 15. UVP/OVP CONTROL
FUNCTION
(don’t care)
CONTROL REGISTER
BITS
OVPC
UVPC
1
x
Pin OVP = VSS (FET ON)
0
x
Pin OVP = VCC (FET OFF)
OVP control: switch pin OVP = VCC/VSS
x
1
Pin UVP = VSS (FET ON)
UVPC
UVP control: switch pin UVP = VCC/VSS
x
0
Pin UVP = VCC (FET OFF)
12
CBC1
CB1 control: switch pin CB1 = VCC/VSS
13
CBC2
CB2 control: switch pin CB2 = VCC/VSS
14
CBC3
CB3 control: switch pin CB3 = VCC/VSS
15
–
(don’t care)
OPERATION
It is possible to set/change the values of OVPC and UVPC
during a protection mode. A change in the state of the pins
OVP/LMON and UVP/OCP, however, will not take place until
the device has returned from the protection mode.
Cell Voltage Balance Control (CBC1–CBC3)
Sleep Control (SLP)
Setting the SLP bit to ‘1’ forces the X3102 into the sleep
mode, if VCC < VSLP. See section “Sleep Mode” on page 20.
TABLE 13. SLEEP MODE SELECTION
This function can be used to adjust individual battery cell
voltage during charging. Pins CB1–CB3 are used to control
external power switching devices. Cell voltage balancing is
achieved via the SPI port.
CONTROL REGISTER BITS
TABLE 16. CB1–CB3 CONTROL
SLP
OPERATION
0
Normal operation mode
1
Device enters Sleep mode
Control Register Bits
CBC3
CBC2
CBC1
x
x
1
Set CB1 = VCC (ON)
x
x
0
Set CB1 = VSS (OFF)
x
1
x
Set CB2 = VCC (ON)
x
0
x
Set CB2 = VSS (OFF)
1
x
x
Set CB3 = VCC (ON)
0
x
x
Set CB3 = VSS (OFF)
x
x
x
Set CB4 = VCC (ON)
x
x
x
Set CB4 = VSS (OFF)
Current Sense Gain (CSG1, CSG0)
These bits set the gain of the current sense amplifier. These
are x10, x25, x80 and x160. For more detail, see section
“Current Monitor Function” on page 25.
TABLE 14. CURRENT SENSE GAIN CONTROL
CONTROL REGISTER BITS
CSG1
CSG0
OPERATION
0
0
Set current sense gain=x10
0
1
Set current sense gain=x25
1
0
Set current sense gain=x80
1
1
Set current sense gain=x160
Charge/Discharge Control (OVPC, UVPC)
The OVPC and UVPC bits allow control of cell charge and
discharge externally, via the SPI port. These bits control the
OVP/LMON and UVP/OCP pins, which in turn control the
external power FETs.
Using P-channel power FETs ensures that the FET is on
when the pin voltage is low (Vss), and off when the pin
voltage is high (Vcc).
17
Operation
CB1–CB3 can be controlled by using the WCNTR Instruction
to set bits CBC1–CBC3 in the control register (Table 16).
Status Register
The status of the X3102 can be verified by using the
RDSTAT command to read the contents of the Status
Register (Table 17).
TABLE 17. STATUS REGISTER
7
6
5
4
3
2
1
0
0
0
0
0
0
CCES +
OVDS
UVDS
VRGS +
OCDS
FN8246.0
December 22, 2004
X3102
The function of each bit in the status register is shown in
Table 18.
Bit 1 of the status register simply indicates whether or not the
X3102 is in over-discharge protection mode.
Bit 0 of the status register (VRGS + OCDS) actually
indicates the status of two conditions of the X3102. Voltage
Regulator Status (VRGS) is an internally generated signal
which indicates that the output of the Voltage Regulator
(VRGO) has reached an output of 5VDC ± 0.5%. In this
case, the voltage regulator is said to be “tuned”. Before the
signal VRGS goes low (i.e. before the voltage regulator is
tuned), the voltage at the output of the regulator is nominally
5VDC ± 10% (See section “Voltage Regulator” on page 26.)
Overcurrent Detection Status (OCDS) is another internally
generated signal which indicates whether or not the X3102
is in overcurrent protection mode.
Bit 2 of the status register (CCES + OVDS) indicates the
status of two conditions of the X3102. Cell Charge Enable
Status (CCES) is an internally generated signal which
indicates the status of any cell voltage (VCELL) with respect
to the Cell Charge Enable Voltage (VCE). Over-charge
Voltage Detection Status (OVDS) is an internally generated
signal which indicates whether or not the X3102 is in overcharge protection mode.
Signals VRGS and OCDS are logically OR’ed together
(VRGS+OCDS) and written to bit 0 of the status register
(See Table 18, Table 17 and Figure 8).
When the cell charge enable function is switched ON
(configuration bit SWCEN = 0), the signals CCES and OVDS
are logically OR’ed (CCES + OVDS) and written to bit 2 of
the status register. If the cell charge enable function is
switched OFF (configuration bit SWCEN = 1), then bit 2 of
the status register effectively only represents information
about the over-charge status (OVDS) of the X3102 (See
Table 18, Table 17 and Figure 8).
TABLE 18. STATUS REGISTER FUNCTIONALITY
BIT(S)
NAME
DESCRIPTION
CASE
STATUS
0
VRGS + OCDS
Voltage regulator status
+
Overcurrent
detection status
-
1
VRGO not yet tuned (VRGO = 5V ± 10%) OR
X3102 in overcurrent protection mode.
0
VRGO tuned (VRGO = 5V ± 0.5%) AND
X3102 NOT in overcurrent protection mode.
Over-discharge
detection status
-
1
X3102 in over-discharge protection mode
0
X3102 NOT in over-discharge protection mode
Cell charge
enable status
+
Over-charge
detection status
SWCEN = 0
(Note)
1
VCELL < VCE OR
X3102 in over-charge protection mode
0
VCELL > VCE AND
X3102 NOT in over-charge protection mode
SWCEN = 1
(Note)
1
X3102 in over-charge protection mode
0
X3102 NOT in over-charge protection mode
–
0
Not used (always return zero)
1
2
3-7
UVDS
CCES + OVDS
-
INTERPRETATION
NOTE: This bit is set in the configuration register.
18
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December 22, 2004
X3102
X3102 Internal Protection Functions
Over-charge Protection
The X3102 provides periodic monitoring (See section
“Periodic Protection Monitoring” on page 19) for over-charge
and over-discharge states and continuous monitoring for an
overcurrent state. It has automatic shutdown when a
protection mode is encountered, as well as automatic return
after the device is released from a protection mode. When
sampling voltages through the analog port (Monitor Mode),
over-charge and over-discharge protection monitoring is
also performed on a continuous basis.
The X3102 monitors the voltage on each battery cell
(VCELL). If for any cell, VCELL > VOV for a time exceeding
TOV, then the Charge FET will be switched OFF
(OVP/LMON=VCC). The device has now entered Overcharge protection mode (Figure 11). The status of the
discharge FET (via pin UVP) will remain unaffected.
Voltage thresholds for each of these protection modes (VOV,
VUV, and VOC respectively) can be individually selected via
software and stored in an internal non-volatile register. This
feature allows the user to avoid the restrictions of mask
programmed voltage thresholds, and is especially useful
during prototype/evaluation design stages or when cells with
slightly different characteristics are used in an existing
design.
Delay times for the detection of, and release from protection
modes (TOV, TUV/TUVR, and TOC/TOCR respectively) can be
individually varied by setting the values of external capacitors
connected to pins OVT, UVT, OCT.
Periodic Protection Monitoring
In normal operation, the analog select pins are set such that
AS2 = L, AS1 = L, AS0 = L. In this mode the X3102
conserves power by sampling the cells for over or overdischarge conditions.
In this state over-charge and over-discharge protection
circuitry are usually off, but are periodically switched on by
the internal Protection Sample Rate Timer (PSRT). The overcharge and over-discharge protection circuitry is on for
approximately 2ms in each 125ms period. Overcurrent
monitoring is continuous. In monitor mode (See page 25)
over-charge and over-discharge monitoring is also
continuous.
Normal Operation Mode
While in over-charge protection mode, it is possible to
change the state of the OVPC bit in the control register such
that OVP/LMON=Vss (Charge FET=ON). Although the
OVPC bit in the control register can be changed, the change
will not be seen at pin OVP until the X3102 returns from
over-charge protection mode.
The over-charge detection delay TOV, is varied using a
capacitor (COV) connected between pin OVT and GND. A
typical delay time is shown in Table 10. The delay TOV that
results from a particular capacitance COV, can be
approximated by the following linear equation:
TOV (s) ≈ 10 x COV (µF).
TABLE 19. TYPICAL OVER-CHARGE DETECTION TIME
Symbol
COV
Delay
TOV
0.1µF
1.0s (Typ)
The device further continues to monitor the battery cell
voltages, and is released from over-charge protection mode
when VCELL< VOVR, for all cells. When the X3102 is
released from over-charge protection mode, the charge FET
is automatically switched ON (OVP/LMON=VSS). When the
device returns from over-charge protection mode, the status
of the discharge FET (pin UVP/OCP) remains unaffected.
The value of VOV can be selected from the values shown in
Table 4 by setting bits VOV1, VOV0. These bits are set by
using the WCFIG instruction to write to the configuration
register.
Over-charge
Protection Mode
Normal Operation Mode
VOV
VOVR
VCELL
TOV
VCC
OVP/LMON
VSS
Event
0
1
2
3
FIGURE 11. OVER-CHARGE PROTECTION MODE-EVENT DIAGRAM
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December 22, 2004
X3102
TABLE 20. OVER-CHARGE PROTECTION MODE-EVENT DIAGRAM DESCRIPTION
EVENT
[0,1)
EVENT DESCRIPTION
• Discharge FET is ON (UVP/OCP=VSS).
• Charge FET is ON (OVP/LMON=VSS), and hence battery cells are permitted to receive charge.
• All cell voltages (VCELL – VCELL4) are below the over-charge voltage threshold (VOV).
• The device is in normal operation mode (i.e. not in a protection mode).
[1]
• The voltage of one or more of the battery cells (VCELL), exceeds VOV.
• The internal over-charge detection delay timer begins counting down.
• The device is still in normal operation mode
(1,2)
[2]
The internal over-charge detection delay timer continues counting for TOV seconds.
The internal over-charge detection delay timer times out
AND
VCELL still exceeds VOV.
• Therefore, the internal over-charge sense circuitry switches the charge FET OFF (OVP/LMON=Vcc).
• The device has now entered over-charge protection mode.
(2,3)
• While in over-charge protection mode:
• The battery cells are permitted to discharge via the discharge FET, and diode D2 across the charge FET
• The X3102 monitors the voltages VCELL1 - VCELL4 to determine whether or not they have all fallen below the “Return from overcharge threshold” (VOVR).
• (It is possible to change the status of UVP/OCP or OVP/LMON using the control register)
[3]
• All cell voltages fall below VOVR—The device is now in normal operation mode.
• The X3102 automatically switches charge FET = ON (OVP/LMON = Vss)
• The status of the discharge FET remains unaffected.
• Charging of the battery cells can now resume.
Over-discharge Protection
If VCELL < VUV, for a time exceeding TUV, the cells are said
to be in a over-discharge state (Figure 12). In this instance,
the X3102 automatically switches the discharge FET OFF
(UVP/OCP=Vcc), and then enter sleep mode.
The over-discharge (undervoltage) value, VUV, can be
selected from the values shown in Table 5 by setting bits
VUV1, VUV0 in the configuration register. These bits are set
using the WCFIG command. Once in the sleep mode, the
following steps must occur before the X3102 allows the
battery cells to discharge:
• The X3102 must wake from sleep mode (See section
“Voltage Regulator” on page 26).
• The charge FET must be switched ON by the
microcontroller (OVP/LMON=VSS), via the control register
(See section “CONTROL REGISTER FUNCTIONALITY”
on page 17).
• All battery cells must satisfy the condition: VCELL > VUVR
for a time exceeding TUVR.
• The discharge FET must be switched ON by the
microcontroller (UVP/OCP=VSS), via the control register
(See section “CONTROL REGISTER FUNCTIONALITY”
on page 17)
The times TUV/TUVR are varied using a capacitor (CUV)
connected between pin UVT and GND (Table 13). The delay
20
TUV that results from a particular capacitance CUV, can be
approximated by the following linear equation:
TUV (s) ≈ 10 x CUV (µF)
TUVR (ms) ≈ 70 x CUV (µF)
TABLE 21. TYPICAL OVER-DISCHARGE DELAY TIMES
SYMBOL
TUV
TUVR
DESCRIPTION
CUV
DELAY
Over-discharge
detection delay
0.1µF
1.0s (Typ)
Over-discharge release
time
0.1µF
7ms (Typ)
Sleep Mode
The X3102 can enter sleep mode in two ways:
i)
The device enters the over-discharge protection mode.
ii) The user sends the device into sleep mode using the control register.
A sleep mode can be induced by the user, by setting the SLP
bit in the control register (Table 13) using the WCNTR
Instruction.
In sleep mode, power to all internal circuitry is switched off,
minimizing the current drawn by the device to 1µA (max). In
this state, the discharge FET and the charge FET are
switched OFF (OVP/LMON=VCC and UVP/OCP=VCC), and
the 5VDC regulated output (VRGO) is 0V. Control of
FN8246.0
December 22, 2004
X3102
UVP/OCP and OVP/LMON via bits UVPC and OVPC in the
control register is also prohibited.
cell then both the Charge FET and the discharge FET are OFF
(OVP/LMON = VCC and UVP/OCP = VCC). Thus both charge
and discharge of the battery cells via terminals P+ / P- is
prohibited (See Note).
The device returns from sleep mode when VCC ≥ VSLR. (e.g.
when the battery terminals are connected to a battery
charger). In this case, the X3102 restores the 5VDC
regulated output (section “Voltage Regulator” on page 26),
and communication via the SPI port resumes.
NOTE: In this case, charging of the battery may resume ONLY if the
cell charge enable function is switched OFF by setting bit SWCEN=1
in the configuration register (See Above, “CONFIGURATION
REGISTER FUNCTIONALITY” on page 15).
If the Cell Charge Enable function is enabled when VCC
rises above VSLR, the X3102 internally verifies that the
individual battery cell voltages (VCELL) are larger than the
cell charge enable voltage (VCE) before allowing the FETs to
be turned on. The value of VCE is selected by using the
WCFIG command to set bits VCE1–VCE0 in the
configuration register.
The cell charging threshold function can be switched ON or
OFF by the user, by setting bit SWCEN in the configuration
register (Table 7) using the WCFIG command. In the case
that this cell charge enable function is switched OFF, then
VCE is effectively set to 0V.
The X3102 cannot enter sleep mode (automatically or
manually, by setting the SLP bit) if VCC ≥ VSLR. This is to
ensure that the device does not go into a sleep mode while
the battery cells are at a high voltage (e.g. during cell
charging).
Only if the condition “VCELL > VCE” is satisfied can
the state of charge and discharge FETs be changed via the
control register. Otherwise, if VCELL < VCE for any battery
VSLR
VCC
Cell Charge Prohibited if SWCEN=0
AND VCELL < VCE
VCELL
0.7V
VUVR
VUV
TUVR
VCE
TUV
VCC
Note 3
Over-discharge Protection Mode
UVP/OCP
VSS
The Longer of TOV+200ms OR TUV+200ms
VCC
Notes 1, 2
OVP/LMON
RGO
VSS
5V
Sleep Mode
0V
Event
1
0
2
3
4
5
NOTES:
1. If SWEN=0 and VCELL < VCE, then OVP/LMON stays high and charging is prohibited.
2. OVP/LMON stays high until the microcontroller writes a “1” to the OVPC bit in the control register. This sets the signal low, which turns on the charge FET. It cannot be turned
on prior to this time.
3. UVP/OCP stays high until the microcontroller writes a “1” to the UVPC bit in the control register. This sets the signal low, which turns on the discharge FET. The FET cannot
be turned on prior to this time.
FIGURE 12. OVER-DISCHARGE PROTECTION MODE-EVENT DIAGRAM
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December 22, 2004
X3102
TABLE 22. OVER-DISCHARGE PROTECTION MODE—EVENT DIAGRAM DESCRIPTION
EVENT
[0,1)
EVENT DESCRIPTION
• Charge FET is ON (OVP/LMON = VSS)
• Discharge FET is ON (UVP/OCP = VSS), and hence battery cells are permitted to discharge.
• All cell voltages (VCELL1–VCELL4) are above the Over-discharge threshold voltage (VUV).
• The device is in normal operation mode (i.e. not in a protection mode).
[1]
• The voltage of one or more of the battery cells (VCELL), falls below VUV.
• The internal over-discharge detection delay timer begins counting down.
• The device is still in normal operation mode
(1,2)
[2]
• The internal over-discharge detection delay timer continues counting for TUV seconds.
• The internal over-discharge detection delay timer times out, AND VCELL is still below VUV.
• The internal over-discharge sense circuitry switches the discharge FET OFF (UVP/OCP = Vcc).
• The charge FET is switched OFF (OVP/LMON = VCC).
• The device has now entered over-discharge protection mode.
• At the same time, the device enters sleep mode (See section “Voltage Regulator” on page 26).
(2,3)
• While device is in sleep (in over-discharge protection) mode:
• The power to ALL internal circuits is switched OFF limiting power consumption to less than 1µA.
• The output of the 5VDC voltage regulator (RGO) is 0V.
• Access to the X3102 via the SPI port is NOT possible.
[3]
• Return from sleep mode (but still in over-discharge protection mode):
• Vcc rises above the “Return from Sleep mode threshold Voltage” (VSLR)—This would normally occur in the case that the battery
pack was connected to a charger. The X3102 is now powered via P+/P-, and not the battery pack cells.
• Power is returned to ALL internal circuitry
• 5VDC output is returned to the regulator output (RGO).
• Access is enabled to the X3102 via the SPI port.
• The status of the discharge FET remains OFF (It is possible to change the status of UVPC in the control register, although it will
have no effect at this time).
(3,4)
If the cell charge enable function is • The X3102 initiates a reset operation that takes the longer of TOV+200ms or TUV+200ms to
complete. Do not write to the FET control bits during this time.
switched ON
AND VCELL > VCE
• The charge FET is switched On (OVP/LMON = Vss) by the microcontroller by writing a “1” to
OR
the OVPC bit in the control register.
Charge enable function is
• The battery cells now receive charge via the charge FET and diode D1 across the discharge
switched OFF
FET (which is OFF).
• The X3102 monitors the VCELL voltage to determine whether or not it has risen above VUVR.
If the cell charge enable function is • Charge/discharge of the battery cells via P+ is no longer permitted (Charge FET and discharge
switched ON
FET are held OFF).
AND
• (Charging may re-commence only when the Cell Charge Enable function is switched OFF VCELL < VCE
See Sections: “Configuration Register” page 4, and “Sleep mode” page 17.)
[4]
• The voltage of all of the battery cells (VCELL), have risen above VUVR.
• The internal Over-discharge release timer begins counting down.
• The X3102 is still in over-discharge protection mode.
(4,5)
• The internal over-discharge release timer continues counting for tUVR seconds.
• The X3102 should be in monitor mode (AS2:AS0 not all low) for recovery time based on tUVR. Otherwise recovery is based on two
successive samples about 120ms apart.
[5]
• The internal over-discharge release timer times out, AND VCELL is still above VUVR.
• The device returns from over-discharge protection mode, and is now in normal operation mode.
• The Charger voltage can now drop below VSLR and the X3102 will not go back to sleep.
• The discharge FET is can now be switched ON (UVP/OCP = VSS) by the microcontroller by writing a “1” to the UVPC bit of the
control register.
• The status of the charge FET remains unaffected (ON)
• The battery cells continue to receive charge via the charge FET and discharge FET (both ON).
22
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December 22, 2004
X3102
TOCR (ms) ≈ 10,000 x COC (µF)
Overcurrent Protection
In addition to monitoring the battery cell voltages, the X3102
continually monitors the voltage VCS21 (VCS2–VCS1)
across the current sense resistor (RSENSE). If VCS21 > VOC
for a time exceeding TOC, then the device enters overcurrent
protection mode (Figure 7). In this mode, the X3102
automatically switches the discharge FET OFF (UVP/OCP =
Vcc) and hence prevent current from flowing through the
terminals P+ and P-.
P+
ILMON
Q2
VRGO
OVP/LMON
Symbol
TOC
TOCR
COC
Delay
Overcurrent
detection delay
0.001µF
10ms (Typ)
Overcurrent
release time
0.001µF
10ms (Typ)
Description
The value of VOC can be selected from the values shown in
Table 6, by setting bits VOC1, VOC0 in the configuration
register using the WCFIG command.
Note: If the Charge FET is turned off, due to an overcharge
condition or by direct command from the microcontroller, the
cells are not in an undervoltage condition and the pack has a
load, then excessive current may flow through Q10 and
diode D1. To eliminate this effect, the gate of Q10 can be
turned off by the microcontroller.
D1
Q10
TABLE 23. TYPICAL OVERCURRENT DELAY TIMES
ROCR
(Load)
X3102
FET Control
Circuitry
VSS
VCS1
VCS2
P-
RSENSE
FIGURE 13. OVERCURRENT PROTECTION
The 5VDC voltage regulator output (VRGO) is always active
during an overcurrent protection mode.
Once the device enters overcurrent protection mode, the
X3102 begin a load monitor state. In the load monitor state, a
small current (ILMON = 7.5µA typ.) is passed out of pin OVP/
LMON in order to determine the load resistance. The load
resistance is the impedance seen looking out of pin OVP/
LMON, between terminal P+ and pin VSS (See Figure 13.)
If the load resistance > ROCR (ILMON = 0µA) for a time
exceeding TOCR, then the X3102 is released from
overcurrent protection mode. The discharge FET is then
automatically switched ON (UVP/OCP = Vss) by the X3102,
unless the status of UVP/OCP has been changed in control
register (by manipulating bit UVPC) during the overcurrent
protection mode.
TOC/TOCR are varied using a capacitor (COC) connected
between pin OCT and VSS. A list of typical delay times is
shown in Table 23. Note that the value COC should be larger
than 1nF.
The delay TOC and TOCR that results from a particular
capacitance COC can be approximated by the following
equations:
TOC (ms) ≈ 10,000 x COC (µF)
23
FN8246.0
December 22, 2004
X3102
Overcurrent Protection Mode
Normal Operation Mode
Normal Operation Mode
B+
P+
P+ = (RLOAD+RSENSE) x ILMON
VOC
Voc
VCS2
VSS
TOC
TOCR
VCC
UVP/OCP
VSS
Event
0
1
3
2
4
FIGURE 14. OVERCURRENT PROTECTION MODE - EVENT DIAGRAM
TABLE 24. OVERCURRENT PROTECTION MODE-EVENT DIAGRAM DESCRIPTION
EVENT
[0,1)
[1]
(1,2)
EVENT DESCRIPTION
• Discharge FET is ON (OCP = Vss). Battery cells are permitted to discharge.
• VCS21 (VCS2–VCS1) is less than the overcurrent threshold voltage (VOC).
• The device is in normal operation mode (i.e. not in a protection mode).
•
•
•
•
Excessive current flows through the battery terminals P+, dropping the voltage. (See Figure 14.).
The positive battery terminal voltage (P+) falls, and VCS21 exceeds VOC.
The internal overcurrent detection delay timer begins counting down.
The device is still in Normal Operation Mode
The internal Overcurrent detection delay timer continues counting for TOC seconds.
[2]
• The internal overcurrent detection delay timer times out, AND VCS21 is still above VOC.
• The internal overcurrent sense circuitry switches the discharge FET OFF (UVP/OCP = Vcc).
• The device now begins a load monitor state by passing a small test current (ILMON = 7.5µA) out of pin OVP/LMON. This senses if
an overcurrent condition (i.e. if the load resistance < ROCR) still exists across P+/P-.
• The device has now entered overcurrent protection mode.
• It is possible to change the status of UVPC and OVPC in the control register, although the status of pins UVP/OCP and OVP/LMON
will not change until the device has returned from overcurrent protection mode.
(2,3)
• The X3102 now continuously monitors the load resistance to detect whether or not an overcurrent condition is still present across
the battery terminals P+/P-.
[3]
(3,4)
[4]
•
•
•
•
•
•
The device detects the load resistance has risen above ROCR.
Voltages P+ and VCS21 return to their normal levels.
The test current from pin OVP/LMON is stopped (ILMON = 0µA)
The device has now returned from the load monitor state
The internal overcurrent release time timer begins counting down.
Device is still in overcurrent protection mode.
The internal overcurrent release timer continues counting for TOCR seconds.
• The internal overcurrent release timer times out, and VCS21 is still below VOC.
• The device returns from overcurrent protection mode, and is now in normal operation mode.
• The discharge FET is automatically switched ON (UVP/OCP = Vss) - unless the status of UVPC has been changed in the control
register during the overcurrent protection mode.
• The status of the charge FET remains unaffected.
• Discharge of the battery cells is once again possible.
24
FN8246.0
December 22, 2004
X3102
Monitor Mode
Analog Multiplexer Selection
AS1
AS0
L
L
L
VSS(1)
L
L
H
VCELL1–VCELL2 (VCELL12)
L
H
L
VCELL2–VCELL3 (VCELL23)
R2
+
AO OUTPUT
H
H
VCELL3–VCELL4 (VCELL34)
H
L
L
VCELL4–Vss (VCELL4)
H
L
H
VCS1–VCS2 (VCS12)(2)
H
H
L
VCS2–VCS1 (VCS21)(2)
H
H
H
VSS
AO
OP1
R2
R1
L
AS0
AS1
AS2
Analog MUX
Cell 2 Voltage
Cell 3 Voltage
Cell 4 Voltage
2.5V
TABLE 25. AO SELECTION MAP
AS2
Cell 1 Voltage
Voltage
Level
Shifters
The X3102 can be used to externally monitor individual
battery cell voltages, and battery current. Each quantity can
be monitored at the analog output pin (AO), and is selected
using the analog select (AS0–AS2) pins (Table 25). Also,
see Figure 15.
S0
R1
Config
Register
Gain
Setting
SPI
SCL
I/F
CS
CSG1 CSG0
Cross-Bar
Switch
SI
Overcurrent
Protection
X3102
NOTES:
VCS1
1. This is the normal state of the X3102. While in this state Overcharge and Over-discharge Protection conditions are
periodically monitored (See “Periodic Protection Monitoring” on
page 19.)
2. VCS1, VCS2 are read at AO with respect to a DC bias voltage of
2.5V (See section “Current Monitor Function” on page 25).
Current Monitor Function
The voltages monitored at pins VCS1 and VCS2 can be
used to calculate current flowing through the battery
terminals, using an off-board microcontroller with an A/D.
Since the value of the sense resistor (RSENSE) is small
(typically in the order of tens of mΩ), and since the resolution
of various A/D converters may vary, the voltage across
RSENSE (VCS1 and VCS2) is amplified internally with a gain
of between 10 and 160, and output to pin AO (Figure 15).
VCS2
P-
RSENSE
FIGURE 15. MONITOR CIRCUIT
The internal gain of the X3102 current sense voltage
amplifier can be selected by using the WCNTR Instruction to
set bits CSG1 and CSG0 in the control register (Table 14).
The CSG1 and CSG0 bits select one of four input resistors
to Op Amp OP1. The feedback resistors remain constant.
This ratio of input to feedback resistors determines the gain.
Putting external resistors in series with the inputs reduces the
gain of the amplifier.
VCS1 and VCS2 are read at AO with respect to a DC bias
voltage of 2.5V. Therefore, the voltage range of VCS12 and
VCS21 changes depending upon the direction of current flow
(i.e. battery cells are in Charge or Discharge - Table 21).
TABLE 26. AO VOLTAGE RANGE FOR VCS12 AND VCS21
AO
CELL STATE
AO VOLTAGE RANGE
VCS12
Charge
2.5V ≤ AO ≤ 5.0V
VCS12
Discharge
0V ≤ AO ≤ 2.5V
VCS21
Charge
0V ≤ AO ≤ 2.5V
VCS21
Discharge
2.5V ≤ AO ≤ 5.0V
By calculating the difference of VCS12 and VCS21 the offset
voltage of the internal op-amp circuitry is cancelled. This
allows for the accurate calculation of current flow into and
out of the battery cells.
Pack current is calculated using the following formula:
( VCS 12 – VCS 21 )
Pack Current = --------------------------------------------------------------------------------------------------------( 2 ) ( gain setting )(current sense resistor)
25
FN8246.0
December 22, 2004
X3102
Voltage Regulator
The X3102 is able to supply peripheral devices with a regulated
5VDC±0.5% output at pin RGO. The voltage regulator should
be configured externally as shown in Figure 16.
The non-inverting input of OP1 is fed with a high precision
5VDC supply. The voltage at the output of the voltage
regulator (VRGO) is compared to this 5V reference via the
inverting input of OP1. The output of OP1 in turn drives the
regulator pnp transistor (Q1). The negative feedback at the
regulator output maintains the voltage at 5VDC ±0.5%
(including ripple) despite changes in load, and differences in
regulator transistors.
Tuning
5VDC
Precision
Voltage
Reference
Typical values for RLMT and ILMT are shown in Table 27. In
order to protect the voltage regulator circuitry from damage
in case of a short-circuit, RLMT ≥ 10Ω should always be
used.
TABLE 27. TYPICAL VALUES FOR RLMT AND ILMT
RLMT
VOLTAGE REGULATOR CURRENT LIMIT (ILMT)
10Ω
250mA ± 50% (Typical)
25Ω
100mA ± 50% (Typical)
50Ω
50mA ± 50% (Typical)
When choosing the value of RLMT, the drive limitations of the
PNP transistor used should also be taken into consideration.
The transistor should have a gain of at least 100 to support
an output current of 250mA.
Un-Regulated
Voltage
Input
RLMT
X3102
Q2
+
_
RGP
ILMT
RGC
Q1
OP1
Regulated
When power is applied to pin VCC of the X3102, VRGO is
regulated to 5VDC±10% for a nominal time of TOC+2ms.
During this time period, VRGO is “tuned” to attain a final
value of 5VDC ±0.5% (Figure 8).
The maximum current that can flow from the voltage
regulator (ILMT) is controlled by the current limiting resistor
(RLMT) connected between RGP and VCC. When the voltage
across VCC and RGP reaches a nominal 2.5V (i.e. the
threshold voltage for the FET), Q2 switches ON, shorting VCC
to the base of Q1. Since the base voltage of Q1 is now
higher than the emitter voltage, Q1 switches OFF, and hence
the supply current goes to zero.
VCC
To Internal Voltage
Regulating Circuitry
RGO
5VDC Output
0.1
µF
VRGO
FIGURE 16. VOLTAGE REGULATOR OPERATION
4KBit EEPROM Memory
The X3102 contains a CMOS 4k-bit serial EEPROM,
internally organized as 512 x 8 bits. This memory is
accessible via the SPI port, and features the IDLock
function.
The 4kbit EEPROM array can be accessed by the SPI port at
any time, even during a protection mode, except during sleep
mode. After power is applied to VCC of the X3102, EEREAD
and EEWRITE Instructions can be executed only after times
tPUR (power up to read time) and tPUW (power up to write
time) respectively.
IDLock is a programmable locking mechanism which allows
the user to lock data in different portions of the EEPROM
memory space, ranging from as little as one page to as
much as 1/2 of the total array. This is useful for storing
information such as battery pack serial number,
manufacturing codes, battery cell chemistry data, or cell
characteristics.
EEPROM Write Enable Latch
The X3102 contains an EEPROM “Write Enable” latch. This
latch must be SET before a write to EEPROM operation is
initiated. The WREN instruction will set the latch and the
WRDI instruction will reset the latch (Figure 17). This latch is
automatically reset upon a power-up condition and after the
completion of a byte or page write cycle.
IDLock Memory
Intersil’s IDLock memory provides a flexible mechanism to
store and lock battery cell/pack information. There are seven
distinct IDLock memory areas within the array which vary in
size from one page to as much as half of the entire array.
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X3102
Prior to any attempt to perform an IDLock operation, the
WREN instruction must first be issued. This instruction sets
the “Write Enable” latch and allows the part to respond to an
IDLock sequence. The EEPROM memory may then be
IDLocked by writing the SET IDL instruction (Table 30 and
Figure 25), followed by the IDLock protection byte.
TABLE 28. IDLock PARTITION BYTE DEFINITION
IDLock PROTECTION
BYTES
EEPROM MEMORY ADDRESS
IDLocked
0000 0000
None
0000 0001
000h–07Fh
0000 0010
080h–0FFh
0000 0011
100h–17Fh
0000 0100
180h–1FFh
0000 0101
000h–0FFh
0000 0110
000h–00Fh
0000 0111
1F0h–1FFh
memory array that are IDLocked can be read but not written
until IDLock is removed or changed.
TABLE 29. IDLock REGISTER
7
6
5
4
3
2
1
0
0
0
0
0
0
IDL2
IDL1
IDL0
NOTE: Bits [7:3] specified to be “0’s”.
X3102 SPI Serial Communication
The X3102 is designed to interface directly with the
synchronous Serial Peripheral Interface (SPI) of many
popular microcontroller families. This interface uses four
signals, CS, SCK, SI and SO. The signal CS when low,
enables communications with the device. The SI pin carries
the input signal and SO provides the output signal. SCK
clocks data in or out. The X3102 operates in SPI mode 0
which requires SCK to be normally low when not transferring
data. It also specifies that the rising edge of SCK clocks data
into the device, while the falling edge of SCK clocks data out.
The IDLock protection byte contains the IDLock bits IDL2IDL0, which defines the particular partition to be locked
(Table 28). The rest of the bits [7:3] are unused and must be
written as zeroes. Bringing CS HIGH after the two byte
IDLock instruction initiates a nonvolatile write to the status
register. Writing more than one byte to the status register will
overwrite the previously written IDLock byte.
Once an IDLock instruction has been completed, that IDLock
setup is held in a nonvolatile IDLock Register (Table 29) until
the next IDLock instruction is issued. The sections of the
This SPI port is used to set the various internal registers,
write to the EEPROM array, and select various device
functions.
The X3102 contains an 8-bit instruction register. It is
accessed by clocking data into the SI input. CS must be
LOW during the entire operation. Table 30 contains a list of
the instructions and their opcodes. All instructions,
addresses and data are transferred MSB first.
Data input is sampled on the first rising edge of SCK after
CS goes LOW. SCK is static, allowing the user to stop the
clock, and then start it again to resume operations where
left off.
TABLE 30. INSTRUCTION SET
INSTRUCTION
NAME
INSTRUCTION
FORMAT*
WREN
0000 0110
Set the write enable latch (write enable operation) (Figure 17)
WRDI
0000 0100
Reset the write enable latch (write disable operation) (Figure 17)
EEWRITE
0000 0010
Write command followed by address/data (4kbit EEPROM) (Figure 18, Figure 19)
EEREAD STAT
0000 0101
Reads IDLock settings & status of EEPROM EEWRITE instruction (Figure 20)
EEREAD
0000 0011
Read operation followed by address (for 4kbit EEPROM) (Figure 21)
WCFIG
0000 1001
Write to configuration register followed by two bytes of data (Figure 10, Figure 22). Data stored in
SRAM only and will power-up to previous settings (Figure 9)
WCNTR
0000 1010
Write to control register, followed by two bytes of data (Figure 23)
RDSTAT
0000 1011
Read contents of status register (Figure 24)
SET IDL
0000 0001
Set EEPROM ID lock partition followed by partition byte (Figure 25)
DESCRIPTION
*Instructions have the MSB in leftmost position and are transferred MSB first.
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December 22, 2004
X3102
Write Enable/Write Disable (WREN/WRDI)
the data to be written. Only the last 9 bits of the address are
used and bits [15:9] are specified to be zeroes. This is
minimally a thirty-two clock operation. CS must go LOW and
remain LOW for the duration of the operation. The host may
continue to write up to 16 bytes of data to the X3102. The
only restriction is the 16 bytes must reside on the same
page. If the address counter reaches the end of the page
and the clock continues, the counter will “roll over” to the first
address of the page and overwrite any data that may have
been previously written.
Any write to a nonvolatile array or register, requires the
WREN command be sent prior to the write command. This
command sets an internal latch allowing the write operation to
proceed. The WRDI command resets the internal latch if the
system decides to abort a write operation. See Figure 17.
CS
0
1
2
3
4
5
6
For a byte or page write operation to be completed, CS can
only be brought HIGH after bit 0 of the last data byte to be
written is clocked in. If it is brought HIGH at any other time,
the write operation will not be completed. Refer to Figure 18
and Figure 19 for detailed illustration of the write sequences
and time frames in which CS going HIGH are valid.
7
SCK
WREN
Instruction
(1 Byte)
SI
SO
EEPROM Read Status Operation (EEREAD STAT)
WRDI
High Impedance
If there is not a nonvolatile write in progress, the EEREAD
STAT instruction returns the IDLock byte from the IDLock
register which contains the IDLock bits IDL2-IDL0 (Table 29).
The IDLock bits define the IDLock condition (Table 28). The
other bits are reserved and will return ‘0’ when read.
FIGURE 17. EEPROM WRITE ENABLE LATCH (WREN/WRDI)
OPERATION SEQUENCE
EEPROM Write Sequence (EEWRITE)
Prior to any attempt to write data into the EEPROM of the
X3102, the “Write Enable” latch must first be set by issuing
the WREN instruction (See Table 30 and Figure 17). CS is
first taken LOW. Then the WREN instruction is clocked into
the X3102. After all eight bits of the instruction are
transmitted, CS must then be taken HIGH. If the user
continues the write operation without taking CS HIGH after
issuing the WREN instruction, the write operation will be
ignored.
If a nonvolatile write to the EEPROM (i.e. EEWRITE
instruction) is in progress, the EEREAD STAT returns a
HIGH on SO. When the nonvolatile write cycle in the
EEPROM is completed, the status register data is read out.
Clocking SCK is valid during a nonvolatile write in progress,
but is not necessary. If the SCK line is clocked, the pointer to
the status register is also clocked, even though the SO pin
shows the status of the nonvolatile write operation (See
Figure 20).
To write data to the EEPROM memory array, the user issues
the EEWRITE instruction, followed by the 16 bit address and
CS
0
1
2
3
4
5
6
7
8
9
20
21
22
23
24
25
26
27
28
29
30
31
SCK
EEWRITE Instruction
(1 Byte)
Byte Address (2 Byte)
15
SI
14
3
2
Data Byte
1
0
7
6
5
4
3
2
1
0
High Impedance
SO
FIGURE 18. EEPROM BYTE WRITE (EEWRITE) OPERATION SEQUENCE
28
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December 22, 2004
X3102
CS
0
1
2
3
4
5
6
7
8
9
20
10
21
22
23
24
25
26
27
28
29
30
31
1
0
SCK
EEWRITE
Instruction
Byte Address
(2 Byte)
15
SI
14
13
3
Data Byte 1
2
1
0
7
6
5
4
3
2
38
39
40
41
42
43
44
45
46
47
1
0
6
5
151
37
150
36
149
35
148
34
147
33
146
32
145
CS
1
0
SCK
Data Byte 2
SI
7
6
5
4
3
Data Byte 3
2
1
0
7
6
5
4
3
2
Data Byte 16
4
3
2
FIGURE 19. EEPROM PAGE WRITE (EEWRITE) OPERATION SEQUENCE
CS
0
1
2
3
4
5
6
7
...
SCK
EEREAD STAT
Instruction
...
SI
Nonvolatile EEWRITE in Progress
I
D
L
2
SO
SO High During Nonvolatile
EEWRITE Cycle
I
D
L
1
I
D
L
0
...
SO=Status Reg Bit When No Nonvolatile
EEWRITE Cycle
FIGURE 20. EEPROM READ STATUS (EEREAD STAT) OPERATION SEQUENCE
EEPROM Read Sequence (EEREAD)
When reading from the X3102 EEPROM memory, CS is first
pulled LOW to select the device. The 8-bit EEREAD instruction
is transmitted to the X3102, followed by the 16-bit address,
of which the last 9 bits are used (bits [15:9] specified to be
zeroes). After the EEREAD opcode and address are sent, the
data stored in the memory at the selected address is shifted
out on the SO line. The data stored in memory at the next
address can be read sequentially by continuing to provide
clock pulses. The address is automatically incremented to the
next higher address after each byte of data is shifted out.
When the highest address is reached (01FFh), the address
counter rolls over to address 0000h, allowing the read cycle
29
to be continued indefinitely. The read operation is terminated
by taking CS HIGH. Refer to the EEPROM Read (EEREAD)
operation sequence illustrated in Figure 21.
Write Configuration Register (WCFIG)
The Write Configuration Register (WCFIG) instruction
updates the static part of the Configuration Register. These
new values take effect immediately, for example writing a
new Over-discharge voltage limit. However, to make these
changes permanent, so they remain if the cell voltages are
removed, an EEWRITE operation to the EEPROM array is
required following the WCFIG command. This command is
shown in Figure 22.
FN8246.0
December 22, 2004
X3102
CS
0
1
2
3
4
5
6
7
8
20
9
21
22
23
24
25
26
27
28
29
30
31
1
0
SCK
EEREAD Instruction
(1 Byte)
Data Out
Byte Address (2 Byte)
15
SI
3
14
2
1
0
High Impedance
7
SO
6
5
4
3
2
FIGURE 21. EEPROM (EEREAD) READ OPERATION SEQUENCE
CS
0
1
2
3
4
5
6
7
8
20
9
21
22
23
2
1
0
SCK
Configuration
Register Data
WCFIG Instruction
15
SI
3
14
(2 BYTE)
(1 BYTE)
High Impedance
SO
FIGURE 22. WRITE CONFIGURATION REGISTER (WCFIG) OPERATION SEQUENCE
CS
0
1
2
3
4
5
6
7
8
18
9
19
20
21
22
23
4
3
2
1
0
SCK
Control
Register Data
WCNTR Instruction
15
SI
(1 Byte)
5
14
(2 Byte)
High Impedance
SO
Control
Bits
Old Control Bits
New Control Bits
FIGURE 23. WRITE CONTROL REGISTER (WCNTR) OPERATION SEQUENCE
Write Control Register (WCNTRL)
The Write Control Register (WCNTRL) instruction updates
the contents of the volatile Control Register. This command
sets the status of the FET control pins, the cell balancing
outputs, the current sense gain and external entry to the
30
sleep mode. Since this instruction controls a volatile
register, no other commands are required and there is no
delay time needed after the instruction, before subsequent
commands. The operation of the WCNTRL command is
shown in Figure 23.
FN8246.0
December 22, 2004
X3102
Read Status Register (RDSTAT)
Set ID Lock (SET IDL)
The Read Status Register (RDSTAT) command returns the
status of the X3102. The Status Register contains three bits
that indicate whether the voltage regulator is stabilized, and
if there are any protection failure conditions. The operation
of the RDSTAT instruction is shown in Figure 24.
The contents of the EEPROM memory array in the X3102
can be locked in one of eight configurations using the SET
ID lock command. When a section of the EEPROM array is
locked, the contents cannot be changed, even when a valid
write operation attempts a write to that area. The SET IDL
command operation is shown in Figure 25.
CS
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
2
1
0
SCK
RDSTAT
Instruction
SI
(1 Byte)
SO
High Impedance
Status Register Output
FIGURE 24. READ STATUS REGISTER (RDSTAT) OPERATION SEQUENCE
CS
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
I
D
L
2
I
D
L
1
I
D
L
0
SCK
Set IDL
Instruction
SI
IDLock
Byte
High Impedance
SO
FIGURE 25. EEPROM IDLock (SET IDL) OPERATION SEQUENCE
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December 22, 2004
X3102
28-Lead Plastic, TSSOP, Package Code V28
.026 (.65) BSC
.169 (4.3)
.252 (6.4) BSC
.177 (4.5)
.377 (9.60)
.385 (9.80)
.047 (1.20)
.0075 (.19)
.0118 (.30)
.002 (.06)
.005 (.15)
.010 (.25)
Gage Plane
0° – 8°
(4.16) (7.72)
Seating Plane
.020 (.50)
.030 (.75)
(1.78)
Detail A (20X)
(0.42)
(0.65)
.031 (.80)
.041 (1.05)
All Measurements are Typical
See Detail “A”
NOTE: All dimensions in inches (in parentheses in millimeters)
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
32
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