XICOR X3100

APPLICATION NOTE
A V A I L A B L E
3 or 4 Cell Li-Ion BATTERY PACKS
Preliminary Information
Preliminary
X3100/X3101
4 cell / 3 cell
3 or 4 Cell Li-Ion Battery Protection and Monitor IC
FEATURE
BENEFIT
• Software Selectable Protection Levels and
Variable Protect Detection/Release Times
• Integrated FET Drive Circuitry
• Cell Voltage and Current Monitoring
• 0.5% Accurate Voltage Regulator
• Integrated 4kbit EEPROM
• Flexible Power Management with 1µA Sleep
Mode
• Cell Balancing Control
• Optimize protection for chosen cells to allow
maximum use of pack capacity.
• Reduce component count and cost
• Simplify implementation of gas gauge
• Accurate voltage and current measurements
• Record battery history to optimize gas gauge,
track pack failures and monitor system use
• Reduce power to extend battery life
• Increase battery capacity and improve cycle life
battery life
DESCRIPTION
Using an internal analog multiplexer, the X3100 or
X3101 allow battery parameters such as cell voltage
and current (using a sense resistor) to be monitored
externally by a separate microcontroller with A/D
converter. Software on this microcontroller implements
gas gauge and cell balancing functionality in software.
The X3100 is a protection and monitor IC for use in
battery packs consisting of 4 series Lithium-Ion
battery cells. The X3101 is designed to work in 3 cell
applications. Both devices provide internal overcharge, over-discharge, and over-current protection
circuitry, internal EEPROM memory, an internal
voltage regulator, and internal drive circuitry for
external FET devices that control cell charge,
discharge, and cell voltage balancing.
Over-charge, over-discharge, and over-current
thresholds reside in an internal EEPROM memory
register and are selected independently via software
using a 3MHz SPI serial interface. Detection and timeout delays can also be individually varied using
external capacitors.
The X3100 and X3101 contain a current sense
amplifier. Selectable gains of 10, 25, 80 and 160 allow
an external 10 bit A/D converter to achieve better
resolution than a more expensive 14 bit converter.
An internal 4kbit EEPROM memory featuring
IDLock™, allows the designer to partition and “lock in”
written battery cell/pack data.
The X3100 and X3101 are each housed in a 28 Pin
TSSOP package.
FUNCTIONAL DIAGRAM
VCC
5VDC
Regulator
VCELL1
CB1
VCELL2
CB2
VCELL3
CB3
Over-charge
Over-discharge
Protection
Sense
Circuits
Protection
Sample Rate
Timer
VSS
UVP/OCP
OVP/LMON
FET Control
Circuitry
Analog
MUX
VCS1 VCS2
Protection Circuit
Timing Control
& Configuration
AS0
AS1
AS2
AO
Internal Voltage Regulator
Power On reset &
Status Register
4 kbit
EEPROM
Over-current
Protection &
Current Sense
VCELL4/VSS
CB4
REV 1.1.8 12/10/02
RGP RGC RGO
Configuration
Register
Control
Register
S0
SPI
SCK
I/F
CS
SI
OVT UVT OCT
www.xicor.com
Characteristics subject to change without notice.
1 of 40
X3100/X3101 – Preliminary Information
PRINCIPLES OF OPERATION
PIN NAMES
The X3100 and X3101 provide two distinct levels of
functionality and battery cell protection:
Pin
First, in Normal mode, the device periodically checks
each cell for an over-charge and over-discharge state,
while continuously watching for a pack over-current
condition. A protection mode violation results from an
over-charge, over-discharge, or over-current state. The
thresholds for these states are selected by the user
through software. When one of these conditions occur, a
Discharge FET or a Charge FET or both FETs are
turned off to protect the battery pack. In an overdischarge condition, the X3100 and X3101 devices go
into a low power sleep mode to conserve battery power.
During sleep, the voltage regulator turns off, removing
power from the microcontroller to further reduce pack
current.
2
Second, in Monitor mode, a microcontroller with A/D
converter measures battery cell voltage and pack current
via pin AO and the X3100 or X3101 on-board MUX. The
user can thus implement protection, charge/discharge,
cell balancing or gas gauge software algorithms to suit
the specific application and characteristics of the cells
used. While monitoring these voltages, all protection
circuits are on continuously.
In a typical application, the microcontroller is also
programmed to provide an SMBus interface along with
the Smart Battery System interface protocols. These
additions allow an X3100 or X3101 based module to
adhere to the latest industry battery pack standards.
PIN CONFIGURATION
28 Lead TSSOP
1
3
4
5
6
7
Symbol
Description
VCELL1 Battery cell 1 voltage input
CB1
Cell balancing FET control output 1
VCELL2 Battery cell 2 voltage
CB2
Cell balancing FET control output 2
VCELL3 Battery cell 3 voltage
CB3
Cell balancing FET control output 3
VCELL4/ Battery cell 4 voltage (X3100)
VSS
Ground (X3101)
8
CB4
Cell balancing FET control output 4
9
VSS
Ground
10
VCS1
Current sense voltage pin 1
11
VCS2
Current sense voltage pin 2
12
OVT
Over-charge detect/release time input
13
UVT
Over-discharge detect/release time input
14
OCT
Over-current detect/release time input
15
AO
Analog multiplexer output
16
AS0
Analog output select pin 0
17
AS1
Analog output select pin 1
18
AS2
Analog output select pin 2
19
SI
Serial data input
20
SO
21
SCK
Serial data output
22
CS
23
OVP/
LMON
Over-charge Voltage Protection output/
Load Monitor output
24
UVP/
OCP
Over-discharge protection output/
Over-current protection output
Serial data clock input
Chip select input pin
VCELL1
1
28
VCC
CB1
VCELL2
2
27
RGP
25
RGO
Voltage regulator output pin
3
26
RGC
26
RGC
Voltage regulator control pin
CB2
4
25
RGO
27
RGP
Voltage regulator protection pin
28
VCC
Power supply
VCELL3
5
24
UVP/OCP
CB3
6
23
OVP/LMON
VCELL4/VSS*
7
CB4
VSS
8
X3100/
X3101 22
21
9
20
VCS1
10
Battery Cell Voltage (VCELL1-VCELL4):
19
SI
AS2
These pins are used to monitor the voltage of each
battery cell internally. The voltage of an individual cell
can also be monitored externally at pin AO.
11
18
OVT
12
13
17
16
14
15
*For X3101, Connect to ground.
REV 1.1.8 12/10/02
PIN DESCRIPTIONS
SCK
SO
VCS2
UVT
OCT
CS
AS1
AS0
AO
The X3100 monitors 4 battery cells. The X3101 monitors
3 battery cells. For the X3101 device connect the
VCELL4/VSS pin to ground.
www.xicor.com
Characteristics subject to change without notice.
2 of 40
X3100/X3101 – Preliminary Information
Cell Voltage Balancing Control (CB1-CB4):
These outputs are used to switch external FETs in order
to perform cell voltage balancing control. This function
can be used to adjust individual cell voltages (e.g.
during cell charging). CB1–CB4 can be driven high
(Vcc) or low (Vss) to switch external FETs ON/OFF. When
using the X3101, the CB4 pin can be left unconnected,
or the FET control can be used for other purposes.
Analog Output Select (AS0–AS2):
These pins select which voltage is to be multiplexed to
the output AO (see section “Sleep Control (SLP)” on
page 10 and section “Current Monitor Function” on
page 20)
Serial Input (SI):
SI is the serial data input pin. All opcodes, byte
addresses, and data to be written to the device are input
on this pin.
Current Sense Inputs (VCS1–VCS2):
A sense resistor (RSENSE) is connected between VCS1
and VCS2 (Figure 1). RSENSE has a resistance in the
order of 20mΩ to 100mΩ, and is used to monitor current
flowing through the battery terminals, and protect
against over-current conditions. The voltage at each end
of RSENSE can also be monitored at pin AO.
Serial Output (SO):
SO is a push/pull serial data output pin. During a read
cycle, data is shifted out on this pin. Data is clocked out
by the falling edge of the serial clock. While CS is HIGH,
SO will be in a High Impedance state.
Over-charge Voltage detect Time control (OVT):
This pin is used to control the delay time (TOV)
associated with the detection of an over-charge
condition (see section “Over-charge Protection” on page
13).
Note: SI and SO may be tied together to form one line
(SI/SO). In this case, all serial data communication with
the X3100 or X3101 is undertaken over one I/O line.
This is permitted ONLY if no simultaneous read/write
operations occur.
Over-discharge detect/release time control (UVT):
This pin is used to control the delay times associated
with the detection (TUV) and release (TUVR) of an overdischarge (under-voltage) condition (see section “Overdischarge Protection” on page 15).
Serial Clock (SCK):
The Serial Clock controls the serial bus timing for data
input and output. Opcodes, addresses, or data present
on the SI pin are latched on the rising edge of the clock
input, while data on the SO pin change after the falling
edge of the clock input.
Over-current detect/release time control (OCT):
This pin is used to control the delay times associated
with the detection (TOC) and release (TOCR) of an overcurrent condition (see section “Over-Current Protection”
on page 18).
Chip Select (CS):
When CS is HIGH, the device is deselected and the SO
output pin is at high impedance. CS LOW enables the
SPI serial bus.
Analog Output (AO):
The analog output pin is used to externally monitor
various battery parameter voltages. The voltages which
can be monitored at AO (see section “Analog
Multiplexer Selection” on page 20) are:
– Individual cell voltages
– Voltage across the current sense resistor (RSENSE).
This voltage is amplified with a gain set by the user in
the control register (see section “Current Monitor
Function” on page 20.)
The analog select pins pins AS0–AS2 select the desired
voltage to be monitored on the AO pin.
REV 1.1.8 12/10/02
Over-charge Voltage Protection/Load Monitor
(OVP/LMON):
This one pin performs two functions depending upon
the present mode of operation of the X3100 or X3101.
—Over-charge Voltage Protection (OVP)
This pin controls the switching of the battery pack charge
FET. This power FET is a P-channel device. As such,
cell charge is possible when OVP/LMON=VSS, and cell
charge is prohibited when OVP/LMON=VCC. In this
configuration the X3100 and X3101 turn off the charge
voltage when the cells reach the over-charge limit. This
prevents damage to the battery cells due to the
application of charging voltage for an extended period of
time (see section “Over-charge Protection” on page 13).
www.xicor.com
Characteristics subject to change without notice.
3 of 40
X3100/X3101 – Preliminary Information
—Load Monitor (LMON)
In Over-current Protection mode, a small test current
(7.5µA typ.) is passed out of this pin to sense the load
resistance. The measured load resistance determines
whether or not the X3100 or X3101 returns from an
over-current protection mode (see section “Over-Current
Protection” on page 18).
Over-discharge (Under Voltage) Protection/
Over-current Protection (UVP/OCP):
Pin UVP/OCP controls the battery cell discharge via an
external power FET. This P-channel FET allows cell
discharge when UVP/OCP=Vss, and prevents cell
discharge when UVP/OCP=Vcc. The X3100 and X3101
turn the external power FET off when the X3100 or
X3101 detects either:
—Over-discharge Protection (UVP)
In this case, pin 24 is referred to as “Over-discharge
(Under-Voltage) protection (UVP)” (see section “Overdischarge Protection” on page 15). UVP/OCP turns off
the FET to prevent damage to the battery cells by being
discharged to excessively low voltages.
—Over-current protection (OCP)
In this case, pin 24 is referred to as “Over-current
protection (OCP)” (see section “Over-Current Protection”
on page 18). UVP/OCP turns off the FET to prevent
damage to the battery pack caused by excessive current
drain (e.g. as in the case of a surge current resulting
from a stalled disk drive).
TYPICAL APPLICATION CIRCUIT
The X3100 and X3101 have been designed to operate
correctly when used as connected in the Typical
Application Circuit (see Figure 1 on page 5).
The power MOSFET’s Q1 and Q2 are referred to as the
“Discharge FET” and “Charge FET,” respectively. Since
these FETs are p-channel devices, they will be ON when
the gates are at VSS, and OFF when the gates are at
VCC. As their names imply, the discharge FET is used to
control cell discharge, while the charge FET is used to
control cell charge. Diode D1 allows the battery cells to
receive charge even if the Discharge FET is OFF, while
diode D2 allows the cells to discharge even if the charge
FET is OFF. D1 and D2 are integral to the Power FETs. It
should be noted that the cells can neither charge nor
discharge if both the charge FET and discharge FET are
OFF.
Power to the X3100 or X3101 is applied to pin VCC via
diodes D6 and D7. These diodes allow the device to be
REV 1.1.8 12/10/02
powered by the Li-Ion battery cells in normal operating
conditions, and allow the device to be powered by an
external source (such as a charger) via pin P+ when the
battery cells are being charged. These diodes should
have sufficient current and voltage ratings to handle both
cases of battery cell charge and discharge.
The operation of the voltage regulator is described in
section “Voltage Regulator” on page 21. This regulator
provides a 5VDC±0.5% output. The capacitor (C1)
connected from RGO to ground provides some noise
filtering on the RGO output. The recommended value is
0.1µF or less. The value chosen must allow VRGO to
decay to 0.1V in 170ms or less when the X3100 or
X3101 enter the sleep mode. If the decay is slower than
this, a resistor (R1) can be placed in parallel with the
capacitor.
During an initial turn-on period (TPUR + TOC), VRGO has
a stable, regulated output in the range of 5VDC ± 10%
(see Figure 2). The selection of the microcontroller
should take this into consideration. At the end of this turn
on period, the X3100 and X3101 “self-tunes” the output
of the voltage regulator to 5V+/-0.5%. As such, VRGO
can be used as a reference voltage for the A/D converter
in the microcontroller. Repeated power up operations,
consistently re-apply the same “tuned” value for VRGO.
Figure 1 shows a battery pack temperature sensor
implemented as a simple resistive voltage divider,
utilizing a thermistor (RT) and resistor (RT’). The voltage
VT can be fed to the A/D input of a microcontroller and
used to measure and monitor the temperature of the
battery cells. RT’ should be chosen with consideration of
the dynamic resistance range of RT as well as the input
voltage range of the microcontroller A/D input. An output
of the microcontroller can be used to turn on the
thermistor divider to allow periodic turn-on of the sensor.
This reduces power consumption since the resistor
string is not always drawing current.
Diode D3 is included to facilitate load monitoring in an
Over-current protection mode (see section “OverCurrent Protection” on page 18), while preventing the
flow of current into pin OVP/LMON during normal
operation. The N-Channel transistor turns off this
function during the sleep mode.
Resistor RPU is connected across the gate and drain of
the charge FET (Q2). The discharge FET Q1 is turned
off by the X3100 or X3101, and hence the voltage at pin
OVP/LMON will be (at maximum) equal to the voltage of
the battery terminal, minus one forward biased diode
voltage drop (VP+–VD7). Since the drain of Q2 is
connected to a higher potential (VP+) a pull-up resistor
www.xicor.com
Characteristics subject to change without notice.
4 of 40
REV 1.1.8 12/10/02
www.xicor.com
B-
RCB
RCB
RCB
100
100
100
100
8
0.01uF
7
0.01uF
6
5
0.01uF
4
3
0.01uF
2
1
1µF
For the X3101, or X3100
when 3 cells are used,
VCELL4/VSS MUST be
tied to Ground (Vss). CB4
is left unconnected.
Q9
Q8
Q7
Q6
RCB
B+
3 or 4
Li-Ion cells†
9
VSS
CB4
RSENSE
10
11
VCS1 VCS2
VCELL4/VSS
CB3
UVT
COV
12
CUV
13
14
COC
OCT
AO
AS2
AS1
AS0
SI
VCELL3
CS
SCK
SO
OVT
X3100/X3101
1M
15
17
16
18
22
21
20
19
(Optional)
R1
1M
VT
Choose R1 and
C1 such that
VRGO goes to
0.1V (or less) in
170ms (or less)
when entering
the Sleep Mode
(at 25oC).
C1
0.1µF
Q10
D3
ILMON
Charge FET
RPU
CB2
VCELL2
CB1
VCELL1
UVP/ OVP/
OCP LMON
RGO
RGC
RGP
VCC
23
24
25
26
VRGO
Q2
27
RLMT
Q3
Q1
D1 D2
28
.
Discharge FET
ILMT
BAT54 BAT54
D6 D7
RT
RT’
GP
I/O
A/D Input
A/D Input
GP
I/O
A/D
Ref
VCC
GP
I/O
Reset
µC,
ASIC
Q4
SMBCLK
100
100 SMBDATA
Set High
after power
up to enable
SMBus and
LMON
P-
FETs Q4 and Q5 are needed
only if external pull-ups on
the SMBus lines cause
voltage to appear at the uC
Vcc pin during sleep mode.
Q5
CPOR
RPOR
Transistor Recommendations
Q1, Q2 = Si4435
Q3 = 2N3906
Q4 - Q10 = 2N7002
P+
X3100/X3101 – Preliminary Information
Figure 1. Typical Application Circuit
Characteristics subject to change without notice.
5 of 40
X3100/X3101 – Preliminary Information
(RPU) in the order of 1MΩ should be used to ensure that
the charge FET is completely turned OFF when OVP/
LMON=VCC.
The capacitors on the VCELL1 to VCELL4 inputs are used
in a first order low pass filter configuration, at the battery
cell voltage monitoring inputs (VCELL1–VCELL4) of the
X3100 or X3101. This filter is used to block any
unwanted interference signals from being inadvertently
injected into the monitor inputs. These interference
signals may result from:
– Transients created at battery contacts when the battery pack is being connected/disconnected from the
charger or the host.
– Electrostatic discharge (ESD) from something/someone touching the battery contacts.
– Unfiltered noise that exists in the host device.
– RF signals which are induced into the battery pack
from the surrounding environment.
Such interference can cause the X3100 or X3101 to
operate in an unpredictable manner, or in extreme
cases, damage the device. As a guide, the capacitor
should be in the order of 0.01µF and the resistor, should
be in the order of 10KΩ. The capacitors should be of the
ceramic type. In order to minimize interference, PCB
tracks should be made as short and as wide as possible
to reduce their impedance. The battery cells should also
be placed as close to the X3100 or X3101 monitor inputs
as possible.
Resistors RCB and the associated n-channel MOSFET’s
(Q6–Q9) are used for battery cell voltage balancing. The
X3100 and X3101 provide internal drive circuitry which
allows the user to switch FETs Q6–Q9 ON or OFF via
the microcontroller and SPI port (see section “Cell
Voltage Balance Control (CBC1-CBC4)” on page 11).
When any of the these FETs are switched ON, a
current, limited by resistor RCB, flows across the
particular battery cell. In doing so, the user can control
the voltage across each individual battery cell. This is
important when using Li-Ion battery cells since
imbalances in cell voltages can, in time, greatly reduce
the usable capacity of the battery pack. Cell voltage
balancing may be implemented in various ways, but is
usually performed towards the end of cell charging
(“Top-of-charge method”). Values for RCB will vary
according to the specific application.
discharge cycles, and minimum/maximum conditions.
Battery pack manufacturing data as well as serial
number information can also be stored in the EEPROM
array. An SPI serial bus provides the communication link
to the EEPROM.
A current sense resistor (RSENSE) is used to measure
and monitor the current flowing into/out of the battery
terminals, and is used to protect the pack from overcurrent conditions (see section “Over-Current
Protection” on page 18). RSENSE is also used to
externally monitor current via a microcontroller (see
section “Current Monitor Function” on page 20).
FETs Q4 and Q5 may be required on general purpose
I/Os of the microcontroller that connect outside of the
package. In some cases, without FETs, pull-up resistors
external to the pack force a voltage on the VCC pin of the
microcontroller during a pack sleep condition. This
voltage can affect the proper tuned voltage of the
X3100/X3101 regulator. These FETs should be turnedon by the microcontroller. (See Figure 1.)
POWER ON SEQUENCE
Initial connection of the Li-Ion cells in the battery pack
will not normally power up the battery pack. Instead, the
X3100 or X3101 enters and remains in the SLEEP
mode. To exit the SLEEP mode, after the initial power up
sequence, or following any other SLEEP MODE, a
minimum of 16V (X3100 VSLR) or 12V (X3101 VSLR) is
applied to the VCC pin, as would be the case during a
battery charge condition. (See Figure 2.)
When VSLR is applied to VCC, the analog select pins
(AS2-AS0) and the SPI communication pins (CS, CLK,
SI, SO) must be low, so the X3100 and X3101 power up
correctly into the normal operating mode. This can be
done by using a power-on reset circuit.
When entering the normal operating mode, either from
initial power up or following the SLEEP MODE, all bits in
the control register are zero. With UVPC and OVPC bits
at zero, the charge and discharge FETs are off. The
microcontroller must turn these on to activate the pack.
The microcontroller would typically check the voltage
and current levels prior to turning on the FETs via the
SPI port. The software should prevent turning on the
FETs throughout an initial measurement/calibration
period. The duration of this period is TOV+200ms or
TUV+200ms, whichever is longer.
The internal 4kbit EEPROM memory can be used to
store the cell characteristics for implementing such
functions as gas gauging, battery pack history, charge/
REV 1.1.8 12/10/02
www.xicor.com
Characteristics subject to change without notice.
6 of 40
X3100/X3101 – Preliminary Information
Figure 2. Power Up Timing (Initial Power Up or after Sleep Mode)
TPUR
VSLR
VCC
0V
5V±10% (Stable and Repeatable)
VRGO Tuned to 5V±0.5%
5V
VRGO
0V
2ms (Typ.)
1
Voltage Regulator Output Status
(Internal Signal)
VRGS
0
TOC
1
1 = X3100/1 in Over-Current Protection Mode
0 = X3100/1 NOT in Over-Current Protection Mode
Over-current Detection Status
(Internal Signal)
OCDS
0
1
Status Register Bit 0
VRGS+OCDS
1 = X3100/1 in Over-Current Protection Mode OR VRGO Not Yet Tuned
0 = X3100/1 NOT in Over-Current Protection Mode AND VRGO Tuned
0
TOV+200ms
1
Status Register Bit 2
(SWCEN=0)
0
CCES+OVDS
1 = VCELL < VCE OR X3100/1 in Over-charge Protection Mode
0 = VCELL > VCE OR X3100/1 NOT in Over-charge Protection Mode
1
Status Register Bit 2
(SWCEN=1)
0
OVDS
From
Microcontroller
1 = X3100/1 in Over-charge Protection Mode
0 = X3100/1 NOT in Over-charge Protection Mode
AS2_AS0
TOV+200ms OR TUV+200ms (whichever is longer)
SPI PORT
Any Read or Write Operation, except
turn-on of FETs can start here.
REV 1.1.8 12/10/02
www.xicor.com
Charge, Discharge FETs can be
turned on here.
Characteristics subject to change without notice.
7 of 40
X3100/X3101 – Preliminary Information
The X3100 and X3101 can be configured for specific
user requirements using the Configuration Register.
Over-discharge Settings
VUV1 and VUV0 control the cell over-discharge (under
voltage threshold) level. See section “Over-discharge
Protection” on page 15.
Table 1. Configuration Register Functionality
Table 5. Over-discharge Threshold Selection.
CONFIGURATION REGISTER
Bit(s)
Name
0-5
–
Configuration
Register Bits
Function
(don’t care)
6
SWCEN
Switch Cell Charge Enable
threshold function ON/OFF
7
CELLN
Set the number of Li-Ion battery
cells used (3 or 4)
8-9
VCE1-VCE0
Select Cell Charge Enable
threshold
10-11
VOC1-VOC0 Select over-current threshold
12-13
VUV1-VUV0
Select over-discharge (under
voltage) threshold
14-15
VOV1-VOV0
Select over-charge voltage
threshold
14
13
VOV1 VOV0
12
VUV1
11
10
VUV1
VUV0
X3100
X3101
0
0
VUV=1.95V
VUV=2.25V
(X3101 default)
0
1
VUV=2.05V
VUV=2.35V
1
0
VUV=2.15V
VUV=2.45V
1
1
VUV=2.25V
(X3100 default)
VUV=2.55V
Over-current Settings
VOC1 and VOC0 control the pack over-current level.
See section “Over-Current Protection” on page 18.
Table 6. Over-Current Threshold Voltage Selection.
Table 2. Configuration Register—Upper Byte
15
Operation
9
8
VUV0 VOC1 VOC0 VCE1
VCE0
Configuration Register Bits
VOC1
VOC0
Operation
0
0
VOC=0.075V (Default)
0
1
VOC=0.100V
1
0
VOC=0.125V
1
1
VOC=0.150V
X3100 Default = 30H; X3101 Default = 00H.
Table 3. Configuration Register—Lower Byte
7
6
5
4
3
2
1
0
CELLN
SWCEN
x
x
x
x
x
x
X3100 Default = C0H; X3101 Default = 40H.
Over-charge Voltage Settings
VOV1 and VOV0 control the cell over-charge level. See
section “Over-charge Protection” on page 13.
Cell Charge Enable Settings
VCE1, VCE0 and SWCEN control the pack charge
enable function. SWCEN enables or disables a circuit
that prevents charging if the cells are at too low a
voltage. VCE1 and VCE0 select the voltage that is
recognized as too low. See section “Sleep Mode” on
page 15.
Table 4. Over-charge Voltage Threshold Selection
Table 7. Cell Charge Enable Function
Configuration Register
Bits
Configuration
Register Bit
VOV1
VOV0
0
0
VOV = 4.20V (Default)
0
1
VOV = 4.25V
0
Charge enable function: ON
1
0
VOV = 4.30V
1
Charge enable function: OFF
1
1
VOV = 4.35V
REV 1.1.8 12/10/02
Operation
www.xicor.com
SWCEN
Operation
Characteristics subject to change without notice.
8 of 40
X3100/X3101 – Preliminary Information
Table 8. Cell Charging Threshold Voltage Selection.
Configuration Register Bits
Figure 3. Power up of Configuration Register
Configuration Register (SRAM)
VCE1
VCE0
0
0
VCE = 0.5V
0
1
VCE = 0.80V
1
0
VCE = 1.10V
1
1
VCE = 1.40V
Upper Byte
Operation
Lower Byte
Recall
Recall
Shadow EEPROM
Cell Number Selection
The X3100 is designed to operate with four (4) Li-Ion
battery cells. The X3101 is designed to operate with
three (3) Li-Ion battery cells. The CELLN bit of the
configuration register (Table 9) sets the number of cells
recognized. For the X3101, the value for CELLN should
always be zero.
The configuration register is designed for unlimited write
operations to SRAM, and a minimum of 1,000,000 store
operations to the EEPROM. Data retention is specified
to be greater than 100 years.
It should be noted that the bits of the shadow EEPROM
are for the dedicated use of the configuration register,
and are NOT part of the general purpose 4kbit
EEPROM array.
The WCFIG command writes to the configuration
Table 9. Selection of Number of Battery Cells1
Configuration
Register Bit
CELLN
Operation
1
4 Li-Ion battery cells (X3100 default)
0
3 Li-Ion battery cells (X3100 or X3101)
The configuration register consists of 16 bits of
NOVRAM memory (Table 2, Table 3). This memory
features a high-speed static RAM (SRAM) overlaid bitfor-bit with non-volatile “Shadow” EEPROM. An
automatic array recall operation reloads the contents of
the shadow EEPROM into the SRAM configuration
register upon power-up (Figure 3).
1.
register, see Table 30 and section “X3100/X3101 SPI
Serial Communication” on page 22.
After writing to this register using a WCFIG instruction,
data will be stored only in the SRAM of the configuration
register. In order to store data in shadow EEPROM, a
WREN instruction, followed by a EEWRITE to any
address of the 4kbit EEPROM memory array must
occur, see Figure 4. This sequence initiates an internal
nonvolatile write cycle which permits data to be stored
in the shadow EEPROM cells. It must be noted that
even though a EEWRITE is made to the general
purpose 4kbit EEPROM array, the value and address to
which it is written, is unimportant. If this procedure is not
followed, the configuration register will power up to the
last previously stored values following a power down
sequence.
In the case that the X3100 or X3101 is configured for use with
only three Li-Ion battery cells (i.e. CELLN=0), then VCELL4 (pin
7) MUST be tied to Vss (pin 9) to ensure correct operation.
REV 1.1.8 12/10/02
www.xicor.com
Characteristics subject to change without notice.
9 of 40
X3100/X3101 – Preliminary Information
Figure 4. Writing to Configuration Register
Since the control register is volatile, data will be lost
following a power down and power up sequence. The
default value of the control register on initial power up
or when exiting the SLEEP MODE is 00h (for both
upper and lower bytes respectively). The functions that
can be manipulated by the Control Register are shown
in Table 12.
Power Up
Data Recalled
from Shadow
EEPROM to SRAM
Configuration Register
(SRAM=Old Value)
Table 12. Control Register Functionality
WCFIG (New Value)
Configuration Register
(Sram=New Value)
Store
(New Value)
in Shadow
EEPROM
NO
YES
WREN
Write
Enable
Power Down
Power Up
Data Recalled
from Shadow
EEPROM to SRAM
EEWRITE
Write to
4kbit EEPROM
Configuration Register
(SRAM=old value)
Bit(s)
Name
Function
0-4
–
5,6
0, 0
Reserved—write 0 to these locations.
7
SLP
Select sleep mode.
8,9
CSG1,
CSG0
Select current sense voltage gain
10
OVPC
OVP control: switch pin OVP = VCC/VSS
11
UVPC
UVP control: switch pin UVP = VCC/VSS
12
CBC1
CB1 control: switch pin CB1 = VCC/VSS
13
CBC2
CB2 control: switch pin CB2 = VCC/VSS
14
CBC3
CB3 control: switch pin CB3 = VCC/VSS
15
CBC4
CB4 control: switch pin CB4 = VCC/VSS
(don’t care)
Sleep Control (SLP)
Setting the SLP bit to ‘1’ forces the X3100 or X3101 into
the sleep mode, if VCC < VSLP. See section “Sleep
Mode” on page 15.
Power Down
Power Up
Data Recalled
from Shadow
EEPROM to SRAM
Table 13. Sleep Mode Selection
Configuration Register
(SRAM=New Value)
Control Register Bits
SLP
Operation
CONTROL REGISTER
0
Normal operation mode
The Control Register is realized as two bytes of volatile
RAM (Table 10, Table 11). This register is written using
the WCNTR instruction, see Table 30 and section “X3100/
X3101 SPI Serial Communication” on page 22.
1
Device enters Sleep mode
Table 10. Control Register—Upper Byte
15
14
13
12
11
10
9
8
CBC4
CBC3
CBC2
CBC1
UVPC
OVPC
CSG1
CSG0
Table 11. Control Register—Lower Byte
7
6
5
4
3
2
1
0
SLP
0
0
x
x
x
x
x
REV 1.1.8 12/10/02
www.xicor.com
Characteristics subject to change without notice.
10 of 40
X3100/X3101 – Preliminary Information
Current Sense Gain (CSG1, CSG0)
These bits set the gain of the current sense amplifier.
These are x10, x25, x80 and x160. For more detail, see
section “Current Monitor Function” on page 20.
Table 16. CB1—CB4 Control
Control Register Bits
CBC4
CBC3
CBC2
CBC1
Operation
x
x
x
1
Set CB1=VCC (ON)
x
x
x
0
Set CB1=VSS (OFF)
x
x
1
x
Set CB2=VCC (ON)
x
x
0
x
Set CB2=VSS (OFF)
Table 14. Current Sense Gain Control
Control Register Bits
CSG1
CSG0
0
0
Set current sense gain=x10
x
1
x
x
Set CB3=VCC (ON)
0
1
Set current sense gain=x25
x
0
x
x
Set CB3=VSS (OFF)
1
0
Set current sense gain=x80
1
x
x
x
Set CB4=VCC (ON)
Set current sense gain=x160
0
x
x
x
Set CB4=VSS (OFF)
1
1
Operation
Charge/Discharge Control (OVPC, UVPC)
The OVPC and UVPC bits allow control of cell charge
and discharge externally, via the SPI port. These bits
control the OVP/LMON and UVP/OCP pins, which in turn
control the external power FETs.
CB1–CB4 can be controlled by using the WCNTR Instruction to set bits CBC1–CBC4 in the control register
(Table 16).
Using P-channel power FETs ensures that the FET is
on when the pin voltage is low (Vss), and off when the
pin voltage is high (Vcc).
The status of the X3100 or X3101 can be verified by
using the RDSTAT command to read the contents of the
Status Register (Table 17).
OVP/LMON and UVP/OCP can be controlled by using
the WCNTR Instruction to set bits OVPC and UVPC in
the Control register (See page 10).
Table 17. Status Register.
Table 15. UVP/OVP Control
Control Register Bits
7
6
5
4
3
2
1
0
0
0
0
0
0
CCES+
OVDS
UVDS
VRGS+
OCDS
The function of each bit in the status register is shown
in Table 18.
OVPC
UVPC
1
x
Pin OVP=VSS (FET ON)
0
x
Pin OVP=VCC (FET OFF)
x
1
Pin UVP=VSS (FET ON)
x
0
Pin UVP=VCC (FET OFF)
Operation
It is possible to set/change the values of OVPC and
UVPC during a protection mode. A change in the state
of the pins OVP/LMON and UVP/OCP, however, will not
take place until the device has returned from the
protection mode.
Cell Voltage Balance Control (CBC1-CBC4)
This function can be used to adjust individual battery
cell voltage during charging. Pins CB1–CB4 are used to
control external power switching devices. Cell voltage
balancing is achieved via the SPI port.
REV 1.1.8 12/10/02
STATUS REGISTER
Bit 0 of the status register (VRGS+OCDS) actually
indicates the status of two conditions of the X3100 or
X3101. Voltage Regulator Status (VRGS) is an
internally generated signal which indicates that the
output of the Voltage Regulator (VRGO) has reached an
output of 5VDC ± 0.5%. In this case, the voltage
regulator is said to be “tuned”. Before the signal VRGS
goes low (i.e. before the voltage regulator is tuned), the
voltage at the output of the regulator is nominally 5VDC
± 10% (See section “Voltage Regulator” on page 21.)
Over-current Detection Status (OCDS) is another
internally generated signal which indicates whether or
not the X3100 or X3101 is in over-current protection
mode.
Signals VRGS and OCDS are logically OR’ed together
(VRGS+OCDS) and written to bit 0 of the status register
(See Table 18, Table 17 and Figure 2).
www.xicor.com
Characteristics subject to change without notice.
11 of 40
X3100/X3101 – Preliminary Information
or not the X3100 or X3101 is in over-charge protection
mode.
Bit 1 of the status register simply indicates whether or
not the X3100 or X3101 is in over-discharge protection
mode.
When the cell charge enable function is switched ON
(configuration bit SWCEN=0), the signals CCES and
OVDS are logically OR’ed (CCES+OVDS) and written to
bit 2 of the status register. If the cell charge enable
function is switched OFF (configuration bit SWCEN=1),
then bit 2 of the status register effectively only represents
information about the over-charge status (OVDS) of the
X3100 or X3101 (See Table 18, Table 17 and Figure 2).
Bit 2 of the status register (CCES+OVDS) indicates the
status of two conditions of the X3100 or X3101. Cell
Charge Enable Status (CCES) is an internally generated
signal which indicates the status of any cell voltage
(VCELL) with respect to the Cell Charge Enable Voltage
(VCE). Over-charge Voltage Detection Status (OVDS) is
an internally generated signal which indicates whether
Table 18. Status Register Functionality.
Bit(s)
0
1
2
3–7
Name
Description
Case
Voltage regulator
status
VRGS+OCDS
+
Over-current
detection status
-
UVDS
Over-discharge
detection status
-
CCES+OVDS
Cell charge
enable status
+
Over-charge
detection status
-
Status
1
VRGO not yet tuned (VRGO=5V ± 10%) OR
X3100/X3101 in over-current protection mode.
0
VRGO tuned (VRGO=5V ± 0.5%) AND
X3100/X3101 NOT in over-current protection mode.
1
X3100/X3101 in over-discharge protection mode
0
X3100/X3101 NOT in over-discharge protection mode
1
VCELL < VCE OR
X3100/X3101 in over-charge protection mode
0
VCELL > VCE AND
X3100/X3101 NOT in over-charge protection mode
1
X3100/X3101 in over-charge protection mode
0
X3100/X3101 NOT in over-charge protection mode
0
Not used (always return zero)
SWCEN =0†
SWCEN =1†
-
Interpretation
Notes: † This bit is set in the configuration register.
X3100/X3101 INTERNAL PROTECTION FUNCTIONS
The X3100 and the X3101 provide periodic monitoring
(see section “Periodic Protection Monitoring” on page
12) for over-charge and over-discharge states and
continuous monitoring for an over-current state. It has
automatic shutdown when a protection mode is
encountered, as well as automatic return after the
device is released from a protection mode. When
sampling voltages through the analog port (Monitor
Mode), over-charge and over-discharge protection
monitoring is also performed on a continuous basis.
Voltage thresholds for each of these protection modes
(VOV, VUV, and VOC respectively) can be individually
selected via software and stored in an internal nonvolatile register. This feature allows the user to avoid the
restrictions of mask programmed voltage thresholds, and
is especially useful during prototype/evaluation design
REV 1.1.8 12/10/02
stages or when cells with slightly
characteristics are used in an existing design.
different
Delay times for the detection of, and release from
protection modes (TOV, TUV/TUVR, and TOC/TOCR
respectively) can be individually varied by setting the
values of external capacitors connected to pins OVT,
UVT, OCT.
Periodic Protection Monitoring
In normal operation, the analog select pins are set such
that AS2=L, AS1=L, AS0=L. In this mode the X3100 and
X3101 conserve power by sampling the cells for over or
over-discharge conditions.
In this state over-charge and over-discharge protection
circuitry are usually off, but are periodically switched on
by the internal Protection Sample Rate Timer (PSRT). The
www.xicor.com
Characteristics subject to change without notice.
12 of 40
X3100/X3101 – Preliminary Information
over-charge and over-discharge protection circuitry is on
for approximately 2ms in each 125ms period. Overcurrent monitoring is continuous. In monitor mode (see
page 20) over-charge and over-discharge monitoring is
also continuous.
Over-charge Protection
The X3100 and X3101 monitor the voltage on each
battery cell (VCELL). If for any cell, VCELL > VOV for a
time exceeding TOV, then the Charge FET will be
switched OFF (OVP/LMON=VCC). The device has now
entered Over-charge protection mode (Figure 5). The
status of the discharge FET (via pin UVP) will remain
unaffected.
While in over-charge protection mode, it is possible to
change the state of the OVPC bit in the control register
such that OVP/LMON=Vss (Charge FET=ON).
Although the OVPC bit in the control register can be
changed, the change will not be seen at pin OVP until
the X3100 or X3101 returns from over-charge
protection mode.
The over-charge detection delay TOV, is varied using a
capacitor (COV) connected between pin OVT and GND.
A typical delay time is shown in Table 10. The delay TOV
that results from a particular capacitance COV, can be
approximated by the following linear equation:
TOV (s) ≈ 10 x COV (µF).
Table 19. Typical over-charge detection time
Symbol
COV
Delay
TOV
0.1µF
1.0s (Typ)
The device further continues to monitor the battery cell
voltages, and is released from over-charge protection
mode when VCELL< VOVR, for all cells. When the X3100
or X3101 is released from over-charge protection
mode, the charge FET is automatically switched ON
(OVP/LMON=VSS). When the device returns from overcharge protection mode, the status of the discharge
FET (pin UVP/OCP) remains unaffected.
The value of VOV can be selected from the values
shown in Table 4 by setting bits VOV1, VOV0. These bits
are set by using the WCFIG instruction to write to the
configuration register.
Figure 5. Over-charge Protection Mode—Event Diagram
Normal Operation Mode
Normal Operation Mode
Over-charge
Protection
Mode
VOV
VOVR
VCELL
TOV
VCC
OVP/LMON
VSS
Event
0
REV 1.1.8 12/10/02
1
2
www.xicor.com
3
Characteristics subject to change without notice.
13 of 40
X3100/X3101 – Preliminary Information
Table 20. Over-charge Protection Mode—Event Diagram Description
Event
[0,1)
[1]
(1,2)
Event Description
— Discharge FET is ON (UVP/OCP=VSS).
— Charge FET is ON (OVP/LMON=VSS), and hence battery cells are permitted to receive charge.
— All cell voltages (VCELL-VCELL4) are below the over-charge voltage threshold (VOV).
— The device is in normal operation mode (i.e. not in a protection mode).
— The voltage of one or more of the battery cells (VCELL), exceeds VOV.
— The internal over-charge detection delay timer begins counting down.
— The device is still in normal operation mode
The internal over-charge detection delay timer continues counting for TOV seconds.
The internal over-charge detection delay timer times out
AND
VCELL still exceeds VOV.
[2]
— Therefore, the internal over-charge sense circuitry switches the charge FET OFF (OVP/LMON=Vcc).
— The device has now entered over-charge protection mode.
(2,3)
[3]
While in over-charge protection mode:
— The battery cells are permitted to discharge via the discharge FET, and diode D2 across the charge FET
— The X3100 or X3101 monitors the voltages VCELL1-VCELL4 to determine whether or not they have all fallen
below the “Return from over-charge threshold” (VOVR).
— (It is possible to change the status of UVP/OCP or OVP/LMON using the control register)
— All cell voltages fall below VOVR—The device is now in normal operation mode.
— The X3100/X3101 automatically switches charge FET=ON (OVP/LMON=Vss)
— The status of the discharge FET remains unaffected.
— Charging of the battery cells can now resume.
REV 1.1.8 12/10/02
www.xicor.com
Characteristics subject to change without notice.
14 of 40
X3100/X3101 – Preliminary Information
Over-discharge Protection
If VCELL < VUV, for a time exceeding TUV, the cells are
said to be in a over-discharge state (Figure 6). In this
instance, the X3100 and X3101 automatically switch
the discharge FET OFF (UVP/OCP=Vcc), and then
enter sleep mode.
The over-discharge (under-voltage) value, VUV, can be
selected from the values shown in Table 5 by setting
bits VUV1, VUV0 in the configuration register. These
bits are set using the WCFIG command. Once in the
sleep mode, the following steps must occur before the
X3100 or X3101 allows the battery cells to discharge:
– The X3100 and X3101 must wake from sleep mode
(see section “Voltage Regulator” on page 21).
– The charge FET must be switched ON by the microcontroller (OVP/LMON=VSS), via the control register
(see section “Control Register Functionality” on page
10).
– All battery cells must satisfy the condition: VCELL >
VUVR for a time exceeding TUVR.
– The discharge FET must be switched ON by the microcontroller (UVP/OCP=VSS), via the control register
(see section “Control Register Functionality” on page
10)
The times TUV/TUVR are varied using a capacitor (CUV)
connected between pin UVT and GND (Table 13). The
delay TUV that results from a particular capacitance CUV,
can be approximated by the following linear equation:
TUV (s) ≈ 10 x CUV (µF)
TUVR (ms) ≈ 70 x CUV (µF)
Table 21. Typical Over-discharge Delay Times
Symbol
CUV
Delay
TUV
Over-discharge
detection delay
Description
0.1µF
1.0s (Typ)
TUVR
Over-discharge
release time
0.1µF
7ms (Typ)
Sleep Mode
The X3100 or X3101 can enter sleep mode in two
ways:
A sleep mode can be induced by the user, by setting
the SLP bit in the control register (Table 13) using the
WCNTR Instruction.
In sleep mode, power to all internal circuitry is switched
off, minimizing the current drawn by the device to 1µA
(max). In this state, the discharge FET and the charge
FET are switched OFF (OVP/LMON=VCC and UVP/
OCP=VCC), and the 5VDC regulated output (VRGO) is
0V. Control of UVP/OCP and OVP/LMON via bits UVPC
and OVPC in the control register is also prohibited.
The device returns from sleep mode when VCC ≥ VSLR.
(e.g. when the battery terminals are connected to a
battery charger). In this case, the X3100 or the X3101
restores the 5VDC regulated output (section “Voltage
Regulator” on page 21), and communication via the SPI
port resumes.
If the Cell Charge Enable function is enabled when VCC
rises above VSLR, the X3100 and X3101 internally
verifies that the individual battery cell voltages (VCELL)
are larger than the cell charge enable voltage (VCE)
before allowing the FETs to be turned on. The value
of VCE is selected by using the WCFIG command to set
bits VCE1–VCE0 in the configuration register.
Only if the condition “VCELL > VCE” is satisfied can
the state of charge and discharge FETs be changed
via the control register. Otherwise, if VCELL < VCE for
any battery cell then both the Charge FET and the
discharge FET are OFF (OVP/LMON=Vcc and UVP/
OCP=VCC). Thus both charge and discharge of the
battery cells via terminals P+ / P- is prohibited1.
The cell charging threshold function can be switched
ON or OFF by the user, by setting bit SWCEN in the
configuration register (Table 7) using the WCFIG
command. In the case that this cell charge enable
function is switched OFF, then VCE is effectively set to
0V.
Neither the X3100 nor the X3101 enter sleep mode
(automatically or manually, by setting the SLP bit) if VCC
≥ VSLR. This is to ensure that the device does not go
into a sleep mode while the battery cells are at a high
voltage (e.g. during cell charging).
i) The device enters the over-discharge protection mode.
ii) The user sends the device into sleep mode using the
control register.
REV 1.1.8 12/10/02
1.
www.xicor.com
In this case, charging of the battery may resume ONLY if the cell
charge enable function is switched OFF by setting bit SWCEN =
1 in the configuration register (See Above, “Configuration
Register Functionality” on page 8).
Characteristics subject to change without notice.
15 of 40
X3100/X3101 – Preliminary Information
Figure 6. Over-discharge Protection Mode—Event Diagram
VSLR
VCC
Cell Charge Prohibited if SWCEN=0
AND VCELL < VCE
VCELL
0.7V
VUVR
VUV
TUVR
VCE
TUV
VCC
Note 3
Over-discharge Protection Mode
UVP/OCP
VSS
The Longer of TOV+200ms OR TUV+200ms
VCC
Note 1, 2
OVP/LMON
RGO
VSS
5V
Sleep Mode
0V
Event
0
1
2
3
4
5
Note 1: If SWEN=0 and VCELL < VCE, then OVP/LMON stays high and charging is prohibited.
Note 2: OVP/LMON stays high until the microcontroller writes a “1” to the OVPC bit in the control register. This sets the signal low, which turns on the
charge FET. It cannot be turned on prior to this time.
Note 3: UVP/OCP stays high until the microcontroller writes a “1” to the UVPC bit in the control register. This sets the signal low, which turns on the
discharge FET. The FET cannot be turned on prior to this time.
Table 22. Over-discharge Protection Mode—Event Diagram Description
Event
[0,1)
[1]
(1,2)
[2]
Event Description
— Charge FET is ON (OVP/LMON=VSS)
— Discharge FET is ON (UVP/OCP=VSS), and hence battery cells are permitted to discharge.
— All cell voltages (VCELL1-VCELL4) are above the Over-discharge threshold voltage (VUV).
— The device is in normal operation mode (i.e. not in a protection mode).
— The voltage of one or more of the battery cells (VCELL), falls below VUV.
— The internal over-discharge detection delay timer begins counting down.
— The device is still in normal operation mode
The internal over-discharge detection delay timer continues counting for TUV seconds.
— The internal over-discharge detection delay timer times out, AND VCELL is still below VUV.
— The internal over-discharge sense circuitry switches the discharge FET OFF (UVP/OCP=Vcc).
— The charge FET is switched OFF (OVP/LMON=VCC).
— The device has now entered over-discharge protection mode.
— At the same time, the device enters sleep mode (See section “Voltage Regulator” on page 21).
REV 1.1.8 12/10/02
www.xicor.com
Characteristics subject to change without notice.
16 of 40
X3100/X3101 – Preliminary Information
Table 22. Over-discharge Protection Mode—Event Diagram Description (Continued)
Event
(2,3)
[3]
(3,4)
[4]
(4,5)
[5]
Event Description
While device is in sleep (in over-discharge protection) mode:
— The power to ALL internal circuits is switched OFF limiting power consumption to less than 1µA.
— The output of the 5VDC voltage regulator (RGO) is 0V.
— Access to the X3100/X3101 via the SPI port is NOT possible.
Return from sleep mode (but still in over-discharge protection mode):
— Vcc rises above the “Return from Sleep mode threshold Voltage” (VSLR)—This would normally occur in the
case that the battery pack was connected to a charger. The X3100/X3101 is now powered via P+/P-, and
not the battery pack cells.
— Power is returned to ALL internal circuitry
— 5VDC output is returned to the regulator output (RGO).
— Access is enabled to the X3100/X3101 via the SPI port.
— The status of the discharge FET remains OFF (It is possible to change the status of UVPC in the control register, although it will have no effect at this time).
If the cell charge enable function is switched ON
AND VCELL > VCE
OR
Charge enable function is
switched OFF
— The X3100/X3101 initiates a reset operation that takes the longer of
TOV+200ms or TUV+200ms to complete. Do not write to the FET control bits
during this time.
— The charge FET is switched On (OVP/LMON=Vss) by the microcontroller by
writing a “1” to the OVPC bit in the control register.
— The battery cells now receive charge via the charge FET and diode D1 across
the discharge FET (which is OFF).
— The X3100/X3101 monitors the VCELL voltage to determine whether or not it
has risen above VUVR.
If the cell charge enable function is switched ON
AND
VCELL < VCE
— Charge/discharge of the battery cells via P+ is no longer permitted (Charge
FET and discharge FET are held OFF).
— (Charging may re-commence only when the Cell Charge Enable function is
switched OFF - See Sections: “Configuration Register” page 4, and “Sleep
mode” page 17.)
— The voltage of all of the battery cells (VCELL), have risen above VUVR.
— The internal Over-discharge release timer begins counting down.
— The X3100/X3101 is still in over-discharge protection mode.
— The internal over-discharge release timer continues counting for tUVR seconds.
— The X3100/X3101 should be in monitor mode (AS2:AS0 not all low) for recovery time based on tUVR. Otherwise recovery is based on two successive samples about 120ms apart.
— The internal over-discharge release timer times out, AND VCELL is still above VUVR.
— The device returns from over-discharge protection mode, and is now in normal operation mode.
— The Charger voltage can now drop below VSLR and the X3100/X3101 will not go back to sleep.
— The discharge FET is can now be switched ON (UVP/OCP=VSS) by the microcontroller by writing a “1” to
the UVPC bit of the control register.
— The status of the charge FET remains unaffected (ON)
— The battery cells continue to receive charge via the charge FET and discharge FET (both ON).
REV 1.1.8 12/10/02
www.xicor.com
Characteristics subject to change without notice.
17 of 40
X3100/X3101 – Preliminary Information
Over-Current Protection
In addition to monitoring the battery cell voltages, the
X3100 and X3101 continually monitor the voltage VCS21
(VCS2–VCS1) across the current sense resistor
(RSENSE). If VCS21 > VOC for a time exceeding TOC,
then the device enters over-current protection mode
(Figure 7). In this mode, the X3100 and X3101
automatically switch the discharge FET OFF (UVP/
OCP=Vcc) and hence prevent current from flowing
through the terminals P+ and P-.
Figure 7. Over-Current Protection
P+
ILMON
Q2
If the load resistance > 150kΩ (ILMON=0µA) for a time
exceeding TOCR, then the X3100 or X3101 is released
from over-current protection mode. The discharge FET
is then automatically switched ON (UVP/OCP=Vss) by
the X3100 or X3101, unless the status of UVP/OCP has
been changed in control register (by manipulating bit
UVPC) during the over-current protection mode.
TOC/TOCR are varied using a capacitor (COC) connected
between pin OCT and VSS. A list of typical delay times
is shown in Table 23. Note that the value COC should be
larger than 1nF.
The delay TOC and TOCR that results from a particular
capacitance COC can be approximated by the following
equations:
TOC (ms) ≈ 10,000 x COC (µF)
D1
TOCR (ms) ≈ 10,000 x COC (µF)
VRGO
Q10
Load
Table 23. Typical Over-Current Delay Times
OVP/LMON
X3100/X3101
Symbol
FET Control
Circuitry
TOC
TOCR
VSS
VCS1
COC
Delay
Over-current
detection delay
0.001µF
10ms (Typ)
Over-current
release time
0.001µF
10ms (Typ)
VCS2
P-
RSENSE
The 5VDC voltage regulator output (VRGO) is always
active during an over-current protection mode.
Once the device enters over-current protection mode,
the X3100 and X3101 begin a load monitor state. In the
load monitor state, a small current (ILMON=7.5µA typ.) is
passed out of pin OVP/LMON in order to determine the
load resistance. The load resistance is the impedance
seen looking out of pin OVP/LMON, between terminal
P+ and pin VSS (See Figure 7.)
REV 1.1.8 12/10/02
Description
The value of VOC can be selected from the values
shown in Table 6, by setting bits VOC1, VOC0 in the
configuration register using the WCFIG command.
Note: If the Charge FET is turned off, due to an
overcharge condition or by direct command from the
microcontroller, the cells are not in an undervoltage
condition and the pack has a load, then excessive
current may flow through Q10 and diode D1. To
eliminate this effect, the gate of Q10 can be turned off by
the microcontroller through an unused X3101 cell
balance output, or directly from a microcontroller port
instead of connecting to VRGO.
www.xicor.com
Characteristics subject to change without notice.
18 of 40
X3100/X3101 – Preliminary Information
Figure 8. Over-Current Protection Mode—Event Diagram
Over-Current Protection Mode
Normal Operation Mode
Normal Operation Mode
B+
P+
P+ = (RLOAD+RSENSE) x ILMON
VOC
Voc
VCS2
VSS
TOCR
TOC
VCC
UVP/OCP
VSS
Event
0
1
4
3
2
Table 24. Over-Current Protection Mode—Event Diagram Description
Event
[0,1)
[1]
(1,2)
[2]
(2,3)
Event Description
— Discharge FET is ON (OCP=Vss). Battery cells are permitted to discharge.
— VCS21 (VCS2–VCS1) is less than the over-current threshold voltage (VOC).
— The device is in normal operation mode (i.e. not in a protection mode).
— Excessive current flows through the battery terminals P+, dropping the voltage. (See Figure 8.).
— The positive battery terminal voltage (P+) falls, and VCS21 exceeds VOC.
— The internal over-current detection delay timer begins counting down.
— The device is still in Normal Operation Mode
The internal Over-current detection delay timer continues counting for TOC seconds.
— The internal over-current detection delay timer times out, AND VCS21 is still above VOC.
— The internal over-current sense circuitry switches the discharge FET OFF (UVP/OCP=Vcc).
— The device now begins a load monitor state by passing a small test current (ILMON=7.5µA) out of pin
OVP/LMON. This senses if an over-current condition (i.e. if the load resistance < 150kΩ) still exists
across P+/P-.
— The device has now entered over-current protection mode.
— It is possible to change the status of UVPC and OVPC in the control register, although the status of pins
UVP/OCP and OVP/LMON will not change until the device has returned from over-current protection
mode.
— The X3100/X3101 now continuously monitors the load resistance to detect whether or not an overcurrent condition is still present across the battery terminals P+/P-.
REV 1.1.8 12/10/02
www.xicor.com
Characteristics subject to change without notice.
19 of 40
X3100/X3101 – Preliminary Information
Table 24. Over-Current Protection Mode—Event Diagram Description (Continued)
Event
Event Description
— The device detects the load resistance has risen above 250kΩ.
— Voltages P+ and VCS21 return to their normal levels.
— The test current from pin OVP/LMON is stopped (ILMON=0µA)
— The device has now returned from the load monitor state
— The internal over-current release time timer begins counting down.
— Device is still in over-current protection mode.
[3]
The internal over-current release timer continues counting for TOCR seconds.
(3,4)
— The internal over-current release timer times out, and VCS21 is still below VOC.
— The device returns from over-current protection mode, and is now in normal operation mode.
— The discharge FET is automatically switched ON (UVP/OCP=Vss)—unless the status of UVPC has
been changed in the control register during the over-current protection mode.
— The status of the charge FET remains unaffected.
— Discharge of the battery cells is once again possible.
[4]
MONITOR MODE
Analog Multiplexer Selection
The X3100 and X3101 can be used to externally monitor
individual battery cell voltages, and battery current.
Each quantity can be monitored at the analog output pin
(AO), and is selected using the analog select (AS0–AS2)
pins (Table 25). Also, see Figure 9.
Since the value of the sense resistor (RSENSE) is small
(typically in the order of tens of mΩ), and since the
resolution of various A/D converters may vary, the
voltage across RSENSE (VCS1 and VCS2) is amplified
internally with a gain of between 10 and 160, and output
to pin AO (Figure 9).
Figure 9. X3100/X3101 Monitor Circuit
AS2 AS1 AS0
AO output
L
L
L
VSS(1)
L
L
H
VCELL1–VCELL2 (VCELL12)
L
H
L
VCELL2–VCELL3 (VCELL23)
L
H
H
VCELL3–VCELL4 (VCELL34)
H
L
L
VCELL4–Vss (VCELL4)
H
L
H
VCS1–VCS2 (VCS12)(2)
)(2)
H
H
L
VCS2–VCS1 (VCS21
H
H
H
VSS
Cell 1 Voltage
Cell 2 Voltage
Cell 3 Voltage
Cell 4 Voltage
Voltage
Level
Shifters
2.5V
R2
AS0
AS1
AS2
AO
R2
R1
S0
R1
Config
Register
Notes: (1) This is the normal state of the X3100 or X3101. While in
this state Over-charge and Over-discharge Protection
conditions are periodically monitored (See “Periodic Protection Monitoring” on page 12.)
(2) VCS1, VCS2 are read at AO with respect to a DC bias
voltage of 2.5V (See section “Current Monitor Function”
on page 20).
Current Monitor Function
The voltages monitored at pins VCS1 and VCS2 can be
used to calculate current flowing through the battery
terminals, using an off-board microcontroller with an A/D.
The internal gain of the X3100 or X3101 current sense
voltage amplifier can be selected by using the WCNTR
REV 1.1.8 12/10/02
+
OP1
Analog MUX
Table 25. AO Selection Map
Gain
Setting
CSG1 CSG0
Cross-Bar
Switch
SPI
I/F
SCL
CS
SI
Over-Current
Protection
X3100/X3101
VCS1
VCS2
PRSENSE
Instruction to set bits CSG1 and CSG0 in the control
register (Table 14). The CSG1 and CSG0 bits select one
www.xicor.com
Characteristics subject to change without notice.
20 of 40
X3100/X3101 – Preliminary Information
of four input resistors to Op Amp OP1. The feedback
resistors remain constant. This ratio of input to feedback
resistors determines the gain. Putting external resistors
in series with the inputs reduces the gain of the amplifier.
2.5V (i.e. the threshold voltage for the FET), Q2 switches
ON, shorting VCC to the base of Q1. Since the base
voltage of Q1 is now higher than the emitter voltage, Q1
switches OFF, and hence the supply current goes to zero.
VCS1 and VCS2 are read at AO with respect to a DC
bias voltage of 2.5V. Therefore, the voltage range of
VCS12 and VCS21 changes depending upon the
direction of current flow (i.e. battery cells are in Charge
or Discharge—Table 21).
Typical values for RLMT and ILMT are shown in Table 27.
In order to protect the voltage regulator circuitry from
damage in case of a short-circuit, RLMT ≥ 10Ω should
always be used.
Table 27. Typical Values for RLMT and ILMT
Table 26. AO Voltage Range for VCS12 and VCS21
AO
Cell State
AO Voltage Range
VCS12
Charge
2.5V ≤ AO ≤ 5.0V
VCS12
Discharge
VCS21
Charge
VCS21
Discharge
0V ≤ AO ≤ 2.5V
0V ≤ AO ≤ 2.5V
2.5V ≤ AO ≤ 5.0V
By calculating the difference of VCS12 and VCS21 the
offset voltage of the internal op-amp circuitry is
cancelled. This allows for the accurate calculation of
current flow into and out of the battery cells.
RLMT
Voltage Regulator Current Limit (ILMT)
10Ω
250mA ± 50% (Typical)
25Ω
100mA ± 50% (Typical)
50Ω
50mA ± 50% (Typical)
When choosing the value of RLMT, the drive limitations
of the PNP transistor used should also be taken into
consideration. The transistor should have a gain of at
least 100 to support an output current of 250mA.
Figure 10. Voltage Regulator Operation
Pack current is calculated using the following formula:
VCC
( VCS 12 – VCS 21 )
Pack Current = ---------------------------------------------------------------------------------------------------------( 2 ) ( gain setting )(current sense resistor)
To Internal Voltage
Regulating Circuitry
RLMT
X3100/X3101
RGP
Tuning
VOLTAGE REGULATOR
The X3100 and X3101 are able to supply peripheral
devices with a regulated 5VDC±0.5% output at pin
RGO. The voltage regulator should be configured
externally as shown in Figure 10.
5VDC
Precision
Voltage
Reference
Un-Regulated
Voltage
Input
Q2
+
_
ILMT
RGC
Q1
OP1
The non-inverting input of OP1 is fed with a high
precision 5VDC supply. The voltage at the output of the
voltage regulator (VRGO) is compared to this 5V
reference via the inverting input of OP1. The output of
OP1 in turn drives the regulator pnp transistor (Q1). The
negative feedback at the regulator output maintains the
voltage at 5VDC±0.5% (including ripple) despite
changes in load, and differences in regulator transistors.
4KBIT EEPROM MEMORY
When power is applied to pin VCC of the X3100 or
X3101, VRGO is regulated to 5VDC±10% for a nominal
time of TOC+2ms. During this time period, VRGO is
“tuned” to attain a final value of 5VDC±0.5% (Figure 2).
The X3100 and X3101 contain a CMOS 4k-bit serial
EEPROM, internally organized as 512 x 8 bits. This
memory is accessible via the SPI port, and features the
IDLock function.
The maximum current that can flow from the voltage
regulator (ILMT) is controlled by the current limiting
resistor (RLMT) connected between RGP and VCC. When
the voltage across VCC and RGP reaches a nominal
The 4kbit EEPROM array can be accessed by the SPI
port at any time, even during a protection mode, except
during sleep mode. After power is applied to VCC of the
X3100 or X3101, EEREAD and EEWRITE Instructions
REV 1.1.8 12/10/02
RGO
Regulated
5VDC Output
0.1
µF
www.xicor.com
Characteristics subject to change without notice.
VRGO
21 of 40
X3100/X3101 – Preliminary Information
can be executed only after times tPUR (power up to read
time) and tPUW (power up to write time) respectively.
IDLock is a programmable locking mechanism which
allows the user to lock data in different portions of the
EEPROM memory space, ranging from as little as one
page to as much as 1/2 of the total array. This is useful
for storing information such as battery pack serial
number, manufacturing codes, battery cell chemistry
data, or cell characteristics.
EEPROM Write Enable Latch
The X3100 and X3101 contain an EEPROM “Write
Enable” latch. This latch must be SET before a write to
EEPROM operation is initiated. The WREN instruction
will set the latch and the WRDI instruction will reset the
latch (Figure 11). This latch is automatically reset upon a
power-up condition and after the completion of a byte or
page write cycle.
IDLock Memory
Xicor’s IDLock memory provides a flexible mechanism to
store and lock battery cell/pack information. There are
seven distinct IDLock memory areas within the array
which vary in size from one page to as much as half of
the entire array.
Prior to any attempt to perform an IDLock operation, the
WREN instruction must first be issued. This instruction
sets the “Write Enable” latch and allows the part to
respond to an IDLock sequence. The EEPROM memory
may then be IDLocked by writing the SET IDL instruction
(Table 30 and Figure 19), followed by the IDLock
protection byte.
Table 28. IDLock Partition Byte Definition
IDLock Protection
Bytes
EEPROM Memory Address
IDLocked
0000 0000
None
0000 0001
000h–07Fh
0000 0010
080h–0FFh
0000 0011
100h–17Fh
0000 0100
180h–1FFh
0000 0101
000h–0FFh
0000 0110
000h–00Fh
0000 0111
1F0h–1FFh
and must be written as zeroes. Bringing CS HIGH after
the two byte IDLock instruction initiates a nonvolatile write
to the status register. Writing more than one byte to the
status register will overwrite the previously written
IDLock byte.
Once an IDLock instruction has been completed, that
IDLock setup is held in a nonvolatile IDLock Register
(Table 29) until the next IDLock instruction is issued. The
sections of the memory array that are IDLocked can be
read but not written until IDLock is removed or changed.
Table 29. IDLock Register
7
6
5
4
3
2
1
0
0
0
0
0
0
IDL2
IDL1
IDL0
Note:
Bits [7:3] specified to be “0’s”
X3100/X3101 SPI SERIAL COMMUNICATION
The X3100 and X3101 are designed to interface directly
with the synchronous Serial Peripheral Interface (SPI) of
many popular microcontroller families. This interface
uses four signals, CS, SCK, SI and SO. The signal CS
when low, enables communications with the device. The
SI pin carries the input signal and SO provides the
output signal. SCK clocks data in or out. The X3100 and
X3101 operate in SPI mode 0 which requires SCK to be
normally low when not transferring data. It also specifies
that the rising edge of SCK clocks data into the device,
while the falling edge of SCK clocks data out.
This SPI port is used to set the various internal registers,
write to the EEPROM array, and select various device
functions.
The X3100 and X3101 contain an 8-bit instruction
register. It is accessed by clocking data into the SI input.
CS must be LOW during the entire operation. Table 30
contains a list of the instructions and their opcodes. All
instructions, addresses and data are transferred MSB
first.
Data input is sampled on the first rising edge of SCK
after CS goes LOW. SCK is static, allowing the user to
stop the clock, and then start it again to resume
operations where left off.
The IDLock protection byte contains the IDLock bits
IDL2-IDL0, which defines the particular partition to be
locked (Table 28). The rest of the bits [7:3] are unused
REV 1.1.8 12/10/02
www.xicor.com
Characteristics subject to change without notice.
22 of 40
X3100/X3101 – Preliminary Information
Table 30. X3100/X3101 Instruction Set
Instruction
Name
Instruction
Format*
WREN
0000 0110
Set the write enable latch (write enable operation)—Figure 11
Description
WRDI
0000 0100
Reset the write enable latch (write disable operation)—Figure 11
EEWRITE
0000 0010
Write command followed by address/data (4kbit EEPROM)—Figure 12, Figure 13
EEREAD STAT
0000 0101
Reads IDLock settings & status of EEPROM EEWRITE instruction—Figure 14
EEREAD
0000 0011
Read operation followed by address (for 4kbit EEPROM)—Figure 15
WCFIG
0000 1001
Write to configuration register followed by two bytes of data—Figure 4, Figure 16.
Data stored in SRAM only and will power-up to previous settings—Figure 3
WCNTR
0000 1010
Write to control register, followed by two bytes of data—Figure 17
RDSTAT
0000 1011
Read contents of status register—Figure 18
SET IDL
0000 0001
Set EEPROM ID lock partition followed by partition byte—Figure 19
*Instructions have the MSB in leftmost position and are transferred MSB first.
Write Enable/Write Disable (WREN/WRDI)
Any write to a nonvolatile array or register, requires the
WREN command be sent prior to the write command.
This command sets an internal latch allowing the write
operation to proceed. The WRDI command resets the
internal latch if the system decides to abort a write
operation. See Figure 11.
Figure 11. EEPROM Write Enable Latch (WREN/WRDI) Operation Sequence
CS
0
1
2
3
4
5
6
7
WREN
SCK
Instruction
(1 Byte)
SI
SO
REV 1.1.8 12/10/02
High Impedance
www.xicor.com
WRDI
Characteristics subject to change without notice.
23 of 40
X3100/X3101 – Preliminary Information
EEPROM Write Sequence (EEWRITE)
Prior to any attempt to write data into the EEPROM of
the X3100 or X3101, the “Write Enable” latch must first
be set by issuing the WREN instruction (See Table 30
and Figure 11). CS is first taken LOW. Then the WREN
instruction is clocked into the X3100 or X3101. After all
eight bits of the instruction are transmitted, CS must
then be taken HIGH. If the user continues the write
operation without taking CS HIGH after issuing the
WREN instruction, the write operation will be ignored.
To write data to the EEPROM memory array, the user
issues the EEWRITE instruction, followed by the 16 bit
address and the data to be written. Only the last 9 bits of
the address are used and bits [15:9] are specified to be
zeroes. This is minimally a thirty-two clock operation. CS
must go LOW and remain LOW for the duration of the
operation. The host may continue to write up to 16 bytes
of data to the X3100 or X3101. The only restriction is the
16 bytes must reside on the same page. If the address
counter reaches the end of the page and the clock
continues, the counter will “roll over” to the first address
of the page and overwrite any data that may have been
previously written.
to be written is clocked in. If it is brought HIGH at any
other time, the write operation will not be completed.
Refer to Figure 12 and Figure 13 for detailed illustration
of the write sequences and time frames in which CS
going HIGH are valid.
EEPROM Read Status Operation (EEREAD STAT)
If there is not a nonvolatile write in progress, the
EEREAD STAT instruction returns the IDLock byte from
the IDLock register which contains the IDLock bits IDL2IDL0 (Table 29). The IDLock bits define the IDLock
condition (Table 28). The other bits are reserved and will
return ‘0’ when read.
If a nonvolatile write to the EEPROM (i.e. EEWRITE
instruction) is in progress, the EEREAD STAT returns a
HIGH on SO. When the nonvolatile write cycle in the
EEPROM is completed, the status register data is read
out.
Clocking SCK is valid during a nonvolatile write in
progress, but is not necessary. If the SCK line is clocked,
the pointer to the status register is also clocked, even
though the SO pin shows the status of the nonvolatile
write operation (See Figure 14).
For a byte or page write operation to be completed, CS
can only be brought HIGH after bit 0 of the last data byte
Figure 12. EEPROM Byte Write (EEWRITE) Operation Sequence
CS
0
1
2
3
4
5
6
7
8
9
20 21 22 23 24 25 26 27 28 29 30 31
SCK
EEWRITE Instruction
(1 Byte)
Byte Address (2 Byte)
15 14
SI
3
2
Data Byte
1
0
7
6
5
4
3
2
1
0
High Impedance
SO
REV 1.1.8 12/10/02
www.xicor.com
Characteristics subject to change without notice.
24 of 40
X3100/X3101 – Preliminary Information
Figure 13. EEPROM Page Write (EEWRITE) Operation Sequence
CS
0
1
2
3
4
5
6
7
8
9
20 21 22 23 24 25 26 27 28 29 30 31
10
SCK
EEWRITE
Instruction
Byte Address
(2 Byte)
15 14 13
SI
3
Data Byte 1
2
1
0
7
6
5
4
3
2
1
0
150
151
149
148
147
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
146
145
CS
1
0
SCK
Data Byte 2
SI
7
6
5
4
3
Data Byte 3
2
1
0
7
6
5
4
3
2
Data Byte 16
1
0
6
5
4
3
2
Figure 14. EEPROM Read Status (EEREAD STAT) Operation Sequence
CS
0
1
2
3
4
5
6
7
...
SCK
EEREAD STAT
Instruction
...
SI
Nonvolatile EEWRITE in Progress
I
D
L
2
SO
SO High During
Nonvolatile
EEWRITE Cycle
REV 1.1.8 12/10/02
www.xicor.com
I
D
L
1
I
D
L
0
...
SO=Status Reg Bit
When No Nonvolatile
EEWRITE Cycle
Characteristics subject to change without notice.
25 of 40
X3100/X3101 – Preliminary Information
EEPROM Read Sequence (EEREAD)
When reading from the X3100 or X3101 EEPROM
memory, CS is first pulled LOW to select the device. The 8bit EEREAD instruction is transmitted to the X3100 or
X3101, followed by the 16-bit address, of which the last
9 bits are used (bits [15:9] specified to be zeroes). After
the EEREAD opcode and address are sent, the data
stored in the memory at the selected address is shifted
out on the SO line. The data stored in memory at the next
address can be read sequentially by continuing to provide
clock pulses. The address is automatically incremented to
the next higher address after each byte of data is shifted
out. When the highest address is reached (01FFh), the
address counter rolls over to address 0000h, allowing
the read cycle to be continued indefinitely. The read
operation is terminated by taking CS HIGH. Refer to the
EEPROM Read (EEREAD) operation sequence
illustrated in Figure 15.
Figure 15. EEPROM (EEREAD) Read Operation Sequence
CS
0
1
2
3
4
5
6
7
8
9
20 21 22 23 24 25 26 27 28 29 30 31
SCK
EEREAD Instruction
(1 Byte)
Byte Address (2 Byte)
15 14
SI
3
2
High Impedance
1
0
7
SO
REV 1.1.8 12/10/02
Data Out
www.xicor.com
6
5
4
3
2
1
0
Characteristics subject to change without notice.
26 of 40
X3100/X3101 – Preliminary Information
Write Configuration Register (WCFIG)
The Write Configuration Register (WCFIG) instruction
updates the static part of the Configuration Register.
These new values take effect immediately, for example
writing a new Over-discharge voltage limit. However, to
make these changes permanent, so they remain if the
cell voltages are removed, an EEWRITE operation to
the EEPROM array is required following the WCFIG
command. This command is shown in Figure 16.
Write Control Register (WCNTRL)
The Write Control Register (WCNTRL) instruction
updates the contents of the volatile Control Register.
This command sets the status of the FET control pins,
the cell balancing outputs, the current sense gain and
external entry to the sleep mode. Since this instruction
controls a volatile register, no other commands are
required and there is no delay time needed after the
instruction, before subsequent commands. The
operation of the WCNTRL command is shown in
Figure 17.
Figure 16. Write Configuration Register (WCFIG) Operation Sequence
CS
0
1
2
3
4
5
6
7
8
20 21 22 23
9
SCK
Configuration
Register Data
WCFIG Instruction
3
15 14
SI
2
1
0
(2 BYTE)
(1 BYTE)
High Impedance
SO
Figure 17. Write Control Register (WCNTR) Operation Sequence
CS
0
1
2
3
4
5
6
7
8
18 19 20 21 22
9
23
SCK
Control
Register Data
WCNTR Instruction
5
15 14
SI
4
3
2
1
0
(2 Byte)
(1 Byte)
High Impedance
SO
Control
Bits
REV 1.1.8 12/10/02
Old Control Bits
www.xicor.com
New Control Bits
Characteristics subject to change without notice.
27 of 40
X3100/X3101 – Preliminary Information
Read Status Register (RDSTAT)
The Read Status Register (RDSTAT) command returns
the status of the X3100 or X3101. The Status Register
contains three bits that indicate whether the voltage
regulator is stabilized, and if there are any protection
failure conditions. The operation of the RDSTAT
instruction is shown in Figure 18.
Set ID Lock (SET IDL)
The contents of the EEPROM memory array in the
X3100 or X3101 can be locked in one of eight
configurations using the SET ID lock command. When a
section of the EEPROM array is locked, the contents
cannot be changed, even when a valid write operation
attempts a write to that area. The SET IDL command
operation is shown in Figure 19.
Figure 18. Read Status Register (RDSTAT) Operation Sequence
CS
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
SCK
RDSTAT
Instruction
SI
(1 Byte)
High Impedance
2
SO
1
0
Status Register Output
Figure 19. EEPROM IDLock (SET IDL) Operation Sequence
CS
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
SCK
Set IDL
Instruction
IDLock
Byte
I
D
L
2
SI
I
D
L
1
I
D
L
0
High Impedance
SO
REV 1.1.8 12/10/02
www.xicor.com
Characteristics subject to change without notice.
28 of 40
X3100/X3101 – Preliminary Information
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Min.
Max.
Unit
Storage temperature
-55
125
°C
Operating temperature
-40
85
°C
5
mA
300
°C
VSS-0.5
VSS+27.0
V
DC output current
Lead temperature (soldering 10 seconds)
VCC
Power supply voltage
VCELL
Cell voltage
-0.5
6.75
V
VTERM1
Terminal voltage (Pins: SCK, SI, SO, CS, AS0, AS1, AS2, VCS1,
VCS2, OVT, UVT, OCT, AO)
VSS-0.5
VRGO + 0.5
V
VTERM2
Terminal voltage (VCELL1)
VSS-0.5
VCC + 1.0
V
VTERM3
Terminal voltage (all other pins)
VSS-0.5
VCC + 0.5
V
Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is
a stress rating only; the functional operation of the device (at these or any other conditions above those indicated in
the operational sections of this specification) is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
Temperature
Min.
Max.
Supply Voltage
Limits
Commercial
-20°C
+70°C
X3100/X3101
6V to 24V
D.C. OPERATING CHARACTERISTICS
(Over the recommended operating conditions, unless otherwise specified.)
Limits
Symbol
Parameter
Min.
Max.
Units
ILI
Input leakage current (SCK, SI, CS,
ASO, AS1, AS2)
±10
µA
ILO
Output leakage current (SO)
±10
µA
VRGO x 0.3
V
VRGO x 0.7 VRGO + 0.3
V
VIL(1)
Input LOW voltage
(SCK, SI, CS, AS0, AS1, AS2)
VIH(1)
Input HIGH voltage
(SCK, SI, CS, AS0, AS1, AS2)
VOL1
Output LOW voltage (SO)
VOH1
Output HIGH voltage (SO)
VOL2
Output LOW voltage
(UVP/OCP, OVP/LMON, CB1-CB4)
VOH2
Output HIGH voltage
(UVP/OCP, OVP/LMON, CB1-CB4)
VOL3
Output LOW voltage (RGC)
VOH3
Output HIGH voltage (RGC)
Note:
- 0.3
0.4
VRGO - 0.8
0.4
VCC-0.4
0.4
VCC-4.0
Test Conditions
V
IOL = 1.0mA
V
IOH = -0.4mA
V
IOL = 100uA
V
IOH = -20uA
V
IOL = 2mA, RGP = VCC,
RGO = 5V
V
IOH = -20µA, RGP = VCC - 4V,
RGO = 5V
(1) VIL min. and VIH max. are for reference only and are not 100% tested.
REV 1.1.8 12/10/02
www.xicor.com
Characteristics subject to change without notice.
29 of 40
X3100/X3101 – Preliminary Information
OPERATING CHARACTERISTICS X3100 (Over the recommended operating conditions unless otherwise specified)
Description
5V regulated voltage
5VDC voltage regulator current
limit
Sym
VRGO
Condition
Min
Typ(2)
Max
Unit
5.5
V
On power up or at wake-up
4.5
After self-tuning
(@10mA VRGO current; 25oC)
4.98
After self-tuning
(@10mA VRGO current; 0 - 50oC)(5)
4.95
5.02
After self-tuning
(@50mA VRGO current)(5)
4.90
5.00
ILMT(3) RLMT=10Ω
4.99
5.00
250
V
mA
VCC supply current (1)
Icc1
Normal operation
85
250
µA
VCC supply current (2)
Icc2
during nonvolatile EEPROM write
1.3
2.5
mA
VCC supply current (3)
Icc3
During EEPROM read
SCK=3.3MHz
0.9
1.2
mA
VCC supply current (4)
Icc4
Sleep mode
1
µA
VCC supply current (5)
Icc5
Monitor mode
AN2, AN1, AN0 not equal to 0.
600
µA
V
Cell over-charge protection mode
voltage threshold
(Default in Boldface)
VOV(4)
VOV = 4.20V (VOV1, VOV0 = 0,0)
0oC to 50oC
4.10
4.15
4.275
4.25
VOV = 4.25V (VOV1, VOV0 = 0,1)
0oC to 50oC
4.15
4.20
4.325
4.30
V
VOV = 4.30V (VOV1, VOV0 = 1,0)
0oC to 50oC
4.2
4.25
4.375
4.35
V
VOV = 4.35V (VOV1, VOV0 = 1,1)
0oC to 50oC
4.25
4.425
V
4.30
4.40
Cell over-charge protection mode
release voltage threshold
(Default in Boldface)
VOVR
Cell over-charge detection time
TOV(5) COV=0.1uF
Cell over-discharge protection
mode (SLEEP) threshold.
(Default in Boldface)
Cell over-discharge protection
mode release threshold
(Default in Boldface)
Cell over-discharge detection time
Cell over-discharge release time
REV 1.1.8 12/10/02
VUV(4)
365
VOV 0.25
VOV 0.20
0.5
1
VOV 0.15
V
1.5
s
VUV = 1.95V (VUV1, VUV0 = 0,0)
1.85
2.05
V
VUV = 2.05V (VUV1, VUV0 = 0,1)
1.95
2.15
V
VUV = 2.15V (VUV1, VUV0 = 1,0)
2.05
2.25
V
VUV = 2.25V (VUV1, VUV0 = 1,1)
2.15
2.35
V
VUVR
VUV +
0.65
VUV +
0.7
VUV +
0.75
V
TUV
CUV=0.1µF(5)
CUV=200pF
0.5
1
1
2
1.5
3
s
ms
TUVR
CUV=0.1µF(5)
CUV=200pF
3.5
80
7
100
10.5
120
ms
µs
www.xicor.com
Characteristics subject to change without notice.
30 of 40
X3100/X3101 – Preliminary Information
Description
Sym
Over-current mode detection
voltage
(Default in Boldface)
VOC(4)
Over-current mode detection time
Over-current mode release time
Min
VOC = 0.075V (VOC1, VOC0 = 0,0)
0oC to 50oC
Typ(2)
Max
Unit
0.050
0.060
0.100
0.090
V
VOC = 0.100V (VOC1, VOC0 = 0,1)
0oC to 50oC
0.075
0.085
0.125
0.115
V
VOC = 0.125V (VOC1, VOC0 = 1,0)
0oC to 50oC
0.100
0.110
0.150
0.140
V
VOC = 0.150V (VOC1, VOC0 = 1,1)
0oC to 50oC
0.125
0.135
0.175
0.165
V
TOC
COC=0.001µF(5)
COC=200pF
5
1
10
2
15
3
ms
TOCR
COC=0.001µF(5)
COC=200pF
5
1
10
2
15
3
ms
Releases when OVP/LMON pin >
2.5V
200
250
VCE
VCE=1.4V (Default)(5)
1.30
1.40
VSLR
See Wake-up test circuit
VSLP
See Sleep test circuit
Load resistance over-current mode
release condition
Cell charge threshold voltage
Condition
kΩ
1.50
V
12.5
15.5
V
11.5
14.5
V
X3100 wake-up voltage
(For Vcc above this voltage, the device
wakes up)
X3100 sleep voltage
(For Vcc above this voltage, the device
cannot go to sleep)
Notes: (2)
(3)
(4)
(5)
Typical at 25°C.
See Figure 10 on page 21.
The default setting is set at the time of shipping, but may be changed by the user via changes in the configuration register.
For reference only, this parameter is not 100% tested.
Wake-up test circuit (X3100)
Sleep test circuit (X3100)
Vcc
Vcc
Vcc
Vcc
RGP
RGC
VCELL2
RGP
VCELL1
VCELL1
RGO
RGC
1V
VCELL2
VRGO
RGO
VRGO
1V
VCELL3
VCELL3
1V
VCELL4
VCELL4
1V
Vss
Vss
Increase Vcc until VRGO turns on
REV 1.1.8 12/10/02
Decrease Vcc until VRGO turns off
www.xicor.com
Characteristics subject to change without notice.
31 of 40
X3100/X3101 – Preliminary Information
OPERATING CHARACTERISTICS X3101 (Over the recommended operating conditions unless otherwise specified)
Description
5V regulated voltage
Sym
VRGO
Condition
Min
Typ(2)
Max
Unit
5.5
V
On power up or at wake-up
4.5
After self-tuning
(@10mA VRGO current; 25oC)
4.98
After self-tuning
(@10mA VRGO current; 0 - 50oC)(5)
4.95
5.02
After self-tuning
(@50mA VRGO current)(5)
4.90
5.00
4.99
5.00
V
5VDC voltage regulator current limit ILMT(3) RLMT=10Ω
250
VCC supply current (1)
Icc1
Normal operation
85
250
µA
VCC supply current (2)
Icc2
during nonvolatile EEPROM write
1.3
2.5
mA
VCC supply current (3)
Icc3
During EEPROM read
SCK=3.3MHz
0.9
1.2
mA
VCC supply current (4)
Icc4
Sleep mode
1
µA
VCC supply current (5)
Icc5
Monitor mode
AN2, AN1, AN0 not equal to 0.
600
µA
V
Cell over-charge protection mode
voltage threshold
(Default in Boldface)
VOV(4)
VOV = 4.20V (VOV1, VOV0 = 0,0)
0oC to 50oC
4.10
4.15
4.275
4.25
VOV = 4.25V (VOV1, VOV0 = 0,1)
0oC to 50oC
4.15
4.20
4.325
4.30
V
VOV = 4.30V (VOV1, VOV0 = 1,0)
0oC to 50oC
4.2
4.25
4.375
4.35
V
VOV = 4.35V (VOV1, VOV0 = 1,1)
0oC to 50oC
4.25
4.425
V
4.30
4.40
Cell over-charge protection mode
release voltage threshold
(Default in Boldface)
VOVR
Cell over-charge detection time
TOV(5) COV=0.1uF
Cell over-discharge protection
mode (SLEEP) threshold.
(Default in Boldface)
Cell over-discharge protection
mode release threshold
(Default in Boldface)
Cell over-discharge detection time
Cell over-discharge release time
REV 1.1.8 12/10/02
VUV(4)
365
mA
VOV 0.25
VOV 0.20
VOV 0.15
V
0.5
1
1.5
s
VUV = 2.25V (VUV1, VUV0 = 0,0)
2.15
2.35
V
VUV = 2.35V (VUV1, VUV0 = 0,1)
2.25
2.45
V
VUV = 2.45V (VUV1, VUV0 = 1,0)
2.35
2.55
V
VUV = 2.55V (VUV1, VUV0 = 1,1)
2.45
2.65
V
VUVR
VUV +
0.65
VUV +
0.7
VUV +
0.75
V
TUV
CUV=0.1µF(5)
CUV=200pF
0.5
1
1
2
1.5
3
s
ms
TUVR
CUV=0.1µF(5)
CUV=200pF
3.5
80
7
100
10.5
120
ms
µs
www.xicor.com
Characteristics subject to change without notice.
32 of 40
X3100/X3101 – Preliminary Information
Description
Sym
Over-current mode detection
voltage
(Default in Boldface)
VOC(4)
Over-current mode detection time
Over-current mode release time
Min
VOC = 0.075V (VOC1, VOC0 = 0,0)
0oC to 50oC
Typ(2)
Max
Unit
0.050
0.060
0.100
0.090
V
VOC = 0.100V (VOC1, VOC0 = 0,1)
0oC to 50oC
0.075
0.085
0.125
0.115
V
VOC = 0.125V (VOC1, VOC0 = 1,0)
0oC to 50oC
0.100
0.110
0.150
0.140
V
VOC = 0.150V (VOC1, VOC0 = 1,1)
0oC to 50oC
0.125
0.135
0.175
0.165
V
TOC
COC=0.001µF(5)
COC=200pF
5
1
10
2
15
3
ms
TOCR
COC=0.001µF(5)
COC=200pF
5
1
10
2
15
3
ms
Releases when OVP/LMON pin >
2.5V
200
250
VCE
VCE=1.4V (Default)(5)
1.30
1.50
V
VSLR
See Wake-up test circuit
10.5
12.5
V
VSLP
See Sleep test circuit
9.5
11.5
V
Load resistance over-current mode
release condition
Cell charge threshold voltage
Condition
kΩ
X3100 wake-up voltage
(For Vcc above this voltage, the device
wakes up)
X3100 sleep voltage
(For Vcc above this voltage, the device
cannot go to sleep)
Notes: (2)
(3)
(4)
(5)
Typical at 25°C.
See Figure 10 on page 21.
The default setting is set at the time of shipping, but may be changed by the user via changes in the configuration register.
For reference only, this parameter is not 100% tested.
Wake-up test circuit (X3101)
Sleep test circuit (X3101)
Vcc
Vcc
Vcc
Vcc
RGP
VCELL1
RGC
VCELL2
RGP
VCELL1
RGO
RGC
1V
VCELL2
VRGO
RGO
VRGO
1V
VCELL3
VCELL3
1V
VCELL4
VCELL4
Vss
Vss
Decrease Vcc until VRGO turns off
Increase Vcc until VRGO turns on
REV 1.1.8 12/10/02
www.xicor.com
Characteristics subject to change without notice.
33 of 40
X3100/X3101 – Preliminary Information
POWER-UP TIMING
Symbol
(6)
tPUR
Parameter
Min.
Power-up to SPI read operation (RDSTAT, EEREAD STAT)
(6)
tPUW1
Max.
TOC+2ms
Power-up to SPI write operation (WREN, WRDI, EEWRITE, WCFIG, SET IDL, WCNTR)
TOC+2ms
TOV+200ms
or
TUV+200ms(7)
tPUW2(6) Power-up to SPI write operation (WCNTR - bits 10 and 11)
Notes: (6) tPUR, tPUW1 and tPUW2 are the delays required from the time VCC is stable until a read or write can be initiated. These parameters
are not 100% tested.
(7) Whichever is longer.
CAPACITANCE TA=+25°C, f= 1 MHz, VRGO=5V
Symbol
COUT
(8)
CIN(8)
Parameter
Max.
Units
Conditions
Output capacitance (SO)
8
pF
VOUT=0V
Input capacitance (SCK, SI, CS)
6
pF
VIN=0V
Notes: (8) This parameter is not 100% tested.
Equivalent A.C. Load Circuit
A.C. TEST CONDITIONS
Input pulse levels
5V
2061Ω
0.5 – 4.5V
Input rise and fall times
10ns
Input and output timing level
2.5V
SO
3025Ω
REV 1.1.8 12/10/02
30pF
www.xicor.com
Characteristics subject to change without notice.
34 of 40
X3100/X3101 – Preliminary Information
A.C. CHARACTERISTICS (Over the recommended operating conditions, unless otherwise specified.)
SERIAL INPUT TIMING
Symbol
Parameter
Voltage
Min.
Max.
Units
0
3.3
MHz
fSCK
Clock frequency
tCYC
Cycle time
300
ns
tLEAD
CS lead time
150
ns
tLAG
CS lag time
150
ns
tWH
Clock HIGH time
130
ns
tWL
Clock LOW time
130
ns
tSU
Data setup time
20
ns
tH
Data hold time
20
ns
(9)
Data in rise time
2
µs
(9)
Data in fall time
2
µs
tRI
tFI
CS deselect time
tCS
(10)
100
ns
Write cycle time
tWC
5
ms
Notes: (9) This parameter is not 100% tested
(10)tWC is the time from the rising edge of CS after a valid write sequence has been sent to the end of the self-timed internal nonvolatile
write cycle.
Serial Input Timing
tCS
CS
tLEAD
tLAG
SCK
tH
tSU
SI
tRI
MSB IN
tFI
LSB IN
SO
REV 1.1.8 12/10/02
www.xicor.com
Characteristics subject to change without notice.
35 of 40
X3100/X3101 – Preliminary Information
Serial Output Timing
Symbol
Parameter
Voltage
Min.
Max.
Units
0
3.3
MHz
fSCK
Clock Frequency
tDIS
Output Disable Time
150
ns
Output Valid from Clock LOW
130
ns
tV
Output Hold Time
tHO
0
ns
(11)
Output Rise Time
50
ns
(11)
Output Fall Time
50
ns
tRO
tFO
Notes: (11)This parameter is not 100% tested.
Serial Output Timing
CS
tCYC
tWH
tLAG
SCK
tHO
tV
SO
SI
MSB Out
MSB–1 Out
tWL
tDIS
LSB Out
ADDR
LSB In
SYMBOL TABLE
WAVEFORM
REV 1.1.8 12/10/02
INPUTS
OUTPUTS
Must be
steady
Will be
steady
May change
from LOW
to HIGH
Will change
from LOW
to HIGH
May change
from HIGH
to LOW
Will change
from HIGH
to LOW
Don’t Care:
Changes
Allowed
N/A
Changing:
State Not
Known
Center Line
is High
Impedance
www.xicor.com
Characteristics subject to change without notice.
36 of 40
X3100/X3101 – Preliminary Information
Analog Output Response Time
Symbol
Parameter
tVSC
tCSGO
tCO
Min.
Typ.
Max.
Units
AO Output Stabilization Time (Voltage Source Change)
1.0
ms
AO Output Stabilization Time (Current Sense Gain Change)
1.0
ms
Control Outputs Response Time (UVP/OCP, OVP/MON, CB4,
CB3, CB2, CB1, RGC)
-1.0
µs
ANALOG OUTPUT RESPONSE TIME
Change in Voltage Source
AS2:AS0
AO
tVSC
tVSC
Change in Current Sense Gain Amplification and Control Bits
CS
SCK
DI
Control Reg
OVPC
Bit10
AO
Current Sense
Gain Change
UVP/OCP
OVP/LMON
CB4:CB1
RGC
Control
Outputs
CSG1 CSG0
SLP
0
Bit9
Bit7
Bit6
Bit8
0
x
Bit5
Old Gain
tCSGO
New Gain
On
Off
tCO
REV 1.1.8 12/10/02
www.xicor.com
Characteristics subject to change without notice.
37 of 40
X3100/X3101 – Preliminary Information
TYPICAL OPERATING CHARACTERISTICS
Norm al Operating Current
Monitor Mode Current
450
125
Current (uA)
Current (uA)
150
100
75
50
400
350
300
-20
25
80
-20
25
Tem perature
X3100 Over Discharge Trip Voltage (Typical)
X3100/X3101 Over Charge Trip Voltage (Typical)
4.35
Voltage (V)
Voltage (V)
4.40
4.30
4.25
4.20
2.30
2.25
2.20
2.15
2.10
2.05
2.00
1.95
4.15
-25
-25
80
Tem perature
25
25
75
75
Temperature (Deg C)
Temperature (Deg C)
4.2V Setting
4.3V Setting
4.25V Setting
4.35V Setting
1.95V Setting
2.15V Setting
X3101 Over Discharge Trip Voltage (Typical)
Voltage Regulator Output (Typical)
Vcc = 10.8V to 16V Rlim = 15 Ohm (Ilim = 200mA)
Voltage (V)
2.55
2.50
2.45
2.40
2.35
2.30
2.25
25
75
Regulator Voltage (V)
2.60
-25
5.020
5.000
4.980
4.960
4.940
4.920
4.900
4.880
Temperature (Deg C)
2.25V Setting
2.45V Setting
2.05V Setting
2.25V Setting
1
10
50
100
Load (mA)
2.35V Setting
2.55V Setting
-25 degC
25 degC
75 degC
Regulated Voltage
Voltage Regulator Output (Typical)
Vcc = 10.8V to 16V Rlim = 15 Ohm (Ilim = 200mA)
5.020
5.000
4.980
4.960
4.940
4.920
4.900
4.880
-25
25
75
Temperature
1mA Load
10mA Load
50mA Load
100 mA Load
For typical performance of current and voltage monitoring circuits, please refer to Application Note AN142 and AN143
REV 1.1.8 12/10/02
www.xicor.com
Characteristics subject to change without notice.
38 of 40
X3100/X3101 – Preliminary Information
28-Lead Plastic, TSSOP, Package Code V28
.026 (.65) BSC
.169 (4.3)
.252 (6.4) BSC
.177 (4.5)
.377 (9.60)
.385 (9.80)
.047 (1.20)
.0075 (.19)
.0118 (.30)
.002 (.06)
.005 (.15)
.010 (.25)
Gage Plane
0° – 8°
(4.16) (7.72)
Seating Plane
.020 (.50)
.030 (.75)
(1.78)
Detail A (20X)
(0.42)
(0.65)
.031 (.80)
.041 (1.05)
All Measurements are Typical
See Detail “A”
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
REV 1.1.8 12/10/02
www.xicor.com
Characteristics subject to change without notice.
39 of 40
X3100/X3101 – Preliminary Information
ORDERING INFORMATION
X3100 P
X3101
T
–
V
VCC Limits
Blank=6V to 24V
Device
Temperature Range
Blank=Commercial= -20°C to +70°C
Package
V28 = 28-Lead TSSOP
LIMITED WARRANTY
©Xicor, Inc. 2000 Patents Pending
Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty, express,
statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. Xicor, Inc. makes
no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices at any time and
without notice.
Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, or licenses are implied.
TRADEMARK DISCLAIMER:
Xicor and the Xicor logo are registered trademarks of Xicor, Inc. AutoStore, Direct Write, Block Lock, SerialFlash, MPS, and XDCP are also trademarks of Xicor, Inc. All
others belong to their respective owners.
U.S. PATENTS
Xicor products are covered by one or more of the following U.S. Patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846;
4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,023,694; 5,084,667; 5,153,880; 5,153,691; 5,161,137;
5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. Foreign patents and additional patents pending.
LIFE RELATED POLICY
In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection and
correction, redundancy and back-up features to prevent such an occurence.
Xicor’s products are not authorized for use in critical components in life support devices or systems.
1.
Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to
perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.
2.
A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
REV 1.1.8 12/10/02
www.xicor.com
Characteristics subject to change without notice.
40 of 40