MC10EP105 Product Preview Quad 2-Input Differential AND/NAND The MC10EP105 is a 2–input differential AND/NAND gate. Each gate is functionally equivalent to a EP05 and LVEL05 devices. With AC performance much faster than the LVEL05 device, the EP105 is ideal for applications requiring the fastest AC performance available. All VCC and VEE pins must be externally connected to power supply to guarantee proper operation. • • • • • • • • • • 190ps Typical Propagation Delay High Bandwidth to 3 Ghz Typical ECL mode: 0V VCC with VEE = –3.0V to –5.5V PECL mode: 3.0V to 5.5V VCC with VEE = 0V Internal Input Pulldown Resistors ESD Protection: >2KV HBM, >100V MM New Differential Input Common Mode Range Moisture Sensitivity Level 2 For Additional Information, See Application Note AND8003/D Flammability Rating: UL–94 code V–0 @ 1/8”, Oxygen Index 28 to 34 Transistor Count = 444 devices http://onsemi.com 32–LEAD TQFP FA SUFFIX CASE 873A MARKING DIAGRAM* A WL YY WW MC10 EP105 AWLYYWW = Assembly Location = Wafer Lot = Year = Work Week 32 1 *For additional information, see Application Note AND8002/D PIN DESCRIPTION LOGIC DIAGRAM PIN D0a D0a D0b D0b D1a D1a D1b D1b D2a D2a D2b D2b D3a D3a D3b D3b Q0 FUNCTION Dna, Dnb, Dna, Dnb ECL Data Inputs Qn, Qn ECL Data Outputs Q0 Q1 VBB Reference Voltage Output VCC Positive Supply VEE Negative, 0 Supply Q1 Q2 TRUTH TABLE Q2 Q3 Q3 Dna Dnb Dna Dnb Qn Qn L L H H L H L H H H L L H L H L L L L H H H H L ORDERING INFORMATION Device This document contains information on a product under development. ON Semiconductor reserves the right to change or discontinue this product without notice. Semiconductor Components Industries, LLC, 1999 December, 1999 – Rev. 0 1 Package Shipping MC10EP105FA TQFP 250 Units/Tray MC10EP105FAR2 TQFP 2000 Tape & Reel Publication Order Number: MC10EP105/D MC10EP105 D0b D1a D1a D1b D1b D2a D2a D2b 24 23 22 21 20 19 18 17 D0b 25 16 D2b D0a 26 15 D3a D0a 27 14 D3a VEE 28 13 VCC MC10EP105 Q0 29 12 D3b Q0 30 11 D3b VCC 31 10 VEE VCC 32 9 NC 1 2 VCC Q1 3 4 5 6 Q1 Q2 Q2 Q3 7 8 Q3 VCC Figure 1. 32–Lead TQFP Pinout (Top View) Warning: All VCC and VEE pins must be externally connected to Power Supply to guarantee proper operation. MAXIMUM RATINGS* Symbol Parameter Value Unit VEE Power Supply (VCC = 0V) –6.0 to 0 VDC VCC Power Supply (VEE = 0V) 6.0 to 0 VDC VI Input Voltage (VCC = 0V, VI not more negative than VEE) –6.0 to 0 VDC VI Input Voltage (VEE = 0V, VI not more positive than VCC) 6.0 to 0 VDC Iout Output Current 50 100 mA TA Operating Temperature Range –40 to +85 °C Tstg Storage Temperature θJA Thermal Resistance (Junction–to–Ambient) θJC Thermal Resistance (Junction–to–Case) Tsol Solder Temperature (<2 to 3 Seconds: 245°C desired) Continuous Surge Still Air 500lfpm * Maximum Ratings are those values beyond which damage to the device may occur. http://onsemi.com 2 –65 to +150 °C 80 55 °C/W 12 to 17 °C/W 265 °C MC10EP105 DC CHARACTERISTICS, ECL/LVECL (VCC = 0V; VEE = –5.5V to –3.0V) (Note 4.) –40°C Symbol Characteristic Min 25°C Typ Max Min Typ 85°C Max Min Typ Max 59 Unit IEE Power Supply Current (Note 1.) VOH Output HIGH Voltage (Note 2.) –1135 –1060 –885 –1070 –945 –820 –1010 –885 –760 mV VOL Output LOW Voltage (Note 2.) –1935 –1810 –1685 –1870 –1745 –1620 –1810 –1685 –1560 mV VIH Input HIGH Voltage Single Ended –1210 –885 –1145 –820 –1085 –760 mV VIL Input LOW Voltage Single Ended –1935 –1610 –1870 –1545 –1810 –1485 mV 0.0 V 150 µA VIHCMR Input HIGH Voltage Common Mode Range (Note 3.) IIH Input HIGH Current IIL Input LOW Current VEE+2.0 0.0 VEE+2.0 150 D D 0.5 –150 mA 0.0 VEE+2.0 150 0.5 –150 µA 0.5 –150 NOTE: 10EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500lfpm is maintained. 1. VCC = 0V, VEE = VEEmin to VEEmax, all other pins floating. 2. All loading with 50 ohms to VCC–2.0 volts. 3. VIHCMR min varies 1:1 with VEE, max varies 1:1 with VCC. 4. Input and output parameters vary 1:1 with VCC. DC CHARACTERISTICS, LVPECL (VCC = 3.3V ± 0.3V, VEE = 0V) (Note 8.) –40°C Symbol Characteristic Min 25°C Typ Max Min Typ 85°C Max Min Typ Max 59 Unit IEE Power Supply Current (Note 5.) VOH Output HIGH Voltage (Note 6.) 2165 2240 2415 2230 2355 2480 2290 2415 2540 mV VOL Output LOW Voltage (Note 6.) 1365 1490 1615 1430 1555 1680 1490 1615 1740 mV VIH Input HIGH Voltage Single Ended 2090 2415 2155 2480 2215 2540 mV VIL Input LOW Voltage Single Ended 1365 1690 1430 1755 1490 1815 mV 2.0 3.3 2.0 3.3 2.0 3.3 V 150 µA VIHCMR Input HIGH Voltage Common Mode Range (Note 7.) IIH Input HIGH Current IIL Input LOW Current 150 D D 0.5 –150 mA 150 0.5 –150 0.5 –150 µA NOTE: 10EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500lfpm is maintained. 5. VCC = 3.3V, VEE = 0V, all other pins floating. 6. All loading with 50 ohms to VCC–2.0 volts. 7. VIHCMR min varies 1:1 with VEE, max varies 1:1 with VCC. 8. Input and output parameters vary 1:1 with VCC. http://onsemi.com 3 MC10EP105 DC CHARACTERISTICS, PECL (VCC = 5.0V ± 0.5V, VEE = 0V) (Note 12.) –40°C Symbol Characteristic Min 25°C Typ Max Min Typ 85°C Max Min Typ Max 59 Unit IEE Power Supply Current (Note 9.) VOH Output HIGH Voltage (Note 10.) 3865 3940 4115 3930 4055 4180 3990 4115 4240 mV VOL Output LOW Voltage (Note 10.) 3065 3190 3315 3130 3255 3380 3190 3315 3440 mV VIH Input HIGH Voltage Single Ended 3790 4115 3855 4180 3915 4240 mV VIL Input LOW Voltage Single Ended 3065 3390 3130 3455 3190 3515 mV 2.0 5.0 2.0 5.0 2.0 5.0 V 150 µA VIHCMR Input HIGH Voltage Common Mode Range (Note 11.) IIH Input HIGH Current IIL Input LOW Current 150 D D 0.5 –150 mA 150 0.5 –150 µA 0.5 –150 NOTE: 10EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500lfpm is maintained. 9. VCC = 5.0V, VEE = 0V, all other pins floating. 10. All loading with 50 ohms to VCC–2.0 volts. 11. VIHCMR min varies 1:1 with VEE, max varies 1:1 with VCC. 12. Input and output parameters vary 1:1 with VCC. AC CHARACTERISTICS (VCC = 0V; VEE = –3.0V to –5.5V) or (VCC = 3.0V to 5.5V; VEE = 0V) –40°C Symbol Characteristic fmax Maximum Toggle Frequency (Note 13.) tPLH, tPHL Propagation Delay to Output Differential tSKEW Duty Cycle Skew (Note 14.) tJITTER Cycle–to–Cycle Jitter VPP Input Voltage Swing (Diff.) Min Typ 25°C Max Min 3.0 Typ 85°C Max Min 3.0 Typ Max 3.0 190 5.0 5.0 TBD 150 800 ps 20 5.0 TBD 1200 150 800 Unit GHz 20 ps 1200 mV TBD 1200 150 800 ps tr Output Rise/Fall Times Q 120 ps tf (20% – 80%) 13. Fmax guaranteed for functionality only. VOL and VOH levels are guaranteed at DC only. 14. Skew is measured between outputs under identical transitions. Duty cycle skew is defined only for differential operation when the delays are measured from the cross point of the inputs to the cross point of the outputs. http://onsemi.com 4 MC10EP105 PACKAGE DIMENSIONS A –T–, –U–, –Z– TQFP FA SUFFIX 32–LEAD PLASTIC PACKAGE CASE 873A–02 ISSUE A 4X A1 32 0.20 (0.008) AB T–U Z 25 1 –U– –T– B V AE P B1 DETAIL Y 17 8 V1 AE DETAIL Y 9 4X –Z– 9 0.20 (0.008) AC T–U Z S1 S DETAIL AD G –AB– 0.10 (0.004) AC AC T–U Z –AC– BASE METAL ÉÉ ÉÉ ÉÉ ÉÉ F 8X M_ R M N D J 0.20 (0.008) SEATING PLANE SECTION AE–AE W K X DETAIL AD Q_ GAUGE PLANE H 0.250 (0.010) C E http://onsemi.com 5 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE –AB– IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS –T–, –U–, AND –Z– TO BE DETERMINED AT DATUM PLANE –AB–. 5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE –AC–. 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.250 (0.010) PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE –AB–. 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE D DIMENSION TO EXCEED 0.520 (0.020). 8. MINIMUM SOLDER PLATE THICKNESS SHALL BE 0.0076 (0.0003). 9. EXACT SHAPE OF EACH CORNER MAY VARY FROM DEPICTION. DIM A A1 B B1 C D E F G H J K M N P Q R S S1 V V1 W X MILLIMETERS MIN MAX 7.000 BSC 3.500 BSC 7.000 BSC 3.500 BSC 1.400 1.600 0.300 0.450 1.350 1.450 0.300 0.400 0.800 BSC 0.050 0.150 0.090 0.200 0.500 0.700 12_ REF 0.090 0.160 0.400 BSC 1_ 5_ 0.150 0.250 9.000 BSC 4.500 BSC 9.000 BSC 4.500 BSC 0.200 REF 1.000 REF INCHES MIN MAX 0.276 BSC 0.138 BSC 0.276 BSC 0.138 BSC 0.055 0.063 0.012 0.018 0.053 0.057 0.012 0.016 0.031 BSC 0.002 0.006 0.004 0.008 0.020 0.028 12_ REF 0.004 0.006 0.016 BSC 1_ 5_ 0.006 0.010 0.354 BSC 0.177 BSC 0.354 BSC 0.177 BSC 0.008 REF 0.039 REF MC10EP105 Notes http://onsemi.com 6 MC10EP105 Notes http://onsemi.com 7 MC10EP105 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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