MC10E111, MC100E111 5VECL 1:9 Differential Clock Driver The MC10E/100E111 is a low skew 1-to-9 differential driver, designed with clock distribution in mind. It accepts one signal input, which can be either differential or else single-ended if the VBB output is used. The signal is fanned out to 9 identical differential outputs. An enable input is also provided. A HIGH disables the device by forcing all Q outputs LOW and all Q outputs HIGH. The device is specifically designed, modeled and produced with low skew as the key goal. Optimal design and layout serve to minimize gate to gate skew within-device, and empirical modeling is used to determine process control limits that ensure consistent t pd distributions from lot to lot. The net result is a dependable, guaranteed low skew device. To ensure that the tight skew specification is met it is necessary that both sides of the differential output are terminated into 50 Ω, even if only one side is being used. In most applications, all nine differential pairs will be used and therefore terminated. In the case where fewer than nine pairs are used, it is necessary to terminate at least the output pairs on the same package side (i.e. sharing the same VCCO) as the pair(s) being used on that side, in order to maintain minimum skew. Failure to do this will result in small degradations of propagation delay (on the order of 10–20 ps) of the output(s) being used which, while not being catastrophic to most designs, will mean a loss of skew margin. The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01 F capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open. The 100 Series contains temperature compensation. • • • • • http://onsemi.com MARKING DIAGRAMS MC10E111FN AWLYYWW PLCC–28 FN SUFFIX CASE 776 A WL YY WW 28 1 = Assembly Location = Wafer Lot = Year = Work Week MC100E111FN AWLYYWW 28 1 ORDERING INFORMATION Device Package Shipping MC10E111FN PLCC–28 37 Units/Rail MC10E111FNR2 PLCC–28 500 Units/Reel Guaranteed Skew Spec MC100E111FN PLCC–28 37 Units/Rail Differential Design MC100E111FNR2 PLCC–28 500 Units/Reel VBB Output PECL Mode Operating Range: VCC= 4.2 V to 5.7 V with VEE= 0 V NECL Mode Operating Range: VCC= 0 V with VEE= –4.2 V to –5.7 V Internal Input Pulldown Resistors • • ESD Protection: > 3 KV HBM • Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test • Moisture Sensitivity Level 1 • • For Additional Information, see Application Note AND8003/D Flammability Rating: UL–94 code V–0 @ 1/8”, Oxygen Index 28 to 34 Transistor Count = 178 devices Semiconductor Components Industries, LLC, 2001 January, 2001 – Rev. 5 1 Publication Order Number: MC10E111/D MC10E111, MC100E111 LOGIC DIAGRAM AND PINOUT ASSIGNMENT Q0 Q0 Q1 VCCO Q1 Q2 Q2 25 24 23 20 19 22 21 Q0 LOGIC SYMBOL Q0 Q1 Q1 VEE 26 18 Q3 EN 27 17 Q3 IN 28 16 Q4 15 VCCO IN Q4 Q4 Pinout: 28-Lead PLCC (Top View) Q2 Q2 Q3 Q3 VCC 1 IN 2 14 Q4 IN VBB 3 13 Q5 EN NC 4 12 Q5 5 6 7 8 Q8 Q8 Q7 VCCO 9 10 11 Q7 Q6 Q6 Q5 Q5 Q6 Q6 Q7 Q7 * All VCC and VCCO pins are tied together on the die. Q8 Warning: All VCC, VCCO, and VEE pins must be externally connected to Power Supply to guarantee proper operation. Q8 VBB PIN DESCRIPTION PIN IN, IN EN Q0, Q0–Q8, Q8 VBB VCC, VCCO VEE NC FUNCTION ECL Differential Input Pair ECL Enable ECL Differential Outputs Reference Voltage Output Positive Supply Negative Supply No Connect MAXIMUM RATINGS (Note 1.) Symbol Parameter Condition 1 Condition 2 Rating Units 8 V VCC PECL Mode Power Supply VEE = 0 V VEE NECL Mode Power Supply VCC = 0 V –8 V VI PECL C Mode ode Input u Voltage o age VEE = 0 V VI VCC 6 V NECL Mode Input Voltage VCC = 0 V VI VEE –6 V Iout Output Current Continuous Surge 50 100 mA mA IBB VBB Sink/Source ± 0.5 mA TA Operating Temperature Range 0 to +85 °C Tstg Storage Temperature Range –65 to +150 °C θJA Thermal Resistance (Junction to Ambient) 0 LFPM 500 LFPM 28 PLCC 28 PLCC 63.5 43.5 °C/W °C/W θJC Thermal Resistance (Junction to Case) std bd 28 PLCC 22 to 26 °C/W VEE PECL Operating Range 4.2 to 5.7 V NECL Operating Range –5.7 to –4.2 V 265 °C Tsol Wave Solder <2 to 3 sec @ 248°C 1. Maximum Ratings are those values beyond which device damage may occur. http://onsemi.com 2 MC10E111, MC100E111 10E SERIES PECL DC CHARACTERISTICS VCCx= 5.0 V; VEE= 0.0 V (Note 1.) –40°C Symbol Characteristic Min 25°C Typ Max 48 60 Min 85°C Typ Max 48 60 Min Typ Max Unit 48 60 mA IEE Power Supply Current VOH Output HIGH Voltage (Note 2.) 4020 4105 4190 4090 4185 4280 mV VOL Output LOW Voltage (Note 2.) 3050 3210 3370 3050 3227 3405 mV VIH Input HIGH Voltage (Single Ended) 3870 4030 4190 3940 4110 4280 mV VIL Input LOW Voltage (Single Ended) 3050 3285 3520 3050 3302 3555 mV VBB Output Voltage Reference 3.57 3.7 3.65 3.75 3.69 3.90 V VIHCMR Input HIGH Voltage Common Mode Range (Differential) (Note 3.) 2.6 4.6 2.6 4.6 2.6 4.6 V IIH Input HIGH Current 150 µA IIL Input LOW Current 150 150 0.5 0.25 0.3 µA 0.2 NOTE: Devices are designed to meet the DC specifications shown in the above table, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained. 1. Input and output parameters vary 1:1 with VCC. VEE can vary +0.46 V / –0.06 V. 2. Outputs are terminated through a 50 ohm resistor to VCC–2 volts. 3. VIHCMR min varies 1:1 with VEE, max varies 1:1 with VCC. 10E SERIES NECL DC CHARACTERISTICS VCCx= 0.0 V; VEE= –5.0 V (Note 1.) –40°C Symbol Characteristic Min 25°C Typ Max 48 60 Min Typ 85°C Max Min Typ Max Unit IEE Power Supply Current 48 60 48 60 mA VOH Output HIGH Voltage (Note 2.) –980 –895 –810 –910 –815 –720 mV VOL Output LOW Voltage (Note 2.) –1950 –1790 –1630 –1950 –1773 –1595 mV VIH Input HIGH Voltage (Single Ended) –1130 –970 –810 –1060 –890 –720 mV VIL Input LOW Voltage (Single Ended) –1950 –1715 –1480 –1950 –1698 –1445 mV VBB Output Voltage Reference –1.43 –1.30 –1.35 –1.25 –1.31 –1.19 V VIHCMR Input HIGH Voltage Common Mode Range (Differential) (Note 3.) –2.4 –0.4 –2.4 –0.4 –0.4 V IIH Input HIGH Current 150 µA IIL Input LOW Current 150 –2.4 150 0.5 0.065 0.3 0.2 µA NOTE: Devices are designed to meet the DC specifications shown in the above table, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained. 1. Input and output parameters vary 1:1 with VCC. VEE can vary +0.46 V / –0.06 V. 2. Outputs are terminated through a 50 ohm resistor to VCC–2 volts. 3. VIHCMR min varies 1:1 with VEE, max varies 1:1 with VCC. http://onsemi.com 3 MC10E111, MC100E111 100E SERIES PECL DC CHARACTERISTICS VCCx= 5.0 V; VEE= 0.0 V (Note 1.) –40°C Symbol Characteristic Min 25°C Typ Max 48 60 Min 85°C Typ Max 48 60 Min Typ Max Unit 55 69 mA IEE Power Supply Current VOH Output HIGH Voltage (Note 2.) 3975 4050 4120 3975 4050 4120 mV VOL Output LOW Voltage (Note 2.) 3190 3255 3380 3190 3260 3380 mV VIH Input HIGH Voltage (Single Ended) 3835 4120 4120 3835 4120 4120 mV VIL Input LOW Voltage (Single Ended) 3190 3525 3525 3190 3525 3525 mV VBB Output Voltage Reference 3.64 3.75 3.62 3.74 3.62 3.74 V VIHCMR Input HIGH Voltage Common Mode Range (Differential) (Note 3.) 2.6 4.6 2.6 4.6 2.6 4.6 V IIH Input HIGH Current 150 µA IIL Input LOW Current 150 150 0.5 0.25 0.5 µA 0.2 NOTE: Devices are designed to meet the DC specifications shown in the above table, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained. 1. Input and output parameters vary 1:1 with VCC. VEE can vary +0.46 V / –0.8 V. 2. Outputs are terminated through a 50 ohm resistor to VCC–2 volts. 3. VIHCMR min varies 1:1 with VEE, max varies 1:1 with VCC. 100E SERIES NECL DC CHARACTERISTICS VCCx= 0.0 V; VEE= –5.0 V (Note 1.) –40°C Symbol Characteristic Min 25°C Typ Max 48 60 Min Typ 85°C Max Min Typ Max Unit IEE Power Supply Current 48 60 55 69 mA VOH Output HIGH Voltage (Note 2.) –1025 –950 –880 –1025 –950 –880 mV VOL Output LOW Voltage (Note 2.) –1810 –1745 –1620 –1810 –1740 –1620 mV VIH Input HIGH Voltage (Single Ended) –1165 –880 –880 –1165 –880 –880 mV VIL Input LOW Voltage (Single Ended) –1810 –1475 –1475 –1810 –1475 –1475 mV VBB Output Voltage Reference –1.38 –1.25 –1.38 –1.26 –1.38 –1.26 V VIHCMR Input HIGH Voltage Common Mode Range (Differential) (Note 3.) –2.4 –0.4 –2.4 –0.4 –2.4 –0.4 V IIH Input HIGH Current 150 µA IIL Input LOW Current 150 150 0.5 0.25 0.5 0.2 µA NOTE: Devices are designed to meet the DC specifications shown in the above table, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained. 1. Input and output parameters vary 1:1 with VCC. VEE can vary +0.46 V / –0.8 V. 2. Outputs are terminated through a 50 ohm resistor to VCC–2 volts. 3. VIHCMR min varies 1:1 with VEE, max varies 1:1 with VCC. http://onsemi.com 4 MC10E111, MC100E111 AC CHARACTERISTICS VCCx = 5.0 V; VEE= 0.0 V or VCCx= 0.0 V; VEE= –5.0 V (Note 1.) –40°C Symbol Characteristic Min 25°C Typ Max Min TBD Typ 85°C Max Min TBD Typ Max TBD Unit fMAX Maximum Toggle Frequency GHz tPLH tPHL Propagation Delay to Output IN (Diff) (Note 2.) IN (SE) (Note 3.) Enable (Note 4.) Disable Note 4.) 380 280 400 400 ts Setup Time (Note 6.) EN to IN 250 0 200 0 200 0 ps tH Hold Time (Note 7.) IN to EN 50 –200 0 –200 0 –200 ps tR Release Time (Note 8.) EN to IN 350 100 300 100 300 100 tskew Within-Device Skew (Note 5.) tJITTER Cycle–to–Cycle Jitter VPP Minimum Input Swing 50 tr, tf Rise/Fall Time 250 ps 680 780 900 900 25 480 430 450 450 580 630 850 850 75 25 TBD 510 460 450 450 50 25 TBD 650 275 ps 50 ps 50 375 ps TBD 50 450 610 660 850 850 600 275 mV 375 600 ps 1. 10 Series: VEE can vary +0.46 V / –0.06 V. 100 Series: VEE can vary +0.46 / –0.8 V. 2. The differential propagation delay is defined as the delay from the crossing points of the differential input signals to the crossing point of the differential output signals. 3. The single-ended propagation delay is defined as the delay from the 50% point of the input signal to the 50% point of the output signal. 4. Enable is defined as the propagation delay from the 50% point of a negative transition on EN to the 50% point of a positive transition on Q (or a negative transition on Q). Disable is defined as the propagation delay from the 50% point of a positive transition on EN to the 50% point of a negative transition on Q (or a positive transition on Q). 5. The within-device skew is defined as the worst case difference between any two similar delay paths within a single device. 6. The setup time is the minimum time that EN must be asserted prior to the next transition of IN/IN to prevent an output response greater than ±75 mV to that IN/IN transition (see Figure 1). 7. The hold time is the minimum time that EN must remain asserted after a negative going IN or a positive going IN to prevent an output response greater than ±75 mV to that IN/IN transition (see Figure 2). 8. The release time is the minimum time that EN must be deasserted prior to the next IN/IN transition to ensure an output response that meets the specified IN to Q propagation delay and output transition times (see Figure 3). IN IN IN IN IN ts EN 50% ≤ 75mV EN Q Q Q Q 50% ≤ 75mV EN tr 50% Q Q ≤ 75mV Figure 1. Setup Time IN th ≤ 75mV Figure 2. Hold Time http://onsemi.com 5 Figure 3. Release Time MC10E111, MC100E111 Q D Receiver Device Driver Device Qb Db 50 50 V TT V TT = V CC – 2.0 V Figure 4. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020 – Termination of ECL Logic Devices.) Resource Reference of Application Notes AN1404 – ECLinPS Circuit Performance at Non–Standard VIH Levels AN1405 – ECL Clock Distribution Techniques AN1406 – Designing with PECL (ECL at +5.0 V) AN1503 – ECLinPS I/O SPICE Modeling Kit AN1504 – Metastability and the ECLinPS Family AN1568 – Interfacing Between LVDS and ECL AN1596 – ECLinPS Lite Translator ELT Family SPICE I/O Model Kit AN1650 – Using Wire–OR Ties in ECLinPS Designs AN1672 – The ECL Translator Guide AND8001 – Odd Number Counters Design AND8002 – Marking and Date Codes AND8020 – Termination of ECL Logic Devices http://onsemi.com 6 MC10E111, MC100E111 PACKAGE DIMENSIONS PLCC–28 FN SUFFIX PLASTIC PLCC PACKAGE CASE 776–02 ISSUE E 0.007 (0.180) B Y BRK –N– M T L-M 0.007 (0.180) U M N S T L-M S S N S D Z –M– –L– W 28 D X 0.010 (0.250) G1 T L-M S N S S V 1 VIEW D–D A 0.007 (0.180) R 0.007 (0.180) Z C M M T L-M T L-M S S N N S 0.007 (0.180) H 0.010 (0.250) S –T– T L-M S N S K SEATING PLANE F VIEW S G1 N S K1 0.004 (0.100) J T L-M S E G M S VIEW S NOTES: 1. DATUMS -L-, -M-, AND -N- DETERMINED WHERE TOP OF LEAD SHOULDER EXITS PLASTIC BODY AT MOLD PARTING LINE. 2. DIMENSION G1, TRUE POSITION TO BE MEASURED AT DATUM -T-, SEATING PLANE. 3. DIMENSIONS R AND U DO NOT INCLUDE MOLD FLASH. ALLOWABLE MOLD FLASH IS 0.010 (0.250) PER SIDE. 4. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 5. CONTROLLING DIMENSION: INCH. 6. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM BY UP TO 0.012 (0.300). DIMENSIONS R AND U ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY. 7. DIMENSION H DOES NOT INCLUDE DAMBAR PROTRUSION OR INTRUSION. THE DAMBAR PROTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE GREATER THAN 0.037 (0.940). THE DAMBAR INTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE SMALLER THAN 0.025 (0.635). DIM A B C E F G H J K R U V W X Y Z G1 K1 INCHES MIN MAX 0.485 0.495 0.485 0.495 0.165 0.180 0.090 0.110 0.013 0.019 0.050 BSC 0.026 0.032 0.020 --0.025 --0.450 0.456 0.450 0.456 0.042 0.048 0.042 0.048 0.042 0.056 --0.020 2 10 0.410 0.430 0.040 --- http://onsemi.com 7 MILLIMETERS MIN MAX 12.32 12.57 12.32 12.57 4.20 4.57 2.29 2.79 0.33 0.48 1.27 BSC 0.66 0.81 0.51 --0.64 --11.43 11.58 11.43 11.58 1.07 1.21 1.07 1.21 1.07 1.42 --0.50 2 10 10.42 10.92 1.02 --- 0.007 (0.180) M T L-M S N S MC10E111, MC100E111 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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