www.fairchildsemi.com FAN8026G3 5-CH Motor Driver Features Description • • • • • The FAN8026G3 is a monolithic integrated circuit suitable for a 5-CH motor driver which drives a tracking actuator, a focus actuator, a sled motor, a spindle motor, and a tray motor of the CDP/CAR-CD/DVDP systems. 5-CH Balanced transformerless (BTL) driver Operating supply voltage : 4.5 V ~ 13.2V Built-in thermal shut down circuit (TSD) Built-in channel mute circuit Built-in 1-OP AMP 28-SSOPH-375SG3 Typical application • • • • Compact disk player Video compact disk player Car compact disk player Digital video disk player Ordering information Device Package Operating temp FAN8026G3 28-SSOPH-375-SG2 -35°C ~ +85°C FAN8026G3Xnote1 28-SSOPH-375-SG2 -35°C ~ +85°C FAN8026G3_NLnote2 28-SSOPH-375-SG2 -35°C ~ +85°C FAN8026G3X_NL 28-SSOPH-375-SG2 -35°C ~ +85°C Notes: 1. X : Tape&Reel 2. NL : Lead free Rev. 1.0.0 ©2004 Fairchild Semiconductor Corporation FAN8026G3 Pin Assignments DO5- DO5+ 28 27 DO4- 26 DO4+ 25 VM2 MUTE REF 24 23 22 FIN IN3 OUT3 21 20 SVCC DO1+ DO1- DO2+ 18 17 16 19 DO2- 15 FAN8026G3 2 1 2 OPIN+ OPIN- 3 OPOUT 4 5 6 7 IN5 OUT5 IN4 OUT4 FIN 8 9 10 11 12 13 GND IN2 OUT2 IN1 VM1 DO3+ 14 DO3- FAN8026G3 Pin Definitions Pin Number Pin Name I/O Pin Function Description 1 OPIN+ I OP-AMP Input(+) 2 OPIN- I OP-AMP Input(-) 3 OPOUT O OP-AMP Output 4 IN5 I CH5 Op-amp Input(-) 5 OUT5 O CH5 Op-amp Output 6 IN4 I CH4 Op-amp Input(-) 7 OUT4 O CH4 Op-amp Output 8 GND - Ground 9 IN2 I CH2 Op-amp Input(-) 10 OUT2 O CH2 Op-amp Output 11 IN1 I CH1 Input 12 VM1 - Power Supply Voltage(For CH2,CH3) 13 DO3+ O CH3 Drive Output(+) 14 DO3- O CH3 Drive Output(-) 15 DO2- O CH2 Drive Output(-) 16 DO2+ O CH2 Drive Output(+) 17 DO1- O CH1 Drive Output(-) 18 DO1+ O CH1 Drive Output(+) 19 SVCC - Power Supply Voltage(For Signal,CH1) 20 OUT3 O CH3 Op-amp Output 21 IN3 I CH3 Op-amp Input(-) 22 REF I CH1,2,3,4,5 Input Reference 23 MUTE I MUTE(CH2,3,4,5) 24 VM2 - Power Supply Voltage(For CH4,CH5,Normal Op-amp) 25 DO4+ O CH4 Drive Output(+) 26 DO4- O CH4 Drive Output(-) 27 DO5+ O CH5 Drive Output(+) 28 DO5- O CH5 Drive Output(-) 3 FAN8026G3 Internal Block Diagram VM2 OPIN+ 1 OPIN- 3 OPOUT 2 SVCC OUT5 5 IN5 4 VM2 10K 27 DO5+ 10K Level Shift 28 DO5- 24 VM2 SVCC VM2 7 IN4 6 SGND 8 10K 25 DO4+ 10K Level Shift OUT4 26 DO4- FIN FIN TSD SVCC VM1 OUT3 20 21 13 DO3+ 10K Level Shift IN3 10K 14 DO3- SVCC VM1 10 IN2 9 12 VM1 10K 16 DO2+ 10K Level Shift OUT2 15 DO2MUTE 23 CH2,3,4,5 SVCC SVCC 22 IN1 11 Level Shift REF 19 SVCC 10K 18 DO1+ 17 DO1- 4 FAN8026G3 Equivalent Circuits BTL CH1 Input BTL CH2,3,4,5 Op-amp Input SVCC SVCC SVCC 11 4 6 9 21 SVCC 1K 100 1K BTL CH2,3,4,5 Op-amp Output 1K BTL CH1 Driver Output SVCC SVCC SVCC SVCC 5 7 20K 10 20 17 18 30K BTL CH2,3 Driver Output BTL CH4,5 Driver Output SVCC VM1 SVCC VM2 20K 30K 20K 13 14 25 26 15 16 27 28 30K 5 FAN8026G3 Equivalent Circuits (Continued) Mute REF SVCC SVCC 50 40K 22 23 Op-amp Input VM2 VM2 VM2 2 1K 6 Op-amp Output VM2 1 1K 40K 40K 40K VM2 1K SVCC 3 FAN8026G3 Absolute Maximum Ratings ( Ta=25°C) Parameter Symbol Value Unit SVCC 15 V VM1 15 V VM2 15 V Maximum supply voltage Power dissipation 2.5 PD note1,2,3 W Operating temperature TOPR −35 ~ +85 °C Storge temperature TSTG −55 ~ +150 °C Notes: 1. When mounted on glass epoxy PCB (76 × 114 × 1.6mm) 2. Power dissipation is reduced at the rate of -20mW/°C for TA≥25°C. 3. Do not exceed Pd and SOA(Safe Operating Area). Pd (mW) 3,000 2,000 SOA 1,000 0 0 25 50 75 100 125 150 175 Ambient temperature, Ta [°C] Recommended Operating Conditions ( Ta=25°C) Parameter Symbol Min. Typ. Max. Unit Supply voltage1 SVCC 4.5 - 13.2 V Supply voltage2 VM1 4.5 - SVCC V Supply voltage3 VM2 4.5 - SVCC V 7 FAN8026G3 Electrical Characteristics (Unless otherwise specified, Ta=25°C, SVCC=8V, VM1=5V, VM2=5V, Vref=1.65V) Parameter Symbol Conditions Min. Typ. Max. Unit - 21 - mA - 12 - mA 2.0 - - V - - 0.5 V Pin22=Variation - - 0.4 V Pin22=Variation 1.0 - - V 1.0 - 3.3 V -50 - +50 mV 6 6.5 - V VIN=100mVpp, f=1kHz 10 12 14 dB VIN=1.65V -50 - +50 mV 3.6 4.0 - V note1 ICC1 MUTE Off note1 MUTE on voltage ICC2 Vmon Pin23=Variation MUTE off voltage Vmoff Pin23=Variation Reference MUTE on voltage Vrmon Reference MUTE off voltage Vrmoff REF Input voltage range Vrefin1 Quiescent current 1* Quiescent current 2* MUTE On - CH1 LOADING DRIVER CIRCUIT (RL=12Ω) Output offset voltage1 VOF1 Maximum output voltage1 Vom1 Close-loop voltage gain1 Gvf1 VIN=1.65V - CH2,3 BTL DRIVER CIRCUIT (RL=8Ω) Output offset voltage2,3,4,5 VOF2,3,4,5 Maximum output voltage2,3,4,5 Vom2,3,4,5 Close-loop voltage gain2,3,5 Close-loop voltage gain4 - Gvf2,3,5 VIN=100mVpp, f=1kHz 10.5 12.5 14.5 dB Gvf4 VIN=100mVpp, f=1kHz 11.5 13.5 15.5 dB INPUT OP-AMP CIRCUIT Input offset voltage1 Input bias current1 - -10 - +10 mV IB1 - - - 300 nA 7 - - V SVCC=8V High level output voltage1 VOH1 Low level output voltage1 VOL1 - - - 0.5 V Output sink current1 ISINK1 - 1 - - mA Output source current1 ISOU1 - 0.5 - - mA Common mode input range1*note1 Vicm1 - -0.3 - 7.0 V f=1kHz, VIN= -75dB - 75 - dB RR1 f=120Hz, VIN= -20dB - 65 - dB SR1 f=120Hz, 2Vp-p - 1 - V/us note1 Open loop voltage gain1* note1 Ripple rejection ratio1* note1 Slew rate1* Note: 1.Guaranteed field. ( No EDS/ Final test . ) 8 VOF1 GVO1 FAN8026G3 Electrical characteristics (Countinued) (Unless otherwise specified, Ta=25°C, SVCC=8V, VM1=5V, VM2=5V, Vref=1.65V) Parameter Symbol Conditions Min. Typ. Max. Unit VOF2 - IB2 - -10 - +10 mV - - 300 nA 4.5 - - V NORMAL OP-AMP CIRCUIT Input offset voltage Input bias current VM2=5V High level output voltage VOH2 Low level output voltage VOL2 - - - 0.5 V Output sink current ISINK2 - 1 - - mA ISOU2 - 0.5 - - mA - Output source current Common mode input range1* note1 Open loop voltage gain*note1 Ripple rejection ratio*note1 *note1 Slew rate Vicm1 -0.3 - 4.0 V f=1kHz, VIN= -75dB - 75 - dB RR2 f=120Hz, VIN= -20dB - 65 - dB SR2 f=120Hz, 2Vp-p - 1 - V/us GVO2 Note: 1.Guaranteed field. ( No EDS/ Final test . ) 9 FAN8026G3 Application information 1. MUTE Function When the mute pin is low(GND), the TR Q1 is turned on and the bias circuit is enabled. On the other hand, when the mute pin is high , the TR Q1 is turned off and the bias circuit is disabled. Bias Current CH2,3,4,5 23 It will make all the circuit blocks except CH1 off, so low power quiescent state can be established. • Truth table is as follows Pin 23 FAN8026 High Mute-On Low Mute-Off Q1 2. TSD Function • When the chip temperature reaches to 175°C by abnormal condition, the TSD circuit is activated • This makes the bias current of the output drivers shut down, and all the output drivers are on cut-off state. Therefore the chip temperature begins to decrease. • When the chip temperature falls to 155°C, the TSD circuit is deactivated and the output drivers start to operate normally. SVCC IREF R1 Q0 R2 Hysteresis Ihys R3 3. Notice • If REF(pin23) is lower than 0.7V, BTL output is off. • Under voltage protecton function. ( If SVcc is lower than 3.8V, Chip is disable. Hysterisis is 0.2V) • Mute on BTL output voltage is as followed: - Mute on BTL output(CH2,3,4,5) = VM / 2 - Mute on BTL output CH1 = ((PVcc2-0.6) / 2 • Each output to output and output to GND short should be kept away. 10 Output driver Bias FAN8026G3 Typical Application Circuit 15 M 16 DO2+ DO3+ 13 17 DO1- VM1 12 18 DO1+ IN1 11 19 SVCC OUT2 10 20 OUT3 IN2 9 21 IN3 GND 8 7 FIN 8V OUT4 7 IN4 6 OUT5 5 DO4+ IN5 4 26 DO4- OPOUT 3 27 DO5+ OPIN- 2 28 DO5- OPIN+ 1 22 REF 23 MUTE 24 VM2 Focus Actuat or 25 Trackin g Actuato r SPINDLE SLED FOCUS TRACKING MUTE 5V VREF S led Motor 5V LOADING Loadin g Motor M FIN M 14 DO3- DO2- FAN8026G3 Spindl e Motor SERVO 11 FAN8026G3 SW2 A A A 21 20 19 18 17 16 DO2+ SW3 V DO4+ VM2 MUTE REF DO3+ DO4- V DO1- DO5+ FIN VM1 22 DO1+ 23 IN1 24 OUT4 25 IN2 26 GND 27 DO5- V 28 8 9 10 11 12 13 15 DO2- A SVCC A OUT3 V A IN3 SW4 SW5 Test Circuits 4 5 6 7 FIN DO3- IN5 3 OUT4 OPOUT 2 IN4 OPIN- 1 OUT5 OPIN+ FAN8026G3 14 V IN- OP-AMP OUT A A A A IN+ SW6 v A A OP-AMP INSW7 OUT SW8 SW9 12 A A SW1 IN+ FAN8026G3 Package Dimension 28-SSOPH-375-SG2 13 FAN8026G3 DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com 3/17/04 0.0m 001 Stock#DSxxxxxxxx 2004 Fairchild Semiconductor Corporation