www.fairchildsemi.com FAN8034 6-CH Motor Driver Features Description • • • • • • • • The FAN8034 is a monolithic integrated circuit suitable for a 6-CH motor driver which drives the tracking actuator, focus actuator, sled motor, spindle motor, and tray motor of the CDP/CAR-CD/DVDP systems. 5-CH Balanced Transformerless (BTL) Driver 1-CH (Forward Reverse) Control DC Motor Driver Operating Supply Voltage (4.5 V ~ 13.2 V) Built in Thermal Shut Down Circuit (TSD) Built in Channel Mute Circuit Built in Power Save Mode Circuit Built in TSD Monitor Circuit Built in 2-OP AMPs Typical Application • • • • Compact Disk Player Video Compact Disk Player Car Compact Disk Player Digital Video Disk Player 48-QFPH-1414 Ordering Information Device FAN8034 FAN8034L Package Operating Temperature 48-QFPH-1414 -35°C ~ +85°C Rev. 1.0.5 ©2002 Fairchild Semiconductor Corporation FAN8034 PVCC1 DO1+ 42 PS 43 OPOUT2 44 FIN (GND) OPIN2− 45 OPIN2+ OPOUT1 OPIN1− 46 VREF 47 SVCC 48 OPIN1+ IN1+ Pin Assignments 41 40 39 38 37 IN1− 1 36 DO1− OUT1 2 35 DO2+ IN2+ 3 34 DO2− IN2− 4 33 PGND1 OUT2 5 32 DO3+ 31 DO3− IN3+ 6 FIN (GND) FIN (GND) FAN8034 IN3− 7 30 DO4+ OUT3 8 29 DO4− IN4+ 9 28 DO5+ 27 DO5− IN4− 10 OUT4 11 26 PGND2 IN5+ 12 2 19 20 21 22 23 24 MUTE5 TSD-M PVCC2 DO6− (GND) FIN MUTE34 18 SGND 17 REV 16 FWD 15 CTL 14 OUT5 IN5− 13 MUTE12 25 DO6+ FAN8034 Pin Definitions Pin Number Pin Name I/O Pin Function Description 1 IN1- I CH1 OP-AMP Input (-) 2 OUT1 O CH1 OP-AMP Output 3 IN2+ I CH2 OP-AMP Input (+) 4 IN2- I CH2 OP-AMP Input (-) 5 OUT2 O CH2 OP-AMP Output 6 IN3+ I CH3 OP-AMP Input (+) 7 IN3- I CH3 OP-AMP Input (-) 8 OUT3 O CH3 OP-AMP Output 9 IN4+ I CH4 OP-AMP Input (+) 10 IN4- I CH4 OP-AMP Input (-) 11 OUT4 O CH4 OP-AMP Output 12 IN5+ I CH5 OP-AMP Input (+) 13 IN5- I CH5 OP-AMP Input (-) 14 OUT5 O CH5 OP-AMP Output 15 CTL I CH6 Motor Speed Control 16 FWD I CH6 Forward Input 17 REV I CH6 Reverse Input 18 SGND - Signal Ground 19 MUTE12 I Mute For CH1,2 20 MUTE34 I Mute For CH3,4 21 MUTE5 I Mute For CH5 22 TSD-M O TSD Monitor 23 PVCC2 - Power Supply Voltage 2 (For CH5, CH6) 24 DO6- O CH6 Drive Ouptut (-) 25 DO6+ O CH6 Drive Output (+) 26 PGND2 - Power Ground 2 (FOR CH5, CH6) 27 DO5- O CH5 Drive Ouptut (-) 28 DO5+ O CH5 Drive Output (+) 29 DO4- O CH4 Drive Ouptut (-) 30 DO4+ O CH4 Drive Output (+) 31 DO3- O CH3 Drive Ouptut (-) 32 DO3+ O CH3 Drive Output (+) 3 FAN8034 Pin Definitions (Continued) 4 Pin Number Pin Name I/O Pin Function Description 33 PGND1 - Power Ground 1 (FOR CH1, CH2, CH3, CH4) 34 DO2- O CH2 Drive Ouptut (-) 35 DO2+ O CH2 Drive Output (+) 36 DO1- O CH1 Drive Ouptut (-) 37 DO1+ O CH1 Drive Output (+) 38 PVCC1 - Power Supply Voltage 1 (FOR CH1, CH2, CH3, CH4) 39 PS I Power Save 40 OPOUT2 O Normal OP-AMP2 output 41 OPIN2- I Normal OP-AMP2 Input (-) 42 OPIN2+ I Normal OP-AMP2 Input (+) 43 VREF I Bias Voltage Input 44 SVCC - Signal & OPAMPs Supply Voltage 45 OPOUT1 O Normal OP-AMP1 Output 46 OPIN1- I Normal OP-AMP1 Input (-) 47 OPIN1+ I Normal OP-AMP1 Input (+) 48 IN1+ I CH1 OP-AMP Intput (+) FAN8034 Internal Block Diagram IN1+ 48 IN1− 1 OUT1 2 OPIN1+ OPIN1− OPOUT1 SVCC 47 46 45 FIN (GND) VREF 44 43 − + OPIN2+ OPIN2− OPOUT2 42 41 40 − + − + PS PVCC1 39 38 DO1+ 37 POWER SAVE 36 DO1− 35 DO2+ − IN2+ + + − + − 3 34 DO2− − IN2− OUT2 + 4 + − 33 PGND1 32 DO3+ 31 DO3− + − 5 − IN3+ + 6 + − + − FIN (GND) FIN (GND) − T.S.D IN3− 7 OUT3 8 IN4+ 9 + + − 30 DO4+ 29 DO4− 28 DO5+ 27 DO5− 26 PGND2 25 DO6+ + − − + + − IN4− 10 OUT4 11 IN5+ 12 M S C S W + D − D MUTE12 13 IN5− Note. + − 14 OUT5 15 CTL 16 FWD 17 18 REV SGND 19 MUTE34 MUTE5 20 21 TSD-M 22 23 24 (GND) MUTE12 MUTE34 MUTE5 TSD-M PVCC2 DO6− FIN Detailed circuit of the output power amp 40K 10K From input opamp Vref 10K Pref 10K − + 40K DO+ 40K + DO- − 10K 40K Pref1 is almost PVCC1 / 2 Pref2 is almost PVCC2 / 2 5 FAN8034 Equivalent Circuits Description Pin No Internal Circuit VCC BTL INPUT 1,4,7,10,13,46 3,6,9,12,47,48 VCC 2K 2K 3 6 1 4 9 12 7 10 47 48 13 46 VCC VCC 5K OP-AMP INPUT 5K 41,42 42 41 VCC VCC 1K VREF 43 43 1K VCC OUTPUT 6 2,5,8,11,14,45 5K 2 5 8 11 14 45 VCC FAN8034 Equivalent Circuits (Continued) Description Pin No Internal Circuit VCC VCC OPOUT 40 0.05k 40 0.05k VCC 20K MUTE1234 19,20,21 19 50K 20 21 50K VCC MUTE5 21 1K 21 39K TSD-M 22 22 20k 7 FAN8034 Equivalent Circuits (Continued) Description Pin No Internal Circuit VCC 100k PS 39 50K 39 50K VCC 30K FWD,REV 16,17 30K 17 30K 16 30K freewheeling diode OUTPUT 27,28,29,30,31,32, 34,35,36,37 27 28 29 30 40 31 32 34 35 36 37 vcc VCC VCC 40K 7K parastic diode freewheeling diode VCC vcc OUTPUT 24,25 24 VCC 25 60K 7K parastic diode 8 FAN8034 Absolute Maximum Ratings ( Ta=25°°C) Parameter Symbol Value Unit SVCCMAX 18 V PVCC1 18 V PVCC2 18 V PD 3note W Operating Temperature TOPR -35 ~ +85 °C Storge Temperature TSTG -55 ~ +150 °C Maximum Output Current IOMAX 1 A Maximum Supply Voltage Power Dissipation Notes: 1. When mounted on 70mm × 70mm × 1.6mm PCB 2. Power dissipation reduces 24mW/°C for using above TA = 25°C 3. Do not exceed PD and SOA Pd (mW) 3,000 2,000 1,000 0 0 25 50 75 100 125 150 175 Ambient temperature, Ta [°C] Recommended Operating Conditions ( Ta=25°°C) Parameter Operating Supply Voltage Symbol Min. Typ. Max. Unit SVCC 4.5 - 13.2 V PVCC1 4.5 - 13.2 V PVCC2 4.5 - 13.2 V 9 FAN8034 Electrical Characteristics (SVCC =5V, PVCC1 = PVCC2 = 11V, TA = 25°C, unless otherwise specified) Parameter Symbol Min. Typ. Max. Unit Under no-load - 30 - mA IPS Under no-load - - 1 mA Power Save On Voltage VPSON Pin39 = Variation - - 0.5 V Power Save Off Voltage VPSOFF Pin39 = Variation 2 - - V Mute12 On Voltage VMON12 Pin19 = Variation - - 0.5 V Mute12 Off Voltage VMOFF12 Pin19 = Variation 2 - - V Mute34 On Voltage VMON34 Pin20 = Variation - - 0.5 V Mute34 Off Voltage VMOFF34 Pin20 = Variation 2 - - V Mute5 On Voltage VMON5 Pin21 = Variation - - 0.5 V Mute5 Off Voltage VMOFF5 Pin21 = Variation 2 - - V Quiescent Circuit Current Power Save On Current ICC note1 Conditions BTL DRIVER CIRCUIT Output Offset Voltage VOO VIN = 2.5V -100 - +100 mV Maximum Output Voltage1 VOM1 RL = 10Ω 7.5 9.0 - V Maximum Output Voltage2 VOM2 RL = 18Ω 8.5 9.5 - V Closed-loop Voltage Gain AVF VIN = 0.1Vrms 16.8 18 19.2 dB RR VIN = 0.1Vrms, f = 120Hz - 60 - dB SR Square, Vout = 4Vp-p 1 2 - V/µs Ripple Rejection Slew Rate Rationote2 note2 INPUT OPAMP CIRCUIT Input Offset Voltage1 Input Bias Current1 High Level Output Voltage1 VOF1 - -10 - +10 mV IB1 - - - 400 nA VOH1 - 4.4 4.7 - V Low Level Output Voltage1 VOL1 - 0.2 0.5 V Output Sink Current1 ISINK1 RL = 50Ω 1 2 - mA Output Source Current1 ISOU1 RL = 50Ω 1 2 - mA Common Mode Input Range1note2 Vicm1 -0.3 - 4.0 V Open Loop Voltage Gain1note2 Ripple Rejection Ratio1 note2 Common Mode Rejection Ratio1note2 Slew Rate1note2 - - GVO1 VIN = -75dB - 80 - dB RR1 VIN = -20dB, f = 120Hz - 65 - dB VIN = -20dB - 80 - dB Square, Vout = 3Vp-p - 1.5 - V/µs CMRR1 SR1 Note1: When the voltage of the pin 39 is below 0.5V then the power save circuit cuts off the main bias current, so that the whole circuits are disabled (Whole circuits are " drive circuit ", " input op amp circuit " and " normal op amp circuit ") Note2: Guaranteed field(No EDS/Final test) 10 FAN8034 Electrical Characteristics (Continued) (SVCC = 5V, PVCC1 = PVCC2 = 11V, TA = 25°°C, unless otherwise specified) Parameter Symbol Conditions Min. Typ. Max. Unit VOF2 - -10 - +10 mV NORMAL OP AMP CIRCUIT 1 Input Offset Voltage2 IB2 - - - 400 nA High Level Output Voltage2 VOH2 - 4.4 4.7 - V Low Level Output Voltage2 VOL2 - - 0.2 0.5 V Output Sink Current2 ISINK2 RL= 50Ω 2 4 - mA Output Source Current2 ISOU2 RL= 50Ω Common Mode Input Range2note Vicm2 Input Bias Current2 Open Loop Voltage Gain2 Ripple Rejection note Ratio2note Common Mode Rejection Ratio2note 2 4 - mA -0.3 - 4.0 V GVO2 VIN = -75dB - 80 - dB RR2 VIN = -20dB, f = 120Hz - 65 - dB VIN = -20dB - 80 - dB Square, Vout = 3Vp-p - 1.5 - V/µs CMRR2 Slew Rate2note - SR2 NORMAL OP AMP CIRCUIT 2 Input Offset Voltage3 Input Bias Current3 High Level Output Voltage3 VOF3 - -15 - +15 mV IB3 - - - 400 nA VOH3 - 3 3.8 - V Low Level Output Voltage3 VOL3 - 1.0 1.5 V Output Sink Current3 ISINK3 RL = 50Ω 10 - - mA ISOU3 RL = 50Ω 10 - - mA GVO3 VIN = -75dB - 80 - dB RR3 VIN = -20dB, f = 120Hz - 65 - dB VIN = -20dB - 80 - dB Square, Vout = 3Vp-p - 1.5 - V/µs - 2 - - V - Output Source Current3 Open Loop Voltage Gain3 Ripple Rejection Ratio3 note note Common Mode Rejection Ratio3note CMRR3 Slew Rate3note SR3 - TRAY DRIVE CIRTUIT Input High Level Voltage VIH Input Low Level Voltage VIL - - 0.5 V - 6 - V Output Voltage1 VO1 PVCC2 = 11V, VCTL = 3V, RL= 45Ω Output Voltage2 VO2 PVCC2 = 13V, VCTL = 4.5V, RL= 45Ω - 9 - V Output Voltage3 VO3 PVCC2 = 11V, VCTL = 1.5V, RL = 10Ω 2.5 3 3.5 V Output Load Regulation ∆VRL VCTL=3V, IL=100mA → 400mA - 300 700 mV Output Offset Voltage1 VOO1 VIN = 5V, 5V -40 - +40 mV Output Offset Voltage2 VOO2 VIN = 0V, 0V -40 - +40 mV Note: Guaranteed field(No EDS/Final test) 11 FAN8034 Application Information 1. Thermal Shutdown • When the chip temperature reaches to 160°C by abnormal condition, then the TSD circuit is activated. • This shut down the bias current of the output drivers, and all the output drivers are in cut-off state. Thus the chip temperature begin to decrease. • when the chip temperature falls to 135°C, the TSD circuit is deactivated and the output drivers are normally operated. • The TSD circuit has the hysteresis temperature of 25°C. SVCC IREF Output driver bias R1 Q0 R2 Hysteresis Ihys R3 2. CH Mute Function • When the pin19,20,21 is high, the TR Q1 is turned on and Q2 is off, so the bias circuit is enabled. On the other hand, when the pin19,20,21 is Low (GND) , the TR Q1 is turned off and Q2 is on, so the bias circuit is disabled. • That is, this function will cause all the output drivers to be in mute state. • Truth table is as follows; Pin 19, 20, 21 FAN8034 High Mute-Off Low Mute-On SVCC Bias blocks (5-Ch BTL) Q2 19 20 Q1 21 3. Power Save Function • When the pin39 is high, the TR Q3 is turned on and Q4 is off, so the bias circuit is enabled. On the other hand, when the pin39 is Low (GND) , the TR Q3 is turned off and Q4 is on, so the bias circuit is disabled. • That is, this function keeps all the circuit blocks of the chip off, thus the low power quiscent state is established. • Truth table is as follows; 12 Pin39 FAN8034 High Power Save Off Low Power Save On SVCC Main Bias Q4 39 Q3 FAN8034 4. Tsd Monitor Function • PIN22 is TSD monitor pin which detects the state of the TSD block and generates the TSD-monitor signal. • In normal state Q5 is turned on, so Q6 is turned off. on the otherhand, When the TSD block is is activated then Q5 is turned off, so the voltage of pin22 is low. • Truth table is as follows TSD Circuit Pin22 FAN8034 - High Tsd Off - Low Tsd On SVCC 22 Q6 Q5 5. Focus, Tracking Actuator, Spindle, Sled Motor Drive Part R2 R1 IN+ IN- OUT 48 3 6 1 4 7 2 5 8 Vref 9 12 + 10 13 − Vin R1 Vp R2 10 14 43 R1 − + R2 DO+ 28 30 32 35 37 DO- 27 29 31 34 36 M R2 + − R2 PVCC1(PVCC2) Dp 60k + − 62k Vp Qp • The voltage, Vref is the reference voltage given by the external bias voltage of the pin 43. • The input signal (Vin) through pins 1,4,7, 10 and 13 is amplified one time and then fed to the output stage. (assume that input opamp was used as a buffer) • The total closed loop voltage gain is as follows Vin = Vref + ∆V DOP = Vp + 4 ∆V DON = Vp – 4 ∆V Vout = DOP – DON = 8 ∆V Vout Gain = 20 log ------------- = 20 log 8 = 18dB ∆V • If you want to change the total closed loop voltage gain, you must use the input opamp as an amplifier • The output stage is the balanced transformerless (BTL) driver. • The bias voltage Vp is expressed as ; 62k Vp = ( PVCC1 – VDp – VcesatQp ) × -------------------------- + VcesatQp 60k + 62k PVCC1 – VDp + VcesatQp = --------------------------------------------------------------------------- + VcesatQp 1.97 ---------- (1) 13 FAN8034 6. Tray, Changer,panel Motor Drive Part out 1 out 2 M 25 24 D D LEVEL SHIFT 6.5V M.S.C CTL V(out1,out2) 15 S.W 0 IN IN FWD REV 16 17 3.25V VCTL • Rotational direction control The forward and reverse rotational direction is controlled by FWD (pin16) and REV (pin17) and the input conditions are as follows. INPUT OUTPUT FWD REV OUT 1 OUT 2 State H H Vp Vp Brake H L H L Forward L H L H Reverse L L - - Hign impedance • Where Vp(Power reference voltage) is approximately about 3.75V at PVCC2=8V ) according to equation (1). • Where out1 pins are pins24 and out2 pins are pins25 • Motor speed control (When SVCC=PVCC2=8V) - The almost maximum torque is obtained when the pin (15(CTL)) is open. - If the voltage of the pins (15 (CTL)) is 0V, the motor will not operate. - When the control voltage of the pin15 is between 0 and 3.25V, the differential output voltage(V(out1,out2)) is about two times of control voltage. Hence, the control to the differential output gain is two. - When the control voltage is greater than 3.25V, the output voltage is saturated at the 6.5V because of the output swing limitation. 14 FAN8034 Test Circuits VCC 50Ω 1 47 46 45 44 43 42 41 40 39 38 37 IN1+ OPIN1+ OPIN1− OPOUT1 SVCC VREF OPIN2+ OPIN2− OPOUT2 PS PVCC1 DO1+ OP IN (-) 48 2 OUT1 3 OP IN (-) 4 IN2- RL1 36 DO1− DO2+ 35 RL2 DO2- 34 IN2+ OP IN (+) OP OUT OP OUT IN1− 1 OP OUT RIPPLE OP IN (+) OP IN (-) OP OUT OP IN (+) OP IN (-) OP IN (+) VREF 2.5V 2 100µF + + 1000µF PGND1 33 5 OUT2 DO3+ 32 6 IN3+ DO3− 31 RL3 OP IN (+) FAN8034 OP IN (-) OP OUT 7 IN3− DO4+ 30 8 OUT3 DO4− 29 RL4 OP IN (+) OP IN (-) 9 IN4+ DO5+ 28 10 IN4− DO5− 27 OP OUT OUT5 CTL FWD REV SGND MUTE12 MUTE34 MUTE5 TSD_M PVCC2 13 14 15 16 17 18 19 20 21 22 23 IN5+ 12 OP OUT PGND2 26 DO6− 11 OUT4 OP IN (+) OP IN (-) IN5− RL5 25 DO6+ 24 RL7 IL CTL INA IL INB OP-AMP PART OPIN(+) OPIN(−) A B OPOUT D 1 VPULSE 2 3 VA 1 2 3 VOUT 50Ω VB C 1 2 VCC 15 FAN8034 Typical Application Circuits 1 [Voltage control mode] SVCC PVCC1 POWER SAVE 47 46 45 44 43 42 41 40 39 38 37 OPOUT1 SVCC VREF OPIN2+ OPIN2− OPOUT2 PS PVCC1 DO1+ 2 OUT1 36 DO2+35 DO2- 34 3 IN2+ DO1− TRACKING 48 OPIN1− 1 OPIN1+ IN1− IN1+ FOCUS PGND1 33 4 IN25 OUT2 DO3+ 32 6 IN3+ DO3− 31 M SLED FAN8034 7 IN3− DO4+ 30 8 OUT3 DO4− 29 9 IN4+ DO5+ 28 10 IN4− DO5−27 REV SGND MUTE12 MUTE34 15 16 17 18 19 20 21 DO6− FWD 14 TSD_M CTL IN5+ 12 PGND2 PVCC2 OUT5 13 11 OUT4 MUTE5 IN5− M SPINDLE 22 23 24 26 25 DO6+ M TRAY pvcc2 PVCC2 SPINDLE MUTE SLED MUTE FOCUS, TRACKING, MUTE TSD MONITOR VREF FOCUS TRACKING INPUT INPUT [SERVO PRE AMP] 16 SLED INPUT SPINDLE INPUT TRAY TRAY CONTROL INPUT [CONTROLLER] FAN8034 Typical Application Circuits 2 [Differential PWM control mode ] SVCC PVCC1 POWER SAVE 4 5 41 40 39 38 37 PS PVCC1 DO1+ OPOUT1 42 36 DO1− TRACKING 3 43 OPOUT2 OPIN1− 2 OUT1 44 OPIN2− 45 OPIN2+ 46 VREF 47 SVCC 48 OPIN1+ IN1− 1 IN1+ FOCUS 35 DO2+ DO2- 34 IN2+ PGND1 33 IN2- DO3+ 32 OUT2 DO3− 31 6 IN3+ M SLED FAN8034 MUTE34 MUTE5 TSD_M 14 15 16 17 18 19 20 21 22 M SPINDLE PGND2 26 DO6− MUTE12 13 OUT4 PVCC2 SGND IN5+ 12 IN4− DO5−27 REV 11 DO5+ 28 FWD 10 IN4+ CTL 9 DO4− 29 OUT3 OUT5 8 DO4+ 30 IN3− IN5− 7 23 24 25 DO6+ M TRAY PVCC2 pvcc2 SPINDLE MUTE SLED MUTE FOCUS, TRACKING MUTE TSD MONITOR VREF FOCUS TRACKING INPUT INPUT SLED INPUT SPINDLE INPUT TRAY TRAY CONTROL INPUT [SERVO PRE AMP] [CONTROLLER] Note: Radiation pin is connected to the internal GND of the package. 17 FAN8034 DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com 9/6/02 0.0m 001 Stock#DSxxxxxxxx 2002 Fairchild Semiconductor Corporation