The following document contains information on Cypress products. FUJITSU SEMICONDUCTOR DATA SHEET DS04–21359–6E ASSP Single Serial Input PLL Frequency Synthesizer On-chip 1.2 GHz Prescaler MB15E03SL ■ DESCRIPTION The Fujitsu Semiconductor MB15E03SL is a serial input Phase Locked Loop (PLL) frequency synthesizer with a 1.2 GHz prescaler. The 1.2 GHz prescaler has a dual modulus division ratio of 64/65 or 128/129 enabling pulse swallowing operation. The supply voltage range is between 2.4 V and 3.6 V. The MB15E03SL uses the latest BiCMOS process, as a result, the supply current is typically 2.0 mA at 2.7 V. A refined charge pump supplies a well balanced output currents of 1.5 mA or 6 mA. The charge pump current is selectable by serial data. ■ FEATURES • High frequency operation: 1.2 GHz max • Low power supply voltage: VCC = 2.4 V to 3.6 V • Ultra Low power supply current: ICC = 2.0 mA typ. (VCC = Vp = 2.7 V, Ta = +25°C, in locking state) ICC = 2.5 mA typ. (VCC = Vp = 3 V, Ta = +25°C, in locking state) • Direct power saving function: Power supply current in power saving mode Typ. 0.1 μA (VCC = Vp = 3 V, Ta = +25°C), Max. 10 μA (VCC = Vp = 3 V) • Dual modulus prescaler: 64/65 or 128/129 • Serial input 14-bit programmable reference divider: R = 3 to 16,383 • Serial input programmable divider consisting of: - Binary 7-bit swallow counter: 0 to 127 - Binary 11-bit programmable counter: 3 to 2,047 • Selectable charge pump current • On-chip phase control for phase comparator • Operating temperature: Ta = –40 to +85°C Copyright©2000-2012 FUJITSU SEMICONDUCTOR LIMITED All rights reserved 2012.5 MB15E03SL ■ PIN ASSIGNMENTS 16-pin SSOP 16-pin QFN OSCOUT OSCIN R OSCIN 1 16 φR OSCOUT 2 15 φP VP 3 14 LD/fout VCC 4 ZC DO 5 TOP 13 VIEW 12 GND 6 11 LE Xfin 7 10 Data fin 8 9 Clock (FPT-16P-M05) 2 PS 16 15 14 P 13 VP 1 12 LD/fout VCC 2 11 ZC DO 3 10 PS 9 GND 4 5 Xfin LE 6 7 8 fin Clock Data (LCC-16P-M69) DS04–21359–6E MB15E03SL ■ PIN DESCRIPTION Pin No. SSOP QFN Pin Name I/O 1 15 OSCIN I Programmable reference divider input. Oscillator input connection to a TCXO. 2 16 OSCOUT O Oscillator output. 3 1 VP — Power supply voltage input for the charge pump. 4 2 VCC — Power supply voltage input. 5 3 DO O Charge pump output. Phase of the charge pump can be selected via programming of the FC bit. 6 4 GND — Ground. 7 5 Xfin I Prescaler complementary input which should be grounded via a capacitor. 8 6 fin I Prescaler input. Connection to an external VCO should be done via AC coupling. 9 7 Clock I Clock input for the 19-bit shift register. Data is shifted into the shift register on the rising edge of the clock. (Open is prohibited.) 10 8 Data I Serial data input using binary code. The last bit of the data is a control bit. (Open is prohibited.) 11 9 LE I Load enable signal input. (Open is prohibited.) When LE is set high, the data in the shift register is transferred to a latch according to the control bit in the serial data. I Power saving mode control. This pin must be set at “L” at Power-ON. (Open is prohibited.) PS = “H”; Normal mode PS = “L”; Power saving mode I Forced high-impedance control for the charge pump (with internal pull up resistor.) ZC = “H”; Normal Do output. ZC = “L”; Do becomes high impedance. 12 13 10 11 PS ZC Descriptions 14 12 LD/fout O Lock detect signal output (LD)/phase comparator monitoring output (fout). The output signal is selected via programming of the LDS bit. LDS = “H”; outputs fout (fr/fp monitoring output) LDS = “L”; outputs LD (“H” at locking, “L” at unlocking.) 15 13 φP O Phase comparator N-channel open drain output for an external charge pump. Phase can be selected via programming of the FC bit. 16 14 φR O Phase comparator CMOS output for an external charge pump. Phase can be selected via programming of the FC bit. DS04–21359–6E 3 MB15E03SL ■ BLOCK DIAGRAM fr (15) OSCIN 1 Reference oscillator circuit Phase comparator (13) 15 P (16) OSCOUT 2 Binary 14-bit reference counter (1) VP 3 14-bit latch Lock detector SW FC LDS CS 4-bit latch fp DO (3) 5 C N T Current switch Charge pump VCC (2) 4 (14) 16 R LD/fr/fp selector (11) 13 ZC 19-bit shift register 7-bit latch Binary 7-bit swallow counter 11-bit latch Binary 11-bit programmable counter (12) 14 LD/fout Intermittent mode control (power save) (10) 12 PS (9) 11 LE (4) GND 6 1-bit cotrol latch (5) Xfin 7 MD (8) 10 Data Prescaler 64 / 65, 128 / 129 (6) fin 8 (7) 9 Clock : SSOP ( ) : QFN 4 DS04–21359–6E MB15E03SL ■ ABSOLUTE MAXIMUM RATINGS Parameter Power supply voltage Input voltage Output voltage Storage temperature Symbol Condition VCC Rating Unit Min. Max. — –0.5 4.0 V VP — VCC 6.0 V VI — –0.5 VCC +0.5 V VO Except Do GND VCC V VO Do GND VP V Tstg — –55 +125 °C Remark WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. ■ RECOMMENDED OPERATING CONDITIONS Parameter Symbol Value Unit Min. Typ. Max. VCC 2.4 3.0 3.6 V VP VCC — 5.5 V Input voltage VI GND — VCC V Operating temperature Ta –40 — +85 °C Power supply voltage Remark WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their representatives beforehand. DS04–21359–6E 5 MB15E03SL ■ ELECTRICAL CHARACTERISTICS (VCC = 2.4 to 3.6 V, Ta = –40 to +85°C) Parameter Symbol Condition Value Min. Typ. Max. Unit Power supply current*1 ICC VCC = VP = 2.7 V (VCC = VP = 3.0 V) — 2.0 (2.5) — mA Power saving current IPS ZC = “H” or open — 0.1*2 10 μA Operating frequency Input sensitivity “H” level input voltage “L” level input voltage “H” level input current “L” level input current “H” level input current “L” level input current “H” level input current fin fin — 100 — 1200 MHz OSCIN fOSC — 3 — 40 MHz fin*3 Pfin –15 — +2 dBm OSCIN*3 VOSC — 0.5 — VCC Vp-p Data, Clock, LE, PS, ZC VIH — VCC × 0.7 — — VIL — — — VCC × 0.3 Data, Clock, LE, PS IIH*4 — –1.0 — +1.0 IL*4 I — –1.0 — +1.0 IIH — 0 — +100 IL*4 I — –100 — 0 IIH*4 — –1.0 — +1.0 –100 — 0 — — 0.4 VCC – 0.4 — — — — 0.4 OSCIN ZC 50 Ω system (Refer to the Measurment circuit.) V μA μA μA I Pull up input “L” level output voltage φP VOL Open drain output “H” level output voltage φR, “L” level output voltage LD/fout VOH VCC = VP = 3 V, IOH = –1 mA VOL VCC = VP = 3 V, IOL = 1 mA “H” level output voltage VDOH VCC = VP = 3 V, IDOH = –0.5 mA VP – 0.4 — — VDOL VCC = VP = 3 V, IDOL = 0.5 mA — — 0.4 High impedance cutoff Do current IOFF VCC = VP = 3 V, VOFF = 0.5 V to VP – 0.5 V — — 2.5 nA “L” level output current φP IOL Open drain output 1.0 — — mA “H” level output current φR, “L” level output current LD/fout IOH — — — –1.0 IOL — 1.0 — — CS bit = “H” — –6.0 — CS bit = “L” — –1.5 — CS bit = “H” — 6.0 — CS bit = “L” — 1.5 — — 3 — % — 10 — % — 10 — % “L” level input current “L” level output voltage IL*4 Do “H” level output current IDOH*4 Do “L” level output current IDOL IDOL/IDOH I Charge pump current rate DOMT*5 VCC = 3 V, VP = 3 V, VDO = VP/2 Ta = +25°C VDD = VP/2 vs VDO IDOVD*6 0.5 V ≤ VDO ≤ VP – 0.5 V vs Ta IDOTA*7 – 40°C ≤ Ta ≤ +85°C V V V mA mA (Continued) 6 DS04–21359–6E MB15E03SL (Continued) *1: Conditions; fin = 1200 MHz, fosc = 12 MHz, Ta = +25°C, in locking state. *2: VCC = VP = 3.0 V, fosc = 12.8 MHz, Ta = +25°C, in power saving mode *3: AC coupling. 1000 pF capacitor is connected under the condition of min. operating frequency. *4: The symbol “–” (minus) means direction of current flow. *5: VCC = VP = 3.0 V, Ta = +25°C (|I3| – |I4|) / [(|I3| + |I4|) /2] × 100(%) *6: VCC = VP = 3.0 V, Ta = +25°C [(|I2| – |I1|) /2] / [(|I1| + |I2|) /2] × 100(%) (Applied to each IDOL, IDOH) *7: VCC = VP = 3.0 V, VDO = VP/2 (|IDO(+85°C) – IDO(–40°C)| /2) / (|IDO(+85°C) + IDO(–40°C)| /2) × 100(%) (Applied to each IDOL, IDOH) I1 I3 I2 IDOL IDOH I4 I2 I1 0.5 VP/2 VP − 0.5 VP Charge Pump Output Voltage (V) DS04–21359–6E 7 MB15E03SL ■ FUNCTIONAL DESCRIPTION 1. Pulse Swallow Function The divide ratio can be calculated using the following equation: fVCO = [(M × N) + A] × fOSC ÷ R (A < N) fVCO : Output frequency of external voltage controlled oscillator (VCO) N : Preset divide ratio of binary 11-bit programmable counter (3 to 2,047) A : Preset divide ratio of binary 7-bit swallow counter (0 ≤ A ≤ 127) fOSC : Output frequency of the reference frequency oscillator R : Preset divide ratio of binary 14-bit programmable reference counter (3 to 16,383) M : Preset divide ratio of the dual modulus prescaler (64 or 128) 2. Serial Data Input Serial data is processed using the Data, Clock, and LE pins. Serial data controls the programmable reference divider and the programmable divider separately. Binary serial data is entered through the Data pin. One bit of data is shifted into the shift register on the rising edge of the Clock. When the LE pin is taken high, stored data is latched according to the control bit data as follows: Table 1. Control Bit Control Bit (CNT) Destination of Serial Data H For the programmable reference divider L For the programmable divider (1) Shift Register Configuration Programmable Reference Counter MSB LSB Data Flow 1 2 CNT R1 CNT R1 to R14 SW FC LDS CS 3 4 5 6 7 8 9 R2 R3 R4 R5 R6 R7 R8 10 11 12 13 14 15 16 17 18 19 FC LDS CS R9 R10 R11 R12 R13 R14 SW : Control bit : Divide ratio setting bit for the programmable reference counter (3 to 16,383) : Divide ratio setting bit for the prescaler (64/65 or 128/129) : Phase control bit for the phase comparator : LD/fout signal select bit : Charge pump current select bit [Table 1] [Table 2] [Table 5] [Table 8] [Table 7] [Table 6] Note: Start data input with MSB first. 8 DS04–21359–6E MB15E03SL Programmable Counter MSB LSB Data Flow 1 2 CNT A1 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 A2 A3 A4 A5 A6 A7 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 CNT : Control bit N1 to N11: Divide ratio setting bits for the programmable counter (3 to 2,047) A1 to A7 : Divide ratio setting bits for the swallow counter (0 to 127) 18 19 [Table 1] [Table 3] [Table 4] Note: Start data input with MSB first. Table 2. Binary 14-bit Programmable Reference Counter Data Setting Divide ratio (R) R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 3 0 0 0 0 0 0 0 0 0 0 0 0 1 1 4 0 0 0 0 0 0 0 0 0 0 0 1 0 0 ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ 16383 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Note: Divide ratio less than 3 is prohibited. Table 3. Binary 11-bit Programmable Counter Data Setting Divide ratio (N) N11 N10 N9 N8 N7 N6 N5 N4 N3 N2 N1 3 0 0 0 0 0 0 0 0 0 1 1 4 0 0 0 0 0 0 0 0 1 0 0 ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ 2047 1 1 1 1 1 1 1 1 1 1 1 Note: Divide ratio less than 3 is prohibited. Table 4. Binary 7-bit Swallow Counter Data Setting Divide ratio (A) A7 A6 A5 A4 A3 A2 A1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ 127 1 1 1 1 1 1 1 DS04–21359–6E 9 MB15E03SL Table 5. Prescaler Data Setting SW Prescaler Divide Ratio H 64/65 L 128/129 Table 6. Charge Pump Current Setting CS Current Value H ±6.0 mA L ±1.5 mA Table 7. LD/fout Output Select Data Setting LD/fOUT Output Signal LDS H fout signal L LD signal (2) Relation between the FC Input and Phase Characteristics The FC bit changes the phase characteristics of the phase comparator. Both the internal charge pump output level (DO) and the phase comparator output (φR, φP) are reversed according to the FC bit. Also, the monitor pin (fout) output is controlled by the FC bit. The relationship between the FC bit and each of DO, φR, and φP is shown below. Table 8. FC Bit Data Setting (LDS = “H”) FC = High FC = Low DO φR φP fr > fp H L L fr < fp L H Z* fr = fp Z* L Z* LD/fout fout = fr DO φR φP L H Z* H L L Z* L Z* LD/fout fout = fp * : High impedance When designing a synthesizer, the FC pin setting depends on the VCO and LPF characteristics. • When the LPF and VCO characteristics are similar to (1), set FC bit high. • When the VCO characteristics are similar to (2), set FC bit low. PLL LPF VCO (1) VCO Output Frequency (2) LPF Output Voltage 10 DS04–21359–6E MB15E03SL 3. Do Output Control Table 9. ZC Pin Setting ZC pin Do output H Normal output L High impedance DS04–21359–6E 11 MB15E03SL 4. Power Saving Mode (Intermittent Mode Control Circuit) Table 10. PS Pin Setting PS pin Status H Normal mode L Power saving mode The intermittent mode control circuit reduces the PLL power consumption. By setting the PS pin low, the device enters into the power saving mode, reducing the current consumption. See the Electrical Characteristics chart for the specific value. The phase detector output, Do, becomes high impedance. For the signal PLL, the lock detector, LD, remains high, indicating a locked condition. Setting the PS pin high, releases the power saving mode, and the device works normally. The intermittent mode control circuit also ensures a smooth startup when the device returns to normal operation. When the PLL is returned to normal operation, the phase comparator output signal is unpredictable. This is because of the unknown relationship between the comparison frequency (fp) and the reference frequency (fr) which can cause a major change in the comparator output, resulting in a VCO frequency jump and an increase in lockup time. To prevent a major VCO frequency jump, the intermittent mode control circuit limits the magnitude of the error signal from the phase detector when it returns to normal operation. Notes: •When power (VCC) is first applied, the device must be in standby mode, PS = Low, for at least 1 μs. •PS pin must be set “L” for Power-ON. OFF VCC ON tV ≥ 1 μs Clock Data LE tPS ≥ 100 ns PS (1) (2) (3) (1) PS = L (power saving mode) at Power ON (2) Set serial data 1 μs later after power supply remains stable (VCC > 2.2 V). (3) Release power saving mode (PS: “L” → “H”) 100 ns later after setting serial data. 12 DS04–21359–6E MB15E03SL ■ SERIAL DATA INPUT TIMING 1st data 2nd data Control bit Invalid data ∼ Data MSB LSB ∼ ∼ Clock t1 t2 t3 t6 t7 LE ∼ t4 t5 On the rising edge of the clock, one bit of data is transferred into the shift register. Parameter Min. Typ. Max. Unit Parameter Min. Typ. Max. Unit t1 20 — — ns t5 100 — — ns t2 20 — — ns t6 20 — — ns t3 30 — — ns t7 100 — — ns t4 30 — — ns Note: LE should be “L” when the data is transferred into the shift register. DS04–21359–6E 13 MB15E03SL ■ PHASE COMPARATOR OUTPUT WAVEFORM fr fp t WU t WL LD [FC = “H”] H DO Z L [FC = “L”] H DO Z L Notes:• Phase error detection range: –2π to +2π • Pulses on Do output signal during locked state are output to prevent dead zone. • LD output becomes low when phase is tWU or more. LD output becomes high when phase error is tWL or less and continues to be so for three cycles or more. • tWU and tWL depend on OSCIN input frequency. tWU > 2/fosc (s) (e. g. tWU > 156.3 ns, fosc = 12.8 MHz) tWU < 4/fosc (s) (e. g. tWL < 312.5 ns, fosc = 12.8 MHz) • LD becomes high during the power saving mode (PS = “L”). 14 DS04–21359–6E MB15E03SL ■ MEASURMENT CIRCUIT (for Measuring Input Sensitivity fin/OSCIN) 1000 pF 0.1 1000 pF F 0.1 1000 pF F S.G. S.G. fin Xfin GND DO VCC VP OSCOUT OSCIN 50 50 8 7 6 5 4 3 2 1 9 10 11 12 13 14 15 16 Clock Data LE PS ZC LD/fout P R VCC Controller (setting divide ratio) Oscilloscope Note : SSOP-16 DS04–21359–6E 15 MB15E03SL ■ TYPICAL CHARACTERISTICS 1. fin input sensitivity Input sensitivity - Input frequency (Prescaler 64/65) Ta = +25 °C Input sensitivity Pfin (dBm) 10 0 SPEC -10 -20 VCC = 2.4 V -30 VCC = 2.7 V VCC = 3.0 V -40 VCC = 3.6 V -50 0 500 1000 1500 2000 Input frequency fin (MHz) 2. OSCIN input sensitivity Input sensitivity - Input frequency Ta = +25 °C Input sensitivity VOSC (dBm) 10 SPEC 0 -10 -20 -30 VCC = 2.4 V -40 VCC = 3.0 V -50 VCC = 3.6 V -60 0 50 100 Input frequency fOSC (MHz) 16 DS04–21359–6E MB15E03SL 3. Do output current 1.5 mA mode VDO − IDO Ta = +25 °C Charge pump output current IDO (mA) 10.00 VCC = 3.0 V VP = 3.0 V 2.000 /div IOL 0 IOH − 10.00 0 4.800 .6000/div Charge pump output voltage VDO (V) 6.0 mA mode VDO − IDO Ta = +25 °C Charge pump output current IDO (mA) 10.00 VCC = 3.0 V VP = 3.0 V IOL 2.000 /div 0 IOH − 10.00 0 .6000/div 4.800 Charge pump output voltage VDO (V) DS04–21359–6E 17 MB15E03SL 4. fin input impedance 1 : 297.63 Ω −656.53 Ω 100 MHz 2 : 24.523 Ω −185.55 Ω 400 MHz 3 : 9.3789 Ω −77.168 Ω 800 MHz 4 : 10.188 Ω −33.143 Ω 1.2 GHz 1 2 4 3 START 100.000 000 MHz STOP 1 200.000 000 MHz 5. OSCIN input impedance 1: 9.063 kΩ −3.113 kΩ 3 MHz 2: 3.8225 Ω −4.6557 kΩ 10 MHz 3: 1.5735 Ω −3.2154 kΩ 20 MHz 1 3 3 4: 405.69 Ω −1.8251 kΩ 40 MHz 4 START 3.000 000 MHz 18 STOP 40.000 000 MHz DS04–21359–6E MB15E03SL ■ REFERENCE INFORMATION S.G. OSCIN LPF DO fin Spectrum Analyzer VCO fVCO = 810.425 MHz KV = 17 MHz/V fr = 25 kHz fOSC = 14.4 MHz exp current: 6.0 mA • LPF 9.1 kΩ Do VCO 4.2 kΩ 4700 pF 1500 pF 47000 pF (Continued) DS04–21359–6E 19 MB15E03SL • PLL Reference Leakage ATTEN 10 dB RL − 5.0 dBm ΔMKR − 79.83 dB 25.0 kHz 79.8 dBc Ta = +25°C CENTER 810.42500 MHz 1.0 kHz VBW 1.0 kHz * RBW SPAN 200.0 kHz 1.00 s * SWP • PLL Phase Noise ATTEN 10 dB RL − 5.0 dBm ΔMKR − 53.00 dB 2.23 kHz 73.0 dBc/Hz Ta = +25°C CENTER 810.42500 MHz 100 Hz VBW 100 Hz * RBW SPAN 20.00 kHz 3.00 s * SWP (Continued) 20 DS04–21359–6E MB15E03SL (Continued) PLL Lock Up Time PLL Lock Up Time 810.425 MHz → 826.425±1 kHz Lch → Hch 1.40 ms 826.425 MHz → 810.425±1 kHz Hch → Lch 1.52 ms 850.00500 MHz 860.00000 MHz 10.00000 Hz/div 10.00000 Hz/div 810.00000 MHz 810.00000 MHz 5.0000000 ms 5.0000000 ms 830.00500 MHz 830.00500 MHz 2.00 KHz/div 2.00 KHz/div 829.99500 MHz 829.99500 MHz 5.0000000 ms DS04–21359–6E 5.0000000 ms 21 MB15E03SL ■ APPLICATION EXAMPLE VP 10 kΩ Output VCO LPF 12 kΩ 12 kΩ 10 kΩ Lock detect. From a controller φR φP LD/fout ZC PS LE Data Clock 16 15 14 13 12 11 10 9 MB15E03SL 1 2 3 4 5 6 7 8 OSCIN OSCOUT VP VCC DO GND Xfin fin 1000 pF 1000 pF 1000 pF 0.1 μF 0.1 μF TCXO VP: 5.5 V Max Notes: • In case of using a crystal resonator, it is necessary to optimize matching between the crystal and this LSI, and perform detailed system evaluation. It is recommended to consult with a supplier of the crystal resonator. (Reference oscillator circuit provides its own bias, feedback resistor is 100 kΩ (typ).) • SSOP-16 ■ USAGE PRECAUTIONS To protect against damage by electrostatic discharge, note the following handling precautions: -Store and transport devices in conductive containers. -Use properly grounded workstations, tools, and equipment. -Turn off power before inserting device into or removing device from a socket. -Protect leads with a conductive sheet when transporting a board-mounted device. 22 DS04–21359–6E MB15E03SL ■ ORDERING INFORMATION Part number Package MB15E03SLPFV1 16-pin, Plastic SSOP (FPT-16P-M05) MB15E03SLWQN 16-pin, Plastic QFN (LCC-16P-M69) DS04–21359–6E Remarks 23 MB15E03SL ■ PACKAGE DIMENSIONS 16-pin plastic SSOP (FPT-16P-M05) 16-pin plastic SSOP (FPT-16P-M05) Lead pitch 0.65 mm Package width × package length 4.40 × 5.00 mm Lead shape Gullwing Sealing method Plastic mold Mounting height 1.45mm MAX Weight 0.07g Code (Reference) P-SSOP16-4.4×5.0-0.65 Note 1) *1 : Resin protrusion. (Each side : +0.15 (.006) Max). Note 2) *2 : These dimensions do not include resin protrusion. Note 3) Pins width and pins thickness include plating thickness. Note 4) Pins width do not include tie bar cutting remainder. *1 5.00±0.10(.197±.004) 0.17±0.03 (.007±.001) 9 16 *2 4.40±0.10 6.40±0.20 (.173±.004) (.252±.008) INDEX Details of "A" part +0.20 1.25 –0.10 +.008 .049 –.004 LEAD No. 1 8 0.65(.026) "A" 0.24±0.08 (.009±.003) 0.10(.004) C 24 (Mounting height) 2003-2010 FUJITSU SEMICONDUCTOR LIMITED F16013S-c-4-8 0.13(.005) M 0~8° 0.50±0.20 (.020±.008) 0.60±0.15 (.024±.006) 0.10±0.10 (Stand off) (.004±.004) 0.25(.010) Dimensions in mm (inches). Note: The values in parentheses are reference values. DS04–21359–6E MB15E03SL 16-pin plastic QFN Lead pitch 0.50 mm Package width × package length 4.00 mm × 4.00 mm Sealing method Plastic mold Mounting height 0.80 mm MAX Weight 0.04 g (LCC-16P-M69) 16-pin plastic QFN (LCC-16P-M69) 2.60±0.10 (.102±.004) 4.00±0.10 (.157±.004) 4.00±0.10 (.157±.004) INDEX AREA 0.25±0.05 (.010±.002) 2.60±0.10 (.102±.004) 0.40±0.05 (.016±.002) 0.50(.020) TYP +0.03 0.02 –0.02 (.001 +.001 –.001 ) C 1PIN CORNER (C0.35 (C.014)) 0.75±0.05 (.030±.002) (0.20(.008)) 2010 FUJITSU SEMICONDUCTOR LIMITED HMbC16-69Sc-1-1 Dimensions in mm (inches). Note: The values in parentheses are reference values. Please check the latest package dimension at the following URL. http://edevice.fujitsu.com/package/en-search/ DS04–21359–6E 25 MB15E03SL MEMO 26 DS04–21359–6E MB15E03SL MEMO DS04–21359–6E 27 MB15E03SL FUJITSU SEMICONDUCTOR LIMITED Nomura Fudosan Shin-yokohama Bldg. 10-23, Shin-yokohama 2-Chome, Kohoku-ku Yokohama Kanagawa 222-0033, Japan Tel: +81-45-415-5858 http://jp.fujitsu.com/fsl/en/ For further information please contact: North and South America FUJITSU SEMICONDUCTOR AMERICA, INC. 1250 E. Arques Avenue, M/S 333 Sunnyvale, CA 94085-5401, U.S.A. Tel: +1-408-737-5600 Fax: +1-408-737-5999 http://us.fujitsu.com/micro/ Asia Pacific FUJITSU SEMICONDUCTOR ASIA PTE. LTD. 151 Lorong Chuan, #05-08 New Tech Park 556741 Singapore Tel : +65-6281-0770 Fax : +65-6281-0220 http://sg.fujitsu.com/semiconductor/ Europe FUJITSU SEMICONDUCTOR EUROPE GmbH Pittlerstrasse 47, 63225 Langen, Germany Tel: +49-6103-690-0 Fax: +49-6103-690-122 http://emea.fujitsu.com/semiconductor/ FUJITSU SEMICONDUCTOR SHANGHAI CO., LTD. 30F, Kerry Parkside, 1155 Fang Dian Road, Pudong District, Shanghai 201204, China Tel : +86-21-6146-3688 Fax : +86-21-6146-3660 http://cn.fujitsu.com/fss/ Korea FUJITSU SEMICONDUCTOR KOREA LTD. 902 Kosmo Tower Building, 1002 Daechi-Dong, Gangnam-Gu, Seoul 135-280, Republic of Korea Tel: +82-2-3484-7100 Fax: +82-2-3484-7111 http://kr.fujitsu.com/fsk/ FUJITSU SEMICONDUCTOR PACIFIC ASIA LTD. 10/F., World Commerce Centre, 11 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel : +852-2377-0226 Fax : +852-2376-3269 http://cn.fujitsu.com/fsp/ Specifications are subject to change without notice. For further information please contact each office. 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