FUJITSU SEMICONDUCTOR DATA SHEET DS04-21339-2E ASSP Dual Serial Input PLL Frequency Synthesizer On-Chip 1.1 GHz Prescaler MB15U10 ■ DESCRIPTION The Fujitsu MB15U10 is a dual serial input phase-locked loop (PLL) frequency synthesizer and is ideally suitable for mobile communications such as cellular phones. The MB15U10 has two PLL frequency synthesizer circuits on a single chip: one for transmission and the other for reception (PLL1 and PLL2). It can operate from a +2.6V to 5.5V supply. Fujitsu’s advanced technology achieves an Icc of 7 mA (typical) as well as 10 µA (max.) at power saving mode. ■ FEATURES • • • • • • • • • Two PLLs’ for transmission/reception Low current consumption : ICC = 7 mA typ. at 3 V Power saving function : IPS = 10 µA max. Divide ratio setting with serial data input : Binary 12-bit reference counter:6 to 4,095 Binary 17-bit main counter: 1,024 to 131,071 *Main counters can be programmed individually each other. On-chip constant current source charge pumps Adjustable charge pump output current with an external resistor Lock detection function Phase matching circuit helps fast intermittent operation Plastic 20-pin SSOP (shrink small outline) package ■ PACKAGE 20-pin, Plastic SSOP (FPT-20P-M03) This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields. However, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit. 1 MB15U10 ■ PIN ASSIGNMENT (Top View) P1/fp1 1 20 ISET P2/fp2 2 19 P0/LD Do1 3 18 VP VDD1 4 17 Do2 PS 5 16 AGND fin1 6 15 fin2 DGND 7 14 VDD2 OSCin 8 13 LE P3/fr2 9 12 Data OSCout 10 11 Clock (FPT-20P-M03) 2 MB15U10 ■ PIN DESCRIPTION Pin No. Pin name Descriptions 1 P1/fp1 Data output / fp1 monitoring output (Open drain output) 2 P2/fp2 Data output / fp2 monitoring output (Open drain output) 3 Do1 Charge pump output (PLL1) 4 VDD1 Power supply for digital blocks (PLL1) 5 PS Power saving mode control (input ”L” : power saving mode) 6 fin1 RF input (PLL1) 7 DGND Ground for digital blocks 8 OSCin Crystal oscillator or TCXO input 9 P3/fr2 Data output / fr2 monitoring output (Open drain output) 10 OSCout 11 Clock Clock input 12 Data Data input 13 LE 14 VDD2 Power supply for digital blocks (PLL2) 15 fin2 RF input (PLL2) 16 AGND 17 Do2 Charge pump output (PLL2) 18 VP Power supply for charge pump 19 P0/LD 20 ISET Crystal oscillator output (CMOS output) Load enable of serial input data (input ”H” : Data is shifted into a latch.) Ground for the charge pumps Data output / lock detector output (Open drain output) Output is selected by ”OLA” and ”OLB” bits in a serial data Charge pump output current adjustment (A resistor is connected.) 3 MB15U10 ■ BLOCK DIAGRAM VDD1 4 18 Power saving circuit Charge pump Phase comparator 17-bit latch (comparisonal division) 3 VP Do1 PS1 ISET fin1 fp1 Main counter (binary 17-bit) 6 CR1 LD1 PS 5 PLL1 OSCin 8 fr1 Crystal oscillator OSCout Reference counter fr2 +1/+2 10 TS SR Selector P0 LD2 OLA, B 14-bit latch (referencial division) fr2 9 Selector fp1 Power saving circuit 19 P0/LD 17-bit latch (comparisonal division) P3/fr2 1 P1/fp1 2 P2/fp2 fp2 PS2 Main counter (binary 17-bit) fin2 15 PLL2 Phase comparator fp2 CR2 OLA, B 10-bit latch CR1, 2 Latch selector Data 12 Shift register (21-bit) Clock 11 4 17 Do2 P0 P1, 2, 3 LE 13 Charge pump 14 7 16 VDD2 DGND AGND 20 ISET MB15U10 ■ ABSOLUTE MAXIMUM RATINGS Parameter Symbol Rating Unit VDD1, 2 –0.3 to +6.0 V VP VDD to 6.0 V Output voltage VO –0.3 to VDD +0.3 V Output current IO ±10 mA Open drain withstand voltage VOOP –0.5 to 7.0 V Storage temperature Tstg –55 to +125 °C Power supply voltage Remark Note: Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ■ RECOMMENDED OPERATING CONDITIONS Parameter Symbol Value Unit Min Typ Max VDD1, VDD2 2.6 – 5.5 V VP VDD – 6.0 V Input voltage VI GND – VDD V Operating temperature Ta –30 – +85 °C Power supply voltage Remark Notes: To protect against damage by electrostatic discharge, note the following handling precautions: – Store and transport devices in conductive containers. – Use properly grounded workstations, tools, and equipment. – Turn off power before inserting or removing this device into or from a socket. – Protect leads with conductive sheet, when transporting a board mounted device. 5 MB15U10 ■ ELECTRICAL CHARACTERISTICS Ta = 25°C Parameter Symbol Power supply current (IDD1 + IDD2) Stand by current IDD VDD1, 2 IPS Value Condition Typ Max – 7.0 9.0 mA *1 – 11.0 13.5 mA *2 – – 10 µA fin1, 2 fin* 90 – 1100 MHz OSCin fOSC 3 12.8 35 MHz fin1, 2 Vfin –13 – +1 dBm 50Ω, Vcc = 2.6 to 3.5V fin1, 2 Vfin –7 – +1 dBm 50Ω, Vcc = 3.5 to 5.5V OSCin VOSC 0.5 – – Vp-p Data, Clock, LE, PS VIH VDD × 0.7 – – V VIL – – VDD × 0.3 V IIH – – 1.0 µA Low-level input current Data, Clock, LE, PS IIL –1.0 – – µA Input current OSCin IOSC –100 – 100 µA Low-level output voltage P0 to P3 VOL – – 0.4 V Open drain output Set output voltage ISET VSET – 1.2 – V RSET = 5kΩ to 60kΩ High-impedance cut off current DO, P0 to P3 IOFF – – 1.1 µA IDOH1*4 1.4 1.9 2.4 mA IDOL1*4 1.4 1.9 2.4 mA IDOH0 0.7 0.96 1.2 mA IDOL0 0.7 0.96 1.2 mA RSET = 7kΩ connected. CR1, 2 bits = ”0” VDD = 3.0V, VP = 5.0V IOL 1.0 – – mA Open drain Operating frequency Input sensitivity High-level input voltage Low-level input voltage High-level input current DO1, 2 Output current DO1, 2 P0 to P3 3 Note: *1 ; fIN = 1.1 GHz, OSCIN = 12.8 MHz, VDD = 3.0 V. In locked state. *2 ; fIN = 1.1 GHz, OSCIN = 12.8 MHz, VDD = 5.0 V. In locked state. *3 ; AC coupling with a 1000 pF capacitor connected. *4 ; The symbol “–” (minus) means direction of current flow. 6 Unit Min RSET = 7kΩ connected. CR1, 2 bits = ”1” VDD = 3.0V, VP = 5.0V MB15U10 ■ FUNCTIONAL DESCRIPTIONS Serial Data Input Serial data is processed using the Data, Clock, and LE pins. Serial data controls the programmable reference divider, programmable divider (PLL1) and programmable divider (PLL2) separately by means of address setting. Binary serial data is entered via the Data pin. One bit of data is shifted into the internal shift register on the rising edge of the clock. When the load enable pin is high, stored data is latched. a) Serial data input format Direction of data input (MSB) (LSB) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 X X X P 0 O L A O L B C R 1 C R 2 X X P S 1 P S 2 P 3 P 2 P 1 X X 0 0 0 1 M A 16 M A 15 M A 14 M A 13 M A 12 M A 11 M A 10 M A 9 M A 8 M A 7 M A 6 M A 5 M A 4 M A 3 M A 2 M A 1 M A 0 0 1 0 0 0 0 0 T S S R R 11 R 10 R 9 R 8 R 7 R 6 R 5 R 4 R 3 R 2 R 1 R 0 0 1 0 1 M B 16 M B 15 M B 14 M B 13 M B 12 M B 11 M B 10 M B 9 M B 8 M B 7 M B 6 M B 5 M B 4 M B 3 M B 2 M B 1 M B 0 0 1 1 0 0 0 0 0 Auxiliary bit for test (no need at ordinary use) Data setting MA0 to 16 MB0 to 16 R0 to 11 SR P0 to 3 OLA, B CR1, 2 PS1, 2 TS X 0 : : : : : : : : : : : Divide ratio setting bits of the main counter (PLL1) Divide ratio setting bits of the main counter (PLL2) Divide ratio setting bits of the reference counter Divide ratio select bit of reference frequency (PLL1 and PLL2) Setting bits of P0 to P3 output pins Select bits of P0/LD pin output Select bits of charge pump output current Power saving mode control bits Test bits (Set ”0” at ordinary use.) Dummy bits (Set ”0” or ”1”.) Set ”0” Address [ See Table 1 ] [ See Table 2 ] [ See Table 3 ] [ See Table 4 ] [ See Table 5 ] [ See Table 6 ] [ See Table 7 ] [ See Table 8 ] [ See Table 9 ] Note: Start data input with MSB first. 7 MB15U10 b) Data setting description • Table 1 : MA0 to MA16 : Divide ratio of the binary 17-bit main counter (PLL1) Divide Ratio (MA) M A 16 M A 15 M A 14 M A 13 M A 12 M A 11 M A 10 M A 9 M A 8 M A 7 M A 6 M A 5 M A 4 M A 3 M A 2 M A 1 M A 0 1024 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1025 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 • • • • • • • • • • • • • • • • • • Note: • Divide ratios less than 1,024 are prohibited. (Divide ratio = 1,024 to 131,071) • Table 2 : MB0 to MB16 : Divide ratio of the binary 17-bit main counter (PLL2) Divide Ratio (MB) M B 16 M B 15 M B 14 M B 13 M B 12 M B 11 M B 10 M B 9 M B 8 M B 7 M B 6 M B 5 M B 4 M B 3 M B 2 M B 1 M B 0 1024 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1025 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 • • • • • • • • • • • • • • • • • • Note: • Divide ratios less than 1,024 are prohibited. (Divide ratio = 1,024 to 131,071) • Table 3 : R0 to R11 : Divide ratio of the binary 12-bit reference counter Divide Ratio (R) R 11 R 10 R 9 R 8 R 7 R 6 R 5 R 4 R 3 R 2 R 1 R 0 6 0 0 0 0 0 0 0 0 0 1 1 0 7 0 0 0 0 0 0 0 0 0 1 1 1 • • • • • • • • • • • • • Note: • Divide ratios less than 6 are prohibited. (Divide ratio = 6 to 4,095) • Table 4 : Divide ratio select bit of reference frequency (PLL1 and PLL2) SR Divide ratio of reference frequency (PLL1) Divide ratio of reference frequency (PLL2) 0 R R 1 R 2R Note: R = Programmed value with R0 to R11 bits 8 MB15U10 • Table 5 : P0 to P3 ; P0 to P3 outputs control PX bit PX output (19, 1, 2, 9 pins) 0 ON (”L”) 1 OFF (”Z”) Notes: X = 0 to 3 • Table 6 : OLA, OLB ; 19-pin output selection OLA OLB 19-pin output 0 0 P0 signal 0 1 Lock detect signal (PLL2) 1 0 Lock detect signal (PLL1) 1 1 Lock detect signal (PLL1 and PLL2) • Table 7 : CR1, CR2 ; Charge pump output current selection CR1, 2 Charge pump output current 0 IDO 1 2IDO Notes: PLL1 and PL2 can be controlled individually. • Table 8 : PS ; Power saving control PS1, 2 Operating mode 0 Power saving mode 1 Operation Notes: PLL1 and PL2 can be controlled individually. • Table 9 : TS ; Test bit (Set to "0" at ordinary use.) TS 1-pin 2-pin 9-pin 0 Output P1 signal Output P2 signal Output P3 signal 1 Outputs fp1 Outputs fp2 Outputs fp3 Notes: Reference frequency and comparison frequency can be monitored via P1 to P3 pins. 9 MB15U10 Serial Data Input Timing • t1 (≥ 20 ns), t2 (≥ 20 ns), Data t3 (≥ 50 ns), t4 (≥ 50 ns), t5 (≥ 20 ns), t6 (≥ 1000 ns) LSB MSB Clock LE t1 t2 t5 t3 t4 Note: One bit of data is shifted into the shift register on the rising edge of the clock. 10 t6 MB15U10 ■ TEST CIRCUIT (for Measuring fin Input Sensitivity) VDD2 7kΩ 0.1µF Controller 1000pF S.G 50Ω 50Ω 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 12 11 9 10 X’tal S.G VDD1 1000pF Oscilloscope 0.1µF Oscilloscope 2kΩ 2kΩ VDD 0.1µF 11 MB15U10 ■ TYPICAL CHARACTERISTICS Do Output Current Conditions : Ta = +25°C VDD = 3 V Vp = 5 V ISETR = 5 k, 7 k, 15 k, 60 k 7 k Ω CR = “L” 5 k Ω 60 60 15 k k k Ω Ω Ω 5.0 5.0 4.0 4.0 3.0 3.0 VOL (V) VOH (V) 60 60 15 7 5 15 k k k k k k Ω Ω Ω Ω Ω Ω CR = “H” 2.0 1.0 7 5 15 k k k Ω ΩΩ 7 k Ω 5 k Ω 2.0 1.0 0 0 0 –1.0 –2.0 –3.0 –4.0 0 1.0 2.0 IOH (mA) 3.0 4.0 IOL (mA) fin Input Sensitivity [Ta = +25°C] +10 × × × Vfin (dBm) 0 SPEC –10 × × × –20 × –30 × 0 × × × × × × × × × × :VDD = 2.6 V • :VDD = 3.0 V :VDD = 3.6 V × × 500 1000 fin (MHz) 1500 2000 [Ta = +25°C] +10 Vfin (dBm) 0 SPEC –10 –20 :VDD = 4.5 V :VDD = 5.0 V :VDD = 5.5 V –30 –40 0 500 1000 fin (MHz) 1500 2000 (Continued) 12 MB15U10 (Continued) OSCin Input Sensitivity [Ta = +25°C] +10 SPEC VOSC(dBm) 0 –10 –20 × :VDD = 2.6 V • :VDD = 3.0 V :VDD = 3.6 V –30 :VDD = 4.5 V :VDD = 5.0 V :VDD = 5.5 V –40 0 50 100 fOSC (MHz) 150 200 13 MB15U10 ■ APPLICATION EXAMPLE Output LPF VCO VDD2 Controller VP 0.1µF 1000pF 0.1µF R1 Lock Det ISET 20 P0/LD 19 VP 18 Do2 17 16 VDD2 fin2 AGND 15 LE Data Clock 14 13 12 11 7 8 9 10 MB15U10 1 P1/fp1 2 3 P2/fp2 4 Do1 VDD1 5 VDD1 6 PS DGNG fin1 OSCIN P3/fr2 OSCOUT X’tal 1000pF 0.1µF C1 C2 Controller Output LPF R1 C1, C2 Clock, Data, LE PS 14 VCO : Values(5 to 60 kΩ) are used to determine the output current for charge pump. : Determined by the crystal oscillator : Insert pull down/pull up resistors to prevent oscillation when the terminals are left open. : When not in use, insert a pull up resistor with respect to the power supply. MB15U10 ■ REFERENCE INFORMATION Typical plots measured with the test circuit are shown below. Each plots shows lock up time, phase noise, and reference leakage. • fVCO • KV • fr • fOSC • LPF Test Circuit S.G. OSCin LPF Do = 836.490 MHz = 12 MHz/V = 30 kHz = 15.36 MHz 9.1 kΩ fin 5.1 kΩ 0.033 µF Spectrum Analyzer ∆ Mkr VCO PLL Lock Up Time = 11.0 ms PLL Lock Up Time = 10.6 ms (824.01 MHz → 848.97 MHz, within ±800 Hz) (848.97 MHz → 824.01 MHz, within ±800 Hz) x: y: 10.99990891 ms 24.961502 MHz A evts N/A ∆ Mkr x: y: 30.00150 MHz 30.00150 MHz 500.0 Hz/div 500.0 Hz/div 29.99900 MHz 29.99900 MHz 100.2131 µs ∆ Mkr 0.01 µF 0.33 µF x: y: 10.99990891 ms 24.961502 MHz 100.1353 µs 59.9002131 ms A evts N/A ∆ Mkr x: y: 50.00000 MHz 60.00000 MHz 10.00000 MHz/div 10.00000 MHz/div 0 Hz 10.59999719 ms –24.960989 MHz 10.59999719 ms –24.960989 MHz A evts N/A 59.9003853 ms A evts N/A 10.00000 MHz 100.2131 µs 59.9002131 ms 100.1353 µs 59.9003853 ms (Continued) 15 MB15U10 (Continued) PLL Phase Noise (TX mode) PLL Reference Leakage (TX mode) @±1 kHz offset at 836.49 MHz = 75 dBc/Hz REF 0.0 dBm ATT 10 dB @±30 kHz offset at 836.49 MHz = 82 dBc REF 0.0 dBm MKR 10 dB/ 10 dB/ RBW 100 Hz RBW 1kHz VBW 100 Hz VBW 1kHz SWP 3 s SPAN 5.00 kHz CENTER 836.49000 MHz SWP 800 ms ATT 10 dB MKR SPAN 150 kHz CENTER 836.490 MHz fin Input Impedance 1: 20.93 Ω –130.75 Ω 500 MHz 2: 11.281 Ω –71.824 Ω 800 MHz 3: 11.871 Ω –51.166 Ω 1 GHz 4: 11.627 Ω –42.119 Ω 3.4352 pF 1.1 GHz 4 1 3 2 OSCin Input Impedance 1: 1.5699 kΩ –2.6509 kΩ 10 MHz 2: 889.63 Ω –2.0951 kΩ 15 MHz 4 12 3 16 3: 537.31 Ω –1.6434 kΩ 20 MHz 4: 342.19 Ω –1.3733 kΩ 4.6357 pF 25 MHz MB15U10 ■ ORDERING INFORMATION Part number Package MB15U10PFV 20pin, Plastic SSOP (FPT-20P-M03) Remarks 17 MB15U10 ■ PACKAGE DIMENSION *: These dimensions do not include resin protrusion. 20 pin, Plastic SSOP (FPT-20P-M03) +0.20 * 6.50±0.10(.256±.004) 1.25 –0.10 +.008 .049 –.004 (Mounting height) 0.10(.004) INDEX *4.40±0.10 6.40±0.20 (.173±.004) (.252±.008) 0.65±0.12 (.0256±.0047) 5.85(.230)REF C 18 1994 FUJITSU LIMITED F20012S-2C-4 +0.10 0.22 –0.05 +.004 .009 –.002 "A" 5.40(.213) NOM +0.05 0.15 –0.02 +.002 .006 –.001 Details of "A" part 0.10±0.10(.004±.004) (STAND OFF) 0 10° 0.50±0.20 (.020±.008) Dimensions in mm (inches). FUJITSU LIMITED For further information please contact: Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices KAWASAKI PLANT, 4-1-1, Kamikodanaka Nakahara-ku, Kawasaki-shi Kanagawa 211-88, Japan Tel: (044) 754-3763 Fax: (044) 754-3329 North and South America FUJITSU MICROELECTRONICS, INC. Semiconductor Division 3545 North First Street San Jose, CA 95134-1804, U.S.A. Tel: (408) 922-9000 Fax: (408) 432-9044/9045 Europe FUJITSU MIKROELEKTRONIK GmbH Am Siebenstein 6-10 63303 Dreieich-Buchschlag Germany Tel: (06103) 690-0 Fax: (06103) 690-122 Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE. LIMITED #05-08, 151 Lorong Chuan New Tech Park Singapore 556741 Tel: (65) 281-0770 Fax: (65) 281-0220 All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. 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If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Control Law of Japan, the prior authorization by Japanese government should be required for export of those products from Japan. F9703 FUJITSU LIMITED Printed in Japan 24