FUJITSU MB90234PFV

FUJITSU SEMICONDUCTOR
DATA SHEET
DS07-13504-2E
16-bit Proprietary Microcontroller
CMOS
F2MC-16F MB90230 Series
MB90233/234/P234/W234
■ DESCRIPTION
The MB90230 series is a member of general-purpose, 16-bit microcontrollers designed for those applications which
require high-speed realtimeprocessing, proving to be suitable for various industrial machines, camera and video
devices, OA equipment, and for process control. The CPU used in this series is the F2MC*-16F. The instruction
set for the F2MC-16F CPU core is designed to be optimized for controller applications while inheriting the AT
architecture of the F2MC-16/16H series, allowing a wide range of control tasks to be processed efficiently at high
speed.
The peripheral resources integrated in the MB90230 series include: the UART (clock asynchronous/synchronous
transfer) × 1 channel, the extended serial I/O interface × 1 channel, the A/D converter (8/10-bit precision) × 8
channels, the D/A converter (8-bit precision) × 2 channels, the level comparator × 1 channel, the external interrupt
input × 4 lines, the 8-bit PPG timer (PWM/single-shot function) × 1 channel, the 8-bit PWM controller × 6 channels,
the 16-bit free run timer × 1 channel, the input capture unit × 4 channels, the output compare unit × 6 channels,
and the serial E2PROM interface.
*: F2MC stands for FUJITSU Flexible Microcontroller.
■ FEATURES
F2MC-16F CPU block
• Minimum execution time: 62.5 ns (at machine clock frequency of 16 MHz)
• Instruction set optimized for controllers
Various data types supported (bit, byte, word, and long-word)
Extended addressing modes: 23 types
High coding efficiency
Higher-precision operation enhanced by a 32-bit accumulator
Signed multiplication and division instructions
(Continued)
■ PACKAGE
100-pin Plastic LQFP
100-pin Ceramic LQFP
(FPT-100P-M05)
(FPT-100C-C01)
MB90230 Series
(Continued)
• Enhanced instructions applicable to high-level language (C) and multitasking
System stack pointer
Enhanced pointer-indirect instructions
Barrel shift instructions
• Increased execution speed: 8-byte instruction queue
• 8-level, 32-factor powerful interrupt service functions
• Automatic transfer function independent of the CPU (EI2OS)
• General-purpose ports: Up to 84 lines
Ports with input pull-up resistor available: 24 lines
Ports with output open-drain available: 9 lines
Peripheral blocks
• ROM:48 Kbytes (MB90233)
96 Kbytes (MB90234)
EPROM: 96 Kbytes (MB90W234)
One-time PROM: 96 Kbytes (MB90P234)
• RAM: 2 Kbytes (MB90233)
3 Kbytes (MB90234/W234/P234)
• PWM control circuit: (simple 8 bits): 6 channels
• Serial interface
UART: 1 channel
Extended serial I/O interface
Switchable I/O port: 1 channel
Communication prescaler (Source clock generator for the UART, serial I/O interface, CKOT, and level
comparator): 1 channel
• Serial E2PROM interface: 1 channel
• A/D converter with 8/10-bit resolution: input 8 channels
• Level comparator: 1 channel
4-bit D/A converter integrated
• D/A converter with 8-bit resolution: 2 channels
8-bit PPG timer: 1 channel
• Input/output timer
16-bit free run timer: 1 channel
16-bit output compare unit: 6 channels
16-bit input capture unit: 4 channels
• 18-bit timebase timer
• Watchdog timer function
• Standby modes
Sleep mode
Stop mode
2
MB90230 Series
■ PRODUCT LINEUP
Part number
MB90233
NB90234
MB90P234
MB90W234
MB90V230
One-time PROM
model
EPROM model
Evaluation
model
Parameter
Classification
Mask ROM products
ROM size
48 Kbytes
96 Kbytes
96 Kbytes
96 Kbytes
—
RAM size
2 Kbytes
3 Kbytes
3 Kbytes
3 Kbytes
4 Kbytes
CPU functions
Number of instructions: 420
Instruction bit length: 8 or 16 bits
Instruction length: 1 to 7 bytes
Data bit length: 1, 4, 8, 16, or 32 bits
Minimum execution time: 62.5 ns at 16 MHz (internal)
Ports
Up to 84 lines
I/O ports (CMOS): 51
I/O ports (CMOS) with pull-up resistor available: 24
I/O ports (open-drain): 9
UART
Number of channels: 1 (switchable I/O)
Clock synchronous communication (2404 to 38460 bps, full-duplex double buffering)
Clock asynchronous communication (500K to 5M bps, full-duplex double buffering)
Serial interface
Number of channels: 1
Internal or external clock mode
Clock synchronous transfer (62.5 kHz to 1 MHz, “LSB first” or “MSB first” transfer)
A/D converter
Resolution: 10 or 8 bits, Number of input lines: 4
Single conversion mode (conversion for a specified input channel)
Scan conversion mode (continuous conversion for specified consecutive channels)
Continuous conversion mode (repeated conversion for a specified channel)
Stop conversion mode (periodical conversion)
D/A converter
Resolution: 8 bits, Number of output pins: 2
Level
comparator
PWM
PPG timer
Comparison to internal D/A converter (4-bit resolution)
Number of channels: 6
8-bit PWM control circuit (operation of 1×φ, 2×φ, 16×φ, 32×φ)
Number of channels: 1 channel with 8-bit resolution
PWM function: Continuous output of pulse synchronous to trigger
Single-shot function: Output of single pulse by trigger
Serial E2PROM
interface
Number of channels: 1
Instruction code (NS type)
Variable address length: 8 to 11 bits (with address increment function)
Variable data length: 8 or 16 bits
Timer
Number of channels: 6
16-bit reload timer operation (operation clock cycle of 0.25 µs to 1.05 s)
Free run timer
External interrupt
input
Standby mode
Package
Number of channels: 1
16-bit input capture unit: 4 channels
16-bit output compare unit: 6 channels
Number of input pins: 4
Stop mode and sleep mode
FPT-100P-M05
FPT-100C-C01
PGA256-A02
3
MB90230 Series
■ PIN ASSIGNMENT
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
P21/A01
P20/A00
P17/D15
P16/D14
P15/D13
P14/D12
P13/D11
P12/D10
P11/D09
P10/D08
P07/D07
P06/D06
P05/D05
P04/D04
P03/D03
P02/D02
P01/D01
P00/D00
VCC
X1
X0
VSS
P57
P56/RD
P55/WRL
(TOP VIEW)
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
P71/EDI
P72/EDO
P73/ESK
P74/ECS
P75/DA0
P76/DA1
AVCC
AVRH
AVRL
AVSS
P60/AN0
P61/AN1
P62/AN2
P63/AN3
VSS
P64/AN4
P65/AN5
P66/AN6
P67/AN7/CMP
P80/INT0
P81/INT1
MD0
MD1
MD2
HST
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
P22/A02
P23/A03
P24/A04
P25/A05
P26/A06
P27/A07
P30/A08
P31/A09
VSS
P32/A10
P33/A11
P34/A12
P35/A13
P36/A14
P37/A15
PWM0/P40/A16
PWM1/P41/A17
PWM2/P42/A18
PWM3/P43/A19
PWM4/P44/A20
VCC
PWM5/P45/A21
TRG/P46/A22
PPG/P47/A23
ATG/P70
(FPT-100P-M05)
(FPT-100C-C01)
4
RST
P54/WRH
P53/HRQ
P52/HAK
P51/RDY
P50/CLK
PA5/SCK2
PA4/SOT2
PA3/SIN2
PA2/SCK1
PA1/SOT1
PA0/SIN1
P96/SCK0
P95/SOT0
P94/SIN0
P93/IN3/CKOT
P92/IN2
P91/IN1
P90/IN0
P87/OUT5
P86/OUT4
P85/OUT3
P84/OUT2
P83/OUT1/INT3
P82/OUT0/INT2
MB90230 Series
■ PIN DESCRIPTION
Pin no.
Pin name
80
X0
81
X1
82
83 to 90
Circuit
type
A
Oscillator pins
VCC
—
Power supply pin
P00 to P07
G
General-purpose I/O port
An input pull-up resistor can be added to the port by setting the
pull-up resistor setting register.
These pins serve as D00 to D07 pins in bus modes other than the
single-chip mode.
D00 to D07
91 to 98
P10 to P17
I/O pins for the lower eight bits of the external data bus.
These pins are enabled in an external-bus enabled mode.
G
D08 to D15
99, 100
1 to 6
P20 to P27
P30, P31
G
10 to 15
General-purpose I/O port
An input pull-up resistor can be added to the port by setting the
pull-up resistor setting register.
These pins are enabled in the single-chip mode.
I/O pins for the lower eight bits of the external data bus
These pins are enabled in an external-bus enabled mode.
E
A08, A09
9
General-purpose I/O port
An input pull-up resistor can be added to the port by setting the pull-up
resistor setting register.
These pins are enabled in the single-chip mode with the external-bus
enabled and the 8-bit data bus specified.
I/O pins for the upper eight bits of the external data bus
These pins are enabled in an external-bus enabled mode with the 16bit data bus specified.
A00 to A07
7, 8
Function
General-purpose I/O port
This port is enabled in the single-chip mode or when the middle
address control register setting is “port.”
I/O pins for the middle eight bits of the external data bus
These pins are enabled in an external-bus enabled mode when the
middle address control register setting is “address.”
VSS
—
Power supply pin
P32 to P37
E
General-purpose I/O port
This port is enabled in the single-chip mode or when the middle
address control register setting is “port.”
A10 to A15
I/O pins for the middle eight bits of the external data bus
These pins are enabled in an external-bus enabled mode when the
middle address control register setting is “address.”
(Continued)
5
MB90230 Series
Pin no.
16
17
18
19
20
21
Pin name
P40
Circuit
type
E
Function
General-purpose I/O port
This port is enabled in the single-chip mode or when the upper
address control register setting is “port.”
A16
Output pin for external address A16
This pin is enabled in the external-bus enabled mode with the upper
address control register set to “address.”
PWM0
This pin serves as the output pin for 8-bit PWM0
The pin is enabled for output by the control status register.
P41
E
General-purpose I/O port
This port is enabled in the single-chip mode or when the upper
address control register setting is “port.”
A17
Output pin for external address A17
This pin is enabled in the external-bus enabled mode with the upper
address control register set to “address.”
PWM1
This pin serves as the output pin for 8-bit PWM1.
The pin is enabled for output by the control status register.
P42
E
General-purpose I/O port
This port is enabled in the single-chip mode or when the upper
address control register setting is “port.”
A18
Output pin for external address A18
This pin is enabled in the external-bus enabled mode with the upper
address control register set to “address.”
PWM2
This pin serves as the output pin for 8-bit PWM2.
This pin is enabled for output by the control status register.
P43
E
General-purpose I/O port
This port is enabled in the single-chip mode or when the upper
address control register setting is “port.”
A19
Output pin for external address A19
This pin is enabled in the external-bus enabled mode with the upper
address control register set to “address.”
PWM3
This pin serves as the output pin for 8-bit PWM3.
This pin is enabled for output by the control status register.
P44
E
General-purpose I/O port
This port is enabled in the single-chip mode or when the upper
address control register setting is “port.”
A20
Output pin for external address A20
This pin is enabled in the external-bus enabled mode with the upper
address control register set to “address.”
PWM4
This pin serves as the output pin for 8-bit PWM4.
The pin is enabled for output by the control status register.
VCC
—
Power supply pin
(Continued)
6
MB90230 Series
Pin no.
22
23
24
25
Pin name
P45
Circuit
type
E
Output pin for external address A21
This pin is enabled in the external-bus enabled mode with the upper
address control register set to “address.”
PWM5
This pin serves as the output pin for 8-bit PWM5.
The pin is enabled for output by the control status register.
P46
L*1
Output pin for external address A22
This pin is enabled in the external-bus enabled mode with the upper
address control register set to “address.”
TRG
This pin serves as the external trigger pin for the 8-bit PPG timer
The pin is enabled for triggering by the control status register.
P47
E
Output pin for external address A23
This pin is enabled in the external-bus enabled mode with the upper
address control register set to “address.”
PPG
This pin serves as the output pin for the 8-bit PPG timer.
The pin is enabled for output by the control status register.
P70
L*1
P71
P72
P73
P74
ECS
General-purpose I/O port
External trigger input pin for the A/D converter
This pin functions when enabled by the control status register.
F
General-purpose I/O port
Data input pin for the serial EEPROM interface
This pin functions when enabled by the control status register.
E
General-purpose I/O port
Data output pin for the serial EEPROM interface
This pin functions when enabled by the control status register.
E
ESK
29
General-purpose I/O port
This port is enabled in the single-chip mode or when the upper
address control register setting is “port.”
A23
EDO
28
General-purpose I/O port
This port is enabled in the single-chip mode or when the upper
address control register setting is “port.”
A22
EDI
27
General-purpose I/O port
This port is enabled in the single-chip mode or when the upper
address control register setting is “port.”
A21
ATG
26
Function
General-purpose I/O port
Clock output pin for the serial EEPROM interface
This pin functions when enabled by the control status register.
E
General-purpose I/O port
Chip select signal output pin for the serial EEPROM interface
This pin functions when enabled by the control status register.
(Continued)
7
MB90230 Series
Pin no.
30, 31
Pin name
P75, P76
Circuit
type
K
DA0
DA1
Function
General-purpose I/O port
This pin serves as the D/A converter output pin.
The pin functions when enabled by the control status register.
32
AVCC
—
A/D converter power supply pin
33
AVRH
—
“H” reference power supply pin for the A/D converter
34
AVRL
—
“L” reference power supply pin for the A/D converter
35
AVSS
—
A/D converter power pin (GND)
P60 to P63
J
General-purpose I/O port
This port is enabled when the analog input enable register setting is
“port.”
36 to 39
AN0 to AN3
40
41 to 43
A/D converter analog input pins
These pins are enabled when the analog input enable register setting
is “analog input.”
VSS
—
Power pin (GND)
P64 to P66
J
General-purpose I/O port
This port is enabled when the analog input enable register setting is
“port.”
AN4 to AN6
44
45
P67
A/D converter analog input pins
These pins are enabled when the analog input enable register setting
is “analog input.”
J
AN7
A/D converter analog input pin
This pin is enabled when the analog input enable register setting is
“analog input.”
CMP
Comparator input pin
P80
L*2
INT0
46
General-purpose I/O port
This port is enabled when the analog input enable register setting is
“port.”
P81
General-purpose I/O port
This port is always enabled.
External interrupt request input 0
Since this pin serves for interrupt request as required when external
interrupt is enabled, other outputs must be off unless used
intentionally.
L*2
INT1
General-purpose I/O port
This port is always enabled.
External interrupt request input 1
Since this pin serves for interrupt request as required when external
interrupt is enabled, other outputs must be off unless used
intentionally.
47
MD0
C
Mode pin
This pin must be fixed to VCC or VSS.
48
MD1
C
Mode pin
This pin must be fixed to VCC or VSS.
(Continued)
8
MB90230 Series
Pin no.
Pin name
Circuit
type
Function
49
MD2
C
Mode pin
This pin must be fixed to VSS.
50
HST
D
Hardware standby input pin
51, 52
53 to 56
P82, P83
2
L*
OUT0,
OUT1
Output compare output pins
These pins function when enabled by the control status register.
INT2,
INT3
External interrupt request inputs 2 and 3.
Since these pins serve for interrupt request as required when external
interrupt is enabled, other outputs must be off unless used
intentionally.
P84 to P87
E
OUT2 to OUT5
57 to 59
P90 to P92
61
P93
L*1
L*1
General-purpose I/O port
This port is always enabled.
IN3
Input capture edge input pin
This pin functions when enabled by the control status register.
CKOT
Prescaler output pin
This pin functions when enabled by the control status register.
P94
I
P95
P96
SCK0
General-purpose I/O port
This port is always enabled.
The port serves as an open-drain output depending on the open-drain
setting register.
Serial data input pin for the UART
This pin functions when enabled by the control status register.
H
SOT0
63
General-purpose I/O port
This port is always enabled.
Input capture edge input pins
These pins function when enabled by the control status register.
SIN0
62
General-purpose I/O port
This pin is always enabled.
Output compare output pins
These pins function when enabled by the control status register.
IN0 to IN2
60
General-purpose I/O port
General-purpose I/O port
This port is always enabled.
The port serves as an open-drain output depending on the open-drain
setting register.
Serial data output pin for the UART
This pin functions when enabled by the control status register.
I
General-purpose I/O port
This port is always enabled.
The port serves as an open-drain output depending on the open-drain
setting register.
UART clock output pin
This pin functions when enabled by the control status register.
(Continued)
9
MB90230 Series
Pin no.
64
Pin name
PA0
Circuit
type
Function
I
General-purpose I/O port
This port is always enabled.
The port serves as an open-drain output depending on the open-drain
setting register.
SIN1
65
PA1
Serial data input pin for the extended serial I/O interface
This pin functions when enabled by the control status register and by
the serial port switching register.
H
SOT1
66
PA2
Serial data output pin for the extended serial I/O interface
This pin functions when enabled by the control status register and by
the serial port switching register.
I
SCK1
67
PA3
PA4
I
PA5
SCK2
General-purpose I/O port
This port is always enabled.
The port serves as an open-drain output depending on the open-drain
setting register.
Serial data input pin for the extended serial I/O interface
This pin functions when enabled by the control status register and by
the serial port switching register.
H
SOT2
69
General-purpose I/O port
This port is always enabled.
The port serves as an open-drain output depending on the open-drain
setting register.
Clock output pin for the extended serial I/O interface
This pin functions when enabled by the control status register and by
the serial port switching register.
SIN2
68
General-purpose I/O port
This port is always enabled.
The port serves as an open-drain output depending on the open-drain
setting register.
General-purpose I/O port
This port is always enabled.
The port serves as an open-drain output depending on the open-drain
setting register.
Serial data output pin for the extended serial I/O interface
This pin functions when enabled by the control status register and by
the serial port switching register.
I
General-purpose I/O port
This port is always enabled.
The port serves as an open-drain output depending on the open-drain
setting register.
Clock output pin for the extended serial I/O interface
This pin functions when enabled by the control status register and by
the serial port switching register.
The pin is a general-purpose I/O port.
(Continued)
10
MB90230 Series
(Continued)
Pin no.
70
Pin name
P50
Circuit
type
Function
H
This pin is enabled in the single-chip mode and when the CLK output
is disabled.
CLK
71
P51
CLK output pin
This pin is enabled in an external-bus enabled mode with the CLK
output enabled.
F
RDY
72
P52
Ready signal input pin
This pin is enabled in an external-bus enabled mode.
E
P53
E
HRQ
74
P54
General-purpose I/O port
This port is enabled in the single-chip mode or when the hold function
is disabled.
Hold acknowledge signal output pin
This pin is enabled in the single-chip mode or when the hold function
is enabled.
HAK
73
General-purpose I/O port
This port is enabled in the single-chip mode.
General-purpose I/O port
This port is enabled in the single-chip mode or when the hold function
is disabled.
Hold acknowledge signal output pin
This pin is enabled in the single-chip mode or when the hold function
is enabled.
E
WRH
General-purpose I/O port
This port is enabled in the single-chip mode, in external-bus 8-bit
mode, or when the WR pin output is disabled.
Write strobe output pin for the upper eight bits of the data bus
This pin is enabled in an external-bus enabled mode and in external
bus 16-bit mode with the WR pin output enabled.
75
RST
B
Reset signal input pin
76
P55
E
This port is enabled in the single-chip mode, in external-bus 8-bit
mode, or when the WR pin output is disabled
WRL
77
P56
Write strobe output pin for the lower eight bits of the data bus
This pin is enabled in an external-bus enabled mode and in external
bus 16-bit mode with the WR pin output enabled.
The pin is a general-purpose I/O port.
E
RD
This pin is enabled in the single-chip mode.
Read strobe output pin for the data bus
This pin is enabled in an external-bus enabled mode.
78
P57
E
General-purpose I/O port
79
VSS
—
Power pin (GND)
*1: Enabled in any standby mode
*2: Enabled only in the hardware standby mode
11
MB90230 Series
■ I/O CIRCUIT TYPE
Type
Circuit
Remarks
A
• Oscillation feedback resistor:
Approx. 1 MΩ
X1
X0
Standby control
B
• Hysteresis input with pull-up
resistor
C
• CMOS input port
D
• Hysteresis input port
E
• CMOS level output
CMOS
Standby control
(Continued)
12
MB90230 Series
Type
Circuit
Remarks
F
• CMOS level output
• Hysteresis input
Standby control
G
Pull-up control
• Input pull-up resistor control
provided
• CMOS level input/output
CMOS
Standby control
H
• CMOS level input/output
• Open-drain control provided
Open-drain control signal
CMOS
Standby control
(Continued)
13
MB90230 Series
(Continued)
Type
Circuit
Remarks
I
Open-drain control signal
• CMOS level output
• Hysteresis input
• Open-drain control provided
CMOS
Standby control
J
• CMOS level input/output
• Analog input
Analog input
CMOS
Standby control
K
• CMOS level input/output
• Analog output
• Also serving for D/A output
DA output
CMOS
Standby control
L
Open-drain control signal
Standby control
14
• CMOS level output
• Hysteresis input
• Open-drain control provided
MB90230 Series
■ HANDLING DEVICES
1. Preventing Latchup
Latchup may occur on CMOS ICs if voltage higher than VCC or lower than VSS is applied to input and output pins
other than medium- to high-voltage pins or if higher than the voltage wihich shows on “1. Absolute Maximum
Ratings” in section “■ Electrical Characteristics” is applied between VCC and VSS.
When latchup occurs, power supply current increases rapidly and might thermally damage elements. When
using, take great care not to exceed the absolute maximum ratings.
Also, take care to prevent the analog power supply (AVCC and AVR) and analog input from exceeding the digital
power supply (VCC) when the analog system power supply is turned on and off.
2. Treatment of Unused Pins
Leaving unused input pins open could cause malfunctions. They should be connected to a pull-up or pull-down
resistor.
3. External Reset Input
To reset the internal circuit by the Low-level input to the RST pin, the Low-level input to the RST pin must be
maintained for at least five machine cycles. Pay attention to it if the chip uses external clock input.
4. VCC and VSS Pins
Apply equal potential to the VCC and VSS pins.
5. Notes on Using an External Clock
When using an external clock, drive the X0 pin as illustrated below:
Use of External Clock
X0
MB90234
X1
6. Power-on Sequence for A/D Converter Power Supplies and Analog Inputs
Be sure to turn on the digital power supply (VCC) before applying voltage to the A/D converter power supplies
(AVCC, AVRH, and AVRL) and analog inputs (AN0 to AN15).
When turning power supplies off, turn off the A/D converter power supplies (AVCC, AVRH, and AVRL) and analog
inputs (AN0 to AN15) first, then the digital power supply (AVCC).
When turning AVRH on or off, be careful not to let it exceed AVCC.
7. Pin set when turning on power supplies
When turning on power supplies, set the hardware standby input pin (HST) to “H”.
15
MB90230 Series
8. Program Mode
When shipped from Fujitsu, and after each erasure, all bits (96K × 8 bits) in the MB90W234 and MB90P234 are
in the “1” state. Data is introduced by selectively programming “0’s” into the desired bit locations. Bits cannot
be set to 1 electrically.
9. Erasure Procedure
Data written in the MB90W234 is erased (from 0 to 1) by exposing the chip to ultraviolet rays with a wavelength
of 2,537Å through the translucent cover.
Recommended irradiation dosage for exposure is 10 Wsec/cm2. This amount is reached in 15 to 20 minutes
with a commercial ultraviolet lamp positioned 2 to 3 cm above the package (when the package surface
illuminance is 1200 µW/cm2).
If the ultraviolet lamp has a filter, remove the filter before exposure. Attaching a mirrored plate to the lamp
increases the illuminance by a factor of 1.4 to 1.8, thus shortening the required erasure time. If the translucent
part of the package is stained with oil or adhesive, transmission of ultraviolet rays is degraded, resulting in a
longer erasure time. In that case, clean the translucent part using alcohol (or other solvent not affecting the
package).
The above recommended dosage is a value which takes the guard band into consideration and is a multiple of
the time in which all bits can be evaluated to have been erased. Observe the recommended dosage for erasure;
the purpose of the guard band is to ensure erasure in all temperature and supply voltage ranges. In addition,
check the lifespan of the lamp and control the illuminance appropriately.
Data in the MB90W234 is erased by exposure to light with a wavelength of 4000Å or less.
Data in the device is also erased even by exposure to fluorescent lamp light or sunlight although the exposure
results in a much lower erasure rate than exposure to 2537Å ultraviolet rays. Note that exposure to such lights
for an extended period will therefore affect system reliability. If the chip is used where it is exposed to any light
with a wavelength of 4000Å or less, cover the translucent part, for example, with a protective seal to prevent
the chip from being exposed to the light.
Exposure to light with a wavelength of 4,000 to 5,000Å or more will not erase data in the device. If the light
applied to the chip has a very high illuminance, however, the device may cause malfunction in the circuit for
reasons of general semiconductor characteristics. Although the circuit will recover normal operation when
exposure is stopped, the device requires proper countermeasures for use in a place exposed continuously to
such light even though the wavelength is 4,000Å or more.
16
MB90230 Series
10. Recommended Screening Conditions
High-temperature aging is recommended for screening before packaging.
Program, verify
Aging
+150°C, 48 Hrs.
Data verification
Assembly
11. Write Yield
OTPROM products cannot be write-tested for all bits due to their nature. Therefore the write yield cannot always
be guaranteed to be 100%.
17
MB90230 Series
■ BLOCK DIAGRAM
X0, X1
RST
HST
4
CPU
F2MC-16F
Clock controller
Interrupt controller
RAM
ROM
CKOT
INT0
to
4 INT3
UART
Communication prescaler
PWM0
to
PWM5
8-bit PWM
F2MC-16 bus
SIN0
SOT0
SCK0
External interrupt
6 ch
TRG
PPG
8-bit PPG timer
SIN1, 2
SOT1, 2
SCK1, 2
AVcc
AVRH, AVRL
AVss
ATG
AN0 to AN7
DA0
DA1
I/O timer
Extended serial
I/O interface
16-bit free run timer
OUT0, 1
OUT2, 3
OUT4, 5
16-bit output compare × 6
2
10-bit A/D converter
Serial E2PROM interface
D/A converter
Level comparator
I/O ports (84 lines)
8
8
8
8
8
8
8
7
8
7
6
P00
to
P07
P10
to
P17
P20
to
P27
P30
to
P37
P40
to
P47
P50
to
P57
P60
to
P67
P70
to
P76
P80
to
P87
P90
to
P96
PA0
to
PA5
P00 to P27 (24 lines): Provided with input pull-up resistor setting registers
P94 to P96, PA0 to PA5 (9 lines): Provided with open-drain setting registers
18
IN0, 1
IN2, 3
16-bit input capture × 4
ECS, ESK
EDO
EDI
CMP
MB90230 Series
■ MEMORY MAP
FFFFFFH
Single-chip mode
Internal ROM and
external bus
ROM area
ROM area
ROM area
(FF bank image)
ROM area
(FF bank image)
External ROM and
external bus
Address1#
00FFFFH
Address#2
Address#3
RAM
Registers
RAM
Registers
RAM
Registers
000100H
0000C0H
Peripherals
000000H
Peripherals
Internal
External
Peripherals
Inhibited area
Note: 000000H to 000005H and 000010H to 000015H are allocated for external use
when the external bus is enabled.
Product type
MB90233
Address#1
FF4000H
Address#2
004000H
Address#3
000900H
MB90234
MB90P234
MB90W234
FE8000H
FE8000H
004000H
004000H
000D00H
000D00H
MB90V230
(FE0000H)
(004000H)
(001100H)
The MB90230 series can access the 00 bank to read ROM data written to the upper 48-KB locations in the FF
bank. An advantage of reading written to data addresses FFFFFFH-FF4000H from addresses 00FFFFH-004000H is
that you can use the small model of a C compiler.
Note, however, that the products with more than 48KB ROM space (MB90V230, MB90P/W234, MB90234) cannot
read data in addresses other than FFFFFFH to FF4000H from the 00 bank.
19
MB90230 Series
■ I/O MAP
Address
Register
Register
name
Access
Resouce
name
Initial value
00H
Port 0 data register
PDR0
R/W
Port 0
XXXXXXXX
01H
Port 1 data register
PDR1
R/W
Port 1
XXXXXXXX
02H
Port 2 data register
PDR2
R/W
Port 2
XXXXXXXX
03H
Port 3 data register
PDR3
R/W
Port 3
XXXXXXXX
04H
Port 4 data register
PDR4
R/W
Port 4
XXXXXXXX
05H
Port 5 data register
PDR5
R/W
Port 5
XXXXXXXX
06H
Port 6 data register
PDR6
R/W
Port 6
XXXXXXXX
07H
Port 7 data register
PDR7
R/W
Port 7
– XXXXXXX
08H
Port 8 data register
PDR8
R/W
Port 8
XXXXXXXX
09H
Port 9 data register
PDR9
R/W
Port 9
– XXXXXXX
0AH
Port A data register
PDRA
R/W
Port A
– – XXXXXX
10H
Port 0 direction register
DDR0
R/W
Port 0
00000000
11H
Port 1 direction register
DDR1
R/W
Port 1
00000000
12H
Port 2 direction register
DDR2
R/W
Port 2
00000000
13H
Port 3 direction register
DDR3
R/W
Port 3
00000000
14H
Port 4 direction register
DDR4
R/W
Port 4
00000000
15H
Port 5 direction register
DDR5
R/W
Port 5
00000000
16H
Port 6 direction register
DDR6
R/W
Port 6
00000000
17H
Port 7 direction register
DDR7
R/W
Port 7
–0000000
18H
Port 8 direction register
DDR8
R/W
Port 8
00000000
19H
Port 9 direction register
DDR9
R/W
Port 9
–0000000
1AH
Port A direction register
DDRA
R/W
Port A
––000000
1BH
Port 0 resistor register
RDR0
R/W
Port 0
00000000
1CH
Port 1 resistor register
RDR1
R/W
Port 1
00000000
1DH
Port 2 resistor register
RDR2
R/W
Port 2
00000000
1EH
Port 9 pin register
ODR9
R/W
Port 9
–000––––
1FH
Port A pin register
ODRA
R/W
Port A
––000000
20H
Mode control register
UMC
R/W
UART
00000100
21H
Status register
USR
R/W
22H
Serial input register
/Serial output register
UIDR
/UODR
R/W
23H
Rate and data register
URD
R/W
24H
Serial mode control status register
SMCS
R/W
25H
00010000
XXXXXXXX
0000––00
Extended serial
I/O interface
–––00000
00000010
(Continued)
20
MB90230 Series
Address
Register
Register
name
Access
Resouce
name
Initial value
SDR
R/W
Extended serial
I/O interface
XXXXXXXX
—
—
—
—
26H
Serial data register
27H
Reserved area
28H
Cycle setting register
PCSR
W
29H
Duty factor setting register
PDUT
W
2AH
Control status register
PCNTL
R/W
2BH
8-bit
PPG timer
Reserved area
2DH
XXXXXXXX
00000000
PCNTH
2CH
XXXXXXXX
0000000–
—
—
Communication prescaler
CDCR
R/W
UART, CKOT,
I/O, serial IF
0–––1111
2EH
Clock control register
CLKR
R/W
CKOT output
–––––000
2FH
Level comparator
LVLC
R/W
Level
comparator
XXXX0 0 0 0
30H
Interrupt/DTP enable register
ENIR
R/W
––––0000
31H
Interrupt/DTP factor register
EIRR
R/W
DTP/external
interrupt
32H
Request level setting register
ELVR
R/W
33H
Reserved area
—
—
34H
Analog input enable register
ADER
R/W
35H
Reserved area
—
—
36H
Control status data register
ADCS0
R/W
Data register
39H
ADCR0
—
––––0000
00000000
—
10-bit A/D
converter
—
11111111
—
00000000
ADCS1
37H
38H
—
00000000
R
XXXXXXXX
ADCR1
0 0 0 0 0 0 XX
3AH
Reserved area
—
—
—
—
3BH
Reserved area
—
—
—
—
3CH
D/A converter data register 0
DAT0
R/W
3DH
D/A converter data register 1
DAT1
R/W
3EH
D/A control register
DACR
R/W
3FH
Reserved area
—
—
40H
PWM data register 0
PWD0
R/W
41H
PWM data register 1
PWD1
R/W
42H
Control status data register 0, 1
PWC01
R/W
43H
Reserved area
—
—
44H
PWM data register 2
PWD2
R/W
45H
PWM data register 3
PWD3
R/W
46H
Control status register 2, 3
PWC23
R/W
8-bit D/A
converter
XXXXXXXX
00000000
––––––00
—
8-bit
PWM0, 1
—
00000000
00000000
00000000
—
8-bit
PWM2, 3
—
00000000
00000000
00000000
(Continued)
21
MB90230 Series
Address
Register
Register
name
Access
Resouce
name
Initial value
—
—
—
—
47H
Reserved area
48H
PWM data register 4
PWD4
R/W
49H
PWM data register 5
PWD5
R/W
4AH
Control status register 4, 5
PWC45
R/W
4BH
Reserved area
—
—
4CH
Data register
TCDT
R
4DH
4EH
Control status register
4FH
Reserved area
50H
Compare register 0
Compare register 1
00000000
00000000
—
16-bit free
run timer
—
00000000
00000000
R/W
—
—
—
—
OCP0
R/W
Output
compare 0, 1
XXXXXXXX
OCP1
00000000
R/W
XXXXXXXX
XXXXXXXX
XXXXXXXX
53H
54H
00000000
TCCS
51H
52H
8-bit
PWM4, 5
Control status register 0, 1
55H
CS00
R/W
0000––00
CS01
–––00000
56H
Reserved area
—
—
—
—
57H
Reserved area
—
—
—
—
58H
Compare register 2
OCP2
R/W
Output
compare 2, 3
XXXXXXXX
59H
5AH
Compare register 3
OCP3
R/W
XXXXXXXX
5BH
5CH
XXXXXXXX
XXXXXXXX
Control status register 2, 3
CS10
R/W
0000––00
CS11
5DH
–––00000
5EH
Reserved area
—
—
—
—
5FH
Reserved area
—
—
—
—
60H
Compare register 4
OCP4
R/W
Output
compare 4, 5
XXXXXXXX
61H
62H
Compare register 5
OCP5
63H
64H
65H
Control status register 4, 5
66H
Reserved area
67H to
6FH
Reserved area
CS20
CS21
XXXXXXXX
XXXXXXXX
R/W
XXXXXXXX
0000––00
R/W
–––00000
—
—
—
—
—
—
—
—
(Continued)
22
MB90230 Series
Address
70H
Register
Capture register 0
Register
name
Access
ICP0
R/W
71H
72H
Capture register 1
ICP1
Resouce
name
Input capture 0,
1
R/W
XXXXXXXX
XXXXXXXX
74H
Control status register 0, 1
75H to
77H
Reserved area
78H
Capture register 2
ICS0
R/W
—
—
ICP2
R/W
79H
Capture register 3
ICP3
00000000
—
Input capture 2,
3
R/W
—
XXXXXXXX
XXXXXXXX
XXXXXXXX
7BH
XXXXXXXX
7CH
Control status register 2, 3
7DH to
7FH
Reserved area
80H
ICS1
R/W
—
—
OP code register
EOPC
R/W
81H
Format status register
ECTS
R/W
82H
Data register
EDAT
R/W
00000000
—
Serial E2PROM
interface
—
––––0000
00000000
XXXXXXXX
83H
84H
XXXXXXXX
XXXXXXXX
73H
7AH
Initial value
XXXXXXXX
Address register
EADR
R/W
00000000
00–––000
85H
86H to
8FH
Reserved area
—
—
—
—
90H to
9EH
System reserved area
—
*1
—
—
9FH
Delayed interrupt source generate/
release register
DIRR
R/W
Delayed interrupt
generation module
–––––––0
A0H
Standby control register
STBYC
R/W
Low-power
consumption
mode
0 0 0 1 XXXX
A1H
Reserved area
—
—
—
—
A2H
Reserved area
—
—
—
—
A3H
Middle address control register
MACR
W
External pin
*2
A4H
Upper address control register
HACR
W
External pin
*2
A5H
External pin control register
EPCR
W
External pin
*2
A6H
Reserved area
—
—
—
—
A7H
Reserved area
—
—
—
—
A8H
Watchdog timer control register
TWC
R/W
Watchdog timer/
reset
XXXXXXXX
(Continued)
23
MB90230 Series
Address
Register
Register
name
Access
TBTC
R/W
—
—
Resouce
name
Initial value
A9H
Timebase timer control register
AAH to
AFH
Reserved area
B0H
Interrupt control register 00
ICR00
R/W
B1H
Interrupt control register 01
ICR01
R/W
B2H
Interrupt control register 02
ICR02
R/W
00000111
B3H
Interrupt control register 03
ICR03
R/W
00000111
B4H
Interrupt control register 04
ICR04
R/W
00000111
B5H
Interrupt control register 05
ICR05
R/W
00000111
B6H
Interrupt control register 06
ICR06
R/W
00000111
B7H
Interrupt control register 07
ICR07
R/W
00000111
B8H
Interrupt control register 08
ICR08
R/W
00000111
B9H
Interrupt control register 09
ICR09
R/W
00000111
BAH
Interrupt control register 10
ICR10
R/W
00000111
BBH
Interrupt control register 11
ICR11
R/W
00000111
BCH
Interrupt control register 12
ICR12
R/W
00000111
BDH
Interrupt control register 13
ICR13
R/W
00000111
BEH
Interrupt control register 14
ICR14
R/W
00000111
BFH
Interrupt control register 15
ICR15
R/W
00000111
C0H to
FFH
External area
—
—
Timebase
timer
—
Interrupt
controller
—
–––00000
—
00000111
00000111
*3
Initial values
0: The initial value for the bit is “0.”
1: The initial value for the bit is “1.”
X: The initial value for the bit is undefined.
–: The bit is not used; the initial value is undefined.
*1: Access inhibited
*2: The initial value depends on each bus mode.
*3: Only this area can be used as the external access area in the area that follows address 0000FFH. Access to
any address in reserved areas specified in the I/O map table is handled as access to an internal area. An
access signal to the external bus is not generated.
24
MB90230 Series
■ INTERRUPT VECTORS AND INTERRUPT CONTROL REGISTERS FOR INTERRUPT
SOURCES
Interrupt source
Interrupt vector
I2OS
support
No.
Address
Interrupt control
register
ICR
Address
Reset
×
#08
08H
FFFFDCH
—
—
INT9 instruction
×
#09
09H
FFFFD8H
—
—
Exceptional
×
#10
0AH
FFFFD4H
—
—
External interrupt (INT0) 0 ch
#11
0BH
FFFFD0H
ICR00
0000B0H
External interrupt (INT1) 1 ch
#12
0CH
FFFFCCH
External interrupt (INT2) 2 ch
#13
0DH
FFFFC8H
ICR01
0000B1H
External interrupt (INT3) 3 ch
#14
0EH
FFFFC4H
Extended serial I/O interface
#15
0FH
FFFFC0H
ICR02
0000B2H
Serial E2PROM interface
#17
11H
FFFFB8H
ICR03
0000B3H
Input capture channel 0
#19
13H
FFFFB0H
ICR04
0000B4H
Input capture channel 1
#21
15H
FFFFA8H
ICR05
0000B5H
Input capture channel 2
#23
17H
FFFFA0H
ICR06
0000B6H
Input capture channel 3
#24
18H
FFFF9CH
Output compare channel 0
#25
19H
FFFF98H
ICR07
0000B7H
Output compare channel 1
#26
1AH
FFFF94H
Output compare channel 2
#27
1BH
FFFF90H
ICR08
0000B8H
Output compare channel 3
#28
1CH
FFFF8CH
Output compare channel 4
#29
1DH
FFFF88H
ICR09
0000B9H
Output compare channel 5
#30
1EH
FFFF84H
16-bit free run timer overflow
#31
1FH
FFFF80H
ICR10
0000BAH
Timebase timer overflow
#32
20H
FFFF7CH
8-bit PPG timer
#33
21H
FFFF78H
ICR11
0000BBH
Level comparator
#34
22H
FFFF74H
UART reception
#35
23H
FFFF70H
ICR12
0000BCH
UART transmission
#37
25H
FFFF68H
ICR13
0000BDH
End of A/D conversion
#39
27H
FFFF60H
ICR14
0000BEH
Delayed interrupt
×
#42
2AH
FFFF54H
ICR15
0000BFH
Stack fault
×
#256
FFH
FFFC00H
—
—
: The request flag is cleared by the EI2OS interrupt clear signal.
: The request flag is cleared by the EI2OS interrupt clear signal. The stop request is available.
: The request flag is not cleared by the EI2OS interrupt clear signal.
25
MB90230 Series
■ PERIPHERAL RESOURCES
1. I/O Ports
Each pin in each port can be specified for input or output by setting the direction register when the corresponding
peripheral resource is not set to use that pin. When the data register is read, the value depending on the pin
level is read whenever the pin serves for input. When the data register is read with the pin serving for output,
the latch value of the data register is read. This also applies to read operation by the read modify write instruction.
• General-purpose I/O port
Internal data bus
Data register read
Data register
Pin
Data register write
Direction register
Direction register write
Direction register read
• Port with pull-up resistor setting register
Pull-up resistor (Approx. 50 kΩ)
Internal data bus
Data register
Direction register read
Resistor register
26
Port input/output
MB90230 Series
• Port with open-drain setting register
Internal data bus
Data register
Port input/output
Direction register
Pin register
27
MB90230 Series
(1) Register Configuration
bit
14/6
13/5
12/4
11/3
10/2
9/1
8/0
Address: 000000H
P07
P06
P05
P04
P03
P02
P01
P00
Address: 000001H
P17
P16
P15
P14
P13
P12
P11
P10
Address: 000002H
Address: 000003H
P27
P37
P47
P57
P67
P25
P35
P45
P24
P34
P44
P23
P33
P43
P22
P32
P42
P21
P31
P41
P20
P30
Address: 000004H
Address: 000005H
P26
P36
P46
P56
P66
P55
P65
P54
P64
P53
P63
P52
P62
P51
P61
P40
P50
P60
P87
P76
P86
P75
P85
P74
P84
P73
P83
P72
P82
P71
P81
P70
P80
—
—
P96
—
P95
PA5
P94
PA4
P93
PA3
P92
PA2
P91
PA1
PA0
15/7
14/6
13/5
12/4
11/3
10/2
9/1
8/0
Address: 000006H
Address: 000007H
Address: 000008H
Address: 000009H
Address: 00000AH
bit
—
P90
Address: 000010H
P07
P06
P05
P04
P03
P02
P01
P00
Address: 000011H
P17
P16
P15
P14
P13
P12
P11
P10
Address: 000012H
Address: 000013H
P27
P37
P26
P36
P25
P35
P24
P34
P23
P33
P22
P32
P21
P31
P20
P30
Address: 000014H
Address: 000015H
P47
P57
P46
P56
P45
P55
P44
P54
P43
P53
P42
P52
P41
P51
P40
P50
Address: 000016H
Address: 000017H
P67
—
P66
P76
P65
P75
P64
P74
P63
P73
P62
P72
P61
P71
P60
P70
Address: 000018H
Address: 000019H
P87
—
—
P86
P96
P85
P95
P84
P94
P83
P93
P82
P92
P81
P91
—
PA5
PA4
PA3
PA2
PA1
P80
P90
PA0
15
14
13
12
11
10
9
8
Address: 00001AH
bit
Address: 000034H
ADE7 ADE6 ADE5 ADE4 ADE3 ADE2 ADE1 ADE0
Port 0 data register (PDR0)
Port 1 data register (PDR1)
Port 2 data register (PDR2)
Port 3 data register (PDR3)
Port 4 data register (PDR4)
Port 5 data register (PDR5)
Port 6 data register (PDR6)
Port 7 data register (PDR7)
Port 8 data register (PDR8)
Port 9 data register (PDR9)
Port A data register (PDRA)
Port 0 direction register (DDR0)
Port 1 direction register (DDR1)
Port 2 direction register (DDR2)
Port 3 direction register (DDR3)
Port 4 direction register (DDR4)
Port 5 direction register (DDR5)
Port 6 direction register (DDR6)
Port 7 direction register (DDR7)
Port 8 direction register (DDR8)
Port 9 direction register (DDR9)
Port A direction register (DDRA)
Analog input enable register (ADER)
15/7
14/6
13/5
12/4
11/3
10/2
9/1
8/0
Address: 00001BH
P07
P06
P05
P04
P03
P02
P01
P00
Port 0 resistor register (RDR0)
Address: 00001CH
Address: 00001DH
P17
P27
P16
P26
P15
P25
P14
P24
P13
P23
P12
P22
P11
P21
P10
P20
Port 1 resistor register (RDR1)
Port 2 resistor register (RDR2)
15/7
14/6
13/5
12/4
11/3
10/2
9/1
8/0
Address: 00001EH
—
P96
P95
P94
—
—
—
—
Address: 00001FH
—
—
PA5
PA4
PA3
PA2
PA1
PA0
bit
bit
28
15/7
Port 9 pin register (ODR9)
Port A pin register (ODRA)
MB90230 Series
Ports 0 to 5 in the MB90230 series share the external bus and pins. Each pin function is selected depending on
the bus mode and register settings.
Function
Pin name
Single-chip mode
External bus extended mode
8 bits
P07 to P00
16 bits
D07 to D00
P17 to P10
Port
EPROM write
D07 to D00
D15 to D08
D15 to D08
P27 to P20
A07 to A00
A07 to A00
P37 to P30
A15 to A08*1
A15 to A08
A23 to A16*1
A23 to A16
P47 to P45
P44
P43 to P40
P50
CLK*2
Port
P51
RDY*2
P52
HAK*2
P53
HRQ*2
Not used
P54
Port
WRH*2
CE
P55
WR
WRL*2
OE
P56
RD
PGM
P57
Port
“0”
*1: The pin can be used as an I/O port by setting the upper and middle address control registers.
*2: The pin can be used as an I/O port by setting the external pin control register.
29
MB90230 Series
2. 8-bit PWM (with 6 channels in this series)
The PWM module consists of a pair of 8-bit PWM output circuits. The MB90230 series incorporates a set of
three PWM modules. They can output a waveform continuously from the port at an arbitrary duty factor according
to the register settings.
•
•
•
•
8-bit down counter
8-bit data registers
Compare circuit
Control registers
(1) Register Configuration
bit
15
000041, 40H
000045, 44H
000049, 48H
8 7
PWDx
0
7
000042H
000046H
00004AH
PWM data registers 0 to 5
PWDx
0
PWCxx
Control registers 0 to 5
(2) Block Diagram
8-bit down counter
Bus
Comparator, PWM output section
8-bit data registers
Control registers
30
PWM output
MB90230 Series
3. UART
The UART is a serial I/O port for synchronous or asynchronous communication with external resources. It has
the following features:
•
•
•
•
•
•
•
•
•
Full-duplex double buffering
Data transfer synchronous or asynchronous with clock pulses
Multiprocessor mode support (Mode 2)
Internal dedicated baud-rate generator
Arbitrary baud-rate setting from external clock input or internal timer
Variable data length (7 to 9 bits (without parity bit); 6 to 8 bits (with parity bit))
Error detection function (Framing, overrun, parity)
Interrupt function (Two sources for transmission and reception)
Transfer in NRZ format
(1) Register Configuration
8
15
bit
Address: 000020H
bit
Address: 000021H
bit
Address: 000022H
bit
Address: 000023H
bit
Address: 00002DH
7
0
USR
UMC
(R/W)
URD
UIDR (R)/UODR (W)
(R/W)
8 bits
8 bits
7
6
5
4
3
2
1
0
PEN
SBL
MC1
MC0
SMDE
RFC
SCKE
SOE
15
14
13
12
11
10
9
8
PE
TDRE
RIE
TIE
RBF
TBF
RDRF ORFE
7
6
5
4
3
2
1
0
D7
D6
D5
D4
D3
D2
D1
D0
15
14
13
12
11
10
9
8
—
RC2
RC1
RC0
—
—
P
D8
15
14
13
12
11
10
9
8
MD
—
—
—
DIV3
DIV2
DIV1
DIV0
Mode control register
(UMC)
Status register
(USR)
Serial input data register
Serial output data register
(UIDR/UODR)
Rate and data register
(URD)
Communication prescaler
(CDCR)
31
MB90230 Series
(2) Block Diagram
CONTROL BUS
Reception interrupt
(To CPU)
Dedicated baud-rate clock
SCK0
Transmission interrupt
(To CPU)
Transmitting clock
Internal timer
Clock selector
circuit
Receiving clock
External clock
Reception control circuit
Transmission control circuit
Start bit detector
Transmission start circuit
Received bit counter
Transmission bit counter
Received parity counter
Transmission parity counter
SIN0
SOT0
Reception status
detection circuit
Reception shifter
Transmission shifter
End of reception
Start of transmission
UODR
UIDR
Reception error
occurrence signal for EI2OS
(To CPU)
Data bus
UMC
register
PEN
SBL
MC1
MC0
SMDE
RFC
SCKE
SOE
USR
register
RDRF
ORFE
PE
TDRE
RIE
TIE
RBF
TBF
URD
register
BCH
RC2
RC1
RC0
P
D8
CONTROL BUS
32
MB90230 Series
4. Extended Serial I/O Interface
This block is a serial I/O interface implemented on a single 8-bit channel that can transfer data in synchronization
with clock pulses. It allows the “LSB first” or “MSB first” option to be selected for data transfer. The serial I/O
port to be used can also be selected.
There are two serial I/O operation modes available:
• Internal shift clock mode: Transfers data in synchronization with internal clock pulses.
• External shift clock mode: Transfers data in synchronization with clock pulses entered from an external pin
(SCKx). In this mode, data can be transferred by instructions from the CPU by
operating the general-purpose port that shares the external pin (SCKx).
(1) Register Configuration
15
bit
Address: 000025H
14
SMD2 SMD1
bit
Address: 000024H
bit
Address: 000026H
13
12
11
10
9
8
SMD0
SIE
SIR
BUSY
STOP
STRT
4
3
2
1
0
BDS
SOE
SCOE
7
6
5
—
—
—
7
6
5
4
3
2
1
0
D7
D6
D5
D4
D3
D2
D1
D0
OUTC MODE
Serial mode control status
register (SMCS)
Serial data register
(SDR)
(2) Block Diagram
Internal data bus
(MSB first) D0 to D7
D7 to D0 (LSB first)
Selecting transfer direction
SIN1, 2
Read
Write
SDR (Serial data register)
SOT1, 2
SCK1, 2
Shift clock counter
Control circuit
Internal clock
2
1
0
SMD2 SMD1 SMD0
SIE
SIR
BUSY STOP STRT MODE BDS
SOE SCOE
Interrupt
request
Internal data bus
33
MB90230 Series
5. A/D Converter
The A/D converter converts the analog input voltage to a digital value. It has the following features:
Conversion time: 5 µs min. per channel (at 16 MHz machine clock)
RC-type successive approximation with sample-and-hold circuit
8-bit or 10-bit resolution
Eight analog input channels programmable for selection
A/D conversion mode selectable from the following three:
One-shot conversion mode: Converts a specified channel once.
Consecutive conversion mode: Converts a specified channel repeatedly.
Stop conversion mode: Converts one channel and suspends its own operation until the next activation (allowing
synchronized conversion start).
• Conversion mode:
Single conversion mode: Converts one channel (when the start and stop channels are the same).
Scan conversion mode: Converts multiple consecutive channels (when the start and stop channels are
different).
• On completion of A/D conversion, the converter can generate an interrupt request for termination of A/D
conversion to the CPU. This interrupt generation can activate the EI2OS to transfer the A/D conversion result
to memory, making the converter suitable for continuous operation.
• Conversion can be activated by software, external trigger (falling edge), and/or timer (rising edge) as selected.
•
•
•
•
•
(1) Register Configuration
bit
7
0
000037, 36H
ADCS1
ADCS0
Control status register
000039, 38H
ADCR1
ADCR0
Data register
000034H
34
8
15
ADER
Analog input enable register
MB90230 Series
(2) Block Diagram
AVCC
AVRH,
AVRL
AVSS
D/A converter
MPX
Input circuit
Successive
approximation register
Comparator
Data bus
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
Sample-and-hold circuit
Decoder
Data register
ADCR1, 0
A/D control register 0
A/D control register 1
ADCS1, 0
ATG
Activation trigger
Activation by timer
Timer
Interlocked with PPG timer
φ
Operation clock
Prescaler
35
MB90230 Series
6. 16-bit I/O Timer
The 16-bit I/O timer consists of 16-bit free run timer, 6-line output compare, and 4-line input capture modules.
The 16-bit I/O timer can output six independent waveforms based on the 16-bit free run timer, allowing the input
pulse width and external clock cycle to be measured.
(1) Outline of Functions
16-bit free run timer (× 1)
The 16-bit free run timer consists of a 16-bit up-count timer, a control register, and a prescaler. The value output
from this timer/counter is used as the base time by the input capture and output compare modules.
• The counter operation clock cycle can be selected from the following four:
Four internal clock cycles (φ/4, φ/16, φ/32, φ/64)
• The interrupt counter value can be generated by compare/match operation with the overflow register and
compare register 0 (compare/match operation requires the mode setting).
• The counter value can be initialized to “0000H” by compare/match operation with the reset register, software
clear register, and compare register 0.
Output compare module (× 6)
The output compare module consists of six 16-bit compare registers, compare output latches, and control
registers. When the compare value matches the 16-bit free run timer value, this module can generates an
interrupt while inverting the output level.
• Six compare registers can operate independently, and have each output pin and interrupt flag.
• Two compare resisters can be used to control the same output pin.
• The initial value for each output pin can be set.
• The interrupt can be generated by compare/match operation.
Input capture module (× 4)
The input capture module consists of four external input pins and associated capture and control registers. This
module can detect an arbitrary edge of the signal input from each external input pin to generate an interrupt
while holding the 16-bit free run timer value in the capture register.
• The external input signal edge can be selected from the rising edge, failing edge or both edges.
• Four input capture lines can operate independently.
• The interrupts can be generated by a valid edge of external input signals. The extended intelligent I/O service
(EI2OS) can be activated.
36
MB90230 Series
(2) Register Configuration
• 16-bit free run timer
bit
0
15
00004CH
Timer data register
TCDT
Control status register
TCCS
00004EH
• 16-bit output compare module
bit
000050, 52, 58, 5AH
000060, 62H
0
15
Compare register 0 to 5
OCP0 to 5
000054, 55H
00005C, 5DH
000064, 65H
CS × 1
CS × 0
Control status register 0 to 5
• 16-bit input capture module
bit
000070, 72, 78, 7AH
000074, 7CH
0
15
Compare register 0 to 3
IPCP0 to 3
ICS0 to 3
Control status register 0 to 3
37
MB90230 Series
(3) Block Diagram
To each block
Control logic
16-bit free run timer
16-bit timer
Clear
Bus
Output compare 0
Compare register 0
TQ
OUT 0
Compare register 1
TQ
OUT 1
Compare register 2
TQ
OUT 2
Compare register 3
TQ
OUT 3
Compare register 4
TQ
OUT 4
Compare register 5
TQ
OUT 5
Output compare 1
Output compare 2
Input capture 0
Capture register 0
Edge selection
IN 0
Capture register 1
Edge selection
IN 1
Capture register 2
Edge selection
IN 2
Capture register 3
Edge selection
IN 3
Input capture 1
Interrupt
10
38
MB90230 Series
7. PPG Timer (Programmable Pulse Generator)
This module can output the pulse synchronized with an external or software trigger. The cycle and duty factor
of the output pulse can be changed arbitrarily by changing the values in two 8-bit registers.
PWM function: Outputs a pulse in programmable mode while changing the values in the two registers in
synchronization with the input trigger.
This module can also be used as a D/A converter using an external circuit.
Single-shot function: Detects the trigger input edge to output a single pulse.
(1) Module Configuration
This module consists of an 8-bit down counter, prescaler, 8-bit cycle setting register, 8-bit duty factor setting
register, 16-bit control register, external trigger input pin, and PPG output pin.
(2) Register Configuration
bit
8
15
Address: 000028H
7
0
PCSR
000029H
PDUT
00002BH, 2AH
PCNTH
Cycle setting register
Duty factor setting register
PCNTL
Control status register
39
MB90230 Series
(3) Block Diagram
PCSR
PDUT
Prescaler
1/φ
4/φ
cmp
ck
Load
16 / φ
8-bit
64 / φ
down counter
Start
Borrow
PPG mask
S
Q
PPG output
R
Enable
TRG input
Edge detection
Software trigger
40
Interrupt selection
Inverted bit
IRQ
MB90230 Series
8. Serial E2PROM Interface
This module is the interface circuit dedicated to external bit-serial E2PROM.
(1) Features
•
•
•
•
•
•
Instruction code support (compatible with the MB8557).
Selectable address length: 8 to 11 bits
Selectable data length: 8 or 16 bits
Automatic address increment function
Transmit/receive data transfer enabled by EI2OS
Up to 2048-by-16 bit access enabled (at an address length of 11 bits and a data length of 16 bits)
(2) Register Configuration
bit
8
15
7
0
Status format register
Data register
Address register
bit
Address: 000081H
bit
Address: 000080H
bit
Address: 000083H
bit
Address: 000082H
bit
Address: 000085H
bit
Address: 000084H
15
14
13
12
11
10
9
8
IFEN
INT
INTE
BUSY
ADL1
ADL0
DTL
CON
7
6
5
4
3
2
1
0
—
—
—
—
OP3
OP2
OP1
OP0
15
14
13
12
11
10
9
8
D15
D14
D13
D12
D11
D10
D9
D8
7
6
5
4
3
2
1
0
D7
D6
D5
D4
D3
D2
D1
D0
15
14
13
12
11
10
9
8
CLK
FRQ
—
—
—
A10
A9
A8
7
6
5
4
3
2
1
0
A7
A6
A5
A4
A3
A2
A1
A0
Format status register
(ECTS)
Op code register
(EOPC)
Data register
(EDAT)
Data register
(EDAT)
Address register
(EADR)
Address register
(EADR)
41
MB90230 Series
(3) Block Diagram
Op code register
Bus
Address register
EDI
Data register
Data register
EDO
Format register
ECS
Status register
Operation clock
φ
Machine cycle
42
Prescaler
ESK
MB90230 Series
9. DTP/External Interrupt
The data transfer peripheral (DTP) is located between external peripherals and the F2MC-16F CPU. It receives
a DMA request or interrupt request generated by the external peripherals and reports it to the F2MC-16F CPU
to activate the extended intelligent I/O service or interrupt handler. The user can select two request levels of
“H” and “L” for extended intelligent I/O service (EI2OS) or, four request levels of “H,” “L,” rising edge, and falling
edge for external interrupt requests.
(1) Register Configuration
bit
8
15
Address: 000031H, 30H
EIRR
000032H
7
0
ENIR
Interrupt/DTP enable register
ELVR
Request level setting register
(2) Block Diagram
F2MC-16 bus
4
4
4
8
Interrupt DTP source register
Gate
Source F/F
Edge detection circuit
3
Request input
Interrupt DTP source register
Request level setting register
43
MB90230 Series
10. D/A Converter
This block is an R-2R type D/A converter with 8-bit resolution.
The D/A converter incorporates two channels, each of which can be controlled for output independently by the
D/A control register.
(1) Register Configuration
bit
DAT1
Address: 00003DH
DAT0
Address: 00003CH
DACR
Address: 00003EH
15
14
13
12
11
10
9
8
DA17
DA16
DA15
DA14
DA13
DA12
DA11
DA10
7
6
5
4
3
2
1
0
DA07
DA06
DA05
DA04
DA03
DA02
DA01
DA00
7
6
5
4
3
2
1
0
—
—
—
—
—
—
DAE1
DAE0
D/A converter data register 1
D/A converter data register 2
D/A control register
(2) Block Diagram
F2MC-16 bus
DA DA DA DA DA DA DA DA
17 16 15 14 13 12 11 10
DA DA DA DA DA DA DA DA
07 06 05 04 03 02 01 00
AVCC
AVCC
DA17
DA07
2R
DA16
2R
DA15
R
R
DA11
44
R
2R
R
2R
R
DA05
DA01
2R
DA10
2R
DA06
R
DA00
2R 2R
DAE1
Standby control
2R 2R
DAE0
Standby control
DA output
ch. 1
DA output
ch. 0
MB90230 Series
11. Level Comparator
This module compares the input level (by checking whether it is high or low).
The module consists of a comparator, 4-bit resistor ladder, and control register.
• The external input can be compared to the internal 4-bit resistor ladder.
(1) Register Configuration
bit
0
8
Address: 00002FH
Level comparator
LVLC
(2) Block Diagram
AVRL
RD3
RD2
RD1
RD0
CPLV
INT
INTE
CPEN
Bus
Resistor ladder
4-bit D/A
AVRH
4
Analog input
CMP
S/H
Interrupt
Comparator
45
MB90230 Series
12.Watchdog Timer and Timebase Timer
The watchdog timer consists of a 2-bit watchdog counter using carry signals from an 18-bit timebase counter
as the clock source, a control register, and a watchdog reset control section. The timebase timer consists of
an 18-bit timer and an interval interrupt control circuit.
(1) Register Configuration
bit
8
15
Address: 0000A9H, A8H
7
TBTC
0
WTC
Timebase timer control register
(2) Block Diagram
Oscillation clock
F2MC-16 bus
TBTC
TBC1
Selector
TBC0
TBR
TBIE
AND
Q
Clock input
2 12
2 14
2 16
Timebase timer
2 18
TBTRES
2 14 2 16 2 17 2 18
S
R
TBOF
Timebase
interrupt
WTC
WT1
Selector
WT0
2-bit counter
OF
CLR
Watchdog reset
generator
CLR
WDGRST
To internal reset generator
WTE
PONR
From power-on occurrence
STBR
From hardware standby
control circuit
WRST
46
ERST
RST pin
SRST
From RST bit in STBYC register
MB90230 Series
13. Delay Interruupt Generation Module
The delayed interrupt generation module is used to generate an interrupt for task switching. Using this module
allows an interrupt request to the F2MC-16F CPU to be generated or canceled by software.
(1) Register Configuration
bit
Delayed interrupt source
generate/release register
Address: 00009FH
Read/write →
Initial value →
15
14
13
12
11
10
9
8
—
—
—
—
—
—
—
R0
(—)
(X)
(—)
(X)
(—)
(X)
(—)
(X)
(—)
(X)
(—)
(X)
(—)
(X)
(R/W)
(0)
DIRR
F2MC-16 bus
(2) Block Diagram
Delayed interrupt source generate/release decoder
Interrupt source latch
14. Clock Output Control Register
The clock output control register outputs the output from the communication prescaler to the pin.
(1) Register Configuration
bit
Clock control register
15
14
13
12
11
10
9
8
Address: 00002EH
—
—
—
—
—
CKEN
FRQ1
FRQ0
(—)
(—)
(—)
(—)
(—)
(—)
(—)
(—)
(—)
(—)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
Read/write →
Initial value →
CLKR
47
MB90230 Series
15.Low-power Consumption Control Circuit
The low-power consumption control circuit consists of a low-power consumption control register, clock generator,
standby status control circuit, and gear divider circuit. These internal circuits implements the sleep, stop, and
hardware standby modes as well as the clock gear function. The gear function allows the machine clock cycle
to be selected as a division of the frequency of crystal oscillation or external clock input by 1, 2, 4, or 16.
(1) Register Configuration
bit
8
15
7
0
Address: 0000A0H
STBYC
Standby control register
(2) Block Diagram
Oscillation clock
Gear divider circuit
1/1 1/2
1/4 1/16
CPU clock
generator
STBYC
CPU clock
CLK1
F2MC-16 bus
Selector
CLK0
Resource clock
generator
SLP
Resource clock
Standby control circuit
STP
RST
Clear HST start
HST pin
Interrupt request or RST
OSC1
Selector
OSC0
20
2 16
2 17
2 18
Clock input
Time-base timer
2 14
SPL
Pin high-impedance control circuit
2 16 2 17 2 18
Pin HI-Z
RST pin
Internal reset generator
RST
Internal RST
To watchdog timer
WDGRST
48
MB90230 Series
■ ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
(VSS = 0.0 V)
Value
Symbol
Parameter
Unit
Min.
Max.
VSS – 0.3
VSS + 7.0
V
VCC – 0.3*1
VSS + 7.0
V
VCC
Power supply voltage
AVCC, AVSS
AVRH, AVRL
Input voltage
VI*2
VSS – 0.3
VCC + 0.3
V
Output voltage
VO*2
VSS – 0.3
VCC + 0.3
V
“L” level output current
IOL

20
mA
“L” level average output current
IOLAV
—
4
mA
“L” level total output current
ΣIOL

50
mA
“H” level output current
IOH

–10
mA
“H” level average output current IOHAV
—
–4
mA
“H” level total output current
ΣIOH
—
–50
mA
Power consumption
PD
—
400
mW
Operating temperature
TA
–40
+70
°C
Storage temperature
TSTG
–55
+150
°C
Remarks
*1: AVRH, AVRL, or AVCC must not exceed VCC.
AVSS and AVRH must not exceed AVRH and AVCC, respectively.
VCC ≥ AVCC ≥ AVRH > AVRL ≥ AVSS ≥ VSS
*2: VI or VO must not exceed “VCC + 0.3 V.”
WARNING: Permanent device damage may occur if the above “Absolute Maximum Ratings” are exceeded.
Functional operation should be restricted to the conditions as detailed in the operational sections of
this data sheet. Exposure to absolute maximum rating conditions for externded periods may affect
device reliability.
2. Recommended Operating Conditions
(VSS = 0.0 V)
Parameter
Symbol
Power supply voltage
VCC
Operating temperature
TA
Value
Unit
Remarks
Min.
Max.
4.75
5.25
V
During normal operation
3.0
5.5
V
In stop mode
–40
+70
°C
49
MB90230 Series
3. DC Characteristics
Parameter
Symbol
Pin
name
VIH
*1
VIHS
*2
VIHM
Condition
(VCC = 5.0 V±5%, VSS = 0.0 V, TA = –40°C to +70°C)
Value
Unit
Remarks
Min.
Typ.
Max.
0.7 VCC
—
VCC + 0.3
V
0.8 VCC
—
VCC + 0.3
V
Hysteresis input
*3
VCC – 0.3
—
VCC + 0.3
V
MD0 to 2
VIL
*1
VSS – 0.3
—
0.3 VCC
V
VILS
*2
VSS – 0.3
—
0.2 VCC
V
Hysteresis input
VILM
*3
VSS – 0.3
—
VSS + 0.3
V
MD0 to 2
“H” level output
voltage
VOH
*1, *2
VCC = 4.75 V
IOH = –2.0 mA
—
—
V
“L” level output
voltage
VOL
*1, *2
VCC = 4.75 V
IOL = 1.8 mA
—
—
0.4
V
Input leakage
current
IIH
*1, *2,
*3
VSS + 4.75 V
<VI <VCC
–10
—
10
µA
—
48
80
mA
—
15
25
mA In sleep mode
—
10
—
µA
“H” level input
voltage
“L” level input
voltage
VCC = 5.0 V±5%
VCC = 5.0 V±5%
ICC
Power supply
current
ICCS
VCC
VCC = 5.0 V±5%
fc = 16 MHz
ICCH
2.4
Input capacity
CIN
Other
than VCC
and VSS
Open-drain
output leakage
current
(N-channel Tr
OFF)
ILEAK
*4
—
—
0.1
10
µA
Pull-up current
IPULL
*5
—
–250
—
–50
µA
—
—
10
—
pF
In stop mode
*1: CMOS I/O pin (Other than hysteresis pins)
*2: Hysteresis input pins: P46/TRG, P70/ATG, P71/ESI, P80/INT0, P81/INT1, P82/OUT0/INT2, P83/OUT1/INT3,
P90/IN0, P91/IN1, P92/IN2, P93/IN3/CKOT, P94/SIN0, P96/SCK0, PA0/SIN1,
PA2/SCK1, PA3/SIN2, PA5/SCK2
*3: Mode pins MD2 to MD0
*4: Open-drain pins P94 to P96 and PA0 to PA5: Set by registers
*5: Pins with pull-up resistor RST and P00 to P27: Set by registers
50
MB90230 Series
4. AC Characteristics
(1) Clock Timing Standards
(VCC = +5.0 V±5%, VSS = 0.0 V, TA = –40°C to +70°C)
Value
Condition
Unit
Remarks
Min.
Max.
Symbol
Pin name
Clock frequency
fC
X0
X1
VCC = 5.0 V ±5%
1
16
MHz
Clock cycle time
tC
X0
X1
VCC = 5.0 V ±5%
62.5
—
ns
Input clock pulse width
PWH
PWL
X0
VCC = 5.0 V ±5%
25.0
—
ns
Input clock rising/falling
time
tcr
tcf
X0
—
5
10
ns
Parameter
Duty = 60%
tc
0.8 VCC
0.2 VCC
PWH
PWL
tcf
tcr
51
MB90230 Series
(2) Reset, Hardware Standby, and Trigger Input Standards
Parameter
Reset input time
Pin
Symbol name
(VCC = +5.0 V±5%, VSS = 0.0 V, TA = –40°C to +70°C)
Value
Condition
Unit
Remarks
Min.
Max.
tRSTL
RST
—
5
—
Machine cycle*
Hardware standby input time tHSTL
HST
—
5
—
Machine cycle*
A/D start trigger input time
tATGX
ATG
—
5
—
Machine cycle*
PPG start trigger input time
tPPGL
TRG
—
5
—
Machine cycle*
Input capture input trigger
tINP
IN0 to
IN3
—
5
—
Machine cycle*
*Machine cycle: tCYC = 1/machine clock = 1/(fC ÷ N)
fC: Oscillation frequency
N: Gear divide ratio (1, 2, 4, 16)
Note: Clock input is required during reset.
The machine cycle at hardware standby input is set to 1/32 divided oscillation.
RST
HST
ATG
TRG
IN0 to IN3
52
tRSTL, tHSTL, tINP
tATGX, tPPGT
MB90230 Series
(3) Power-on Reset
Parameter
Power supply riseing time
Power-off time
Symbol
(VCC = +5.0 V ±5%, VSS = 0.0 V, TA = –40°C to +70°C)
Value
Pin name Condition
Unit
Remarks
Min.
Max.
tR
Vcc
tOFF
—
—
50
ms
1
—
ms
tR
Vcc
4.5 V
0.2 V
tOFF
Keep in mind that abrupt changes in supply voltage may cause a power-on reset.
Vcc 5 V
3V
RAM data refined
Vss
It is recommended to keep the
rising speed of the supply voltage
at 50 mV/ms or slower.
53
MB90230 Series
(4) UART Timing
(VCC = +5.0 V±5%, VSS = 0.0 V, TA = –40°C to +70°C)
Pin
name
Symbol
Parameter
Condition
Value
Max.
8 tCYC
—
ns
–80
80
ns
100
—
ns
Serial clock cycle time
tSCYC
—
SCK ↓ → SOT delay time
tSLOV
—
Valid SIN → SCK ↑
tIVSH
—
SCK ↑ → Valid SIN hold time
tSHIX
—
60
—
ns
Serial clock “H” pulse width
tSHSL
—
4 tCYC
—
ns
Serial clock “L” pulse width
tSLSH
—
4 tCYC
—
ns
SCK ↓ → SOT delay time
tSLOV
—
—
150
ns
Valid SIN → SCK ↑
tIVSH
—
60
—
ns
SCK ↑ → Valid SIN hold time
tSHIX
—
60
—
ns
Internal clock
operation output
pin: CL = 80 pF
External clock
operation output
pin: CL = 80 pF
Notes: • These AC characteristics assume the CLK synchronous mode.
• CL is the value for load capacity applied to the pin under testing.
• tCYC is the machine cycle (in nanoseconds).
• Internal shift clock mode
tSCYC
2.4 V
SCK
0.8 V
0.8 V
tSLOV
2.4 V
SOT
0.8 V
tIVSH
SIN
tSHIX
2.4 V
2.4 V
0.8 V
0.8 V
• External shift clock mode
tSLSH
tSHSL
2.4 V
2.4 V
SCK
0.8 V
0.8 V
tSLOV
SOT
2.4 V
0.8 V
tIVSH
SIN
54
Unit
Min.
tSHIX
2.4 V
2.4 V
0.8 V
0.8 V
Remarks
MB90230 Series
(5) Extended Serial I/O Timing
(VCC = +5.0 V±5%, VSS = 0.0 V, TA = –40°C to +70°C)
Symbol
Parameter
Pin
name
Value
Condition
Unit
Min.
Max.
8 tCYC
—
ns
50
—
ns
1 tCYC
—
ns
Serial clock cycle time
tSCYC
—
SCK ↓ → SOT delay time
tSLOV
—
Valid SIN → SCK ↑
tIVSH
—
SCK ↑ → Valid SIN hold time
tSHIX
—
1 tCYC
—
ns
Serial clock “H” pulse width
tSHSL
—
250
—
ns
Serial clock “L” pulse width
tSLSH
—
250
—
ns
2 tCYC
—
ns
Internal clock
operation output
pin: CL = 80 pF
External clock
operation output
pin: CL = 80 pF
SCK ↓ → SOT delay time
tSLOV
—
Valid SIN → SCK ↑
tIVSH
—
1 tCYC
—
ns
SCK ↑ → Valid SIN hold time
tSHIX
—
2 tCYC
—
ns
Remarks
External clock:
2 MHz max.
Notes: • CL is the value for load capacity applied to the pin under testing.
• tCYC is the machine cycle (in nanoseconds).
• Internal shift clock mode
tSCYC
2.4 V
SCK
0.8 V
0.8 V
tSLOV
2.4 V
SOT
0.8 V
tIVSH
SIN
tSHIX
2.4 V
2.4 V
0.8 V
0.8 V
• External shift clock mode
tSLSH
tSHSL
2.4 V
SCK
0.8 V
2.4 V
0.8 V
tSLOV
SOT
2.4 V
0.8 V
tIVSH
SIN
tSHIX
2.4 V
2.4 V
0.8 V
0.8 V
55
MB90230 Series
5. A/D Converter Electrical Characteristics
(AVCC = VCC = +5.0 V ± 5%, AVSS = VSS = 0.0 V, +3.0 V ≤ AVRH – AVRL, TA = –40°C to +70°C)
Value
Symbol
Pin name
Unit
Parameter
Min.
Typ.
Max.
Resolution
Total error
—
Linearity error
—
10
10
bit
—
—
±3.0
LSB
—
—
±2.0
LSB
—
—
±1.5
LSB
–1.5
+0.5
+2.5
LSB
AVRH –4.5
AVRH –1.5
AVRH +0.5
LSB
5.00
—
—
µs
—
—
10
µA
AVRL
—
AVRH
V
AVRH
AVRL
—
AVCC
V
AVRL
0
—
AVRH
V
—
5
—
mA
—
—
5*
µA
—
200
—
µA
—
—
5*
µA
—
—
4
LSB
—
Differential linearity error
Zero transition voltage
VOT
Full-scale transition voltage
VFST
Conversion time
—
Analog port input current
IAIN
Analog input voltage
Reference voltage
Power supply current
AN0 to AN7
fC = 16 MHz
AN0 to AN7
—
IA
AVCC
IAS
IR
Reference voltage supply
current
IRS
Variation between channels
—
AVRH
AN0 to AN7
* : Current applied in CPU stop mode with the A/D converter inactive (VCC = AVCC = AVRH = 5.5 V).
Notes: • The error becomes larger as |AVRH–AVRL| becomes smaller.
• Use the output impedance of the external circuit for analog input under the following conditions: External
circuit output impedance < Approx. 7 kΩ
• If the output impedance the external circuit is too high, the analog voltage sampling time may be insufficient.
(Sampling time = 3.0 µs at a machine clock frequency of 16 MHz)
• Analog Input Circuit Mode
C0
Analog input
Comparator
RON1
RON2
C1
RON2 + RON2 = Approx. 3 kΩ
C0 = Approx. 60 pF
C1 = Approx. 4 pF
Note: The values shown here are reference values.
56
MB90230 Series
6. A/D Glossary
• Resolution
Analog changes that are identifiable with the A/D converter.
When the number of bits is 10, analog voltage can be divided into 210 = 1024
• Total error
Difference between actual and logical values. This error is caused by a zero transition error, full-scale transition
error, linearity error, differential linearity error, or by noise.
• Linearity error
The deviation of the straight line connecting the zero transition point (“00 0000 0000” ↔ “00 0000 0001”) with
the full-scale transition point (“11 1111 1111” ↔ “11 1111 1110”) from actual conversion characteristics
• Differential linearity error
The deviation of input voltage needed to change the output code by 1 LSB from the theoretical value
Digital output
11 1111 1111
11 1111 1110
•
•
•
•
•
•
•
•
•
•
•
00 0000 0010
00 0000 0001
00 0000 0000
VOT
(1LSB × N + VOT)
Linearity error
Analog input
VFST
VNT V(N+1)T
1LSB
=
VFST − VOT
1022
Linearity error
=
VNT − (1LSB × N + VOT )
(LSB)
1LSB
Differential linearity error =
V( N+1)T − VNT
−1
1LSB
(LSB)
57
MB90230 Series
7. D/A Converter Electrical Characteristics
(AVCC = VCC = +5.0 V±5%, AVSS = VSS = 0.0 V, TA = –40°C to +70°C)
Symbol
Pin name
Resolution
—
Differential linearity error
Parameter
Unit
Min.
Typ.
Max.
—
—
8
8
bit
—
—
—
—
±0.9
LSB
Conversion time
—
—
—
10*
20*
µs
Analog output impedance
—
—
—
28
—
KΩ
*: A load capacity of 20 pF is assumed.
58
Value
MB90230 Series
8. Serial E2PROM Interface Timing
(1) E2PROM interface at an operation clock frequency of 1 MHz
Parameter
Symbol
Min.
(VCC = +5.0 V±5%, VSS = 0.0 V, TA = –40°C to +70°C)
Value
Unit
Remarks
Typ.
Max.
Operation cycle
tSK
1.0
—
—
µs
Clock “H” time
tSKH
0.4
0.5
—
µs
Clock “L” time
tSKL
0.4
0.5
—
µs
ECS setup time
tCSS
0.3
—
—
µs
ECS hold time
tCSH
0.0
—
—
µs
EDO data decision time
tPD
0.3
—
—
µs
EDO output hold time
tOH
0.5
—
—
µs
EDI setup time
tDIS
0.0
—
—
µs
EDI hold time
tDIH
0.4
—
—
µs
READY ↑ → ECS ↓
tRCSH
0.4
—
—
µs
ECS “L” time
tCSL
0.8
1.0
—
µs
(2) E2PROM interface at an operation clock frequency of 2 MHz
(VCC = +5.0 V±5%, VSS = 0.0 V, TA = –40°C to +70°C)
Parameter
Symbol
Value
Min.
Typ.
Max.
Unit
Operation cycle
tSK
0.5
—
—
µs
Clock “H” time
tSKH
0.2
0.25
—
µs
Clock “L” time
tSKL
0.2
0.25
—
µs
ECS setup time
tCSS
0.15
—
—
µs
ECS hold time
tCSH
0.0
—
—
µs
EDO data decision time
tPD
0.15
—
—
µs
EDO output hold time
tOH
0.25
—
—
µs
EDI setup time
tDIS
0.0
—
—
µs
EDI hold time
tDIH
0.2
—
—
µs
READY ↑ → ECS ↓
tRCSH
0.2
—
—
µs
ECS “L” time
tCSL
0.4
0.5
—
µs
Remarks
59
MB90230 Series
tSK
tSKH
tSKL
ESK
tPD
EDO
tOH
Determined data
Determined data
tCSH
tCSS
ECS
tDIS
EDI
Input data
tDIH
Input data
tCSL
ECS
tST
DO
(E2PROM output)
Hi-z
BUSY
MB90230 series
ECS
ESK
EDO
EDI
60
READY
E2PROM
ECS
ESK
EDI
EDO
MB90230 Series
■ INSTRUCTIONS (412 INSTRUCTIONS)
Table 1
Description of Instruction Table
Item
Mnemonic
Description
Upper-case letters and symbols: Described directry in assembly code
Lower-case letters: Replaced when described in assembly code
Numbers after lower-case letters: Indicates the bit width within the code
#
Indicates the number of bytes
~
Indicates the number of cycles
See Table 4 for details about meanings of letters in items.
B
Indicates the compensation value for calculating the number of actual cycles during
execution of instruction.
The number of actual cycles during execution of instruction is summed with the value in
the “cycles” column.
Operation
Indicates operation of instruction.
LH
Indicates special operations involving the bits 15 through 08 of the accumulator.
Z: Transfers “0”
X: Extends before transferring
—: No transfer
AH
Indicates special operations involving the high-order 16 bits in the accumulator.
*: Transfers from AL to AH
—: No transfer
Z: Transfers 00H to AH.
X: Transfers 00H or FFH to AH by extending AL
I
S
T
N
Indicates the status of each of the following flags: I (interrupt enable), S (stack), T (sticky
bit), N (negative), Z (zero), V (overflow), and C (carry).
*: Changes due to execution of instruction.
—: No change.
S: Set by execution of instruction.
R: Reset by execution of instruction.
Z
V
C
RMW
Indicates whether the instruction is a read-modify-write instruction (a single instruction
that reads data from memory, etc., processes the data, and then writes the result to
memory.).
*: Instruction is a read-modify-write instruction
—: Instruction is not a read-modify-write instruction
Note: Cannot be used for addresses that have different meanings depending on
whether they are read or written.
61
MB90230 Series
Table 2
Explanation of Symbols in Table of Instructions
Symbol
A
AH
32-bit accumulator
The number of bits used varies according to the instruction.
Byte: Low order 8 bits of AL
Word: 16 bits of AL
Long: 32 bits of AL, AH
High-order 16 bits of A
AL
Low-order 16 bits of A
SP
Stack pointer (USP or SSP)
PC
Program counter
SPCU
Stack pointer upper limit register
SPCL
Stack pointer lower limit register
PCB
Program bank register
DTB
Data bank register
ADB
Additional data bank register
SSB
System stack bank register
USB
User stack bank register
SPB
Current stack bank register (SSB or USB)
DPR
Direct page register
brg1
DTB, ADB, SSB, USB, DPR, PCB, SPB
brg2
DTB, ADB, SSB, USB, DPR, SPB
Ri
R0, R1, R2, R3, R4, R5, R6, R7
RWi
RW0, RW1, RW2, RW3, RW4, RW5, RW6, RW7
RWj
RW0, RW1, RW2, RW3
RLi
RL0, RL1, RL2, RL3
dir
addr16
addr24
addr24 0 to 15
addr24 16 to 23
io
#imm4
#imm8
#imm16
#imm32
ext (imm8)
disp8
disp16
bp
Compact direct addressing
Direct addressing
Physical direct addressing
Bits 0 to 15 of addr24
Bits 16 to 23 of addr24
I/O area (000000H to 0000FFH)
4-bit immediate data
8-bit immediate data
16-bit immediate data
32-bit immediate data
16-bit data signed and extended from 8-bit immediate data
8-bit displacement
16-bit displacement
Bit offset value
vct4
vct8
Vector number (0 to 15)
Vector number (0 to 255)
( )b
Bit address
rel
ear
eam
Branch specification relative to PC
Effective addressing (codes 00 to 07)
Effective addressing (codes 08 to 1F)
rlst
62
Description
Register list
MB90230 Series
Table 3
Code
00
01
02
03
04
05
06
07
Notation
R0
R1
R2
R3
R4
R5
R6
R7
RW0
RW1
RW2
RW3
RW4
RW5
RW6
RW7
RL0
(RL0)
RL1
(RL1)
RL2
(RL2)
RL3
(RL3)
Effective Address Fields
Address format
Number of bytes in
address extemsion*
Register direct
“ea” corresponds to byte, word, and
long-word types, starting from the
left
—
08
09
0A
0B
@RW0
@RW1
@RW2
@RW3
Register indirect
0
0C
0D
0E
0F
@RW0 +
@RW1 +
@RW2 +
@RW3 +
Register indirect with post-increment
0
10
11
12
13
14
15
16
17
@RW0 + disp8
@RW1 + disp8
@RW2 + disp8
@RW3 + disp8
@RW4 + disp8
@RW5 + disp8
@RW6 + disp8
@RW7 + disp8
Register indirect with 8-bit
displacement
1
18
19
1A
1B
@RW0 + disp16
@RW1 + disp16
@RW2 + disp16
@RW3 + disp16
Register indirect with 16-bit
displacemen
2
1C
1D
1E
1F
@RW0 + RW7
@RW1 + RW7
@PC + dip16
addr16
Register indirect with index
Register indirect with index
PC indirect with 16-bit displacement
Direct address
0
0
2
2
* : The number of bytes for address extension is indicated by the “+” symbol in the “#” (number of bytes) column in
the Table of Instructions.
63
MB90230 Series
Table 4
Code
Number of Execution Cycles for Each Form of Addressing
Operand
(a)*
Number of execution cycles for each from of addressing
00 to 07
Ri
RWi
RLi
Listed in Table of Instructions
08 to 0B
@RWj
1
0C to 0F
@RWj +
4
10 to 17
@RWi + disp8
1
18 to 1B
@RWj + disp16
1
1C
1D
1E
1F
@RW0 + RW7
@RW1 + RW7
@PC + dip16
@addr16
2
2
2
1
* : “(a)” is used in the “cycles” (number of cycles) column and column B (correction value) in the Table of Instructions.
Table 5
Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles
Operand
(b)*
(c)*
(d)*
byte
word
long
Internal register
+
0
+
0
+
0
Internal RAM even address
+
0
+
0
+
0
Internal RAM odd address
+
0
+
1
+
2
Even address not in internal RAM
+
1
+
1
+
2
Odd address not in internal RAM
+
1
+
3
+
6
External data bus (8 bits)
+
1
+
3
+
6
* : “(b)”, “(c)”, and “(d)” are used in the “cycles” (number of cycles) column and column B (correction value) in the
Table of Instructions.
64
MB90230 Series
Table 6
Mnemonic
B
Operation
2
2
2
3
1
1
1
2
2+ 2+ (a)
2
2
2
2
2
2
6
3
3
3
3
5
2
2
1
1
(b)
(b)
0
0
(b)
(b)
0
(b)
(b)
(b)
(b)
(b)
0
byte (A) ← (dir)
byte (A) ← (addr16)
byte (A) ← (Ri)
byte (A) ← (ear)
byte (A) ← (eam)
byte (A) ← (io)
byte (A) ← imm8
byte (A) ← ((A))
byte (A) ← ((RLi))+disp8)
byte (A) ← ((SP)+disp8)
byte (A) ←(addr24)
byte (A) ← ((A))
byte (A) ← imm4
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
2
2
MOVX A, dir
2
3
MOVX A, addr16
1
2
MOVX A, Ri
1
2
MOVX A, ear
2+ 2+ (a)
MOVX A, eam
2
2
MOVX A, io
2
2
MOVX A, #imm8
2
2
MOVX A, @A
3
MOVX A,@RWi+disp8 2
6
MOVX A, @RLi+disp8 3
3
3
MOVX A, @SP+disp8
3
5
MOVPX A, addr24
2
2
MOVPX A, @A
(b)
(b)
0
0
(b)
(b)
0
(b)
(b)
(b)
(b)
(b)
(b)
byte (A) ← (dir)
byte (A) ← (addr16)
byte (A) ← (Ri)
byte (A) ← (ear)
byte (A) ← (eam)
byte (A) ← (io)
byte (A) ← imm8
byte (A) ← ((A))
byte (A) ← ((RWi))+disp8)
byte (A) ← ((RLi))+disp8)
byte (A) ← ((SP)+disp8)
byte (A) ←(addr24)
byte (A) ← ((A))
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOVP
MOVP
MOVN
A, dir
A, addr16
A, Ri
A, ear
A, eam
A, io
A, #imm8
A, @A
A, @RLi+disp8
A, @SP+disp8
A, addr24
A, @A
A, #imm4
#
~
Transfer Instructions (Byte) [50 Instructions]
LH AH
I
S
T
N
Z
V
C
RMW
*
*
*
*
*
*
*
–
*
*
*
–
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
R
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
X
X
X
X
X
X
X
X
X
X
X
X
X
*
*
*
*
*
*
*
–
*
*
*
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOVP
dir, A
addr16, A
Ri, A
ear, A
eam, A
io, A
@RLi+disp8, A
@SP+disp8, A
addr24, A
2
2
2
3
1
1
2
2
2+ 2+ (a)
2
2
6
3
3
3
3
5
(b)
(b)
0
0
(b)
(b)
(b)
(b)
(b)
byte (dir) ← (A)
byte (addr16) ← (A)
byte (Ri) ← (A)
byte (ear) ← (A)
byte (eam) ← (A)
byte (io) ← (A)
byte ((RLi)) +disp8) ← (A)
byte ((SP)+disp8) ← (A)
byte (addr24) ← (A)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
MOV
MOV
MOVP
MOV
MOV
MOV
MOV
MOV
MOV
MOV
Ri, ear
Ri, eam
@A, Ri
ear, Ri
eam, Ri
Ri, #imm8
io, #imm8
dir, #imm8
ear, #imm8
eam, #imm8
2
2
2+ 3+ (a)
3
2
3
2
2+ 3+ (a)
2
2
3
3
3
3
2
3
3+ 2+ (a)
0
(b)
(b)
0
(b)
0
(b)
(b)
0
(b)
byte (Ri) ← (ear)
byte (Ri) ← (eam)
byte ((A)) ← (Ri)
byte (ear) ← (Ri)
byte (eam) ← (Ri)
byte (Ri) ← imm8
byte (io) ← imm8
byte (dir) ← imm8
byte (ear) ← imm8
byte (eam) ← imm8
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
–
–
*
–
*
*
*
*
*
*
–
–
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
MOV
@AL, AH
2
(b)
byte ((A)) ← (AH)
–
–
–
–
–
*
*
–
–
–
XCH
XCH
XCH
XCH
A, ear
A, eam
Ri, ear
Ri, eam
0
3
2
2+ 3+ (a) 2× (b)
0
4
2
2+ 5+ (a) 2× (b)
byte (A) ↔ (ear)
byte (A) ↔ (eam)
byte (Ri) ↔ (ear)
byte (Ri) ↔ (eam)
Z
Z
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
2
For an explanation of “(a)” and “(b)”, refer to Table 4, “Number of Execution Cycles for Each Form of Addressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
65
MB90230 Series
Table 7
Mnemonic
B
Operation
2
2
3
2
1
2
1
1
2
1
2+ 2+ (a)
2
2
2
2
3
2
2
3
3
6
3
3
5
3
2
2
(c)
(c)
0
0
0
(c)
(c)
(c)
0
(c)
(c)
(c)
(c)
(c)
word (A) ← (dir)
word (A) ← (addr16)
word (A) ← (SP)
word (A) ← (RWi)
word (A) ← (ear)
word (A) ← (eam)
word (A) ← (io)
word (A) ← ((A))
word (A) ← imm16
word (A) ← ((RWi) +disp8)
word (A) ← ((RLi) +disp8)
word (A) ← ((SP) +disp8
word (A) ← (addr24)
word (A) ← ((A))
–
–
–
–
–
–
–
–
–
–
–
–
–
–
2
3
4
1
1
2
2+
2
2
3
3
5
2
2
2+
2
2+
3
4
4
4+
2
2
2
2
1
2
2+ (a)
2
3
6
3
3
3
2
3+ (a)
3
3+ (a)
2
3
2
2+ (a)
(c)
(c)
0
0
0
0
(c)
(c)
(c)
(c)
(c)
(c)
(c)
0
(c)
0
(c)
0
(c)
0
(c)
word (dir) ← (A)
word (addr16) ← (A)
word (SP) ← imm16
word (SP) ← (A)
word (RWi) ← (A)
word (ear) ← (A)
word (eam) ← (A)
word (io) ← (A)
word ((RWi) +disp8) ← (A)
word ((RLi) +disp8) ← (A)
word ((SP) +disp8) ← (A)
word (addr24) ← (A)
word ((A)) ← (RWi)
word (RWi) ← (ear)
word (RWi) ← (eam)
word (ear) ← (RWi)
word (eam) ← (RWi)
word (RWi) ← imm16
word (io) ← imm16
word (ear) ← imm16
word (eam) ← imm16
MOVW @AL, AH
2
2
(c)
XCHW
XCHW
XCHW
XCHW
2
3
0
2+ 3+ (a) 2× (c)
2
4
0
2+ 5+ (a) 2× (c)
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
A, dir
A, addr16
A, SP
A, RWi
A, ear
A, eam
A, io
A, @A
A, #imm16
A, @RWi+disp8
A, @RLi+disp8
A, @SP+disp8
MOVPWA, addr24
MOVPWA, @A
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
dir, A
addr16, A
SP, # imm16
SP, A
RWi, A
ear, A
eam, A
io, A
@RWi+disp8, A
@RLi+disp8, A
@SP+disp8, A
MOVPWaddr24, A
MOVPW@A, RWi
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
RWi, ear
RWi, eam
ear, RWi
eam, RWi
RWi, #imm16
io, #imm16
ear, #imm16
eam, #imm16
A, ear
A, eam
RWi, ear
RWi, eam
#
Transfer Instructions (Word) [40 Instructions]
~
LH AH
I
S
T
N
Z
V
C
RMW
*
*
*
*
*
*
*
–
*
*
*
*
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
*
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
word ((A)) ← (AH)
–
–
–
–
–
*
*
–
–
–
word (A) ↔ (ear)
word (A) ↔ (eam)
word (RWi) ↔ (ear)
word (RWi) ↔ (eam)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Note: For an explanation of “(a)” and “(c)”, refer to Table 4, “Number of Execution Cycles for Each Form of
Addressing,” and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual
Cycles.”
66
MB90230 Series
Table 8
Mnemonic
#
Transfer Instructions (Long Word) [11 Instructions]
~
B
Operation
LH AH
I
S
T
N
Z
V
C
RMW
MOVL A, ear
2
1
MOVL A, eam
2+ 3+ (a)
MOVL A, # imm32
5
3
MOVL A, @SP + disp8 3
4
MOVPL A, addr24
5
4
MOVPL A, @A
2
3
0
(d)
0
(d)
(d)
(d)
long (A) ← (ear)
long (A) ← (eam)
long (A) ← imm32
long (A) ← ((SP) +disp8)
long (A) ← (addr24)
long (A) ← ((A))
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
MOVPL@A, RLi
(d)
long ((A)) ← (RLi)
–
–
–
–
–
*
*
–
–
–
(d)
(d)
0
(d)
long ((SP) + disp8) ← (A)
long (addr24) ← (A)
long (ear) ← (A)
long (eam) ← (A)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
–
–
–
–
–
–
–
–
–
–
–
–
2
5
MOVL @SP + disp8, A 3
4
MOVPL addr24, A
5
4
MOVL ear, A
2
2
MOVL eam, A
2+ 3+ (a)
For an explanation of “(a)” and “(d)”, refer to Table 4, “Number of Execution Cycles for Each Form of Addressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
67
MB90230 Series
Table 9
Mnemonic
Addition and Subtraction Instructions (Byte/Word/Long Word) [42 Instructions]
#
~
B
Operation
LH AH
I
S
T
N
Z
V
C
RMW
ADD
A, #imm8
ADD
A, dir
ADD
A, ear
ADD
A, eam
ADD
ear, A
ADD
eam, A
ADDC A
ADDC A, ear
ADDC A, eam
ADDDC A
2
2
0
2
3
(b)
2
2
0
2+ 3+ (a) (b)
2
2
0
2+ 3+ (a) 2× (b)
1
2
0
2
2
0
2+ 3+ (a) (b)
1
3
0
byte (A) ← (A) + imm8
byte (A) ← (A) + (dir)
byte (A) ← (A) + (ear)
byte (A) ← (A) + (eam)
byte (ear) ← (ear) + (A)
byte (eam) ← (eam) + (A)
byte (A) ← (AH) + (AL) + (C)
byte (A) ← (A) + (ear) + (C)
byte (A) ← (A) + (eam) + (C)
byte (A) ← (AH) + (AL) + (C) (Decimal)
Z
Z
Z
Z
–
Z
Z
Z
Z
Z
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
*
*
–
–
–
–
SUB
SUB
SUB
SUB
SUB
SUB
SUBC
SUBC
SUBC
SUBDC
2
2
0
2
3
(b)
2
2
0
2+ 3+ (a) (b)
2
2
0
2+ 3+ (a) 2× (b)
1
2
0
2
2
0
2+ 3+ (a) (b)
1
3
0
byte (A) ← (A) – imm8
byte (A) ← (A) – (dir)
byte (A) ← (A) – (ear)
byte (A) ← (A) – (eam)
byte (ear) ← (ear) – (A)
byte (eam) ← (eam) – (A)
byte (A) ← (AH) – (AL) – (C)
byte (A) ← (A) – (ear) – (C)
byte (A) ← (A) – (eam) – (C)
byte (A) ← (AH) – (AL) – (C) (Decimal)
Z
Z
Z
Z
–
–
Z
Z
Z
Z
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
*
*
–
–
–
–
ADDW A
1
2
0
ADDW A, ear
2
2
0
ADDW A, eam
2+ 3+ (a) (c)
ADDW A, #imm16 3
2
0
ADDW ear, A
2
2
0
ADDW eam, A
2+ 3+ (a) 2× (c)
ADDCW A, ear
2
2
0
ADDCW A, eam
2+ 3+ (a) (c)
word (A) ← (AH) + (AL)
word (A) ← (A) + (ear)
word (A) ← (A) + (eam)
word (A) ← (A) + imm16
word (ear) ← (ear) + (A)
word (eam) ← (eam) + (A)
word (A) ← (A) + (ear) + (C)
word (A) ← (A) + (eam) + (C)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
*
*
–
–
SUBW A
1
2
0
SUBW A, ear
2
2
0
SUBW A, eam
2+ 3+ (a) (c)
SUBW A, #imm16 3
2
0
SUBW ear, A
2
2
0
SUBW eam, A
2+ 3+ (a) 2× (c)
SUBCW A, ear
2
2
0
SUBCW A, eam
2+ 3+ (a) (c)
word (A) ← (AH) – (AL)
word (A) ← (A) – (ear)
word (A) ← (A) – (eam)
word (A) ← (A) – imm16
word (ear) ← (ear) – (A)
word (eam) ← (eam) – (A)
word (A) ← (A) – (ear) – (C)
word (A) ← (A) – (eam) – (C)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
*
*
–
–
ADDL
ADDL
ADDL
A, ear
2
5
A, eam
2+ 6+ (a)
A, #imm32 5
4
0
(d)
0
long (A) ← (A) + (ear)
long (A) ← (A) + (eam)
long (A) ← (A) + imm32
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
SUBL
SUBL
SUBL
A, ear
2
5
A, eam
2+ 6+ (a)
A, #imm32 5
4
0
(d)
0
long (A) ← (A) – (ear)
long (A) ← (A) – (eam)
long (A) ← (A) – imm32
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
A, #imm8
A, dir
A, ear
A, eam
ear, A
eam, A
A
A, ear
A, eam
A
For an explanation of “(a)”, “(b)”, “(c)” and “(d)”, refer to Table 4, “Number of Execution Cycles for Each Form of
Addressing,” and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
68
MB90230 Series
Table 10
Increment and Decrement Instructions (Byte/Word/Long Word) [12 Instructions]
Mnemonic
#
~
B
Operation
LH AH
I
S
T
N
Z
V
C
RMW
INC
INC
ear
eam
2
2
0
byte (ear) ← (ear) +1
2+ 3+ (a) 2× (b) byte (eam) ← (eam) +1
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
–
–
*
*
DEC
DEC
ear
eam
2
2
0
byte (ear) ← (ear) –1
2+ 3+ (a) 2× (b) byte (eam) ← (eam) –1
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
–
–
*
*
INCW
INCW
ear
eam
2
2
0
word (ear) ← (ear) +1
2+ 3+ (a) 2× (c) word (eam) ← (eam) +1
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
–
–
*
*
DECW ear
DECW eam
2
2
0
word (ear) ← (ear) –1
2+ 3+ (a) 2× (c) word (eam) ← (eam) –1
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
–
–
*
*
INCL
INCL
ear
eam
2
4
0
long (ear) ← (ear) +1
2+ 5+ (a) 2× (d) long (eam) ← (eam) +1
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
–
–
*
*
DECL
DECL
ear
eam
2
4
0
long (ear) ← (ear) –1
2+ 5+ (a) 2× (d) long (eam) ← (eam) –1
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
–
–
*
*
For an explanation of “(a)”, “(b)”, “(c)” and “(d)”, refer to Table 4, “Number of Execution Cycles for Each Form of
Addressing,” and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
Table 11
Mnemonic
#
Compare Instructions (Byte/Word/Long Word) [11 Instructions]
~
B
Operation
LH AH
I
S
T
N
Z
V
C
RMW
CMP
CMP
CMP
CMP
A
A, ear
A, eam
A, #imm8
1
2
2
2
2+ 2+ (a)
2
2
0
0
(b)
0
byte (AH) – (AL)
byte (A) – (ear)
byte (A) – (eam)
byte (A) – imm8
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
CMPW
CMPW
CMPW
CMPW
A
A, ear
A, eam
A, #imm16
1
2
2
2
2+ 2+ (a)
3
2
0
0
(c)
0
word (AH) – (AL)
word (A) – (ear)
word (A) – (eam)
word (A) – imm16
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
CMPL A, ear
CMPL A, eam
CMPL A, #imm32
2
3
2+ 4+ (a)
5
3
0
(d)
0
long (A) – (ear)
long (A) – (eam)
long (A) – imm32
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
For an explanation of “(a)”, “(b)”, “(c)” and “(d)”, refer to Table 4, “Number of Execution Cycles for Each Form of
Addressing,” and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
69
MB90230 Series
Table 12
Mnemonic
Unsigned Multiplication and Division Instructions (Word/Long Word) [11 Instructions]
#
~
1
DIVU
A
1
*
DIVU
A, ear
2
*2
DIVU
A, eam 2+
MULU
MULU
MULU
MULUW
MULUW
MULUW
Operation
A, eam 2+
*5
0 word (AH) /byte (AL)
Quotient → byte (AL) Remainder → byte (AH)
0 word (A)/byte (ear)
Quotient → byte (A) Remainder → byte (ear)
*6 word (A)/byte (eam)
Quotient → byte (A) Remainder → byte (eam)
0 long (A)/word (ear)
Quotient → word (A) Remainder → word (ear)
*7 long (A)/word (eam)
1
2
2+
1
2
2+
*8
*9
*10
*11
*12
*13
0
0
(b)
0
0
(c)
DIVUW A, ear
DIVUW
B
A
A, ear
A, eam
A
A, ear
A, eam
2
*3
*4
Quotient → word (A) Remainder → word (eam)
byte (AH) × byte (AL) → word (A)
byte (A) × byte (ear) → word (A)
byte (A) × byte (eam) → word (A)
word (AH) × word (AL) → long (A)
word (A) × word (ear) → long (A)
word (A) × word (eam) → long (A)
LH AH
I
S
T
N
Z
V
C RMW
–
–
–
–
–
–
–
*
*
–
–
–
–
–
–
–
–
*
*
–
–
–
–
–
–
–
–
*
*
–
–
–
–
–
–
–
–
*
*
–
–
–
–
–
–
–
–
*
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
For an explanation of “(b)” and “(c), refer to Table 5, “Correction Values for Number of Cycle Used to Calculate
Number of Actual Cycles.”
*1: 3 when dividing into zero, 6 when an overflow occurs, and 14 normally.
*2: 3 when dividing into zero, 5 when an overflow occurs, and 13 normally.
*3: 5 + (a) when dividing into zero, 7 + (a) when an overflow occurs, and 17 + (a) normally.
*4: 3 when dividing into zero, 5 when an overflow occurs, and 21 normally.
*5: 4 + (a) when dividing into zero, 7 + (a) when an overflow occurs, and 25 + (a) normally.
*6: (b) when dividing into zero or when an overflow occurs, and 2 × (b) normally.
*7: (c) when dividing into zero or when an overflow occurs, and 2 × (c) normally.
*8: 3 when byte (AH) is zero, and 7 when byte (AH) is not 0.
*9: 3 when byte (ear) is zero, and 7 when byte (ear) is not 0.
*10: 4 + (a) when byte (eam) is zero, and 8 + (a) when byte (eam) is not 0.
*11: 3 when word (AH) is zero, and 11 when word (AH) is not 0.
*12: 3 when word (ear) is zero, and 11 when word (ear) is not 0.
*13: 4 + (a) when word (eam) is zero, and 12 + (a) when word (eam) is not 0.
70
MB90230 Series
Table 13
Mnemonic
Signed Multiplication and Division Instructions (Word/Long Word) [11 Insturctions]
#
~
1
DIV
A
2
*
DIV
A, ear
2
*2
DIV
A, eam 2+
DIVW A, ear
2
*3
*4
DIVW
A, eam 2+
*5
MUL
MUL
A
A, ear
*8
*9
*10
*11
*12
*13
2
2
MUL
A, eam 2+
MULW A
2
MULW A, ear
2
MULW A, eam 2+
B
Operation
0 word (AH) /byte (AL)
Quotient → byte (AL) Remainder → byte (AH)
0 word (A)/byte (ear)
Quotient → byte (A) Remainder → byte (ear)
*6 word (A)/byte (eam)
Quotient → byte (A) Remainder → byte (eam)
0 long (A)/word (ear)
Quotient → word (A) Remainder → word (ear)
*7 long (A)/word (eam)
Quotient → word (A) Remainder → word (eam)
0
0
(b)
0
0
(b)
byte (AH) × byte (AL) → word (A)
byte (A) × byte (ear) → word (A)
byte (A) × byte (eam) → word (A)
word (AH) × word (AL) → long (A)
word (A) × word (ear) → long (A)
word (A) × word (eam) → long (A)
LH AH
I
S
T
N
Z
V
C
RMW
Z
–
–
–
–
–
–
*
*
–
Z
–
–
–
–
–
–
*
*
–
Z
–
–
–
–
–
–
*
*
–
–
–
–
–
–
–
–
*
*
–
–
–
–
–
–
–
–
*
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
For an explanation of “(b)” and “(c)”, refer to Table 5, “Correction Values for Number of Cycles Used to Calculate
Number of Actual Cycles.”
*1:
*2:
*3:
*4:
*5:
*6:
*7:
*8:
*9:
*10:
*11:
*12:
*13:
3 when dividing into zero, 8 or 18 when an overflow occurs, and 18 normally.
3 when dividing into zero, 10 or 21 when an overflow occurs, and 22 normally.
4 + (a) when dividing into zero, 11 + (a) or 22 + (a) when an overflow occurs, and 23 + (a) normally.
When the dividend is positive: 4 when dividing into zero, 10 or 29 when an overflow occurs, and 30 normally.
When the dividend is negative: 4 when dividing into zero, 11 or 30 when an overflow occurs, and 31 normally.
When the dividend is positive: 4 + (a) when dividing into zero, 11 + (a) or 30 + (a) when an overflow occurs,
and 31 + (a) normally.
When the dividend is negative: 4 + (a) when dividing into zero, 12 + (a) or 31 + (a) when an overflow occurs,
and 32 + (a) normally.
(b) when dividing into zero or when an overflow occurs, and 2 × (b) normally.
(c) when dividing into zero or when an overflow occurs, and 2 × (c) normally.
3 when byte (AH) is zero, 12 when the result is positive, and 13 when the result is negative.
3 when byte (ear) is zero, 12 when the result is positive, and 13 when the result is negative.
4 + (a) when byte (eam) is zero, 13 + (a) when the result is positive, and 14 + (a) when the result is negative.
3 when word (AH) is zero, 12 when the result is positive, and 13 when the result is negative.
3 when word (ear) is zero, 16 when the result is positive, and 19 when the result is negative.
4 + (a) when word (eam) is zero, 17 + (a) when the result is positive, and 20 + (a) when the result is negative.
Note: Which of the two values given for the number of execution cycles applies when an overflow error occurs in
a DIV or DIVW instruction depends on whether the overflow was detected before or after the operation.
71
MB90230 Series
Table 14
Mnemonic
#
~
Logical 1 Instructions (Byte, Word) [39 Instructions]
B
Operation
LH AH
I
S
T
N
Z
V
C
RMW
AND
AND
AND
AND
AND
A, #imm8
A, ear
A, eam
ear, A
eam, A
2
2
0
2
2
0
2+ 3+ (a) (b)
2
3
0
2+ 3+ (a) 2× (b)
byte (A) ← (A) and imm8
byte (A) ← (A) and (ear)
byte (A) ← (A) and (eam)
byte (ear) ← (ear) and (A)
byte (eam) ← (eam) and (A)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
R
R
R
R
R
–
–
–
–
–
–
–
–
*
*
OR
OR
OR
OR
OR
A, #imm8
A, ear
A, eam
ear, A
eam, A
2
2
0
2
2
0
2+ 3+ (a) (b)
2
3
0
2+ 3+ (a) 2× (b)
byte (A) ← (A) or imm8
byte (A) ← (A) or (ear)
byte (A) ← (A) or (eam)
byte (ear) ← (ear) or (A)
byte (eam) ← (eam) or (A)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
R
R
R
R
R
–
–
–
–
–
–
–
–
*
*
XOR
XOR
XOR
XOR
XOR
NOT
NOT
NOT
A, #imm8
A, ear
A, eam
ear, A
eam, A
A
ear
eam
2
2
0
2
2
0
2+ 3+ (a) (b)
2
3
0
2+ 3+ (a) 2× (b)
1
2
0
2
2
0
2+ 3+ (a) 2× (b)
byte (A) ← (A) xor imm8
byte (A) ← (A) xor (ear)
byte (A) ← (A) xor (eam)
byte (ear) ← (ear) xor (A)
byte (eam) ← (eam) xor (A)
byte (A) ← not (A)
byte (ear) ← not (ear)
byte (eam) ← not (eam)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
R
R
R
R
R
R
R
R
–
–
–
–
–
–
–
–
–
–
–
*
*
–
*
*
ANDW
ANDW
ANDW
ANDW
ANDW
ANDW
A
A, #imm16
A, ear
A, eam
ear, A
eam, A
1
2
0
3
2
0
2
2
0
2+ 3+ (a) (c)
2
3
0
2+ 3+ (a) 2× (c)
word (A) ← (AH) and (A)
word (A) ← (A) and imm16
word (A) ← (A) and (ear)
word (A) ← (A) and (eam)
word (ear) ← (ear) and (A)
word (eam) ← (eam) and (A)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
R
R
R
R
R
R
–
–
–
–
–
–
–
–
–
–
*
*
ORW
ORW
ORW
ORW
ORW
ORW
A
A, #imm16
A, ear
A, eam
ear, A
eam, A
1
2
0
3
2
0
2
2
0
2+ 3+ (a) (c)
2
3
0
2+ 3+ (a) 2× (c)
word (A) ← (AH) or (A)
word (A) ← (A) or imm16
word (A) ← (A) or (ear)
word (A) ← (A) or (eam)
word (ear) ← (ear) or (A)
word (eam) ← (eam) or (A)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
R
R
R
R
R
R
–
–
–
–
–
–
–
–
–
–
*
*
XORW
XORW
XORW
XORW
XORW
XORW
NOTW
NOTW
NOTW
A
A, #imm16
A, ear
A, eam
ear, A
eam, A
A
ear
eam
1
2
0
3
2
0
2
2
0
2+ 3+ (a) (c)
2
3
0
2+ 3+ (a) 2× (c)
1
2
0
2
2
0
2+ 3+ (a) 2× (c)
word (A) ← (AH) xor (A)
word (A) ← (A) xor imm16
word (A) ← (A) xor (ear)
word (A) ← (A) xor (eam)
word (ear) ← (ear) xor (A)
word (eam) ← (eam) xor (A)
word (A) ← not (A)
word (ear) ← not (ear)
word (eam) ← not (eam)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
R
R
R
R
R
R
R
R
R
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
–
*
*
For an explanation of “(a)”, “(b)”, “(c)” and “(d)”, refer to Table 4, “Number of Execution Cycles for Each Form of
Addressing,” and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
72
MB90230 Series
Table 15
Mnemonic
#
~
Logical 2 Instructions (Long Word) [6 Instructions]
B
Operation
LH AH
I
S
T
N
Z
V
C
RMW
ANDL A, ear
ANDL A, eam
2
5
2+ 6+ (a)
0
(d)
long (A) ← (A) and (ear)
long (A) ← (A) and (eam)
–
–
–
–
–
–
–
–
–
–
*
*
*
*
R
R
–
–
–
–
ORL
ORL
A, ear
A, eam
2
5
2+ 6+ (a)
0
(d)
long (A) ← (A) or (ear)
long (A) ← (A) or (eam)
–
–
–
–
–
–
–
–
–
–
*
*
*
*
R
R
–
–
–
–
XORL A, ear
XORL A, eam
2
5
2+ 6+ (a)
0
(d)
long (A) ← (A) xor (ear)
long (A) ← (A) xor (eam)
–
–
–
–
–
–
–
–
–
–
*
*
*
*
R
R
–
–
–
–
For an explanation of “(a)” and “(d)”, refer to Table 4, “Number of Execution Cycles for Each Form of Addressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
Table 16
Mnemonic
Sign Inversion Instructions (Byte/Word) [6 Instructions]
#
~
B
2
0
Operation
byte (A) ← 0 – (A)
NEG
A
1
NEG
NEG
ear
eam
2
2
0
byte (ear) ← 0 – (ear)
2+ 3+ (a) 2× (b) byte (eam) ← 0 – (eam)
2
0
word (A) ← 0 – (A)
NEGW A
1
NEGW ear
NEGW eam
2
2
0
word (ear) ← 0 – (ear)
2+ 3+ (a) 2× (c) word (eam) ← 0 – (eam)
LH AH
I
S
T
N
Z
V
C
RMW
X
–
–
–
–
*
*
*
*
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
–
–
–
–
–
*
*
*
*
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
For an explanation of “(a)”, “(b)” and “(c)” and refer to Table 4, “Number of Execution Cycles for Each Form of
Addressing,” and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
Table 17
Mnemonic
ABS
A
ABSW A
ABSL A
Absolute Value Instructions (Byte/Word/Long Word) [3 Insturctions]
#
~
B
Operation
2
2
2
2
2
4
0
0
0
byte (A) ← absolute value (A)
word (A) ← absolute value (A)
long (A) ← absolute value (A)
Table 18
Mnemonic
#
~
B
NRML A, R0
2
*
0
LH AH
I
S
T
N
Z
V
C
RMW
Z
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
–
–
–
–
–
–
–
–
–
Normalize Instructions (Long Word) [1 Instruction]
Operation
long (A) ← Shifts to the position at
which “1” was set first
byte (R0) ← current shift count
LH AH
–
–
I
S
T
N
Z
V
C
RMW
–
–
*
–
–
–
–
–
* : 5 when the contents of the accumulator are all zeroes, 5 + (R0) in all other cases.
73
MB90230 Series
Table 19
Mnemonic
Shift Instructions (Byte/Word/Long Word) [27 Instructions]
#
~
B
RORC A
ROLC A
2
2
2
2
0
0
RORC
RORC
ROLC
ROLC
ear
eam
ear
eam
2
2
0
2+ 3+ (a) 2× (b)
2
2
0
2+ 3+ (a) 2× (b)
ASR
LSR
LSL
A, R0
A, R0
A, R0
2
2
2
*1
*1
*1
ASR
LSR
LSL
A, #imm8 3
A, #imm8 3
A, #imm8 3
Operation
LH AH
I
S
T
N
Z
V
C
RMW
byte (A) ← Right rotation with carry
byte (A) ← Left rotation with carry
–
–
–
–
–
–
–
–
–
–
*
*
*
*
–
–
*
*
–
–
byte (ear) ← Right rotation with carry
byte (eam) ← Right rotation with carry
byte (ear) ← Left rotation with carry
byte (eam) ← Left rotation with carry
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
–
–
–
–
*
*
*
*
*
*
*
*
0
0
0
byte (A) ← Arithmetic right barrel shift (A, R0)
byte (A) ← Logical right barrel shift (A, R0)
byte (A) ← Logical left barrel shift (A, R0)
–
–
–
–
–
–
–
–
–
–
–
–
*
*
–
*
*
*
*
*
*
–
–
–
*
*
*
–
–
–
*3
*3
*3
0
0
0
byte (A) ← Arithmetic right barrel shift (A, imm8)
byte (A) ← Logical right barrel shift (A, imm8)
byte (A) ← Logical left barrel shift (A, imm8)
–
–
–
–
–
–
–
–
–
–
–
–
*
*
–
*
*
*
*
*
*
–
–
–
*
*
*
–
–
–
LSRW A/SHRW A 1
LSLW A/SHLW A 1
2
2
2
0
0
0
word (A) ← Arithmetic right shift (A, 1 bit)
word (A) ← Logical right shift (A, 1 bit)
word (A) ← Logical left shift (A, 1 bit)
–
–
–
–
–
–
–
–
–
–
–
–
* *
* R
– *
*
*
*
–
–
–
*
*
*
–
–
–
2
2
2
*1
*1
*1
0
0
0
word (A) ← Arithmetic right barrel shift (A, R0) –
–
–
–
–
–
–
–
–
–
*
*
–
*
*
*
*
*
*
–
–
–
*
*
*
–
–
–
ASRW A, #imm8 3
LSRW A, #imm8 3
LSLW A, #imm8 3
*3
*3
*3
0
0
0
word (A) ← Arithmetic right barrel shift (A, imm8)
word (A) ← Logical right barrel shift (A, imm8)
–
–
–
–
–
–
–
–
–
–
–
–
*
*
–
*
*
*
*
*
*
–
–
–
*
*
*
–
–
–
ASRL A, R0
LSRL A, R0
LSLL A, R0
2
2
2
*2
*2
*2
0
0
0
long (A) ← Arithmetic right shift (A, R0)
–
long (A) ← Logical right barrel shift (A, R0) –
long (A) ← Logical left barrel shift (A, R0) –
–
–
–
–
–
–
–
–
–
*
*
–
*
*
*
*
*
*
–
–
–
*
*
*
–
–
–
A, #imm8 3
A, #imm8 3
A, #imm8 3
*4
*4
*4
0
0
0
long (A) ← Arithmetic right shift (A, imm8) –
long (A) ← Logical right barrel shift (A, imm8) –
long (A) ← Logical left barrel shift (A, imm8) –
–
–
–
–
–
–
–
–
–
*
*
–
*
*
*
*
*
*
–
–
–
*
*
*
–
–
–
ASRW A
ASRW A, R0
LSRW A, R0
LSLW A, R0
ASRL
LSRL
LSLL
1
word (A) ← Logical right barrel shift (A, R0) –
word (A) ← Logical left barrel shift (A, R0) –
word (A) ← Logical left barrel shift (A, imm8)
For an explanation of “(a)” and “(b)”, refer to Table 4, “Number of Execution Cycles for Each Form of Addressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
*1:
*2:
*3:
*4:
74
3 when R0 is 0, 3 + (R0) in all other cases.
3 when R0 is 0, 4 + (R0) in all other cases.
3 when imm8 is 0, 3 + (imm8) in all other cases.
3 when imm8 is 0, 4 + (imm8) in all other cases.
MB90230 Series
Table 20
Mnemonic
BZ/BEQ
BNZ/BNE
BC/BLO
BNC/BHS
BN
rel
BP
rel
BV
rel
BNV
rel
BT
rel
BNT
rel
BLT
rel
BGE
rel
BLE
rel
BGT
rel
BLS
rel
BHI
rel
BRA
rel
rel
rel
rel
rel
#
~
B
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
1
*
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
3
2
2+
2
2+
4
2
2
3
4+ (a)
3
4+ (a)
3
0
0
0
(c)
0
(d)
0
JMP
JMP
JMP
JMP
JMPP
JMPP
JMPP
@A
addr16
@ear
@eam
@ear *3
@eam *3
addr24
CALL
CALL
CALL
CALLV
CALLP
@ear *4
2
@eam *4 2+
addr16 *5 3
1
#vct4 *5
2
@ear *6
4
(c)
5+ (a) 2× (c)
5
(c)
5
2× (c)
7
2× (c)
CALLP @eam *6
2+
8+ (a)
*2
CALLP addr24 *7
4
7
2× (c)
Branch 1 Instructions [31 Instructions]
Operation
LH AH
I
S
T
N
Z
V
C
RMW
Branch when (Z) = 1
Branch when (Z) = 0
Branch when (C) = 1
Branch when (C) = 0
Branch when (N) = 1
Branch when (N) = 0
Branch when (V) = 1
Branch when (V) = 0
Branch when (T) = 1
Branch when (T) = 0
Branch when (V) xor (N) = 1
Branch when (V) xor (N) = 0
( (V) xor (N) ) or (Z) = 1
( (V) xor (N) ) or (Z) = 0
Branch when (C) or (Z) = 1
Branch when (C) or (Z) = 0
Branch unconditionally
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
word (PC) ← (A)
word (PC) ← addr16
word (PC) ← (ear)
word (PC) ← (eam)
word (PC) ← (ear), (PCB) ← (ear +2)
word (PC) ← (eam), (PCB) ← (eam +2)
word (PC) ← ad24 0 to 15
(PCB) ← ad24 16 to 23
word (PC) ← (ear)
word (PC) ← (eam)
word (PC) ← addr16
Vector call linstruction
word (PC) ← (ear) 0 to 15,
(PCB) ← (ear) 16 to 23
word (PC) ← (eam) 0 to 15,
(PCB) ← (eam) 16 to 23
word (PC) ← addr 0 to 15,
(PCB) ← addr 16 to 23
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
For an explanation of “(a)”, “(c)” and “(d)”, refer to Table 4, “Number of Execution Cycles for Each Form of Addressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
*1:
*2:
*3:
*4:
*5:
*6:
*7:
3 when branching, 2 when not branching.
3 × (c) + (b)
Read (word) branch address.
W: Save (word) to stack; R: Read (word) branch address.
Save (word) to stack.
W: Save (long word) to W stack; R: Read (long word) branch address.
Save (long word) to stack.
75
MB90230 Series
Table 21
Mnemonic
#
~
B
CBNE A, #imm8, rel 3
CWBNE A, #imm16, rel 4
1
0
0
4
4+
5
5+
*
*1
*1
*3
*1
*3
CBNE
CBNE
CWBNE
CWBNE
ear, #imm8, rel
eam, #imm8, rel
ear, #imm16, rel
eam, #imm16, rel
DBNZ
ear, rel
3
*4
DBNZ
eam, rel
3+
*2
DWBNZ ear, rel
3
*4
DWBNZ eam, rel
3+
INT
#vct8
INT
addr16
INTP
addr24
INT9
RETI
RETIQ *6
2
3
4
1
1
2
LINK
2
#imm8
*2
14
12
13
14
9
11
6
1
1
I
S
T
N
Z
V
C
RMW
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
–
–
Branch when byte (ear) ≠ imm8
Branch when byte (eam) ≠ imm8
Branch when word (ear) ≠ imm16
Branch when word (eam) ≠ imm16
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
Branch when byte (ear) =
(ear) – 1, and (ear) ≠ 0
2× (b) Branch when byte (ear) =
(eam) – 1, and (eam) ≠ 0
0 Branch when word (ear) =
(ear) – 1, and (ear) ≠ 0
2× (c) Branch when word (eam) =
(eam) – 1, and (eam) ≠ 0
–
–
–
–
–
*
*
*
–
–
–
–
–
–
–
*
*
*
–
*
–
–
–
–
–
*
*
*
–
–
–
–
–
–
–
*
*
*
–
*
Software interrupt
Software interrupt
Software interrupt
Software interrupt
Return from interrupt
Return from interrupt
–
–
–
–
–
–
–
–
–
–
–
–
R
R
R
R
*
*
S
S
S
S
*
*
–
–
–
–
*
*
–
–
–
–
*
*
–
–
–
–
*
*
–
–
–
–
*
*
–
–
–
–
*
*
–
–
–
–
–
–
At constant entry, save old
frame pointer to stack, set
new frame pointer, and
allocate local pointer area
At constant entry, retrieve old
frame pointer from stack.
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Return from subroutine
Return from subroutine
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
0
(b)
0
(c)
0
8× (c)
6× (c)
6× (c)
8× (c)
6× (c)
*5
(c)
4
5
RET *7
RETP *8
LH AH
–
–
(c)
1
Operation
Branch when byte (A) ≠ imm8
Branch when byte (A) ≠ imm16
5
UNLINK
Branch 2 Instructions [20 Instructions]
(c)
(d)
For an explanation of “(b)”, “(c)” and “(d)”, refer to Table 5, “Correction Values for Number of Cycles Used to Calculate
Number of Actual Cycles.”
*1:
*2:
*3:
*4:
*5:
*6:
4 when branching, 3 when not branching
5 when branching, 4 when not branching
5 + (a) when branching, 4 + (a) when not branching
6 + (a) when branching, 5 + (a) when not branching
3 × (b) + 2 × (c) when an interrupt request is generated, 6 × (c) when returning from the interrupt.
High-speed interrupt return instruction. When an interrupt request is detected during this instruction, the
instruction branches to the interrupt vector without performing stack operations when the interrupt is generated.
*7: Return from stack (word)
*8: Return from stack (long word)
76
MB90230 Series
Table 22
Mnemonic
Other Control Instructions (Byte/Word/Long Word) [36 Instructions]
#
~
B
Operation
LH AH
I
S
T
N
Z
V
C
RMW
PUSHW
PUSHW
PUSHW
PUSHW
A
AH
PS
rlst
1
1
1
2
3
3
3
*3
(c)
(c)
(c)
*4
word (SP) ← (SP) –2, ((SP)) ← (A)
word (SP) ← (SP) –2, ((SP)) ← (AH)
word (SP) ← (SP) –2, ((SP)) ← (PS)
(SP) ← (SP) –2n, ((SP)) ← (rlst)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
POPW
POPW
POPW
POPW
A
AH
PS
rlst
1
1
1
2
3
3
3
*2
(c)
(c)
(c)
*4
word (A) ← ((SP)), (SP) ← (SP) +2
word (AH) ← ((SP)), (SP) ← (SP) +2
word (PS) ← ((SP)), (SP) ← (SP) +2
(rlst) ← ((SP)) , (SP) ← (SP)
–
–
–
–
*
–
–
–
–
–
*
–
–
–
*
–
–
–
*
–
–
–
*
–
–
–
*
–
–
–
*
–
–
–
*
–
–
–
–
–
JCTX
@A
1
9
–
–
*
*
*
*
*
*
*
–
AND
OR
CCR, #imm8 2
CCR, #imm8 2
3
3
0
0
byte (CCR) ← (CCR) and imm8 –
–
byte (CCR) ← (CCR) or imm8
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
2
2
0
0
byte (RP) ← imm8
byte (ILM) ← imm8
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
6× (c) Context switch instruction
MOV RP, #imm8
MOV ILM, #imm8
2
2
MOVEA RWi, ear
MOVEA RWi, eam
MOVEA A, ear
MOVEA A, eam
2
3
2+ 2+ (a)
2
2
2+ 1+ (a)
0
0
0
0
word (RWi) ← ear
word (RWi) ← eam
word(A) ← ear
word (A) ← eam
–
–
–
–
–
–
*
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
ADDSP #imm8
ADDSP #imm16
2
3
3
3
0
0
word (SP) ← ext (imm8)
word (SP) ← imm16
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
MOV
MOV
A, brgl
brg2, A
MOV
brg2, #imm8
2
2
3
*1
1
2
0
0
0
byte (A) ← (brgl)
byte (brg2) ← (A)
byte (brg2) ← imm8
Z
–
–
*
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
–
–
–
–
–
–
–
–
–
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
No operation
Prefix code for the common register bank
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
MOVW SPCU, #imm16 4
MOVW SPCL, #imm16 4
0
0
0
0
word (SPCU) ← (imm16)
word (SPCL) ← (imm16)
Stack check operation enable
Stack check operation disable
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
0
0
0
byte (A) ← position of “1” bit in word (A)
byte (A) ← position of “1” bit in word (A) × 2
byte (A) ← position of “1” bit in word (A) × 4
Z
Z
Z
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
–
–
–
–
–
–
–
–
–
NOP
ADB
DTB
PCB
SPB
NCC
CMR
SETSPC
CLRSPC
2
2
2
2
2
2
BTSCN A
BTSCNSA
BTSCNDA
2
2
2
*5
*6
*7
Prefix code for AD space access
Prefix code for DT space access
Prefix code for PC space access
Prefix code for SP space access
Prefix code for no flag change
For an explanation of “(a)” and “(c)”, refer to Tables 4 and 5.
*1: PCB, ADB, SSB, USB, and SPB: 1 cycle
DTB: 2 cycles
DPR: 3 cycles
*2: 3 + 4 × (pop count)
*3: 3 + 4 × (push count)
*4:
*5:
*6:
*7:
Pop count × (c), or push count × (c)
3 when AL is 0, 5 when AL is not 0.
4 when AL is 0, 6 when AL is not 0.
5 when AL is 0, 7 when AL is not 0.
77
MB90230 Series
Table 23
Bit Manipulation Instructions [21 Instructions]
Mnemonic
#
~
B
MOVB A, dir:bp
MOVB A, addr16:bp
MOVB A, io:bp
3
4
3
3
3
3
(b)
(b)
(b)
MOVB dir:bp, A
MOVB addr16:bp, A
MOVB io:bp, A
3
4
3
4
4
4
SETB
SETB
SETB
dir:bp
addr16:bp
io:bp
3
4
3
CLRB
CLRB
CLRB
dir:bp
addr16:bp
io:bp
BBC
BBC
BBC
Operation
LH AH
I
S
T
N
Z
V
C
RMW
Z
Z
Z
*
*
*
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
–
–
–
–
–
–
–
–
–
2× (b) bit (dir:bp) b ← (A)
2× (b) bit (addr16:bp) b ← (A)
2× (b) bit (io:bp) b ← (A)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
–
–
–
–
–
–
*
*
*
4
4
4
2× (b) bit (dir:bp) b ← 1
2× (b) bit (addr16:bp) b ← 1
2× (b) bit (io:bp) b ← 1
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
3
4
3
4
4
4
2× (b) bit (dir:bp) b ← 0
2× (b) bit (addr16:bp) b ← 0
2× (b) bit (io:bp) b ← 0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
dir:bp, rel
addr16:bp, rel
io:bp, rel
4
5
4
*1
*1
*1
(b)
(b)
(b)
Branch when (dir:bp) b = 0
Branch when (addr16:bp) b = 0
Branch when (io:bp) b = 0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
–
–
–
–
–
–
–
–
–
BBS
BBS
BBS
dir:bp, rel
addr16:bp, rel
io:bp, rel
4
5
4
*1
*1
*1
(b)
(b)
(b)
Branch when (dir:bp) b = 1
Branch when (addr16:bp) b = 1
Branch when (io:bp) b = 1
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
–
–
–
–
–
–
–
–
–
SBBS
addr16:bp, rel
5
*2
2× (b)
Branch when (addr16:bp) b = 1, bit = 1
–
–
–
–
–
–
*
–
–
*
WBTS io:bp
3
*3
*4
Wait until (io:bp) b = 1
–
–
–
–
–
–
–
–
–
–
WBTC io:bp
3
*3
*4
Wait until (io:bp) b = 0
–
–
–
–
–
–
–
–
–
–
byte (A) ← (dir:bp) b
byte (A) ← (addr16:bp) b
byte (A) ← (io:bp) b
For an explanation of “(b)”, refer to Table 5, “Correction Values for Number of Cycles Used to Calculate Number of
Actual Cycles.”
*1:
*2:
*3:
*4:
78
5 when branching, 4 when not branching
7 when condition is satisfied, 6 when not satisfied
Undefined count
Until condition is satisfied
MB90230 Series
Table 24
Mnemonic
SWAP
SWAPW
EXT
EXTW
ZEXT
ZEXTW
Accumulator Manipulation Instructions (Byte/Word) [6 Instructions]
#
~
B
1
1
1
1
1
1
3
2
1
2
1
2
0
0
0
0
0
0
Operation
byte (A) 0 to 7 ← → (A) 8 to 15
word (AH) ← → (AL)
Byte code extension
Word code extension
Byte zero extension
Word zero extension
Table 25
LH AH
I
S
T
N
Z
V
C
RMW
–
–
X
–
Z
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
R
R
–
–
*
*
*
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
I
S
T
N
Z
V
C
RMW
–
*
–
X
–
Z
String Instructions [10 Instructions]
Mnemonic
#
~
B
MOVS/MOVSI
MOVSD
2
2
*2
*2
*3 Byte transfer @AH+ ← @AL+, counter = RW0 –
*3 Byte transfer @AH– ← @AL–, counter = RW0 –
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
SCEQ/SCEQI
SCEQD
2
2
*1
*1
*4 Byte retrieval @AH+ – AL, counter = RW0
*4 Byte retrieval @AH– – AL, counter = RW0
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
–
–
FILS/FILSI
2 5m +3 *5 Byte filling @AH+ ← AL, counter = RW0
–
–
–
–
–
*
*
–
–
–
MOVSW/MOVSWI
2
2
*2
*2
*6 Word transfer @AH+ ← @AL+, counter = RW0
*6 Word transfer @AH– ← @AL–, counter = RW0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
SCWEQD
2
2
*1
*1
*7 Word retrieval @AH+ – AL, counter = RW0
*7 Word retrieval @AH– – AL, counter = RW0
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
–
–
FILSW/FILSWI
2 5m +3 *8 Word filling @AH+ ← AL, counter = RW0
–
–
–
–
–
*
*
–
–
–
MOVSWD
SCWEQ/SCWEQI
Operation
LH AH
m: RW0 value (counter value)
*1:
*2:
*3:
*4:
*5:
*6:
*7:
*8:
3 when RW0 is 0, 2 + 6 × (RW0) for count out, and 6n + 4 when match occurs
4 when RW0 is 0, 2 + 6 × (RW0) in any other case
(b) × (RW0)
(b) × n
(b) × (RW0)
(c) × (RW0)
(c) × n
(c) × (RW0)
79
MB90230 Series
Table 26
Mnemonic
MOVM
MOVM
MOVM
MOVM
MOVMW
MOVMW
MOVMW
MOVMW
MOVM
MOVM
MOVM
MOVM
MOVMW
MOVMW
MOVMW
MOVMW
MOVM
@A, @RLi, #imm8
@A, eam, #imm8
addr16, @RLi, #imm8
addr16, eam, #imm8
@A, @RLi, #imm8
@A, eam, #imm8
addr16, @RLi, #imm8
addr16, eam, #imm8
@RLi, @A, #imm8
eam, @A, #imm8
@RLi, addr16, #imm8
eam, addr16, #imm8
@RLi, @A, #imm8
eam, @A, #imm8
@RLi, addr16, #imm8
eam, addr16, #imm8
bnk : addr16, *5
bnk : addr16, #imm8
MOVMW bnk : addr16, *5
bnk : addr16, #imm8
#
Multiple Data Transfer Instructions [18 Instructions]
~
B
1
3
3
3+
5
5+
3
3+
5
5+
3
3+
5
5+
3
3+
5
5+
7
*
*2
*1
*2
*1
*2
*1
*2
*1
*2
*1
*2
*1
*2
*1
*2
*1
*
*3
*3
*3
*4
*4
*4
*4
*3
*3
*3
*3
*4
*4
*4
*4
*3
7
*1
*4
Operation
Multiple data trasfer byte ((A)) ← ((RLi))
Multiple data trasfer byte ((A)) ← (eam)
Multiple data trasfer byte (addr16) ← ((RLi))
Multiple data trasfer byte (addr16) ← (eam)
Multiple data trasfer word ((A)) ← ((RLi))
Multiple data trasfer word ((A)) ← (eam)
Multiple data trasfer word (addr16) ← ((RLi))
Multiple data trasfer word (addr16) ← (eam)
Multiple data trasfer byte ((RLi)) ← ((A))
Multiple data trasfer byte (eam) ← ((A))
Multiple data transfer byte ((RLi)) ← (addr16)
Multiple data transfer byte (eam) ← (addr16)
Multiple data trasfer word ((RLi)) ← ((A))
Multiple data trasfer word (eam) ← ((A))
Multiple data transfer word ((RLi)) ← (addr16)
Multiple data transfer word (eam) ← (addr16)
Multiple data transfer
byte (bnk:addr16) ← (bnk:addr16)
Multiple data transfer
word (bnk:addr16) ← (bnk:addr16)
LH AH
S
T
N
Z
V
C RMW
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*1: 5 + imm8 × 5, 256 times when imm8 is zero.
*2: 5 + imm8 × 5 + (a), 256 times when imm8 is zero.
*3: Number of transfers × (b) × 2
*4: Number of transfers × (c) × 2
*5:The bank register specified by “bnk” is the same as for the MOVS instruction.
80
I
MB90230 Series
■ ORDERING INFORMATION
Model
Package
Remarks
MB90233PFV-XXX
MB90234PFV-XXX
100-pin Plastic LQFP
(FPT-100P-M05)
MB90234PFV
100-pin Plastic LQFP
(FPT-100P-M05)
Only ES
100-pin Ceramic SQFP
(FPT-100C-C01)
Only ES
MB90W234ZFV
81
MB90230 Series
■ PACKAGE DIMENSIONS
100-pin Plastic LQFP
(FPT-100P-M05)
+0.20
16.00±0.20(.630±.008)SQ
75
1.50 −0.10 (Mounting height)
+.008
.059 −.004
51
14.00±0.10(.551±.004)SQ
76
50
12.00
(.472)
REF
15.00
(.591)
NOM
Details of "A" part
0.15(.006)
INDEX
100
0.15(.006)
26
0.15(.006)MAX
LEAD No.
"B"
25
1
0.40(.016)MAX
"A"
0.50(.0197)TYP
0.18
.007
+0.08
−0.03
+.003
−.001
0.08(.003)
0.127
.005
M
+0.05
−0.02
+.002
−.001
Details of "B" part
0.10±0.10
(STAND OFF)
(.004±.004)
0.50±0.20(.020±.008)
0.10(.004)
0~10˚
1995 FUJITSU LIMITED F100007S-2C-3
C
Dimensions in mm (inches)
100-pin Ceramic LQFP
(FPT-100C-C01)
16.00±0.20 SQ
(.630±.008)
+0.25
13.60 −0.15 SQ
+.010
.535 −.006
12.00(.472)REF
1.70(.067)MAX
(Mounting height)
0.50(.0197)TYP
0.20±0.05
(.008±.002)
0.90(.035)REF
Details of "A" part
15.00±0.25 SQ
(.591±0.10)
0.125±0.05
(.005±.002)
0(0)MIN
STAND OFF
INDEX AREA
0.50±0.20
(.020±.008)
"A"
C
82
1995 FUJITSU LIMITED F100015SC-1-3
Dimensions in mm (inches)
MB90230 Series
FUJITSU LIMITED
For further information please contact:
Japan
FUJITSU LIMITED
Corporate Global Business Support Division
Electronic Devices
KAWASAKI PLANT, 4-1-1, Kamikodanaka
Nakahara-ku, Kawasaki-shi
Kanagawa 211-8588, Japan
Tel: 81(44) 754-3763
Fax: 81(44) 754-3329
http://www.fujitsu.co.jp/
North and South America
FUJITSU MICROELECTRONICS, INC.
Semiconductor Division
3545 North First Street
San Jose, CA 95134-1804, USA
Tel: (408) 922-9000
Fax: (408) 922-9179
Customer Response Center
Mon. - Fri.: 7 am - 5 pm (PST)
Tel: (800) 866-8608
Fax: (408) 922-9179
http://www.fujitsumicro.com/
Europe
FUJITSU MIKROELEKTRONIK GmbH
Am Siebenstein 6-10
D-63303 Dreieich-Buchschlag
Germany
Tel: (06103) 690-0
Fax: (06103) 690-122
http://www.fujitsu-ede.com/
Asia Pacific
FUJITSU MICROELECTRONICS ASIA PTE LTD
#05-08, 151 Lorong Chuan
New Tech Park
Singapore 556741
Tel: (65) 281-0770
Fax: (65) 281-0220
http://www.fmap.com.sg/
All Rights Reserved.
The contents of this document are subject to change without
notice. Customers are advised to consult with FUJITSU sales
representatives before ordering.
The information and circuit diagrams in this document are
presented as examples of semiconductor device applications,
and are not intended to be incorporated in devices for actual use.
Also, FUJITSU is unable to assume responsibility for
infringement of any patent rights or other rights of third parties
arising from the use of this information or circuit diagrams.
FUJITSU semiconductor devices are intended for use in
standard applications (computers, office automation and other
office equipment, industrial, communications, and
measurement equipment, personal or household devices, etc.).
CAUTION:
Customers considering the use of our products in special
applications where failure or abnormal operation may directly
affect human lives or cause physical injury or property damage,
or where extremely high levels of reliability are demanded
(such as aerospace systems, atomic energy controls, sea floor
repeaters, vehicle operating controls, medical devices for life
support, etc.) are requested to consult with FUJITSU sales
representatives before such use. The company will not be
responsible for damages arising from such use without prior
approval.
Any semiconductor devices have an inherent chance of
failure. You must protect against injury, damage or loss from
such failures by incorporating safety design measures into your
facility and equipment such as redundancy, fire protection, and
prevention of over-current levels and other abnormal operating
conditions.
If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Law of Japan, the prior
authorization by Japanese government will be required for
export of those products from Japan.
F9901
 FUJITSU LIMITED Printed in Japan
83