FUJITSU SEMICONDUCTOR DATA SHEET DS07-13710-2E 16-bit Proprietary Microcontroller CMOS F2MC-16LX MB90580C Series MB90583C/583CA/F583C/F583CA/587C/587CA/V580B ■ DESCRIPTION The MB90580C series is a line of general-purpose, Fujitsu 16-bit microcontrollers designed for process control applications which require high-speed real-time processing, such as consumer products. While inheriting the AT architecture of the F2MC*1 family, the instruction set for the F2MC-16LX CPU core of the MB90580C series incorporates additional instructions for high-level languages, supports extended addressing modes, and contains enhanced multiplication and division instructions as well as a substantial collection of improved bit manipulation instructions. In addition, the MB90580C has an on-chip 32-bit accumulator which enables processing of long-word data. The peripheral resources integrated in the MB90580C series include: an 8/10-bit A/D converter, an 8-bit D/A converter, UARTs (SCI) 0 to 4, an 8/16-bit PPG timer, 16-bit I/O timers (16-bit free-run timer, input capture units (ICUs) 0 to 3, output compare units (OCUs) 0 and 1), and an IEBusTM controller *2. Notes: *1: F2MC stands for FUJITSU Flexible Microcontroller, a registered trademark of FUJITSU LIMITED. *2: IEBusTM is a trademark of NEC Corporation. ■ FEATURES • Minimum execution time: 62.5 ns/4 MHz oscillation (Uses PLL clock multiplication) maximum multiplier = 4 • Maximum memory space 16 Mbyte Linear/bank access (Continued) ■ PACKAGES 100-pin plastic LQFP 100-pin plastic QFP (FPT-100P-M05) (FPT-100P-M06) MB90580C Series (Continued) • Instruction set optimized for controller applications Supported data types: bit, byte, word, and long-word types Standard addressing modes: 23 types 32-bit accumulator enhancing high-precision operations Signed multiplication/division and extended RETI instructions • Enhanced high level language (C) and multitasking support instructions Use of a system stack pointer Symmetrical instruction set and barrel shift instructions • Program patch function (for two address pointers) • Enhanced execution speed: 4 byte instruction queue • Enhanced interrupt function Up to eight priority levels programmable External interrupt inputs: 8 lines • Automatic data transmission function independent of CPU operation Up to 16 channels for the extended intelligent I/O service DTP request inputs: 8 lines • Internal ROM FLASH: 128 Kbyte MASKROM: 128 Kbyte (MB90583C/CA) , 64 Kbyte (MB90587C/CA) • Internal RAM FLASH: 6 Kbyte MASKROM: 6 Kbyte (MB90583C/CA) , 4 Kbyte (MB90587C/CA) • General-purpose ports Up to 77 channels (Input pull-up resistor settable for: 22 channels. Output open drain settable for: 8 channels) • IEBusTM controller* Three different data transfer rates selectable Mode 0: 3.9 Kbps (16 bytes/frame) Mode 1: 17.0 Kbps (32 bytes/frame) Mode 2: 26.0 Kbps (128 bytes/frame) *: IEBusTM is a trademark of NEC Corporation. • A/D Converter (RC) : 8 ch 8/10-bit resolution Conversion time: 34.7 µs (Min.) , 12 MHz operation • D/A Converter: 2 ch 8-bit resolutions Setup time: 12.5 µs • UART : 5 ch • 8/16 bit PPG : 1 ch 8 bits × 2 channels: 16 bits × 1 channel: Mode switching function provided • 16 bit reload timer: 3 ch • 16-bit PWC timer: 1 channel Noise filter provided. Available to pulse width counter • 16 bit I/O timer Input capture : 4 ch Output compare : 2 ch Free run timer: 1 ch • Internal clock generator • Time-base counter/watchdog timer: 18-bit (Continued) 2 MB90580C Series (Continued) • Clock monitor function integrated • Low-power consumption mode Sleep mode Stop mode Hardware standby mode CPU intermittent operation mode • Package: LQFP-100 / QFP-100 • CMOS technology 3 MB90580C Series ■ PRODUCT LINEUP Part number Item Classification MB90587C/CA MB90583C/CA Mass-produced products (MASK ROM) MB90F583C/CA MB90V580B Mass-produced products (Flash ROM) Development/ evaluation product ROM size 64 Kbytes 128 Kbytes 128 Kbytes None RAM size 4 Kbytes 6 Kbytes 6 Kbytes 6 Kbytes Two clocks / one clock system Two clocks system None Clock*1 Emulator-specific power supply *2 Two clocks / Two clocks / one clock system one clock system CPU functions The number of instructions: 340 Instruction bit length: 8 bits, 16 bits Instruction length: 1 byte to 7 bytes Data bit length: 1 bit, 8 bits, 16 bits Minimum execution time: 62.5 ns (at machine clock of 16 MHz) Interrupt processing time: 1.5 ms (at machine clock of 16 MHz, minimum value) Ports General-purpose I/O ports (CMOS output) General-purpose I/O port (Can be set as open-drain) General-purpose I/O ports (Input pull-up resistors available) Total: IEBusTM controller None : 45 : 8 : 22 : 77 Communication mode: Half-duplex, asynchronous communication Multi-master system Access control: CDMA/CD Three modes selectable for different transmission speeds Transmit buffer: 8-byte FIFO buffer Receive buffer: 8-byte FIFO buffer Timebase timer 18-bit counter Interrupt interval: 1.024 ms, 4.096 ms, 16.384 ms, 131.072 ms (At oscillation of 4 MHz) Watchdog timer Reset generation interval: 3.58 ms, 14.33 ms, 57.23 ms, 458.75 ms (at oscillation of 4 MHz, minimum value) Clock timer 15-bit counter Interrupt interval: 1 s, 0.5 s, 0.25 s, 31.25 ms (At oscillation of 32.768 kHz) 8/16-bit PPG timer Number of channels: 1 (8-bit × 2 channels) PPG operation of 8-bit or 16-bit A pulse wave of given intervals and given duty ratios can be output. Pulse interval: 62.5 ns to 1 ms (at oscillation of 4 MHz, machine clock of 16 MHz) 16-bit reload timer Number of channels: 3 Event count provided Interval: 125 ns to 131 ms (at oscillation of 4 MHz, machine clock of 16 MHz) PWC timer Number of channels: 1 Timer function (select the counter timer from three internal clocks.) Pulse width measuring function (select the counter timer from three internal clocks.) (Continued) 4 MB90580C Series (Continued) Part number MB90587C/CA Item 16-bit I/O timer MB90583C/CA MB90F583C/CA MB90V580B 16-bit free run timer Number of channels: 1 Overflow interrupts Output compare (OCU) Number of channels: 2 Pin input factor: A match signal of compare register Input capture (ICU) Number of channels: 4 Rewriting a register value upon a pin input (rising, falling, or both edges) Number of inputs: 8 DTP/external interrupt circuit Started by a rising edge, a falling edge, an “H” level input, or an “L” level input. External interrupt circuit or extended intelligent I/O service (EI2OS) can be used. Delayed interrupt generation module An interrupt generation module for switching tasks used in real time operating systems. UART0, 1, 2, 3, 4 Clock synchronized transmission (62.5 Kbps to 1 Mbps) Clock asynchronized transmission (1202 bps to 9615 bps) Transmission can be performed by bi-directional serial transmission or by master/ slave connection. A/D converter Resolution: 8/10-bit changeable Number of inputs: 8 One-shot conversion mode (converts selected channel only once) Scan conversion mode (converts two or more successive channels and can program up to 8 channels.) Continuous conversion mode (converts selected channel repeatedly) Stop conversion mode (converts selected channel and stop operation repeatedly) D/A converter 8-bit resolution Number of channels: 2 channels Based on the R-2R system Low-power consumption (standby) mode Sleep/stop/CPU intermittent operation/clock timer/hardware standby Process CMOS Power supply voltage for operation 4.5 V to 5.5 V*3 *1: Connect the oscillator to both terminals XA0 and XA1 for MB90F587C / 583C / F583C. *2: It is setting of DIP switch S2 when Emulation pod (MB2145-507) is used. Please refer to the MB2145-507 hardware manual (2.7 Emulator-specific Power Pin) about details. *3: Varies with conditions such as the operating frequency (See section “■ ELECTRICAL CHARACTERISTICS”). Assurance for the MB90V580B is given only for operation with a tool at a power supply voltage of 4.5 V to 5.5 V, an operating temperature of 0 to +25 °C, and an operating frequency of 1 MHz to 16 MHz. ■ PACKAGE AND CORRESPONDING PRODUCTS Package MB90583C/CA MB90587C/CA MB90F583C/CA FPT-100P-M05 FTP-100P-M06 : Available ×: Not available Note: For more information about each package, see section “■ PACKAGE DIMENSIONS”. 5 MB90580C Series ■ DIFFERENCES AMONG PRODUCTS Memory Size In evaluation with an evaluation product, note the difference between the evaluation product and the product actually used. The following items must be taken into consideration. • The MB90V580B does not have an internal ROM, however, operations equivalent to chips with an internal ROM can be evaluated by using a dedicated development tool, enabling selection of ROM size by settings of the development tool. • In the MB90V580B, images from FF4000H to FFFFFFH are mapped to bank 00, and FE0000H to FF3FFFH to mapped to bank FE and FF only. (This setting can be changed by configuring the development tool.) • In the MB90583C/583CA/587C/587CA/F583C/F583CA, images from FF4000H to FFFFFFH are mapped to bank 00, and FF0000H to FF3FFFH to bank FF only. IEBusTM Controller • MB90587C/CA does not have an IEBusTM Controller. 6 MB90580C Series ■ PIN ASSIGNMENT 100 P21/A17 99 P20/A16 98 P17/AD15 97 P16/AD14 96 P15/AD13 95 P14/AD12 94 P13/AD11 93 P12/AD10 92 P11/AD09 91 P10/AD08 90 P07/AD07 89 P06/AD06 88 P05/AD05 87 P04/AD04 86 P03/AD03 85 P02/AD02 84 P01/AD01 83 P00/AD00 82 VCC 81 X1 80 X0 79 VSS 78 X0A 77 X1A 76 PA2 (TOP VIEW) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 RST PA1 PA0 P97/POT P96/PWC P95/TOT2/OUT1 P94/TOT1/OUT0 P93/TOT0/IN3 P92/TIN2/IN2 P91/TIN1/IN1 P90/TIN0/IN0 RX* TX* P65/CKOT P64/PPG0 P63/PPG1 P62/SCK2 P61/SOT2 P60/SIN2 P87/IRQ7 P86/IRQ6 P85/IRQ5 P84/IRQ4 P83/IRQ3 P82/IRQ2 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 P71 P72 DVRH DVSS P73/DA00 P74/DA01 AVCC AVRH AVRL AVSS P50/AN0/SIN3 P51/AN1/SOT3 P52/AN2/SCK3 P53/AN3 VSS P54/AN4/SIN4 P55/AN5/SOT4 P56/AN6/SCK4 P57/AN7 P80/IRQ0 P81/IRQ1 MD0 MD1 MD2 HST P22/A18 P23/A19 P24/A20 P25/A21 P26/A22 P27/A23 P30/ALE P31/RD VSS P32/WRL P33/WRH P34/HRQ P35/HAK P36/RDY P37/CLK P40/SIN0 P41/SOT0 P42/SCK0 P43/SIN1 P44/SOT1 VCC P45/SCK1 P46/ADTG P47 C * : N.C. pin on the MB90587C/CA (FPT-100P-M05) 7 MB90580C Series 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 P17/AD15 P16/AD14 P15/AD13 P14/AD12 P13/AD11 P12/AD10 P11/AD09 P10/AD08 P07/AD07 P06/AD06 P05/AD05 P04/AD04 P03/AD03 P02/AD02 P01/AD01 P00/AD00 VCC X1 X0 VSS (TOP VIEW) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 X0A X1A PA2 RST PA1 PA0 P97/POT P96/PWC P95/TOT2/OUT1 P94/TOT1/OUT0 P93/TOT0/IN3 P92/TIN2/IN2 P91/TIN1/IN1 P90/TIN0/IN0 RX* TX* P65/CKOT P64/PPG0 P63/PPG1 P62/SCK2 P61/SOT2 P60/SIN2 P87/IRQ7 P86/IRQ6 P85/IRQ5 P84/IRQ4 P83/IRQ3 P82/IRQ2 HST MD2 DVSS P73/DA00 P74/DA01 AVCC AVRH AVRL AVSS P50/AN0/SIN3 P51/AN1/SOT3 P52/AN2/SCK3 P53/AN3 VSS P54/AN4/SIN4 P55/AN5/SOT4 P56/AN6/SCK4 P57/AN7 P80/IRQ0 P81/IRQ1 MD0 MD1 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 P20/A16 P21/A17 P22/A18 P23/A19 P24/A20 P25/A21 P26/A22 P27/A23 P30/ALE P31/RD VSS P32/WRL P33/WRH P34/HRQ P35/HAK P36/RDY P37/CLK P40/SIN0 P41/SOT0 P42/SCK0 P43/SIN1 P44/SOT1 VCC P45/SCK1 P46/ADTG P47 C P71 P72 DVRH * : N.C. pin on the MB90587C/CA (FPT-100P-M06) 8 MB90580C Series ■ PIN DESCRIPTION Pin no. Pin name Circuit type 80 X0 A Oscillator pin 83 81 X1 A Oscillator pin 52 50 HST C Hardware standby input pin 77 75 RST B Reset input pin QFP*1 LQFP*2 82 85 to 92 83 to 90 P00 to P07 AD00 to AD07 93 to 100 1 to 8 91 to 98 99,100, 1 to 6 P10 to P17 P20 to P27 General-purpose I/O ports In external bus mode, pins for which the corresponding bit in the HACR register is “1” function as the A16 to A23 pins. A16 to A23 7 8 P31 RD P32 12 13 General-purpose I/O ports. A pull-up resistor can be assigned (RD17 to RD10=“1”) by the pullup resistor setting register (RDR1). [These pins are disabled with D (CMOS/H) the output setting (DDR1 register: D17 to D10 =“1”).] In 16-bit external bus mode, the pins function as the upper data I/O or middle address outputs (AD08 to AD15). ALE 10 General-purpose I/O ports. A pull-up resistor can be assigned (RD07 to RD00=“1”) by the pullup resistor setting register (RDR0). [These pins are disabled with D (CMOS/H) the output setting (DDR0 register: D07 to D00=“1”).] In external bus mode, the pins function as the lower data I/O or lower address outputs (AD00 to AD07). AD08 to AD15 P30 9 Function 10 F (CMOS/H) In external bus mode, pins for which the corresponding bit in the HACR register is “1” function as the upper address output pins (A16 to A23). General-purpose I/O port Functions as the ALE pin in external bus mode. F (CMOS/H) Functions as the address latch enable signal pin (ALE) in external bus mode. General-purpose I/O port F Functions as the RD pin in external bus mode. (CMOS/H) Functions as the read strobe output pin (RD) in external bus mode. F (CMOS/H) General-purpose I/O port Functions as the WRL pin in external bus mode if the WRE bit is “1”. WRL Functions as the lower data write strobe output pin (WRL) in external bus mode. P33 General-purpose I/O port Functions as the WRH pin in 16-bit external bus mode if the WRE bit in the EPCR register is “1” 11 WRH F (CMOS/H) Functions as the upper data write strobe output pin (WRH) in external bus mode. *1: FPT-100P-M06 *2: FPT-100P-M05 (Continued) 9 MB90580C Series Pin no. QFP* 14 1 LQFP* 2 12 Pin name P34 HRQ P35 15 13 Circuit type General-purpose I/O port Functions as the HRQ pin in external bus mode if the HDE bit in the F (CMOS/H) EPCR register is “1”. Functions as the hold request input pin (HRQ) in external bus mode. F (CMOS/H) HAK 16 14 P36 RDY P37 17 18 15 Functions as the hold acknowledge output pin (HAK) in external bus mode. General-purpose I/O port Functions as the RDY pin in external bus mode if the RYE bit in the F (CMOS/H) EPCR register is “1”. Functions as the external ready input pin (RDY) in external bus mode. F (CMOS/H) General-purpose I/O port Functions as the CLK pin in external bus mode if the CKE bit in the EPCR register is “1”. Functions as the machine cycle clock output pin (CLK) in external bus mode. P40 General-purpose I/O port. This pin serves as an open-drain output port with OD40 in the opendrain control setting register (ODR4) set to “1”. [The pin is disabled with the input setting (DDR4 register: D40=“0”).] 16 P41 17 SOT0 P42 20 General-purpose I/O port Functions as the HAK pin in external bus mode if the HDE bit in the EPCR register is “1”. CLK SIN0 19 Function 18 SCK0 E (CMOS/H) UART0 serial data input (SIN0) pin. When UART0 is operating for input, this input is used as required and thus the output from any other function to the pin must be off unless used intentionally. General-purpose I/O port. This pin serves as an open-drain output port with OD41 in the opendrain control setting register (ODR4) set to “1”. [The pin is disabled E (CMOS/H) with the input setting (DDR4 register: D41=“0”).] UART0 serial data output pin (SOT0). This pin is enabled with the UART0 serial data output enabled. General-purpose I/O port. This pin serves as an open-drain output port with OD42 in the opendrain control setting register (ODR4) set to “1”. [The pin is disabled E (CMOS/H) with the input setting (DDR4 register: D42=“0”).] UART0 serial clock I/O pin (SCK0). This pin is enabled with the UART0 clock output enabled. *1: FPT-100P-M06 *2: FPT-100P-M05 (Continued) 10 MB90580C Series Pin no. QFP* 1 LQFP* 2 Pin name P43 21 19 SIN1 P44 22 20 SOT1 P45 24 22 SCK1 25 26 23 24 E (CMOS/H) UART1 serial data input (SIN1) pin. When UART1 is operating for input, this input is used as required and thus the output from any other function to the pin must be off unless used intentionally. General-purpose I/O port. This pin serves as an open-drain output port with OD44 in the opendrain control setting register (ODR4) set to “1”. [The pin is disabled E (CMOS/H) with the input setting (DDR4 register: D44=“0”).] UART1 serial data output pin (SOT1). This pin is enabled with the UART1 serial data output enabled. General-purpose I/O port. This pin serves as an open-drain output port with OD45 in the opendrain control setting register (ODR4) set to “1”. [The pin is disabled E (CMOS/H) with the input setting (DDR4 register: D45=“0”).] UART1 serial clock I/O pin (SCK1). This pin is enabled with the UART1 clock output enabled. ADTG External trigger input pin (ADTG) for the A/D converter. P47 General-purpose I/O port. E This pin serves as an open-drain output port with OD47 in the open(CMOS/H) drain control setting register (ODR4) set to “1”. [The pin is disabled with the input setting (DDR4 register: D47=“0”).] 36 SIN3 P51 37 General-purpose I/O port. This pin serves as an open-drain output port with OD43 in the opendrain control setting register (ODR4) set to “1”. [The pin is disabled with the input setting (DDR4 register: D43=“0”).] P46 AN0 39 Function General-purpose I/O port. This pin serves as an open-drain output port with OD46 in the openE drain control setting register (ODR4) set to “1”. [The pin is disabled (CMOS/H) with the input setting (DDR4 register: D46=“0”).] P50 38 Circuit type AN1 SOT3 General-purpose I/O port. Analog input pin (AN0) for use during A/D converter operation. G UART3 serial data input pin (SIN3). (CMOS/H) When UART3 is operating for input, this input is used as required and thus the output from any other function to the pin must be off unless used intentionally. General-purpose I/O port. G Analog input pin (AN1) for use during A/D converter operation. (CMOS/H) UART3 serial data output pin (SOT3). This pin is enabled with the UART3 serial data output enabled. *1: FPT-100P-M06 *2: FPT-100P-M05 (Continued) 11 MB90580C Series Pin no. QFP*1 LQFP*2 Pin name Circuit type P52 40 38 AN2 General-purpose I/O port. G (CMOS/H) Analog input pin (AN2) for use during A/D converter operation. G (CMOS/H) General-purpose I/O port. SCK3 41 39 P53 AN3 P54 44 SIN4 UART4 serial data input pin (SIN4). When UART4 is operating for input, this input is used as required and thus the output from any other function to the pin must be off unless used intentionally. P55 General-purpose I/O port. AN5 G (CMOS/H) SOT4 P56 45 43 Analog input pin (AN3) for use during A/D converter operation. Analog input pin (AN4) for use during A/D converter operation. G (CMOS/H) 41 42 UART3 serial clock I/O pin (SCK3). This pin is enabled with the UART3 clock output enabled. General-purpose I/O port. AN4 43 Function AN6 Analog input pin (AN5) for use during A/D converter operation. UART4 serial data output pin (SOT4). This pin is enabled with the UART4 serial data output enabled. General-purpose I/O port. G (CMOS/H) Analog input pin (AN6) for use during A/D converter operation. General-purpose I/O port. AN7 G (CMOS/H) Analog input pin (AN7) for use during A/D converter operation. 0.1 µF capacitor coupling pin for regulating the power supply. SCK4 P57 UART4 serial clock output pin (SCK4). This pin is enabled with the UART4 clock output enabled. 46 44 27 25 C 28 26 P71 F (CMOS/H) 29 27 P72 F (CMOS/H) General-purpose I/O port. 32 30 P73 H (CMOS/H) DA00 33 31 P74 45 P80 IRQ0 General-purpose I/O port. This pin serves as a D/A output pin (DA00) when the DAE0 bit in the D/A control register (DACR) is “1”. D/A converter output 0 (DA00) pin. H (CMOS/H) DA01 47 General-purpose I/O port. General-purpose I/O port. This pin serves as a D/A output pin (DA01) when the DAE1 bit in the D/A control register (DACR) is “1”. D/A converter output 1 pin (DA01). F (CMOS/H) General-purpose I/O port. Functions as external interrupt request input 0 pin (IRQ0). *1: FPT-100P-M06 *2: FPT-100P-M05 (Continued) 12 MB90580C Series Pin no. QFP*1 LQFP*2 48 46 53 51 54 52 55 53 56 54 57 55 58 56 Pin name Circuit type P81 IRQ1 P82 IRQ2 P83 IRQ3 P84 IRQ4 P85 IRQ5 P86 IRQ6 P87 IRQ7 P60 59 57 SIN2 P61 60 58 SOT2 P62 61 59 SCK2 Function General-purpose I/O port. F (CMOS/H) Functions as external interrupt request input 1 pin (IRQ1). General-purpose I/O port. F (CMOS/H) Functions as external interrupt request input 2 pin (IRQ2). General-purpose I/O port. F (CMOS/H) Functions as external interrupt request input 3 pin (IRQ3). General-purpose I/O port. F (CMOS/H) Functions as external interrupt request input 4 pin (IRQ4). General-purpose I/O port. F (CMOS/H) Functions as external interrupt request input 5 pin (IRQ5). General-purpose I/O port. F (CMOS/H) Functions as external interrupt request input 6 pin (IRQ6). General-purpose I/O port. F (CMOS/H) Functions as external interrupt request input 7 pin (IRQ7). General-purpose I/O port. A pull-up resistor can be assigned (RD60=“1”) by the pull-up resistor setting register (RDR6). [This pin is disabled with the output setting (DDR6 register: D60=“1”).] D (CMOS/H) UART2 serial data input pin (SIN2). When UART2 is operating for input, this input is used as required and thus the output from any other function to the pin must be off unless used intentionally. General-purpose I/O port. A pull-up resistor can be assigned (RD61=“1”) by the pull-up resistor setting register (RDR6). [This pin is disabled with the output setting D (CMOS/H) (DDR6 register: D61=“1”).] UART2 serial data output pin (SOT2). This pin is enabled with the UART2 serial data output enabled. General-purpose I/O port. A pull-up resistor can be assigned (RD62=“1”) by the pull-up resistor setting register (RDR6). [This pin is disabled with the output setting D (CMOS/H) (DDR6 register: D62=“1”).] UART2 serial clock I/O pin (SCK2). This pin is enabled with the UART2 clock output enabled. *1: FPT-100P-M06 *2: FPT-100P-M05 (Continued) 13 MB90580C Series (Continued) Pin no. QFP*1 62 LQFP*2 60 Pin name Circuit type P63 D (CMOS/H) PPG1 63 61 P64 62 P65 D (CMOS/H) D (CMOS/H) 63 TX*3 I 66 64 RX*3 J (CMOS) P90 to P92 F (CMOS/H) TOT0 F (CMOS/H) TOT1, TOT2 General-purpose I/O port. F (CMOS/H) OUT0, OUT1 73 71 P96 PWC Reload timer output pin. This function is applied when the output for reload timer 0 is enabled. Trigger inputs for input capture channel 3. P94, P95 69, 70 Event input pins for reload timers 0, 1, and 2. During reload timer input, these inputs are used continuously and thus the output from any other function to the pins must be avoided unless used intentionally. General-purpose I/O port. IN3 71, 72 This pin serves as the IEBusTM input. Trigger inputs for input capture channels 0 to 2 P93 68 This pin serves as the IEBusTM output. General-purpose I/O port. IN0 to IN2 70 General-purpose I/O port. A pull-up resistor can be assigned (RD65=“1”) by the pull-up resistor setting register (RDR6). [This pin is disabled with the output setting (DDR6 register: D65=“1”).] This pin serves as the CKOT output during CKOT operation. 65 TIN0 to TIN2 General-purpose I/O port. A pull-up resistor can be assigned (RD64=“1”) by the pull-up resistor setting register (RDR6). [This pin is disabled with the output setting (DDR6 register: D64=“1”).] The pin serves as the PPG0 output when PPGs are enabled. CKOT 67 to 69 65 to 67 General-purpose I/O port. A pull-up resistor can be assigned (RD63=“1”) by the pull-up resistor setting register (RDR6). [This pin is disabled with the output setting (DDR6 register: D63=“1”).] The pin serves as the PPG1 output when PPGs are enabled. PPG0 64 Function Reload timer output pins. This function is applied when the output for reload timer 1 and 2 are enabled. Event output for channel 0 and 1 of the output compare F (CMOS/H) General-purpose I/O port. This pin serves as the PWC input with the PWC timer enabled. *1: FPT-100P-M06 *2: FPT-100P-M05 *3: N.C. pin on the MB90587C/CA. (Continued) 14 MB90580C Series (Continued) Pin no. Pin name Circuit type Function QFP*1 LQFP*2 74 72 75, 76 73, 74 78 76 PA2 79 77 X1A A Oscillation input pin. Leave the terminal open for the one clock system parts. 80 78 X0A A Oscillation input pin. Pull-down the terminal externally for the one clock system parts. 34 32 AVCC A/D converter power supply pin. 37 35 AVSS A/D converter power supply pin. 35 33 AVRH A/D converter external reference power supply pin. 36 34 AVRL A/D converter external reference power supply pin. 30 28 DVRH D/A converter external reference power supply pin. 31 29 DVSS D/A converter power supply pin. MD0 to MD2 C Input pin for specifying the operation mode. Connect these pins directly to Vcc or Vss. 49 to 51 47 to 49 P97 POT F (CMOS/H) General-purpose I/O port. This pin serves as the PWC output with the PWC timer enabled. PA0, PA1 F (CMOS/H) General-purpose I/O port. F (CMOS/H) General-purpose I/O port. 23, 84 21, 82 VCC Power supply (5 V) input pin. 11, 42, 81 9, 40, 79 VSS Power supply (0 V) input pin. *1: FPT-100P-M06 *2: FPT-100P-M05 15 MB90580C Series ■ I/O CIRCUIT TYPE Type Circuit Remarks • Oscillation feedback resistance : Approx. 1 MΩ X1, X1A Clock input X0, X0A A HARD,SOFT STANDBY CONTROL • Hysteresis input with pull-up Resistance approx. 50 kΩ B • Hysteresis input C Pull-up resistor control • Incorporates pull-up resistor control (for input) • CMOS level output • Hysteresis input with standby control Resistance approx. 50 kΩ D Standby control signal (Continued) 16 MB90580C Series Type Circuit Remarks • Open-drain control signal • CMOS level output • Hysteresis input with standby control • Incorporates open-drain control E Standby control signal • CMOS level output • Hysteresis input with standby control F Standby control signal • CMOS level output • Hysteresis input with standby control • Analog input G Analog input Standby control signal (Continued) 17 MB90580C Series (Continued) Type Circuit Remarks • CMOS level output • Hysteresis input with standby control • DA output H DA output Standby control signal • CMOS level output I • CMOS input with standby control J Standby control signal 18 MB90580C Series ■ HANDLING DEVICES 1. Preventing Latchup CMOS ICs may cause latchup in the following situations: • When a voltage higher than Vcc or lower than Vss is applied to input or output pins. • When a voltage exceeding the rating is applied between Vcc and Vss. • When AVcc power is supplied prior to the Vcc voltage. If latchup occurs, the power supply current increases rapidly, sometimes resulting in thermal breakdown of the device. Use meticulous care not to let it occur. For the same reason, also be careful not to let the analog power-supply voltage exceed the digital power-supply voltage. 2. Handling unused input pins Unused input pins left open may cause abnormal operation, or latch-up leading to permanent damage. Unused input pins should be pulled up or pulled down through at least 2 kΩ resistance. Unused input/output pins may be left open in output state, but if such pins are in input state they should be handled in the same way as input pins. 3. Treatment of the TX and RX pins with the IEBusTM unused When the IEBus is not used, connect a pull-down resistor to the TX pin and a pull-down/pull-up resistor to the RX pin. 4. Use of the external clock When the device uses an external clock, drive only the X0 pin while leaving the X1 pin open (See the illustration below). MB90580C series X0 Open X1 5. Power Supply Pins (VCC/VSS) In products with multiple VCC or VSS pins, the pins of a same potential are internally connected in the device to avoid abnormal operations including latch-up. However, connect the pins external power and ground lines to lower the electro-magnetic emission level to prevent abnormal operation of strobe signals caused by the rise in the ground level, and to conform to the total current rating. Make sure to connect VCC and VSS pins via lowest impedance to power lines. 19 MB90580C Series It is recommended to provide a bypass capacitor of around 0.1 µF between VCC and VSS pin near the device. VCC VSS VCC VSS VSS VCC MB90580C Series VCC VSS VSS VCC 6. Crystal Oscillator Circuit Noises around X0 or X1 pins may be possible causes of abnormal operations. Make sure to provide bypass capacitors via shortest distance from X0, X1 pins, crystal oscillator (or ceramic resonator) and ground lines, and make sure, to the utmost effort, that lines of oscillation circuit not cross the lines of other circuits. It is highly recommended to provide a printed circuit board art work surrounding X0 and X1 pins with an grand area for stabilizing the operation. 7. Turning-on Sequence of Power Supply to A/D Converter and Analog Inputs Make sure to turn on the A/D converter power supply (AVCC, AVSS, AVRH, AVRL) and analog inputs (AN0 to AN7) after turning-on the digital power supply (VCC). Turn-off the digital power after turning off the A/D converter supply and analog inputs. In this case, make sure that the voltage of AVRH dose not exceed AVCC (turning on/off the analog and digital power supplies simultaneously is acceptable). 8. Connection of Unused Pins of A/D Converter Connect unused pin of A/D converter to AVCC = VCC, AVSS = AVRH = AVRL = VSS. 9. Connection of Unused Pins of D/A Converter Connect unused pin of D/A converter to DVRH = VSS, DVSS = VSS. 10. N.C. Pin The N.C. (internally connected) pin must be opened for use. 11. Notes on Energization To prevent the internal regulator circuit from malfunctioning, set the voltage rise time during energization at 50 µs or more (0.2 V to 2.7 V). 12. Use of the sub-clock Use the one clock system parts when the sub-clock is not used. Connected the oscillator under 32 kHz to the both terminals XA0 and X1A for the two clocks system parts. Pull-down the terminal X0A and leave the terminal X0A open for the one clock system parts. 20 MB90580C Series 13. Indeterminate outputs from ports 0 and 1 The outputs from ports 0 and 1 become indeterminate during a power-on reset after the power is turned on. Pay attention to the port output timing shown as follow. Oscillation settling time*2 Power-on reset*1 VCC (Power-supply pin) PONR (power-on reset) signal RST (external asynchronous reset) signal RST (internal reset) signal Oscillation clock signal KA (internal operation clock A) signal KB (internal operation clock B) signal PORT (port output) signal Period of indeterminate *1: Power-on reset time: Period of “clock frequency x 217” (Clock frequency of 16 MHz: 8.192 ms) *2: Oscillation settling time: Period of “clock frequency x 218” (Clock frequency of 16 MHz: 16.384 ms) 14. Initialization In the device, there are internal registers which are initialized only by a power-on reset. To initialize these registers turning on the power again. 15. Return from standby state If the power-supply voltage goes below the standby RAM holding voltage in the standby state, the device may fail to return from the standby state. In this case, reset the device via the external reset pin to return to the normal state. 16. Precautions for Use of ’DIV A, Ri,’ and ’DIVW A, RWi’ Instructions The signed multiplication-division instructions ’DIV A, Ri,’ and ’DIVW A, RWi’ should be used when the corresponding bank registers (DTB, ADB, USB, SSB) are set to value ’00h.’ If the corresponding bank registers (DTB, ADB, USB, SSB) are set to a value other than ’00h,’ then the remainder obtained after the execution of the instruction will not be placed in the instruction operand register. 17. Precautions for Use of REALOS Extended intelligent I/O service (EI2OS) cannot be used, when REALOS is used. 21 MB90580C Series ■ BLOCK DIAGRAM X0, X1 X0A, X1A RST HST 6 Clock control circuit CPU Core of F2MC-16LX family RAM Interrupt controller ROM CMOS I/O port A 3 I/O timer 3 P00 to P07/ AD00 to AD07 8 P10 to P17/ AD08 to AD15 P20 to P27/ A16 to A23 8 CMOS I/O port 1 8 CMOS I/O port 2 CMOS I/O port 0 16 bit ICU × 4 ch 16 bit OCU × 2 ch 16 bit free run timer CMOS I/O port 3 P30/ALE F2MC-16LX bus P32/WRL P33/WRH P34/HRQ P35/HAK P36/RDY Prescaler × 2 ch P37/CLK CMOS I/O port 4 3 3 SIN4, SOT4, SCK4/ P54 to P56/ AN4 to AN6 TX RX Other pins MD2 to MD0 C,VCC,VSS 22 UART × 2 ch P96/PWC PWC timer 16 bit × 1 ch P97/POT UART × 1 ch 8 / 16 PPG × 1 ch 8 CMOS I/O port 6 External interrupt 8 3 CMOS I/O port 8 Prescaler × 2 ch 2 D/A converter (8 bit) × 2 ch UART × 2 ch CMOS I/O port 5 * IEBusTM controller P63, P64/ PPG1, PPG0 P65/CKOT 3 8 2 SIN2, SOT2, SCK2/ P60 to P62 P80 to P87/ IRQ0 to IRQ7 P71, P72 CMOS I/O port 7 2 3 2 Clock monitor A/D converter (8/10 bit) AVCC AVRH, AVRL AVSS P53/AN3, P57/AN7 Noise filter P94, P95/ TOT1, TOT2/ OUT0, OUT1 Prescaler × 1 ch ADTG / P46 SIN3, SOT3, SCK3/ P50 to P52/ AN0 to AN2 2 CMOS I/O port 9 P47 SIN0, SOT0, SCK0/ P40 to P42 SIN1, SOT1, SCK1/ P43 to P45 P90 to P92/ TIN0 to TIN2/ IN0 to IN2 P93/ TOT0/ IN3 16 bit reload timer × 3 ch P31/RD PA0 to PA2 2 P73, P74 /DA00, DA01 DVRH DVSS Evaluation device (MB90V580B) This chip has no internal ROM. Internal RAM is 6 Kbytes. Internal resources are common. The package is PGA-256C-A02. P00 to 07 (8 channels): Provided with a register available as an input pull-up resistor. P10 to 17(8 channels): Provided with a register available as an input pull-up resistor. P60 to 65(6 channels): Provided with a register available as an input pull-up resistor. P40 to 47 (8 channels): Provided with a register available as an open drain. *: The MB90587C/CA has no IEBusTM controller. The TX and RX pins are N.C. pins. MB90580C Series ■ MEMORY MAP FFFFFFH ROM area ROM area ROM area (image of bank FF) ROM area (image of bank FF) Address#1 FC0000H 010000 H Address#2 : Internal 004000 H 002000 H : External Address#3 RAM 000100 H 0000C0H RAM Register RAM Register Register Peripheral Peripheral Peripheral Single chip mode A mirror function is supported Internal ROM external bus mode A mirror function is External ROM external bus mode 000000 H : Inhibited area supported Parts No. Address#1 Address#2 Address#3 MB90583C/CA FE0000H 004000H 001900H MB90F583C/CA FE0000H 004000H 001900H MB90587C/CA FF0000H 004000H 001100H MB90V580B (FE0000H) 004000H 001900H Note: The ROM data of bank FF is reflected in the upper address of bank 00, realizing effective use of the C compiler small model. The lower 16-bit is assigned to the same address, enabling reference of the table on the ROM without stating “far”. For example, if an attempt has been made to access 00C000H, the contents of the ROM at FFC000H are accessed actually. Since the ROM area of the FF bank exceeds 48 Kbytes, the whole area cannot be reflected in the image for the 00 bank. The ROM data at FF4000H to FFFFFFH looks, therefore, as if it were the image for 00400H to 00FFFFH. Thus, it is recommended that the ROM data table be stored in the area of FF4000H to FFFFFFH. 23 MB90580C Series ■ F2MC-16LX CPU PROGRAMMING MODEL • Dedicated registers AH : Accumulator (A) Dual 16-bit register used for storing results of calculation etc. The two 16-bit registers can be combined to be used as a 32-bit register. : User stack pointer (USP) The 16-bit pointer indicating a user stack address. AL USP : System stack pointer (SSP) The 16-bit pointer indicating the status of the system stack address. SSP : Processor status (PS) The 16-bit register indicating the system status. PS PC DPR PCB : Program bank register (PCB) The 8-bit register indicating the program space. DTB : Data bank register (DTB) The 8-bit register indicating the data space. USB : User stack bank register (USB) The 8-bit register indicating the user stack space. SSB : System stack bank register (SSB) The 8-bit register indicating the system stack space. ADB : Additional data bank register (ADB) The 8-bit register indicating the additional data space. 8 bit 16 bit 32 bit 24 : Program counter (PC) The 16-bit register indicating storing location of the current instruction code. : Direct page register (DPR) The 8-bit register indicating bit 8 through 15 of the operand address in the short direct addressing mode. MB90580C Series • General-purpose registers Maximum of 32 banks R7 R6 RW7 R5 R4 RW6 R3 R2 RW5 R1 R0 RW4 RL3 RL2 RW3 RL1 RW2 RW1 RL0 RW0 000180H + (RP × 10H) 16 bit • Processor status (PS) ILM RP CCR bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 PS Initial value ILM2 ILM1 ILM0 0 0 0 B4 B3 B2 B1 B0 I S T N Z V C 0 0 0 0 0 0 1 X X X X X : Unused X : Undefined 25 MB90580C Series ■ I/O MAP Address Register name Abbreviated register Read/write name Resource name Initial value 00H Port 0 data register PDR0 R/W Port 0 XXXXXXXXB 01H Port 1 data register PDR1 R/W Port 1 XXXXXXXXB 02H Port 2 data register PDR2 R/W Port 2 XXXXXXXXB 03H Port 3 data register PDR3 R/W Port 3 XXXXXXXXB 04H Port 4 data register PDR4 R/W Port 4 XXXXXXXXB 05H Port 5 data register PDR5 R/W Port 5 1 1 1 1 1 1 1 1B 06H Port 6 data register PDR6 R/W Port 6 − − XXXXXXB 07H Port 7 data register PDR7 R/W Port 7 − − − XXXX −B 08H Port 8 data register PDR8 R/W Port 8 XXXXXXXXB 09H Port 9 data register PDR9 R/W Port 9 XXXXXXXXB 0AH Port A data register PDRA R/W Port A − − − − − XXXB 0BH to 0FH (Disabled) 10H Port 0 direction register DDR0 R/W Port 0 0 0 0 0 0 0 0 0B 11H Port 1 direction register DDR1 R/W Port 1 0 0 0 0 0 0 0 0B 12H Port 2 direction register DDR2 R/W Port 2 0 0 0 0 0 0 0 0B 13H Port 3 direction register DDR3 R/W Port 3 0 0 0 0 0 0 0 0B 14H Port 4 direction register DDR4 R/W Port 4 0 0 0 0 0 0 0 0B 15H Port 5 direction register DDR5 R/W Port 5 0 0 0 0 0 0 0 0B 16H Port 6 direction register DDR6 R/W Port 6 − − 0 0 0 0 0 0 0B 17H Port 7 direction register DDR7 R/W Port 7 − − −0000− 18H Port 8 direction register DDR8 R/W Port 8 0 0 0 0 0 0 0 0B 19H Port 9 direction register DDR9 R/W Port 9 0 0 0 0 0 0 0 0B 1AH Port A direction register DDRA R/W Port A − − − − − 0 0 0B 1BH Port 4 output pin register ODR4 R/W Port 4 0 0 0 0 0 0 0 0B 1CH Port 5 analog input enable register ADER R/W Port 4, A/D 1 1 1 1 1 1 1 1B 1DH to 1FH B (Disabled) 20H Serial mode register 0 SMR0 R/W 0 0 0 0 0 0 0 0B 21H Serial control register 0 SCR0 R/W 0 0 0 0 0 1 0 0B 22H Serial input data register 0/ serial output data register 0 SIDR0/ SODR0 R/W 23H Serial status register 0 SSR0 R/W UART0 XXXXXXXXB 0 0 0 0 1 − 0 0B (Continued) 26 MB90580C Series Address Register name Abbreviated register name Read/ write 24H Serial mode register 1 SMR1 R/W 25H Serial control register 1 SCR1 R/W Resource name Initial value 0 0 0 0 0 0 0 0B 0 0 0 0 0 1 0 0B UART1 SIDR1/ SODR1 R/W Serial status register 1 SSR1 R/W 0 0 0 0 1 − 0 0B 28H Serial mode register 2 SMR2 R/W 0 0 0 0 0 0 0 0B 29H Serial control register 2 SCR2 R/W 26H Serial input data register 1/ serial output data register 1 27H 2AH Serial input data register 2/ serial output data register 2 2BH Serial status register 2 2CH Clock division control register 0 SIDR2/ SODR2 R/W SSR2 R/W CDCR0 R/W 2DH 2EH XXXXXXXXB 0 0 0 0 0 1 0 0B UART2 XXXXXXXXB 0 0 0 0 1 − 0 0B Communications prescaler 0 0 − − − 1 1 1 1B Communications prescaler 1 0 − − − 1 1 1 1B (Disabled) Clock division control register 1 CDCR1 2FH R/W (Disabled) 30H DTP/interrupt enable register ENIR R/W 31H DTP/interrupt factor register EIRR R/W 32H Request level setting register lower 33H Request level setting register upper 34H Clock division control register 2 0 0 0 0 0 0 0 0B XXXXXXXXB DTP/external interrupt ELVR 0 0 0 0 0 0 0 0B R/W 0 0 0 0 0 0 0 0B CDCR2 35H R/W Communications prescaler 2 0 − − − 1 1 1 1B (Disabled) 36H Control status register lower ADCS1 R/W 37H Control status register upper ADCS2 R/W 38H Data register lower ADCR1 R 39H Data register upper ADCR2 R or W 0 0 0 0 1 − XXB 3AH D/A converter data register 0 DAT0 R/W 0 0 0 0 0 0 0 0B 3BH D/A converter data register 1 DAT1 R/W 3CH D/A control register 0 DACR0 R/W 3DH D/A control register 1 DACR1 R/W 3EH Clock output enable register CLKR R/W 3FH 0 0 0 0 0 0 0 0B A/D converter D/A converter 0 0 0 0 0 0 0 0B XXXXXXXXB 0 0 0 0 0 0 0 0B − − − − − − − 0B − − − − − − − 0B Clock monitor function − − − − 0 0 0 0B (Disabled) (Continued) 27 MB90580C Series Address Register name Abbreviated Read/ register write name Resource name Initial value 40H Reload register L (ch.0) PRLL0 R/W XXXXXXXXB 41H Reload register H (ch.0) PRLH0 R/W XXXXXXXXB 42H Reload register L (ch.1) PRLL1 R/W XXXXXXXXB 43H Reload register H (ch.1) PRLH1 R/W XXXXXXXXB 8/16 bit PPG0/1 44H PPG0 operating mode control register PPGC0 R/W 45H PPG1 operating mode control register PPGC1 R/W 0 X 0 0 0 0 0 1B 46H PPG0 and 1 operating output control registers PPGOE R/W 0 0 0 0 0 0 0 0B 47H (Disabled) 48H Timer control status register lower 49H Timer control status register upper 4AH 16 bit timer register lower/ 16 bit reload register lower 4BH 16 bit timer register upper/ 16 bit reload register upper 4CH Timer control status register lower 4DH Timer control status register upper 4EH 16bit timer register lower/ 16 bit reload register lower 4FH 16 bit timer register upper/ 16 bit reload register upper 50H Timer control status register lower 51H Timer control status register upper 52H 16 bit timer register lower/ 16 bit reload register lower 53H 16 bit timer register upper/ 16 bit reload register upper 54H PWC control status register lower 55H PWC control status register upper 56H PWC data buffer register lower 57H PWC data buffer register upper 58H Divide ratio control register 59H 0 X 0 0 0 X X 1B TMCSR0 0 0 0 0 0 0 0 0B R/W − − − − 0 0 0 0B 16 bit reload timer 0 TMR0/ TMRLR0 R/W TMCSR1 R/W XXXXXXXXB XXXXXXXXB 0 0 0 0 0 0 0 0B − − − − 0 0 0 0B 16 bit reload timer 1 TMR1/ TMRLR1 R/W TMCSR2 R/W XXXXXXXXB XXXXXXXXB 0 0 0 0 0 0 0 0B − − − − 0 0 0 0B 16 bit reload timer 2 TMR2/ TMRLR2 R/W PWCSR R/W or R XXXXXXXXB XXXXXXXXB PWCR R/W DIVR R/W 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 16 bit PWC timer XXXXXXXXB XXXXXXXXB − − − − − − 0 0B (Disabled) (Continued) 28 MB90580C Series Address Register name 5AH Compare register lower 5BH Compare register upper 5CH Compare register lower 5DH Compare register upper 5EH Abbreviated register Read/write name Resource name Initial value XXXXXXXXB OCCP0 R/W Output compare (ch.0) OCCP1 R/W Output compare (ch.1) Compare control status register 0 OCS0 R/W Output compare (ch.0) 0 0 0 0 − − 0 0B 5FH Compare control status register 1 OCS1 R/W Output compare (ch.1) − − − 0 0 0 0 0B 60H Input capture register lower Input capture register upper R Input capture (ch.0) XXXXXXXXB 61H IPCP0 62H Input capture register lower 63H Input capture register upper IPCP1 R Input capture (ch.1) 64H Input capture register lower 65H Input capture register upper IPCP2 R Input capture (ch.2) 66H Input capture register lower 67H Input capture register upper IPCP3 R Input capture (ch.3) 68H Input capture control status register 01 ICS01 R/W Input capture (ch.0, ch.1) 0 0 0 0 0 0 0 0B Input capture (ch.2, ch.3) 0 0 0 0 0 0 0 0B 69H 6AH XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB (Disabled) Input capture control status register 23 6BH ICS23 R/W (Disabled) 6CH Timer data register lower TCDTL R/W 6DH Timer data register upper TCDTH R/W 6EH Timer control status register TCCS R/W 6FH ROM mirroring function selection register ROMM W 70H Local-office address setting register L MAWL R/W XXXXXXXXB 71H Local-office address setting register H MAWH R/W XXXXXXXXB 72H Slave address setting register L SAWL R/W 73H Slave address setting register H SAWH R/W 74H Message length bit setting register DEWR R/W 0 0 0 0 0 0 0 0B 75H Broadcast control bit setting register DCWR R/W 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B Free-run timer 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B ROM mirror function − − − − − − − 1B IEBusTM controller XXXXXXXXB XXXXXXXXB (Continued) 29 MB90580C Series Address Register name Abbreviated register Read/write name Resource name Initial value 76H Command register L CMRL R/W 1 1 0 0 0 0 0 0B 77H Command register H CMRH R/W 0 0 0 0 0 0 0 XB 78H Status register L STRL R 0 0 1 1 XXXXB 79H Status register H STRH R/W or R 0 0 XX 0 0 0 0B 7AH Lock read register L LRRL R XXXXXXXXB 7BH Lock read register H LRRH R/W or R 7CH Master address read register L MARL R 7DH Master address read register H MARH R 1 1 1 1 XXXXB 7EH Message length bit read register DERR R XXXXXXXXB 7FH Broadcast control bit read register DCRR R 0 0 0 XXXXXB 80H Write data buffer WDB W XXXXXXXXB 81H Read data buffer RDB R XXXXXXXXB 82H Serial mode register 3 SMR3 R/W 0 0 0 0 0 0 0 0B 83H Serial control register 3 SCR3 R/W 0 0 0 0 0 1 0 0B 84H Serial input register 3/ serial output register 3 SIDR3/ SODR3 R/W 85H Serial status register 3 SSR3 R/W 86H PWC noise filter register RNCR R/W PWC noisefilter − − − − − 0 0 0B 87H Clock division control register 3 CDCR3 R/W Communications prescaler 3 0 − − − 1 1 1 1B 88H Serial mode register 4 SMR4 R/W 0 0 0 0 0 0 0 0B 89H Serial control register 4 SCR4 R/W 0 0 0 0 0 1 0 0B 8AH Serial input register 4/ serial output register 4 SIDR4/ SODR4 R/W 8BH Serial status register 4 SSR4 R/W 8CH Port 0 input pull-up resistor setup register RDR0 R/W Port 0 0 0 0 0 0 0 0 0B 8DH Port 1 input pull-up resistor setup register RDR1 R/W Port 1 0 0 0 0 0 0 0 0B 8EH Port 6 input pull-up resistor setup register RDR6 R/W Port 6 − − 0 0 0 0 0 0B 8FH Clock division control register 4 CDCR4 R/W Communications prescaler 4 0 − − − 1 1 1 1B 90H to 9DH IEBusTM controller UART3 1 1 1 0 XXXXB XXXXXXXXB XXXXXXXXB 0 0 0 0 1 − 0 0B UART4 XXXXXXXXB 0 0 0 0 1 − 0 0B (Disabled) (Continued) 30 MB90580C Series Address Register name Abbreviated register name Read/ write Resource name Initial value 9EH Program address detection control/ status register PACSR R/W Address match detection function 0 0 0 0 0 0 0 0B 9FH Delayed interrupt generation/release register DIRR R/W Delayed interrupt generation module − − − − − − − 0B A0H Low-power consumption mode control register LPMCR R/W or W A1H Clock selection register CKSCR R/W or R A2H to A4H Low-power consumption mode 0 0 0 1 1 0 0 −B 1 1 1 1 1 1 0 0B (Disabled) 0 0 1 1 − − 0 0B A5H Auto-ready function selection register ARSR W A6H External address output control register HACR W A7H Bus control signal selection register ECSR W A8H Watch dog timer control register WDTC R or W Watch dog timer XXXXX 1 1 1B A9H Time-base timer control register TBTC R/W, W Timebase timer 1 − − 0 0 1 0 0B AAH Clock timer control register WTC R/W or R Clock timer 1 X 0 0 0 0 0 0B Flash interface 0 0 0 X 0 0 0 0B ABH to ADH AEH External bus pin control circuit 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 −B (Disabled) Flash memory control status register AFH FMCS R/W or R or W (Disabled) B0H Interrupt control register 00 ICR00 R/W 0 0 0 0 0 1 1 1B B1H Interrupt control register 01 ICR01 R/W 0 0 0 0 0 1 1 1B B2H Interrupt control register 02 ICR02 R/W 0 0 0 0 0 1 1 1B B3H Interrupt control register 03 ICR03 R/W 0 0 0 0 0 1 1 1B B4H Interrupt control register 04 ICR04 R/W 0 0 0 0 0 1 1 1B B5H Interrupt control register 05 ICR05 R/W 0 0 0 0 0 1 1 1B B6H Interrupt control register 06 ICR06 R/W 0 0 0 0 0 1 1 1B B7H Interrupt control register 07 ICR07 R/W B8H Interrupt control register 08 ICR08 R/W B9H Interrupt control register 09 ICR09 R/W 0 0 0 0 0 1 1 1B BAH Interrupt control register 10 ICR10 R/W 0 0 0 0 0 1 1 1B BBH Interrupt control register 11 ICR11 R/W 0 0 0 0 0 1 1 1B BCH Interrupt control register 12 ICR12 R/W 0 0 0 0 0 1 1 1B BDH Interrupt control register 13 ICR13 R/W 0 0 0 0 0 1 1 1B BEH Interrupt control register 14 ICR14 R/W 0 0 0 0 0 1 1 1B BFH Interrupt control register 15 ICR15 R/W 0 0 0 0 0 1 1 1B Interrupt controller 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 31 MB90580C Series (Continued) (Continued) Address Register name Abbreviated register Read/write name C0H to FFH (External area) 100H to #H (RAM area) #H to 1FEFH (Reserved area) 1FF0H Program address detection register 0 (lower) 1FF1H Program address detection register 0 (middle) 1FF2H Program address detection register 0 (upper) R/W 1FF3H Program address detection register 1 (lower) R/W 1FF4H Program address detection register 1 (middle) 1FF5H Program address detection register 1 (upper) 1FF6H to 1FFFH PADR0 PADR1 Resource name Initial value R/W XXXXXXXXB R/W XXXXXXXXB Address match detection function XXXXXXXXB XXXXXXXXB R/W XXXXXXXXB R/W XXXXXXXXB (Reserved area) • Explanation of initial values→“0” : initial value“0” / “1” : initial value“1” / “X” : undefined / “−” : undefined (not used) • The addresses following 00FFH are reserved. No external bus access signal is generated. • Boundary #H between the RAM area and the reserved area varies with the product model. Note: For bits that is initialized by an reset operation, the initial value set by the reset operation is listed as an initial value. Note that the values are different from reading results. For LPMCR/CKSCR/WDTC, there are cases where initialization is performed or not performed, depending on the types of the reset. However initial value for resets that initializes the value are listed. 32 MB90580C Series ■ INTERRUPT FACTORS, INTERRUPT VECTORS, INTERRUPT CONTROL REGISTER Interrupt source EI2OS support Interrupt vector Interrupt control register No. Address ICR Address Reset × #08 FFFFDCH INT9 instruction × #09 FFFFD8H Exception × #10 FFFFD4H #11 FFFFD0H × #12 FFFFCCH ICR00 0000B0H DTP0 (external interrupt #0) /UART3 reception complete #13 FFFFC8H DTP1 (external interrupt #1) /UART4 reception complete ICR01 0000B1H #14 FFFFC4H DTP2 (external interrupt #2) /UART3 transmission complete #15 FFFFC0H DTP3 (external interrupt #3) /UART4 transmission complete ICR02 0000B2H #16 FFFFBCH ICR03 0000B3H ICR04 0000B4H ICR05 0000B5H ICR06 0000B6H ICR07 0000B7H ICR08 0000B8H ICR09 0000B9H ICR10 0000BAH ICR11 0000BBH A/D converter Timebase timer DTP4 to 7 (external interrupt #4 to #7) #17 FFFFB8H Output compare (ch.1) match (I/O timer) #18 FFFFB4H UART2 reception complete #19 FFFFB0H UART1 reception complete #20 FFFFACH Input capture (ch.3) include (I/O timer) #21 FFFFA8H Input capture (ch.2) include (I/O timer) #22 FFFFA4H Input capture (ch.1) include (I/O timer) #23 FFFFA0H Input capture (ch.0) include (I/O timer) #24 FFFF9CH #25 FFFF98H #26 FFFF94H 8/16 bit PPG0 counter borrow × 16 bit reload timer 2 to 0 Clock prescaler × #27 FFFF90H Output compare (ch.0) match (I/O timer) #28 FFFF8CH UART2 transmission complete #29 FFFF88H PWC timer measurement complete / over flow #30 FFFF84H UART1 transmission complete #31 FFFF80H 16-bit free run timer (I/O timer) over flow #32 FFFF7CH UART0 transmission complete #33 FFFF78H #34 FFFF74H IEBus reception complete #35 FFFF70H ICR12 0000BCH IEBus transmission start #37 FFFF68H ICR13 0000BDH ICR14 0000BEH ICR15 0000BFH 8/16 bit PPG1 counter borrow × UART0 reception complete #39 FFFF60H Flash memory status × #41 FFFF58H Delayed interrupt × #42 FFFF54H Priority High Low : Indicates that the interrupt request flag is cleared by the EI2OS interrupt clear signal (stop request present). : Indicates that the interrupt request flag is cleared by the EI2OS interrupt clear signal. × : Indicates that the interrupt request flag is not cleared by the EI2OS interrupt clear signal. 33 MB90580C Series ■ PERIPHERAL RESOURCES 1. I/O Ports (1) Outline of I/O ports When a data register serving for control output is read, the data output from it as a control output is read regardless of the value in the direction register. Note that, if a read modify write instruction (such as a bit set instruction) is used to preset output data in the data register when changing its setting from input to output, the data read is not the data register latched value but the input data from the pin. Ports 0 to 4 and 6 to A are input/output ports which serve as inputs when the direction register value is “0” or as outputs when the value is “1”. On the MB90580C series, ports 0 to 3 also serve as external bus pins. When the device is used in external bus mode, therefore, these ports are restricted on use. Ports 2 and 3 can be used as ports even in external bus mode depending on the setting of the corresponding function select bit. (2) Register configuration • Port 0 data register (PDR0) Address bit 15 ………… 8 : 000000H (PDR1) Access Initial value 7 6 5 4 3 2 1 0 P07 P06 P05 P04 P03 P02 P01 P00 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (X) (X) (X) (X) (X) (X) (X) (X) • Port 1 data register (PDR1) bit Address : 000001H 15 14 13 12 11 10 9 8 7 ………… 0 P17 P16 P15 P14 P13 P12 P11 P10 (PDR0) Access (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value (X) (X) (X) (X) (X) (X) (X) (X) • Port 2 data register (PDR2) Address bit 15 ………… 8 : 000002H (PDR3) Access Initial value 7 6 5 4 3 2 1 0 P27 P26 P25 P24 P23 P22 P21 P20 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (X) (X) (X) (X) (X) (X) (X) (X) • Port 3 data register (PDR3) bit Address : 000003H Access Initial value • Port 4 data register (PDR4) Address 15 14 13 12 11 10 9 8 7 ………… 0 P37 P36 P35 P34 P33 P32 P31 P30 (PDR2) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (X) (X) (X) (X) (X) (X) (X) (X) bit 15 ………… 8 : 000004H Access Initial value (PDR5) 7 6 5 4 3 2 1 0 P47 P46 P45 P44 P43 P42 P41 P40 (R/W) (RW) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (X) (X) (X) (X) (X) (X) (X) (X) (Continued) 34 MB90580C Series (Continued) • Port 5 data register (PDR5) bit Address : 000005H Access Initial value • Port 6 data register (PDR6) Address 15 14 13 12 11 10 9 8 7 ………… 0 P57 P56 P55 P54 P53 P52 P51 P50 (PDR4) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (1) (1) (1) (1) (1) (1) (1) (1) bit 15 ………… 8 : 000006H (PDR7) Access Initial value 7 6 5 4 3 2 1 0 P65 P64 P63 P62 P61 P60 () () () () (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (X) (X) (X) (X) (X) (X) • Port 7 data register (PDR7) bit Address : 000007H Access Initial value • Port 8 data register (PDR8) Address 15 14 13 12 11 10 9 8 7 ………… 0 P74 P73 P72 P71 (PDR6) () () () () () (R/W) (R/W) (R/W) (R/W) () () (X) (X) (X) (X) () bit 15 ………… 8 : 000008H (PDR9) Access Initial value 7 6 5 4 3 2 1 0 P87 P86 P85 P84 P83 P82 P81 P80 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (X) (X) (X) (X) (X) (X) (X) (X) • Port 9 data register (PDR9) bit Address : 000009H Access Initial value • Port A data register (PDRA) Address 15 14 13 12 11 10 9 8 7 ………… 0 P97 P96 P95 P94 P93 P92 P91 P90 (PDR8) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (X) (X) (X) (X) (X) (X) (X) (X) bit 15 ………… 8 : 00000AH Access Initial value (Disabled) 7 6 5 4 3 2 1 0 PA2 PA1 PA0 () () () () () () () () () () (R/W) (R/W) (R/W) (X) (X) (X) • Port 0 direction register (DDR0) bit 15 ………… 8 7 6 5 4 3 2 1 0 Address : 000010H (DDR1) D07 D06 D05 D04 D03 D02 D01 D00 Access (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value (0) (0) (0) (0) (0) (0) (0) (0) (Continued) 35 MB90580C Series (Continued) • Port 1 direction register (DDR1) bit Address : 000011H Access Initial value 15 14 13 12 11 10 9 8 7 ………… 0 D17 D16 D15 D14 D13 D12 D11 D10 (DDR0) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (0) (0) • Port 2 direction register (DDR2) bit 15 ………… 8 Address : 000012H (DDR3) Access Initial value 7 6 5 4 3 2 1 0 D27 D26 D25 D24 D23 D22 D21 D20 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (0) (0) • Port 3 direction register (DDR3) bit Address : 000013H Access Initial value 15 14 13 12 11 10 9 8 7 ………… 0 D37 P36 P35 P34 P33 P32 P31 P30 (DDR2) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (0) (0) • Port 4 direction register (DDR4) bit 15 ………… 8 Address : 000014H (DDR5) Access Initial value 7 6 5 4 3 2 1 0 D47 D46 D45 D44 D43 D42 D41 D40 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (0) (0) • Port 5 direction register (DDR5) bit Address : 000015H Access Initial value 15 14 13 12 11 10 9 8 7 ………… 0 D57 D56 D55 D54 D53 D52 D51 D50 (DDR4) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (0) (0) • Port 6 direction register (DDR6) bit 15 ………… 8 Address : 000016H (DDR7) Access Initial value 7 6 5 4 3 2 1 0 D65 D64 D63 D62 D61 D60 () () () () (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) • Port 7 direction register (DDR7) bit Address : 000017H Access Initial value 15 14 13 12 11 10 9 8 7 ………… 0 D74 D73 D72 D71 (DDR6) () () () () () (R/W) (R/W) (R/W) (R/W) () () (0) (0) (0) (0) () (Continued) 36 MB90580C Series • Port 8 direction register (DDR8) bit 15 ………… 8 Address : 000018H (DDR9) Access Initial value 7 6 5 4 3 2 1 0 D87 D86 D85 D84 D83 D82 D81 D80 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (0) (0) • Port 9 direction register (DDR9) ………… 14 8 bit 15 15 Address : 000019H 13 7 12 6 11 5 10 4 39 28 ………… 7 1 0 0 D97 D96 RD07 D95 RD06 D94 RD05 D93 RD04 D92 RD03 D91 RD02 D90 RD01 (DDR8) (RDR1) RD00 Access Initial value (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (0) (0) (0) (0) (0) • Port A direction register (DDRA) bit 15 ………… 8 Address : 00001AH (ODR4) Access Initial value 7 6 5 4 3 2 1 0 DA2 DA1 DA0 () () () () () () () () () () 13 12 11 10 9 (R/W) (R/W) (R/W) (0) (0) (0) • Port 4 output pin register (ODR4) bit Address : 00001BH Access Initial value 15 14 OD47 OD46 OD45 OD44 OD43 OD42 OD41 OD40 : 00001CH 7 (RDR1) Access Initial value : 00008DH Access Initial value 5 4 3 2 1 0 6 5 4 3 2 1 0 RD07 RD06 RD05 RD04 RD03 RD02 RD01 RD00 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (0) (0) • Port 1 input pull-up resistor setup register (RDR1) bit 15 14 13 Address 6 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (1) (1) (1) (1) (1) (1) (1) (1) • Port 0 input pull-up resistor setup register (RDR0) bit 15 ………… 8 7 : 00008CH (DDRA) ADE7 ADE6 ADE5 ADE4 ADE3 ADE2 ADE1 ADE0 Access Initial value Address 7 ………… 0 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (0) (0) • Port 5 analog input enable register (ADER) bit 15 ………… 8 Address 8 12 11 10 9 8 RD17 RD16 RD15 RD14 RD13 RD12 RD11 RD10 7 ………… 0 (RDR0) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (0) (0) • Port 6 input pull-up resistor setup register (RDR6) bit 15 ………… 8 7 6 RD65 RD64 RD63 RD62 RD61 RD60 () () () () (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) Address : 00008EH Access Initial value (CDCR4) 5 4 3 2 1 0 37 MB90580C Series (3) Block Diagram • Input/output port Internal data bus Data register read Data register Pin Data register write Direction register Direction register write Direction register read • Input pull-up resistor setup register Pull-up resistor (About 50 kΩ) Data register Direction register Input pull-up resistor setup register Bus 38 Port I/O MB90580C Series • Output pin register Data register Port I/O Direction register Pin register Bus 39 MB90580C Series 2. Timebase Timer The time-base timer consists of a 18-bit timer and an interval interrupt control circuit. Note that the time-base timer uses the oscillation clock regardless of the setting of the MCS bit in the CKSCR. (1) Register configuration • Timebase timer control register bit Address : 0000A9H Access Initial value 15 14 13 12 11 10 Reserved TBIE TBOF TBR TBC1 TBC0 (R/W) (1) () () () () (R/W) (R/W) (0) (0) (R/W) (R/W) (0) (0) (W) (1) 9 8 TBTC (2) Block Diagram Main clock TBTC Selector TBC1 TBC0 TBR TBIE AND Q 212 214 216 219 TBTRES Clock input Time-base timer 211 213 215 218 S R TBOF Time-base interrupt WDTC WT1 Selector CLR WT0 F2MC-16LX bus 2-bit counter OF Watchdog reset generator CLR WTE To WDGRST internal reset generator WTC WDCS SCE AND Q S R WTC2 WTC1 WTC0 Selector WTR WTIE WTOF AND Q S R 29 210 211 212 213 214 215 WTRES 210 213 214 215 Clock timer Clock input Subclock Clock interrupt WDTC PONR STBR From power-on reset generator From hardware standby control circuit WRST ERST SRST 40 From RST pin From RST bit in STBYC register MB90580C Series 3. Watchdog Timer The watchdog timer consists of a 2-bit watchdog counter using carry signals from the 18-bit time-base timer as the clock source, a control register, and a watchdog reset control section. (1) Register configuration • Watchdog timer control register bit Address 7 : 0000A8H 6 5 4 3 2 1 0 PONR STBR WRST ERST SRST WTE WT1 WT0 Access Initial value (R) (X) (R) (X) (R) (X) (R) (X) (R) (X) (W) (1) (W) (1) WDTC (W) (1) (2) Block Diagram Main clock TBTC TBC1 Selector TBC0 TBR TBIE AND Q 212 214 216 219 TBTRES Clock input Time-base timer 211 213 215 218 S R TBOF Time-base interrupt WDTC WT1 Selector 2-bit counter CLR WT0 OF Watchdog reset generator CLR WTE To WDGRST internal reset generator F2MC-16LX bus WTC WDCS SCE AND Q S R WTC2 WTC1 WTC0 Selector WTR WTIE WTOF AND Q S R 29 210 211 212 213 214 215 WTRES 210 213 214 215 Clock timer Clock input Subclock Clock interrupt WDTC PONR STBR WRST ERST SRST From power-on reset generator From hardware standby control circuit From RST pin From RST bit in STBYC register 41 MB90580C Series 4. Clock timer The clock timer has the functions of a watchdog timer clock source, a subclock oscillation settling time wait timer, and of a periodically interrupt generating interval timer. (1) Register configuration • Clock timer control register bit Address 7 : 0000AAH 6 5 4 3 2 1 0 WDCS SCE WTIE WTOF WTR WTC2 WTC1 WTC0 Access Initial value (R/W) (1) (R) (X) WTC (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (2) Block Diagram Main clock TBTC TBC1 Selector TBC0 TBR TBIE AND Q Clock input 212 214 216 219 TBTRES Time-base timer 211 213 215 218 S R TBOF Time-base interrupt WDTC WT1 Selector 2-bit counter CLR WT0 OF Watchdog reset generator CLR WTE To WDGRST internal reset generator F2MC-16LX bus WTC WDCS SCE AND Q S R WTC2 WTC1 WTC0 Selector WTR WTIE WTOF AND Q S R 29 210 211 212 213 214 215 WTRES 210 213 214 215 Clock timer Clock input Subclock Clock interrupt WDTC PONR STBR From power-on reset generator From hardware standby control circuit WRST ERST SRST 42 From RST pin From RST bit in STBYC register MB90580C Series 5. External Memory Access (External Bus Pin Control Circuit) The external bus pin control circuit controls external bus pins used to expand the address/data buses of the CPU outside. (1) Register configuration • Automatic ready function selection register 15 bit Address 14 13 12 IOR1 IOR0 HMR1 HMR0 : 0000A5H Access Initial value 11 10 9 8 LMR1 LMR0 (W) (0) (W) (0) (W) (1) (W) (1) () () () () (W) (0) (W) (0) 7 6 5 4 3 2 1 0 E23 E22 E21 E20 E19 E18 E17 E16 (W) (0) (W) (0) (W) (0) (W) (0) (W) (0) (W) (0) (W) (0) (W) (0) 15 14 13 12 11 10 9 8 CKE RYE HDE IOBS HMBS WRE LMBS (W) (0) (W) (0) (W) (0) () () ARSR • External address output control register bit Address : 0000A6H Access Initial value HACR • Bus control signal selection register bit Address : 0000A7H Access Initial value (W) (0) (W) (0) (W) (0) (W) (0) ECSR (2) Block Diagram P0 P0 data P1 P2 P3 P3 P0 P0 direction RB Data control Address control Access control Access control 43 MB90580C Series 6. PWC Timer The PWC (pulse width count) timer is a 16-bit multifunction up-counter with reload timer functions and inputsignal pulse-width count functions as well. The PWC timer consists of a 16-bit counter, a input pulse divider, a divide ratio control register, a count input pin, a pulse output pin, and a 16-bit control register. (1) Features of the PWC timer The PWC timer has the following features: • Timer functions Generates an interrupt request at set time intervals. Outputs pulse signals synchronized with the timer cycle. Selects the counter clock from among three internal clocks. • Pulse-width count functions Counts the time between external pulse input events. Selects the counter clock from among three internal clocks. Count mode •H pulse width (rising edge to falling edge)/L pulse width (falling edge to rising edge) •Rising-edge cycle (rising edge to falling edge)/Falling-edge cycle (falling edge to rising edge) •Count between edges (rising or falling edge to falling or rising edge) Capable of counting cycles by dividing input pulses by 22, 24, 26, 28 using an 8-bit input divider. Generates an interrupt request upon the completion of count operation. Selects single or consecutive count operation. 44 MB90580C Series (2) Register configuration • PWC control status register Upper bit Address : 000055H Access Initial value 15 14 13 12 11 10 STRT STOP EDIR EDIE OVIR OVIE (R/W) (R/W) (0) (0) (R/W) (R/W) (R/W) (0) (0) (0) (R) (0) 9 8 ERR POUT PWCSR upper (R) (0) (R/W) (0) 1 0 • PWC control status register Lower bit Address : 000054H 7 6 CKS1 CKS0 Access Initial value 5 4 ReservedReserved 3 S/C 2 MOD2 MOD1 MOD0 PWCSR lower (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (0) (0) • PWC data buffer register Upper bit Address 15 14 13 12 11 10 9 8 : 000057H PWCR upper Access Initial value (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (X) (X) (X) (X) (X) (X) (X) (X) • PWC data buffer register Lower bit Address 7 6 5 4 3 2 1 0 : 000056H PWCR lower Access Initial value (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (X) (X) (X) (X) (X) (X) (X) (X) • Divide ratio control register bit Address : 000058H Access Initial value 7 6 5 4 3 2 1 0 DIV1 DIV0 () () () () () () () () () () () () (R/W) (R/W) (0) (0) 7 6 5 4 3 2 1 0 SW0 EN DIVR • PWC noise filter register bit Address : 000086H Access Initial value SW1 () () () () () () () () () () (R/W) (R/W) (R/W) (0) (0) (0) RNCR 45 MB90580C Series (3) Block Diagram PWCR read Error detection ERR 16 PWCR Write enable 16 16 Internal clock (Machine clock/4) Reload Data transfer 16 Clock Overflow F2MC-16LX bus Timer clear Control bit output Flag set Control circuit Start edge End edge selection selection Count end edge Edge detection Count start edge Count end interrupt request 15 Overflow interrupt request ERR 23 Count enable Clock divider CKS1, CKS0 Divider clear Divider ON/OFF SW1 SW0 Noise Canceller EN 8-bit divider CKS1 CKS0 Overflow PWCSR 2 Divide ratio selection DIVR 46 22 16-bit up-count timer F.F. POT PWC MB90580C Series 7. 16-bit I/O timer The 16-bit I/O timer module consists of one 16-bit free run timer, four input capture circuits, and two output comparators. This module allows two independent waveforms to be output on the basis of the 16-bit free run timer. Input pulse width and external clock periods can, therefore, be measured. (1) 16-bit free-run timer (1 channel) The 16-bit free run timer consists of a 16-bit up-counter, a control register, and a prescaler. The value output from this timer/counter is used as the base time for the input capture and output compare modules. • Counter operation clock (Selectable from among the following four) Four internal clock cycles: φ/4, φ/16, φ/64, φ/256 φ: Machine clock • Interrupts An interrupt can be generated when the 16-bit free-run timer causes a counter overflow or by compare/match operation with compare register 0. (The compare/match operation requires the mode setting). • Counter value An interrupt can be generated when the 16-bit free-run timer causes a counter overflow or when a match with compare register 0 occurs (The compare/match function can be used by the appropriate mode setting). • Initialization The counter value can be initialized to “0000H” at a reset, soft clear operation, or a match with compare register 0. (2) Output compare module (2 channels) The output compare module consists of two 16-bit compare registers, compare output latches, and control registers. When the 16-bit free-run timer value matches the compare register value, this module generates an interrupt while inverting the output level. • Two compare registers can operate independently. Output pin and interrupt flag for each compare register • A pair of compare registers can be used to control the output pin. Two compare registers can be used to invert the output pin polarity. • The initial value for each output pin can be set. • An interrupt can be generated by compare/match operation. (3) Input capture module (4 channels) The input capture module consists of capture registers and control registers respectively associated with four independent external input pins. This module can hold the 16-bit free run timer value in the capture register. In addition, it can detect an arbitrary edge of the signal input from each external input pin to generate an interrupt. • The external input signal edge to be detected can be selected. One or both of the rising and falling edges can be selected. • Four input capture channels can operate independently. • An interrupt can be generated at a valid edge of the external input signal. The extended intelligent I/O service can be activated by the interrupt by the input capture module. 47 MB90580C Series (4) Register configuration • Timer data register (upper) bit Address : 00006DH Access Initial value 15 14 13 12 11 10 9 8 T15 T14 T13 T12 T11 T10 T09 T08 TCDTH (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (0) (0) • Timer data register (lower) bit Address : 00006CH Access Initial value 7 6 5 4 3 2 1 0 T07 T06 T05 T04 T03 T02 T01 T00 TCDTL (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (0) (0) • Timer control status register bit Address 7 6 Reserved : 00006EH Access Initial value 5 4 3 2 1 0 IVF IVFE STOP MODE CLR CLK1 CLK0 TCCS () (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (0) (0) • Compare register (upper) bit Address : ch0 00005BH : ch1 00005DH Access Initial value 15 C15 14 C14 13 12 C13 C12 11 C11 10 C10 9 C09 8 OCCP0 OCCP1 C08 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (X) (X) (X) (X) (X) (X) (X) (X) • Compare register (lower) bit Address : ch0 00005AH : ch1 00005CH Access Initial value 7 6 5 4 3 C07 C06 C05 C04 C03 2 1 0 C02 C01 C00 OCCP0 OCCP1 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (X) (X) (X) (X) (X) (X) (X) (X) • Compare control status register 1 bit Address : ch1 00005FH Access Initial value 15 14 13 12 11 10 9 8 CMOD OTE1 OTE0 OTD1 OTD0 () () () () () () (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) 7 6 5 OCS1 • Compare control status register 0 bit Address : ch0 00005EH Access Initial value 3 2 ICP1 ICP0 ICE1 ICE0 4 1 0 (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) () () () (R/W) (R/W) () (0) (0) CST1 CST0 OCS0 (Continued) 48 MB90580C Series (Continued) • Input capture register (upper) Address bit : ch0 000061H : ch1 000063H : ch2 000065H : ch3 000067H Access Initial value 15 14 13 12 11 10 9 8 IPCP0 upper IPCP1 upper IPCP2 upper IPCP3 upper CP15 CP14 CP13 CP12 CP11 CP10 CP09 CP08 (R) (X) (R) (X) (R) (X) (R) (X) (R) (X) (R) (X) (R) (X) (R) (X) • Input capture register (lower) Address bit : ch0 000060H : ch1 000062H : ch2 000064H : ch3 000066H Access Initial value 7 6 5 4 3 2 1 0 CP07 CP06 CP05 CP04 CP03 CP02 CP01 CP00 (R) (X) (R) (X) (R) (X) (R) (X) (R) (X) (R) (X) (R) (X) (R) (X) 7 6 5 4 3 2 1 0 IPCP0 lower IPCP1 lower IPCP2 lower IPCP3 lower • Input capture control status register 01 bit Address : 000068H ICP1 ICP0 ICE1 ICE0 EG11 EG10 EG01 EG00 Access Initial value ICS01 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (0) (0) • Input capture control status register 23 bit Address : 00006AH Access Initial value 7 6 5 4 3 2 1 0 ICP3 ICP2 ICE3 ICE2 EG31 EG30 EG21 EG20 ICS23 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (0) (0) 49 MB90580C Series (5) Block Diagram φ Interrupt request IVF IVFE STOP MODE CLR Frequency divider CLK1 CLK0 Comparator 0 16-bit up-counter Clock F2MC-16LX bus Output count value (T15 to T00) Compare control T Q OTE0 OUT0 OTE1 OUT1 Compare register ch.0 CMOD Compare control T Q Compare register ch.1 ICP1 ICP0 ICE1 ICE0 Compare interrupt 0 Control block Compare interrupt 1 Each control block Edge detection Input capture data register ch.0, ch.2 IN0, IN2 EG11 EG10 EG01 EG00 Edge detection Input capture data register ch.1, ch.3 ICP1 ICP0 ICE1 IN1, IN3 ICE0 Capture interrupt 1/3 Capture interrupt 0/2 50 MB90580C Series 8. 16-bit Reload Timer The 16-bit reload timer has three channels, each of which consists of a 16-bit down counter, a 16-bit reload register, an input pin (TIN), an output pin (TOT), and a control register. The input clock can be selected from among three internal clocks and one external clock. (1) Register configuration • Timer control status register (upper) Address bit : ch0 000049H : ch1 00004DH : ch2 000051H Access Initial value 15 14 13 12 11 10 9 8 () () () () () () () (R/W) (R/W) (R/W) (R/W) () (0) (0) (0) (0) CSL1 CSL0 MOD2 MOD1 TMCSR0 upper TMCSR1 upper TMCSR2 upper • Timer control status register (lower) Address bit : ch0 000048H : ch1 00004CH : ch2 000050H Access Initial value 7 6 5 4 3 MOD0 OUTE OUTL RELD INTE 2 1 0 UF CNTE TRG (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (0) (0) • 16-bit timer register (upper) /16 bit reload register (upper) Address bit : ch0 00004BH : ch1 00004FH : ch2 000053H Access Initial value 15 14 13 12 11 10 9 8 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (X) (X) (X) (X) (X) (X) (X) (X) • 16-bit timer register (lower) /16 bit reload register (lower) Address bit : ch0 00004AH : ch1 00004EH : ch2 000052H Access Initial value TMCSR0 lower TMCSR1 lower TMCSR2 lower 7 6 5 4 3 2 1 0 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (X) (X) (X) (X) (X) (X) (X) (X) (read) TMR0 upper TMR1 upper TMR2 upper (write) TMRLR0 upper TMRLR1 upper TMRLR2 upper (read) TMR0 lower TMR1 lower TMR2 lower (write) TMRLR0 lower TMRLR1 lower TMRLR2 lower 51 MB90580C Series (2) Block Diagram 16 16-bit reload register 8 Reload RELD 16-bit down-counter UF OUTE 16 OUTL F2MC-16LX bus 2 OUT CTL. GATE INTE UF Clock selector CNTE CSL0 TRG Retrigger 2 IN CTL Output enable EXCK φ φ φ — — — 21 23 25 Prescaler clear 3 Machine clock Clear EI2OSCLR Port (TIN) Port (TOT) MOD2 MOD1 MOD0 3 Note: Reload timer channels and UART channels are connected as follows •Reload timer channel 0 : UART0, UART3 •Reload timer channel 1 : UART1, UART4 •Reload timer channel 2 : UART2 52 IRQ CSL1 Serial baud rate (channel n) MB90580C Series 9. 8/16-bit PPG 8/16-bit PPG is an 8/16-bit reload timer module. The block performs PPG output in which the pulse output is controlled by the operation of the timer. The hardware consists of two 8-bit down-counters, four 8-bit reload registers, one 16-bit control register, two external pulse output pins, and two interrupt outputs. The PPG has the following functions. • 8-bit PPG output in two channels independent operation mode: Two independent PPG output channels are available. • 16-bit PPG output operation mode : One 16-bit PPG output channel is available. • 8 + 8-bit PPG output operation mode : Variable-period 8-bit PPG output operation is available by using the output of channel 0 as the clock input to channel 1. • PPG output operation : Outputs pulse waveforms with variable period and duty ratio. Can be used as a D/A converter in conjunction with an external circuit. (1) Register configuration • PPG0 operating mode control register bit Address 7 : ch0 0000044H PEN0 Access Initial value 6 5 4 3 POE0 PIE0 PUF0 2 1 0 Reserved (R/W) () (R/W) (R/W) (R/W) () (0) (X) (0) (0) (0) (X) () (R/W) (X) (1) 15 9 PPGC0 • PPG1 operating mode control register bit Address : ch1 0000045H PEN1 Access Initial value 14 13 12 11 10 8 POE1 PIE1 PUF1 MD1 MD0 Reserved PPGC1 (R/W) () (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (X) (0) (0) (0) (0) (0) (1) • PPG0 and 1 output control registers bit Address : ch0, 1 0000046H Access Initial value 7 6 5 4 3 2 PCS2 PCS1 PCS0 PCM2PCM1PCM0 1 0 ReReserved served PPGOE (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (0) (0) • Reload register H bit Address : ch0 000041H : ch1 000043H Access Initial value 15 14 13 12 11 10 9 8 PRLH0 PRLH1 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (X) (X) (X) (X) (X) (X) (X) (X) • Reload register L bit Address : ch0 000040H : ch1 000042H Access Initial value 7 6 5 4 3 2 1 0 PRLL0 PRLL1 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (X) (X) (X) (X) (X) (X) (X) (X) 53 MB90580C Series (2) Block Diagram • Block diagram (8 bit PPG (ch.0) ) PPG0 output enable PPG0 Machine clock divided by 16 Machine clock divided by 8 Machine clock divided by 4 Machine clock divided by 2 Machine clock PPG0 output latch Invert Clear PEN0 S R Q PCNT (Down-counter) IRQ Count clock selection Reload Timebase counter output oscillation clock divided by 512 ch.1 borrow L/H Selector L/H select PRLL0 PRLBH0 PIE0 PRLH0 PUF0 L-side data bus H-side data bus PPGC0 (Operation mode control) 54 MB90580C Series • Block Diagram (8/16 bit PPG (ch.1) ) PPG1 output enable Machine clock divided by 16 Machine clock divided by 8 Machine clock divided by 4 Machine clock divided by 2 Machine clock A/D converter PPG1 output latch Invert Count clock selection ch0 borrow Timebase counter output oscillation clock divided by 512 PPG1 Clear PEN1 S R Q PCNT (Down-counter) IRQ Reload L/H Selector L/H select PRLL1 PRLBH1 PIE PRLH1 PUF L-side data bus H-side data bus PPGC1 (Operation mode control) 55 MB90580C Series 10. DTP/External Interrupts The DTP (Data Transfer Peripheral) is a peripheral block that interfaces external peripherals to the F2MC-16LX CPU. The DTP receives DMA and interrupt processing requests from external peripherals and passes the requests to the F2MC-16LX CPU to activate the intelligent I/O service or interrupt processing. Two request levels (“H” and “L”) are provided for the intelligent I/O service. For external interrupt requests, generation of interrupts on a rising or falling edge as well as on “H” and “L” levels can be selected, giving a total of four types. (1) Register configuration • Interrupt/DTP enable register bit Address : 0000030H 7 6 5 4 3 2 1 0 EN7 EN6 EN5 EN4 EN3 EN2 EN1 EN0 Access Initial value ENIR (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (0) (0) • Interrupt/DTP source register bit Address : 0000031H 15 14 13 12 11 10 9 8 ER7 ER6 ER5 ER4 ER3 ER2 ER1 ER0 Access Initial value EIRR (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (X) (X) (X) (X) (X) (X) (X) (X) • Request level setting register (lower) bit Address : 0000032H Access Initial value 7 6 5 4 3 2 1 0 LB3 LA3 LB2 LA2 LB1 LA1 LB0 LA0 ELVR lower (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (0) (0) • Request level setting register (upper) bit Address : 0000033H Access Initial value 15 14 13 12 11 10 9 8 LB7 LA7 LB6 LA6 LB5 LA5 LB4 LA4 ELVR upper (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (0) (0) (2) Block Diagram F2MC-16LX bus 8 8 8 8 56 Interrupt/DTP enable register Gate Source F/F Interrupt/DTP source register Request level setting register Edge detect circuit 8 Request input MB90580C Series 11. Delayed Interrupt Generation Module The delayed interrupt generation module is used to generate the task switching interrupt. Interrupt requests to the F2MC-16LX CPU can be generated and cleared by software using this module. (1) Register configuration The DIRR register controls generation and clearing of delayed interrupt requests. Writing “1” to the register generates a delayed interrupt request. Writing “0” to the register clears the delayed interrupt request. The register is set to the interrupt cleared state by a reset. Either “0” or “1” can be written to the reserved bits. However, considering possible future extensions, it is recommended that the set bit and clear bit instructions are used for register access. • Delayed interrupt generation/release register bit Address : 00009FH Access Initial value 15 14 13 12 11 10 9 8 R0 () () () () () () () () () () () () () (R/W) () (0) DIRR (2) Block Diagram F2MC-16LX bus Delayed interrupt generation/ release decode Interrupt latch 57 MB90580C Series 12. A/D Converter The A/D converter converts analog input voltages to digital values. The A/D converter has the following features. • Conversion time: Minimum of 34.7 µs per channel (for a 12 MHz machine clock) • Uses RC-type successive approximation conversion with a sample and hold circuit. • 8/10-bit resolution • Eight program-selectable analog input channels Single conversion mode: Selectively convert one channel. Scan conversion mode: Continuously convert multiple channels. Maximum of 8 program selectable channels. Continuous conversion mode : Repeatedly convert specified channels. Stop conversion mode:Convert one channel then halt until the next activation. (Enables synchronization of the conversion start timing.) • An A/D conversion completion interrupt request. An A/D conversion completion interrupt request to the CPU can be generated on the completion of A/D conversion. This interrupt can activate EI2OS to transfer the result of A/D conversion to memory and is suitable for continuous operation. • Activation by software, external trigger (falling edge), or timer (rising edge) can be selected. (1) Register configuration • Control status register (upper) bit Address : 000037H 15 14 13 12 11 10 9 8 BUSY INT INTE PAUS STS1 STS0 STRT Access Initial value Reserved ADCS2 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) () (0) (0) (0) (0) (0) (0) (0) (0) • Control status register (lower) bit Address : 000036H 7 6 5 4 3 2 1 0 MD1 MD0 ANS2 ANS1 ANS0 ANE2 ANE1 ANE0 Access Initial value ADCS1 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (0) (0) • Data register (upper) bit Address : 000039H 15 14 13 12 11 SELB ST1 ST0 CT1 CT0 10 9 8 D9 D8 Access Initial value (W) (0) (W) (0) (W) (0) (W) (0) (W) (1) () () (R) (X) (R) (X) bit 7 6 5 4 3 2 1 0 D7 D6 D5 D4 D3 D2 D1 D0 (R) (X) (R) (X) (R) (X) (R) (X) (R) (X) (R) (X) (R) (X) (R) (X) ADCR2 • Data register (lower) Address : 000038H Access Initial value 58 ADCR1 MB90580C Series (2) Block Diagram AVCC AVRH,AVRL AVSS D/A converter Successive approximation register Comparator Sample and hold circuit Decoder AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 Input circuit MPX Data register ADCR1, 2 F2 M C 1 6 L X b u s Control status register upper Control status register lower Trigger activation ADTG Timer activation PPG1 output φ ADCS1, 2 Operating clock Prescaler 59 MB90580C Series 13. D/A Converter D/A converter is an R-2R type D/A converter with 8-bit resolution. The device contains two D/A converters. The D/A control register controls the output of the two D/A converters independently. (1) Register configuration • D/A converter data register 1 bit Address : 00003BH 15 14 13 12 11 10 9 8 DA17 DA16 DA15 DA14 DA13 DA12 DA11 DA10 DAT1 Access (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value (0) (0) (0) (0) (0) (0) (0) (0) • D/A converter data register 0 bit Address : 00003AH 7 6 5 4 3 2 1 0 DA07 DA06 DA05 DA04 DA03 DA02 DA01 DA00 DAT0 Access (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value (0) (0) (0) (0) (0) (0) (0) (0) • D/A control register 1 bit Address : 00003DH Access Initial value 15 14 13 12 11 10 9 8 DAE1 () () () () () () () () () () () () () (R/W) () (0) 7 6 5 4 3 2 1 0 DAE0 () () () () () () () () () () () () () (R/W) () (0) DACR1 • D/A control register 0 bit Address : 00003CH Access Initial value 60 DACR0 MB90580C Series (2) Block Diagram F2MC16LX - BUS DA DA DA DA DA DA DA DA 17 16 15 14 13 12 11 10 DA DA DA DA DA DA DA DA 07 06 05 04 03 02 01 00 DVR DVR DA17 DA07 2R DA16 2R DA15 R R DA11 2R R 2R R 2R R DA06 DA05 DA01 2R DA10 R DA00 2R 2R 2R 2R DAE1 DAE0 Standby control Standby control DA output channel 1 DA output channel 0 61 MB90580C Series 14. Communication Prescaler The register (clock division control register) of the communication prescaler controls division of the machine clock frequency. It is designed to provide a fixed baud rate for a variety of machine clock frequencies depending on the user setting. The output from the communication prescaler is used by the UARTs. (1) Register configuration • Clock division control registers 0 to 4 62 bit 15 14 13 12 Address : 00002CH 00002EH Access 000034H Initial value 000087H 00008FH MD () () () (R/W) (R/W) (R/W) (R/W) () (1) (1) (1) (1) (R/W) () (0) () 11 10 9 8 DIV3 DIV2 DIV1 DIV0 CDCR0 CDCR1 CDCR2 CDCR3 CDCR4 MB90580C Series 15. UART The UART is a serial I/O port for asynchronous (start-stop) communication or clock-synchronous communication. The UART has the following features: • Full-duplex double buffering • Capable of asynchronous (start-stop) and CLK-synchronous communications • Support for the multiprocessor mode • Dedicated baud rate generator integratedBaud rate Operation Asynchronous Baud rate 31250/9615/4808/2404/1202 bps CLK synchronous 2 M/1 M/500 K/250 K/125 K/62.5 Kbps * : Assuming internal machine clock frequencies of 6, 8, 10, 12, and 16 MHz • Capable of setting an arbitrary baud rate using an external clock • Error detection functions (parity, framing, overrun) • HRz sign transfer signal (1) Register configuration • Serial mode register 0 to 4 Address : 0000020H bit 0000024H 0000028H Access 0000082H Initial value 0000088H 7 6 5 4 3 MD1 MD0 CS2 CS1 CS0 2 Reserved 1 0 SCKE SOE (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (0) (0) SMR0 SMR1 SMR2 SMR3 SMR4 • Serial control register 0 to 4 Address : 0000021H bit 0000025H 0000029H Access 0000083H Initial value 0000089H 15 14 13 12 11 10 9 8 PEN P SBL CL A/D REC RXE TXE (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (1) (0) (0) SCR0 SCR1 SCR2 SCR3 SCR4 • Serial input register 0 to 4/serial output register 0 to 4 bit Address : 0000022H 0000026H Access 000002AH Initial value 0000084H 000008AH 7 6 5 4 3 2 1 0 D7 D6 D5 D4 D3 D2 D1 D0 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (X) (X) (X) (X) (X) (X) (X) (X) (read) (write) SIDR0 SODR0 SIDR1 SODR1 SIDR2 SODR2 SIDR3 SODR3 SIDR4 SODR4 • Serial status register 0 to 4 Address : 0000023H bit 0000027H 000002BH Access 0000085H Initial value 000008BH 15 PE 14 13 12 11 10 ORE FRE RDRFTDRE 9 8 RIE TIE (R/W) (R/W) (R/W) (R/W) (R/W) () (R/W) (R/W) (0) (0) (0) (0) (1) () (0) (0) SSR0 SSR1 SSR2 SSR3 SSR4 63 MB90580C Series (2) Block Diagram Control signals Receive interrupt signal (to CPU) SCK0 to SCK4 Dedicated baud rate generator Transmit interrupt signal (to CPU) Transmit clock Clock select circuit 16 bit reload timer channel 0 to 2 Receive clock External clock SIN0 ∼ SIN4 Receive control circuit Transmit control circuit Start bit detection circuit Transmit start circuit Receive bit counter Transmit bit counter Receive parity counter Transmit parity counter SOT0 to SOT4 Receive condition decision circuit Shift register for reception Shift register for transmission Reception complete Reception error generation signal for EI2OS (to CPU) SIDR0 to SIDR4 Start transmission SODR0 to SODR4 F2MC-16LX bus SMR0 to SMR4 register MD1 MD0 CS2 CS1 CS0 SCKE SOE SCR0 to SCR4 register PEN P SBL CL A/D REC RXE TXE SSR0 to SSR4 register PE ORE FRE RDRF TDRE RIE TIE Control signal 64 MB90580C Series 16. IEBusTM Controller The IEBusTM (Inter-Equipment Bus) is a small-scale, two-wire serial bus interface designed for data transfer between pieces of equipment. This interface is applicable, for example, as a bus interface for controlling vehicle-mounted devices. IEBusTM has the following features: • Multitasking Any of the units connected to the IEBusTM can transmit data to another one. • Broadcast function (Communication from one unit to multiple units) Group broadcast : Broadcast to a group of units All-unit broadcast : Broadcast to all units • Three modes can be selected for different transmission speeds. IEBusTM internal frequency 6 MHz 6.29 MHz Mode 0 About 3.9 Kbps About 4.1 Kbps Mode 1 About 17 Kbps About 18 Kbps Mode 2 About 26 Kbps About 27 Kbps • Data buffer for transmission 8-byte FIFO buffer • Data buffer for reception 8-byte FIFO buffer • CPU internal operating frequency (12 MHz, 12.58 MHz) • Frequency tolerance In mode 0 or 1 : ±1.5% In mode 2 : ±0.5% (1) Register configuration • Local-office address setting register H bit Address : 000071H 15 14 13 12 Reserved Reserved Reserved Reserved Access Initial value 11 10 9 8 MA11 MA10 MA09 MA08 MAWH (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (X) (X) (X) (X) (X) (X) (X) (X) • Local-office address setting register L bit Address : 000070H 7 6 5 4 3 2 1 0 MA07 MA06 MA05 MA04 MA03 MA02 MA01 MA00 Access Initial value MAWL (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (X) (X) (X) (X) (X) (X) (X) (X) • Slave address setting register H bit Address : 000073H Access Initial value 15 14 13 12 Reserved Reserved Reserved Reserved 11 10 9 8 SA11 SA10 SA09 SA08 SAWH (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (X) (X) (X) (X) (X) (X) (X) (X) (Continued) 65 MB90580C Series • Slave address setting register L bit Address : 000072H 7 6 5 4 3 2 1 0 SA07 SA06 SA05 SA04 SA03 SA02 SA01 SA00 SAWL Access (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value (X) (X) (X) (X) (X) (X) (X) (X) • Broadcast control bit setting register bit Address : 000075H 15 14 13 12 DO3 DO2 DO1 DO0 11 10 9 8 C3 C2 C1 C0 DCWR Access (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value (0) (0) (0) (0) (0) (0) (0) (0) • Broadcast control bit read register bit Address : 00007FH 15 14 13 12 DO3 DO2 DO1 DO0 Access Initial value 11 10 9 8 C3 C2 C1 C0 (R) (0) (R) (0) (R) (0) (R) (X) (R) (X) (R) (X) (R) (X) (R) (X) 7 6 5 4 3 2 1 0 DE7 DE6 DE5 DE4 DE3 DE2 DE1 DE0 DCRR • Message length bit setting register bit Address : 000074H DEWR Access (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value (0) (0) (0) (0) (0) (0) (0) (0) • Message length bit read register bit Address 7 6 5 4 3 2 1 0 DE7 DE6 DE5 DE4 DE3 DE2 DE1 DE0 Access Initial value (R) (X) (R) (X) (R) (X) (R) (X) (R) (X) (R) (X) (R) (X) (R) (X) bit 15 14 13 12 11 10 9 8 : 00007EH DERR • Command register H Address : 000077H MD1 MD0 PCOM RIE TIE GOTMGOTS Reserved CMRH Access (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value (0) (0) (0) (0) (0) (0) (0) (X) • Command register L bit Address : 000076H 7 6 RXS TXS 5 4 TIT1 TIT0 3 CS1 2 1 0 CS0 RDBC WDBC CMRL Access (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value (1) (1) (0) (0) (0) (0) (0) (0) • Status register H bit Address : 000079H Access Initial value 15 14 13 12 11 10 9 8 COM TE PEF ACK RIF TIF TSL EOD (R) (0) (R) (0) (R) (R/W) (0) (0) (R) (X) (R) (R/W) (R/W) (X) (0) (0) STRH (Continued) 66 MB90580C Series (Continued) • Status register L bit Address : 000078H 7 6 5 4 WDBF RDBF WDBE RDBE Access Initial value 3 2 1 0 ST3 ST2 ST1 ST0 (R) (0) (R) (0) (R) (1) (R) (1) (R) (X) (R) (X) (R) (X) (R) (X) 15 14 13 12 11 10 9 8 STRL • Lock read register H bit Address : 00007BH Reserved Reserved Reserved Access Initial value LOC LD11 LD10 LD09 LD08 (R) (1) (R) (1) (R) (1) (R/W) (0) (R) (X) (R) (X) (R) (X) (R) (X) 7 6 5 4 3 2 1 0 LD07 LD06 LD05 (R) (X) (R) (X) (R) (X) (R) (X) (R) (X) (R) (X) (R) (X) (R) (X) 15 14 13 12 11 10 9 8 LRRH • Lock read register L bit Address : 00007AH Access Initial value LD04 LD03 LD02 LD01 LD00 LRRL • Master address read register H bit Address : 00007DH Reserved Reserved Reserved Reserved Access Initial value MA11 MA10 MA09 MA08 (R) (1) (R) (1) (R) (1) (R) (1) (R) (X) (R) (X) (R) (X) (R) (X) 7 6 5 4 3 2 1 0 MARH • Master address read register L bit Address : 00007CH MA07 MA06 MA05 MA04 MA03 MA02 MA01 MA00 Access Initial value (R) (X) (R) (X) (R) (X) (R) (X) (R) (X) (R) (X) (R) (X) (R) (X) bit 15 14 13 12 11 10 9 8 RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 (R) (X) (R) (X) (R) (X) (R) (X) (R) (X) (R) (X) (R) (X) (R) (X) 7 6 5 4 3 2 1 0 WD7 WD6 WD5 WD4 (W) (X) (W) (X) (W) (X) (W) (X) MARL • Read data buffer Address : 000081H Access Initial value RDB • Write data buffer bit Address : 000080H Access Initial value WD3 WD2 WD1 WD0 (W) (X) (W) (X) (W) (X) WDB (W) (X) 67 MB90580C Series (2) Block Diagram Local-office address setting register Broadcast control bit setting register Message length bit setting register TX 8-byte FIFO, write data buffer Master address read register Broadcast control bit read register Control circuit Message length bit read register Lock read register 8-byte FIFO, read data buffer Command register IEBusTM protocol controller F2MC-16LX internal bus Slave address setting register Status register Interrupt request signal (transmission/reception) Internal clock 12 MHz/12.58 MHz 2 Prescaler 6 MHz/6.29 MHz IEBusTM controller The control circuit in the IEBusTM controller executes the following control functions: • Controls the number of bytes in data to be transmitted and received. • Controls the maximum number of bytes transmitted. • Detects the results of arbitration. • Evaluates the return of acknowledgment of each field. • Generates interrupt signals. 68 RX MB90580C Series 17. Clock Monitor Function The clock monitor function outputs the frequency-divided machine clock signal (for monitoring purposes) from the CKOT pin. (1) Register configuration • Clock output enable register bit Address : 00003EH Access Initial value 7 6 5 4 3 2 1 0 CKEN FRQ2 FRQ1 FRQ0 () () () () () () () (R/W) (R/W) (R/W) (R/W) () (0) (0) (0) (0) CLKR F2MC-16LX bus (2) Block Diagram CKEN FRQ2 FRQ1 FRQ0 Divider circuit Machine clock φ P65/CKOT 69 MB90580C Series 18. Address Match Detection Function When an address matches the value set in the address detection register, the instruction code to be loaded into the CPU is forced to be replaced with the INT9 instruction code (01H). When executing a set instruction, the CPU executes the INT9 instruction. The address match detection function is implemented by processing using the INT9 interrupt routine. The device contains two address detection registers, each provided with a compare enable bit. When the value set in the address detection register matches an address and the interrupt enable bit is “1”, the instruction code to be loaded into the CPU is forced to be replaced with the INT9 instruction code. (1) Register configuration • Program address detection register 0 to 2 (PADR0) 7 bit PADR0 (lower) bit bit 1 0 17 16 15 14 13 12 11 10 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (X) (X) (X) (X) (X) (X) (X) (X) 7 6 5 4 3 2 1 0 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (X) (X) (X) (X) (X) (X) (X) (X) 16 15 14 13 12 11 10 Address : 001FF3H Access Initial value bit Address : 001FF4H Access Initial value bit PADR1 (upper) 2 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (X) (X) (X) (X) (X) (X) (X) (X) • Program address detection register 3 to 5 (PADR1) bit 17 PADR1 (middle) 3 Address : 001FF2H Access Initial value PADR1 (lower) 4 Address : 001FF1H Access Initial value PADR0 (upper) 5 Address : 001FF0H Access Initial value PADR0 (middle) 6 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (X) (X) (X) (X) (X) (X) (X) (X) 7 6 5 4 3 2 1 0 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (X) (X) (X) (X) (X) (X) (X) (X) 17 16 15 14 13 12 11 10 Address : 001FF5H Access Initial value (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (X) (X) (X) (X) (X) (X) (X) (X) • Program address detection control/status register (PACSR) bit 7 6 5 4 3 2 1 0 ReReReReReReAD1E AD0E Address : 00009EH served served served served served served (−) (−) (−) (−) (R/W) (−) (R/W) (−) Access (0) (0) (0) (0) (0) (0) (0) (0) Initial value 70 MB90580C Series Address latch Address detection register Enable bit Compare (2) Block Diagram INT9 Instruction F2MC-16LX CPU core F2MC-16LX bus 71 MB90580C Series 19. ROM Mirroring Function Selection Module The ROM mirroring function selection module can select what the FF bank allocated the ROM sees through the 00 bank according to register settings. (1) Register configuration • ROM mirroring function selection register bit Address 15 14 13 12 11 10 9 8 MI () () () () () () () (W) : 00006FH Access (2) Block Diagram F2MC-16LX bus ROM mirroring function selection register Address area Address Data 72 FF bank 00 bank ROM ROMM MB90580C Series 20. One-Megabit Flash Memory The 1Mbit flash memory is allocated in the FEH to FFH banks on the CPU memory map. Like masked ROM, flash memory is read-accessible and program-accessible to the CPU using the flash memory interface circuit. The flash memory can be programmed/erased by the instruction from the CPU via the flash memory interface circuit. The flash memory can therefore be reprogrammed (updated) while still on the circuit board under integrated CPU control, allowing program code and data to be improved efficiently. Note that sector operations such as “enable sector protect” cannot be used. Features of 1Mbit flash memory • 128K words x 8 bits or 64K words x 16 bits (16K + 512 x 2 + 7K + 8K + 32K + 64K) sector configuration • Automatic program algorithm (Embedded Algorithm*: Same as the MBM29F400TA) • Erasure suspend/resume function integrated • Detection of programming/erasure completion using the data polling or toggle bit • Detection of programming/erasure completion using CPU interrupts • Compatible with JEDEC standard commands • Capable of erasing data sector by sector (arbitrary combination of sectors) • Minimum number of times of programming/erasure: 100,000 * : Embedded Algorithm is a trademark of Advanced Micro Devices, Inc. (1) Register configuration • Flash memory control status register bit Address 7 : 0000AEH INTE Access Initial value (R/W) (0) 6 RDYINT (R/W) (0) 5 4 3 2 1 0 WE RDY Reserved LPM1 Reserved LPM0 (R/W) (0) (R) (X) (W) (0) (R/W) (0) (W) (0) (R/W) (0) FMCS 73 MB90580C Series (2) Sector configuration of 1Mbit flash memory The 1Mbit flash memory has the sector configuration illustrated below. The addresses in the illustration are the upper and lower addresses of each sector. When accessed from the CPU, SA0 and SA1 to SA4 are allocated in the FE and FF bank registers, respectively. Flash memory FFFFFFH Programmer address * 7FFFFH FFC000H FFBFFFH 7C000H 7BFFFH FFA000H FF9FFFH 7A000H 79FFFH FF8000H FF7FFFH 78000H 77FFFH FF0000H FEFFFFH 70000H 6FFFFH FE0000H 60000H CPU address SA4 (16 Kbytes) SA3 (8 Kbytes) SA2 (8 Kbytes) SA1 (32 Kbytes) SA0 (64 Kbytes) * : Programmer addresses correspond to CPU addresses when data is programmed in flash memory by a parallel programmer. Programmer addresses are used to program/erase data using a general-purpose programmer. 74 MB90580C Series 21. Low-Power Consumption Control Circuit The operation modes of the MB90580C series are the PLL clock, PLL sleep, watch, main clock, main sleep, stop, and hardware standby modes. The operation modes excluding the PLL clock mode are classified as lowpower consumption modes. The low power consumption circuit has the following functions. • Main clock mode/Main sleep mode In either mode, the microcontroller operates only with the main clock (OSC oscillation clock), using the main clock as the operating clock while suspending the PLL clock (VCO oscillation clock). • PLL sleep mode/Main sleep mode These modes stop only the operation clock of the CPU, leaving the other clocks active. • Watch mode The watch mode allows only the time-base timer to operate. • Stop mode/Hardware standby mode These modes stop oscillation while retaining data at the lowest power consumption. The CPU intermittent operation function causes the clock supplied to the CPU to operate intermittently when the CPU accesses a register, internal memory, internal resource, or external bus. This function saves power consumption by decreasing the execution speed of the CPU while providing high-speed clock signals to the internal resources. The PLL clock multiplication factor can be selected from among 1, 2, 3, and 4 using the CS1 and CS0 bits in the clock selection register. The WS1 and WS0 bits can be used to set the oscillation settling time for the main clock, which is taken to wake up from the stop or hardware standby mode. (1) Register configuration • Low-power consumption mode control register bit Address : 0000A0H 7 6 5 4 3 2 1 STP SLP SPL RST TMD CG1 CG0 Access Initial value (W) (0) (W) (R/W) (W) (0) (0) (1) 0 LPMCR () (R/W) (R/W) () (1) (0) (0) () • Clock selection register bit Address : 0000A1H Access Initial value 15 14 13 12 11 10 9 8 SCM MCM WS1 WS0 SCS MCS CS1 CS0 (R) (1) CKSCR (R) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (1) (1) (1) (1) (1) (0) (0) 75 MB90580C Series (2) Block Diagram CKSCR SCM SCS Sub clock (OSC oscillation) Subclock switching controller CKSCR MCM MCS Main clock (OSC oscillation) PLL multiplication circuit 1 2 3 4 CPU clock generation F2MC-16LX bus CKSCR 1/2 S CS1 0/9/17/33 intermittent cycle selection CPU clock selector CS0 LPMCR CG1 CG0 LPMCR CPU intermittent operation cycle selector Peripheral clock generation SCM SLP TMD RST WS1 WS0 Peripheral clock SLEEP Standby control circuit STP CKSCR CPU clock Cancel Oscillation stability waiting time selector MSTP Main OSC stop Sub OSC stop STOP HST Start 210 213 215 218 Clock input HST pin Interrupt request or RST Timebase timer 212 214 216 219 LPMCR SPL LPMCR RST Pin hi-impedance control circuit Internal reset generation signal circuit Pin Hi-Z RST pin Internal RST To watchdog timer WDGRST 76 MB90580C Series ■ ELECTRICAL CHARACTERISTICS 1. Absolute Maximum Ratings Parameter (VSS = AVSS = 0.0 V) Rating Symbol Unit Remarks Min. Max. VCC VSS − 0.3 VSS + 6.0 V AVCC VSS − 0.3 VSS + 6.0 V VCC ≥ AVCC *1 AVRH, AVRL VSS − 0.3 VSS + 6.0 V AVCC ≥ AVRH/L, AVRH ≥ AVRL DVCC VSS − 0.3 VSS + 6.0 V VCC ≥ DVCC Input voltage VI VSS − 0.3 VSS + 6.0 V *2 Output voltage VO VSS − 0.3 VSS + 6.0 V *2 “L” level maximum output current IOL 15 mA *3 “L” level average output current IOLAV 4 mA Average output current = operating current × operating efficiency “L” level total maximum output current ΣIOL 100 mA ΣIOLAV 50 mA Average output current = operating current × operating efficiency IOH −15 mA *3 “H” level average output current IOHAV −4 mA Average output current = operating current × operating efficiency “H” level total maximum output current ΣIOH −100 mA ΣIOHAV −50 mA Power consumption PD 300 mW Operating temperature TA −40 +85 °C Tstg −55 +150 °C Power supply voltage “L” level total average output current “H” level maximum output current “H” level total average output current Storage temperature Average output current = operating current × operating efficiency *1 : AVCC shall never exceed VCC when power on. *2 : VI and VO shall never exceed VCC + 0.3 V. *3 : The maximum output current is a peak value for a corresponding pin. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. 77 MB90580C Series 2. Recommended Operating Conditions Parameter Power supply voltage “H” level input voltage “L” level input voltage Symbol Value (VSS = AVSS = 0.0 V) Unit Remarks 5.5 V Normal operation (MB90583C/CA, MB90587C/CA, MB90V580B) 4.5 5.5 V Normal operation (MB90F583C/CA) VCC 3.0 5.5 V Retains status at the time of operation stop VIH 0.7 VCC VCC+0.3 V CMOS input pin VIHS 0.8 VCC VCC+0.3 V CMOS hysteresis input pin VIHM VCC − 0.3 VCC+0.3 V MD pin input VIL VSS − 0.3 0.3 VCC V CMOS input pin VILS VSS − 0.3 0.2 VCC V CMOS hysteresis input pin VILM VSS − 0.3 VSS+0.3 V MD pin input Use a ceramic capacitor or a capacitor with equivalent frequency characteristics. The smoothing capacitor to be connected to the VCC pin must have a capacitance value higher than CS. VCC Min. Max. 3.0 Smoothing capacitor CS 0.1 1.0 µF Operating temperature TA −40 +85 °C • C pin connection circuit C CS WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. 78 MB90580C Series 3. DC Characteristics (VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C) Pin name Parameter Symbol “H” level output voltage VOH All output VCC = 4.5 V, pins IOH = −2.0 mA “L” level output voltage VOL Input leakage current IIL Condition Max. VCC − 0.5 V All output VCC = 4.5 V, pins IOL = 2.0 mA 0.4 V VCC = 5.5 V, VSS < VI< VCC −5 5 µA 27 33 mA 40 50 mA MB90F583C/CA 22 26 mA MB90583C/CA 35 45 mA MB90F583C/CA VCC = 5.0 V, Internal operation at 16 MHz, When data written in flash mode programming of erasing 45 60 mA VCC = 5.0 V, Internal operation at 12.58 MHz, When data written in flash mode programming of erasing 40 50 mA VCC = 5.0 V, Internal operation at 16 MHz, In sleep mode 7 12 mA MB90587C/CA 15 20 MB90583C/CA, mA MB90F583C /CA VCC = 5.0 V Internal operation at 12.58 MHz, In sleep mode 6 10 mA MB90587C/CA 12 18 mA MB90583C/CA, MB90F583C/CA 0.1 1.0 mA MB90583C, MB90587C 4 7 All input pins ICC VCC ICCL Remarks Typ. VCC = 5.0 V, Internal operation at 12.58 MHz, Normal operation ICCS Unit Min. VCC = 5.0 V, Internal operation at 16 MHz, Normal operation Power supply current* Value VCC = 5.0 V, Internal operation at 8 kHz, Subsystem operatin, TA = 25 °C MB90583C/CA, MB90587C/CA MB90F583C/CA mA MB90F583C (Continued) 79 MB90580C Series (Continued) Parameter (VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C) Symbol Pin name Value Unit Typ. Max. VCC = 5.0 V, Internal operation at 8 kHz, In subsleep mode, TA = 25 °C 30 50 µA MB90583C, MB90587C, MB90F583C ICCT VCC = 5.0 V, Internal operation at 8 kHz, In clock mode, TA = 25 °C 15 30 µA MB90583C, MB90587C, MB90F583C ICCH In stop mode, TA = 25 °C 5 20 µA MB90583C/CA MB90587C/CA, MB90F583C/CA VCC CIN Except AVCC, AVSS, C, VCC and VSS 10 80 pF Ileak P40 to P47 0.1 5 µA Pull-up resistance RUP P00 to P07 P10 to P17 P60 to P65 RST 25 50 100 kΩ Pull-down resistance RDOWN MD2 25 50 100 kΩ Input capacitance Open-drain output leakage current Remarks Min. ICCLS Power supply current* Condition Open-drain output setting * : The current value is preliminary value and may be subject to change for enhanced characteristics without previous notice. The power supply current is measured with an external clock. 80 MB90580C Series 4. AC Characteristics (1) Clock Timings (VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C) ConSymbol Pin name dition Parameter Clock frequency Clock cycle time Frequency fluctuation rate locked* Input clock pulse width Input clock rise/fall time Internal operating clock frequency Internal operating clock cycle time Value Min. Typ. Max. Unit Remarks fC X0, X1 3 16 MHz fCL X0A, X1A 32.768 kHz tHCYL X0, X1 62.5 333 ns tLCYL X0A, X1A 30.5 µs ∆f 5 % PWH PWL X0 10 ns PWLH PWLL X0A 15.2 µs tCR tCF X0 5 ns fCP 1.5 16 MHz Main clock operation fLCP 8.192 kHz Subclock operation tCP 62.5 — 666 ns Main clock operation tLCP 122.1 µs Subclock operation Recommened duty ratio of 30% to 70% External clock operation *: The frequency fluctuation rate is the maximum deviation rate of the preset center frequency when the multiplied PLL signal is locked. + ∆f = α fo +α × 100 (%) Center frequency fo −α − • X0, X1 clock timing tHCYL 0.8 VCC X0 0.2 VCC PWH PWL tCF tCR • X0A, X1A clock timing tLCYL 0.8 VCC X0A 0.2 VCC PWLH PWLL tCF tCR 81 MB90580C Series • PLL operation guarantee range Power supply voltage VCC (V) Relationship between internal operating clock frequency and power supply voltage Operation guarantee range of MB90F583C/CA 5.5 4.5 3.3 3.0 Operation guarantee range of MB90583C/CA, MB90587C/CA, MB90V580B 1 3 8 Operation guarantee range of PLL 12 16 Internal clock fCP (MHz) Relationship between oscillating frequency and internal operating clock frequency Internal clock fCP (MHz) 16 Multiplied- Multiplied- Multipliedby-3 by-4 by-2 12 9 8 Not multiplied 4 3 4 8 16 Oscillation clock fC (MHz) The AC ratings are measured for the following measurement reference voltages • Input signal waveform • Output signal waveform Hystheresis input pin Output pin 0.8 VCC 2.4 V 0.2 VCC 0.8 V Pins other than hystheresis input/MD input 0.7 VCC 0.3 VCC 82 Multipliedby-1 MB90580C Series (2) Clock Output Timings (VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C) Symbol Parameter Clock cycle time tCYC CLK↑ → CLK↓ tCHCL Pin name Condition CLK VCC = 5 V ± 10% Value Unit Min. Max. 62.5 ns 20 ns Remarks tCYC tCHCL 2.4 V 2.4 V 0.8 V CLK (3) Reset, Hardware Standby Input Timing (VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C) Symbol Pin name Reset input time tRSTL RST Hardware standby input time tHSTL HST Parameter Condition Value Unit Min. Max. 4 tCP ns 4 tCP ns Remarks tRSTL, tHSTL RST HST 0.2 VCC 0.2 VCC 83 MB90580C Series (4) Power-on Reset (VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C) Symbol Pin name Condition Parameter Power supply rising time tR VCC Power supply cut-off time tOFF VCC Value Unit Min. Max. 0.05 30 ms 4 ms Remarks Due to repeated operations * : VCC must be kept lower than 0.2 V before power-on. Note The above values are used for causing a power-on reset. If HST = “L”, be sure to turn the power supply on using the above values to cause a power-on reset whether or not the power-on reset is required. Some registers in the device are initialized only upon a power-on reset. To initialize these registers, turn the power supply using the above values. tR VCC 2.7 V 0.2 V 0.2 V 0.2 V tOFF Sudden changes in the power supply voltage may cause a power-on reset. To change the power supply voltage while the device is in operation, it is recommended to raise the voltage smoothly to suppress fluctuations as shown below. In this case, change the supply voltage with the PLL clock not used. If the voltage drop is 1 mV or fewer per second, however, you can use the PLL clock. VCC 3.0 V VSS 84 RAM data hold It is recommended to keep the rising speed of the supply voltage at 50 mV/ms or slower. MB90580C Series (5) Bus Timing (Read) (VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C) Symbol Pin name ALE pulse width tLHLL Effective address → ALE ↓ time Parameter Condition Value Unit Remarks Min. Max. ALE tCP/2 − 20 ns tAVLL ALE, A23 to A16, AD15 to AD00 tCP/2 − 20 ns ALE ↓ → address effective time tLLAX ALE, AD15 to AD00 tCP/2 − 15 ns Effective address → RD ↓ time tAVRL A23 to A16, AD15 to AD00, RD tCP − 15 ns Effective address → valid data input tAVDV A23 to A16, AD15 to AD00 5 tCP/2 − 60 ns RD pulse width tRLRH RD 3 tCP/2 − 20 ns RD ↓ → valid data input tRLDV RD, AD15 to AD00 3 tCP/2 − 60 ns RD ↑ → data hold time tRHDX RD, AD15 to AD00 0 ns RD ↑ → ALE ↑ time tRHLH RD, ALE tCP/2 − 15 ns RD ↑ → address effective time tRHAX ALE, A23 to A16 tCP/2 − 10 ns Effective address → CLK ↑ time tAVCH A23 to A16, AD15 to AD00, CLK tCP/2 − 20 ns RD ↓ → CLK ↑ time tRLCH RD, CLK tCP/2 − 20 ns ALE ↓ → RD ↓ time tLLRL ALE, RD tCP/2 − 15 ns 85 MB90580C Series • Bus Timing (Read) tAVCH tRLCH 2.4 V 2.4 V CLK tRHLH 2.4 V 2.4 V 2.4 V ALE tLHLL 0.8 V tRLRH 2.4 V RD tAVLL tLLAX 0.8 V tLLRL tAVRL tRLDV tRHAX 2.4 V 2.4 V 0.8 V 0.8 V A23 to A16 tAVDV AD15 to AD00 86 2.4 V 2.4 V tRHDX 0.8 VCC 0.8 V 0.8 VCC Write data Address 0.8 V 0.2 VCC 0.2 VCC MB90580C Series (6) Bus Timing (Write) (VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C) Parameter Symbol Pin name Effective address → WRH, WRL↓ time tAVWL WRH, WRL pulse width Condition Value Unit Remarks Min. Max. A23 to A16, AD15 to AD00, WRH, WRL tCP − 15 ns tWLWH WRH, WRL 3 tCP/2 − 20 ns Effective data output → WRH, WRL ↑ time tDVWH AD15 to AD00, WRH, WRL 3 tCP/2 − 20 ns WRH, WRL ↑ → data hold time tWHDX WRH, WRL, AD15 to AD00 20 ns WRH, WRL ↑ → address effective time tWHAX WRH, WRL, A23 to A16 tCP/2 − 10 ns WRH, WRL ↑ → ALE ↑ time tWHLH WRH, WRL, ALE tCP/2 − 15 ns WRH, WRL ↓ → CLK ↑ time tWLCH WRH, WRL, CLK tCP/2 − 20 ns • Bus Timing (Write) tWLCH 2.4 V CLK tWHLH 2.4 V ALE tWLWH WRH, WRL 2.4 V 0.8 V tAVWL tWHAX 2.4 V 2.4 V 0.8 V 0.8 V A23 to A16 tDVWH AD15 to AD00 2.4 V 2.4 V 2.4 V Write data Address 0.8 V tWHDX 0.8 V 0.8 V 87 MB90580C Series (7) Ready Input Timing Parameter (VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C) Symbol RDY setup time tRYHS RDY hold time tRYHH Pin name Condition RDY Value Unit Min. Max. 45 ns 0 ns Remarks Note: Use the automatic ready function when the setup time for the rising edge of the RDY signal is not sufficient. 2.4 V 2.4 V CLK ALE RD/ WRH/ WRL tRYHS RDY (wait inserted) RDY (wait not inserted) 88 tRYHS 0.2 VCC 0.2 VCC 0.8 VCC 0.8 VCC tRYHH MB90580C Series (8) Hold Timing (VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C) Parameter Symbol Pin name Condition Pins in floating status → HAK ↓ time tXHAL HAK HAK ↑ → pin valid time tHAHV HAK Value Unit Min. Max. 30 tCP ns tCP 2 tCP ns Remarks Note: More than 1 machine cycle is needed before HAK changes after HRQ pin is fetched. HAK 2.4 V 0.8 V tXHAL Pins tHAHV 2.4 V 0.8 V 2.4 V High impedance 0.8 V 89 MB90580C Series (9) UART0 to UART4 (VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C) Symbol Pin name Serial clock cycle time tSCYC SCK ↓ → SOT delay time tSLOV Valid SIN → SCK ↑ tIVSH SCK ↑ → valid SIN hold time tSHIX Serial clock “H” pulse width Parameter Condition Unit Remarks Min. Max. SCK0 to SCK4 8 tCP ns SCK0 to SCK4, SOT0 to SOT4 CL = 80 pF + 1 TTL for an output pin of SCK0 to SCK4, internal shift clock SIN0 to SIN4 mode SCK0 to SCK4, SIN0 to SIN4 −80 80 ns 100 ns 60 ns tSHSL SCK0 to SCK4 4 tCP ns Serial clock “L” pulse width tSLSH SCK0 to SCK4 4 tCP ns SCK ↓ → SOT delay time tSLOV 150 ns Valid SIN → SCK ↑ tIVSH 60 ns SCK ↑ → valid SIN hold time tSHIX 60 ns SCK0 to SCK4, CL = 80 pF + 1 TTL SOT0 to SOT4 for an output pin of external shift clock SCK0 to SCK4, mode SIN0 to SIN4 SCK0 to SCK4, SIN0 to SIN4 Note : • These are AC ratings in the CLK synchronous mode. • CL is the load capacitance value connected to pins while testing. • tCP is machine cycle time (unit:ns). 90 Value MB90580C Series • Internal shift clock mode tSCYC 2.4 V SCK 0.8 V 0.8 V tSLOV 2.4 V SOT 0.8 V tIVSH SIN tSHIX 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC • External shift clock mode tSLSH SCK 0.2 VCC tSHSL 0.8 VCC 0.8 VCC 0.2 VCC tSLOV 2.4 V SOT 0.8 V tIVSH SIN tSHIX 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC 91 MB90580C Series (10)Timer Input Timing Parameter Input pulse width (VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C) Symbol Pin name Condition tTIWH tTIWL IN0 to IN3, TIN0 to TIN2 0.8 VCC Value Min. Max. 4 tCP tTIWH (11) Timer Output Timing CLK↑→TOUT transition time CLK 0.2 VCC tTIWL (VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C) Symbol Pin name Condition tTO OUT0, OUT1, PPG0, PPG1, TOT0 to TOT2 2.4 V tTO 2.4 V TOUT 0.8 V 92 ns 0.8 VCC 0.2 VCC Parameter Unit Remarks Value Min. Max. 30 Unit ns Remarks MB90580C Series (12) Trigger Input Timimg Parameter Input pulse width (VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C) Symbol Pin name Condition tTRGH tTRGL IRQ0 to IRQ7, ADTG 0.8 VCC Value Min. Max. 5 tCP Unit Remarks ns 0.8 VCC 0.2 VCC tTRGH 0.2 VCC tTRGL 93 MB90580C Series (13) IEBusTM Timing (VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C) Symbol Pin name TX → RX delay time (rise) tDLY1 TX, RX TX → RX delay time (fall) tDLY2 TX, RX Parameter TX Value Condition Max. 0 1000 ns 0 1000 ns 0.7 VCC 0.3 VCC tDLY1 0.7 VCC RX 0.3 VCC tDLY2 MB90580C series Driver/ receiver TX TX BUS+ RX RX BUS− IEBusTM 94 Unit Min. Remarks MB90580C Series 5. A/D Converter Electrical Characteristics (3.0 V ≤ AVRH − AVRL, VCC = AVCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C) Parameter Symbol Pin name Value Min. Typ. Max. Unit Resolution 10 bit Total error ±5.0 LSB Non-linear error ±2.5 LSB Differential linearity error ±1.9 LSB Zero transition voltage VOT AN0 to AN7 AVSS − 3.5 +0.5 AVSS + 4.5 mV Full-scale transition voltage VFST AN0 to AN7 Conversion time 176 tCP ns Sampling period 64 tCP ns Analog port input current IAIN AN0 to AN7 10 µA Analog input voltage VAIN AN0 to AN7 AVRL AVRH V AVRH AVRL + 2.7 AVCC V AVRL 0 AVRH − 2.7 V IA AVCC 5 mA IAH AVCC 5 µA Reference voltage Power supply current AVRH − 6.5 AVRH − 1.5 AVRH + 1.5 Remarks mV Reference voltage supply current IR AVRH 400 µA IRH AVRH 5 µA Offset between channels — AN0 to AN7 4 LSB * * * : The current when the A/D converter is not operating or the CPU is in stop mode (for VCC = AVCC = AVRH = 5.0 V) Note: • The error increases proportionally as |AVRH - AVRL| decreases. •The output impedance of the external circuits connected to the analog inputs should be in the following range. •The output impedance of the external circuit : 15.5 kΩ (Max.) (Sampling time = 4.0 µs) •If the output impedance of the external circuit is too high, the sampling time might be insufficient. C0 Comparator Analog input C1 95 MB90580C Series 6. A/D Converter Glossary Resolution : Analog changes that are identifiable with the A/D converter Linearity error : The deviation of the straight line connecting the zero transition point (“00 0000 0000” ↔ “00 0000 0001”) with the full-scale transition point (“11 1111 1110” ↔ “11 1111 1111”) from actual conversion characteristics Differential linearity error : The deviation of input voltage needed to change the output code by 1 LSB from the theoretical value Total error : The total error is defined as a difference between the actual value and the theoretical value, which includes zero-transition error/full-scale transition error and linearity error. Total error 3FF 3FE 0.5 LSB Actual conversion value Digital output 3FD {1 LSB × (N − 1) + 0.5 LSB} 004 VNT (Measured value) 003 002 001 Actual conversion value Theoretical characteristics 0.5 LSB AVRL AVRH Analog input VNT − {1 LSB × (N − 1) + 0.5 LSB} 1 LSB AVRH − AVRL [V] 1024 Total error for digital output N = 1 LSB = (Theoretical value) [LSB] VOT(Theoretical value) = AVRL + 0.5 LSB [V] VFST(Theoretical value) = AVRH − 1.5 LSB [V] VNT : Voltage at a transition of digital output from (N - 1) to N (Continued) 96 MB90580C Series (Continued) Linearity error 3FE 3FD Digital output Theoretical characteristics Actual conversion value N+1 {1 LSB × (N − 1) + VOT } VFST (Measured value) VNT 004 003 (measured value) Actual conversion value Digital output 3FF Differential linearity error Actual conversion value N V(N + 1)T N−1 (Measured value) VNT 002 001 Theoretical characteristics (Measured value) VOT AVRL (Measured value) Actual conversion value N−2 AVRH AVRL Analog input Linearity error of = digital output N VNT − {1 LSB × (N − 1) + VOT} 1 LSB Differential linearity error V (N + 1) T − VNT = 1 LSB of digital output N 1 LSB = AVRH Analog input VFST − VOT 1022 [LSB] − 1 LSB[LSB] [V] VOT : Voltage at transition of digital output from “000H” to “001H” VFST : Voltage at transition of digital output from “3FEH” to “3FFH” 97 MB90580C Series 7. Notes on Using A/D Converter Select the output impedance value for the external circuit of analog input according to the following conditions. Output impedance values of the external circuit of 7 kΩ or lower are recommended. When capacitors are connected to external pins, the capacitance of several thousand times the internal capacitor value is recommended to minimized the effect of voltage distribution between the external capacitor and internal capacitor. When the output impedance of the external circuit is too high, the sampling period for analog voltages may not be sufficient (sampling period = 4.00 µs @machine clock of 16 MHz) • Equipment of analog input circuit model C0 Analog input Comparator C1 R ≅ 1.5 kΩ, C ≅ 30 pF R ≅ 3.0 kΩ, C ≅ 65 pF R ≅ 2.2 kΩ, C ≅ 45 pF MB90587, MB90V580B MB90F583B MB90583B Note: Listed values must be considered as standards. • Error The smaller the | AVRH - AVRL |, the greater the error would become relatively. 8. D/A Converter Electrical Characteristics (VCC = AVCC = 5.0 V±10%, VSS = AVSS = DVSS = 0.0 V, TA = −40 °C to +85 °C) Parameter Value Min. Typ. Max. Unit Resolution 8 bit Differential linearity error ±0.9 LSB Absolute accuracy ±1.2 % Linearity error ±1.5 LSB Conversion time 10 20 µs Analog reference voltage DVRH VSS + 3.0 AVCC V Reference voltage supply current IDVR 120 300 µA IDVRS 10 µA Analog output impedance 20 kΩ *1 : Load capacitance: 20 pF *2 : In sleep mode 98 Symbol Pin name DVRH Remarks *1 *2 MB90580C Series ■ EXAMPLE CHARACTERISTICS • Power Suppy Current of MB90F583C/CA ICCS vs. VCC TA = 25 °C, external clock input ICC vs. VCC TA = 25 °C, external clock input 45 20 f = 16 MHz 40 f = 12 MHz f = 10 MHz 25 f = 8 MHz 20 f = 12 MHz ICCS (mA) 30 ICC (mA) f = 16 MHz 15 35 f = 10 MHz 10 f = 8 MHz f = 4 MHz 5 15 f = 2 MHz f = 4 MHz 10 0 f = 2 MHz 2 5 0 2 3 4 VCC (V) 5 5 6 ICCLS vs. VCC TA = 25 °C, external clock input (MB90F583C only) f = 8 kHz 50 60 45 40 50 35 40 ICCLS (µA) ICCL (µA) 4 VCC (V) 6 ICCL vs. VCC TA = 25 °C, external clock input (MB90F583C only) 70 3 30 f = 8 kHz 30 25 20 15 20 10 5 10 0 2 0 2 3 4 VCC (V) 5 6 3 4 VCC (V) 5 6 (Continued) 99 MB90580C Series (Continued) ICCT (µA) ICCT vs. VCC TA = 25 °C, external clock input (MB90F583C only) 30 28 26 24 22 20 28 16 14 12 10 8 6 4 2 0 f = 8 kHz 2 3 4 VCC (V) 5 1000 1000 900 900 800 800 700 700 600 600 500 400 500 400 300 300 200 200 100 100 0 0 0 1 2 3 4 5 6 7 IOH (mA) 100 VOL vs. IOL TA = 25 °C, VCC = 4.5 V VOL (V) VCC - VOH (mV) VOH vs. IOH TA = 25 °C, VCC = 4.5 V 6 8 9 10 11 12 0 1 2 3 4 5 6 7 8 IOL (mA) 9 10 11 12 MB90580C Series Power Suppy Current of MB90583C/CA ICC vs. VCC TA = 25 °C, external clock input 30 ICCS vs. VCC TA = 25 °C, external clock input 20 f = 16 MHz 25 f = 10 MHz ICCS (mA) ICC (mA) 20 f = 8 MHz 15 f = 16 MHz 15 f = 12 MHz f = 12 MHz f = 10 MHz 10 f = 8 MHz f = 4 MHz 5 10 f = 4 MHz f = 2 MHz f = 2 MHz 5 0 2 0 2 3 4 VCC (V) 5 3 4 VCC (V) 5 6 6 ICCL vs. VCC TA = 25 °C, external clock input (MB90583C only) 70 ICCLS vs. VCC TA = 25 °C, external clock input (MB90583C only) 50 f = 8 kHz 45 60 40 35 ICCLS (µA) ICCL (µA) 50 40 30 f = 8 kHz 30 25 20 15 20 10 5 10 0 2 0 2 3 4 VCC (V) 5 6 3 4 VCC (V) 5 6 (Continued) 101 MB90580C Series (Continued) ICCT (µA) ICCT vs. VCC TA = 25 °C, external clock input (MB90583C only) 30 28 26 24 22 20 28 16 14 12 10 8 6 4 2 0 f = 8 kHz 2 3 4 VCC (V) 5 6 VOL vs. IOL TA = 25 °C, VCC = 4.5 V 1000 1000 900 900 800 800 700 700 600 600 VOL (V) VCC - VOH (mV) VOH vs. IOH TA = 25 °C, VCC = 4.5 V 500 400 400 300 300 200 200 100 100 0 0 0 1 2 3 4 5 6 7 IOH (mA) 102 500 8 9 10 11 12 0 1 2 3 4 5 6 7 IOL (mA) 8 9 10 11 12 MB90580C Series ■ INSTRUCTIONS (351 INSTRUCTIONS) Table 1 Item Mnemonic # ~ RG B Operation LH AH I S T N Z V C RMW Explanation of Items in Tables of Instructions Meaning Upper-case letters and symbols: Represented as they appear in assembler. Lower-case letters: Replaced when described in assembler. Numbers after lower-case letters: Indicate the bit width within the instruction code. Indicates the number of bytes. Indicates the number of cycles. m : When branching n : When not branching See Table 4 for details about meanings of other letters in items. Indicates the number of accesses to the register during execution of the instruction. It is used calculate a correction value for intermittent operation of CPU. Indicates the correction value for calculating the number of actual cycles during execution of the instruction. (Table 5) The number of actual cycles during execution of the instruction is the correction value summed with the value in the “~” column. Indicates the operation of instruction. Indicates special operations involving the upper 8 bits of the lower 16 bits of the accumulator. Z : Transfers “0”. X : Extends with a sign before transferring. – : Transfers nothing. Indicates special operations involving the upper 16 bits in the accumulator. * : Transfers from AL to AH. – : No transfer. Z : Transfers 00H to AH. X : Transfers 00H or FFH to AH by signing and extending AL. Indicates the status of each of the following flags: I (interrupt enable), S (stack), T (sticky bit), N (negative), Z (zero), V (overflow), and C (carry). * : Changes due to execution of instruction. – : No change. S : Set by execution of instruction. R : Reset by execution of instruction. Indicates whether the instruction is a read-modify-write instruction. (a single instruction that reads data from memory, etc., processes the data, and then writes the result to memory.) * : Instruction is a read-modify-write instruction. – : Instruction is not a read-modify-write instruction. Note: A read-modify-write instruction cannot be used on addresses that have different meanings depending on whether they are read or written. • Number of execution cycles The number of cycles required for instruction execution is acquired by adding the number of cycles for each instruction, a corrective value depending on the condition, and the number of cycles required for program fetch. Whenever the instruction being executed exceeds the two-byte (word) boundary, a program on an internal ROM connected to a 16-bit bus is fetched. If data access is interfered with, therefore, the number of execution cycles is increased. For each byte of the instruction being executed, a program on a memory connected to an 8-bit external data bus is fetched. If data access in interfered with, therefore, the number of execution cycles is increased. When a general-purpose register, an internal ROM, an internal RAM, an internal I/O device, or an external bus is accessed during intermittent CPU operation, the CPU clock is suspended by the number of cycles specified by the CG1/0 bit of the low-power consumption mode control register. When determining the number of cycles required for instruction execution during intermittent CPU operation, therefore, add the value of the number of times access is done × the number of cycles suspended as the corrective value to the number of ordinary execution cycles. 103 MB90580C Series Table 2 Explanation of Symbols in Tables of Instructions Symbol A 32-bit accumulator The bit length varies according to the instruction. Byte : Lower 8 bits of AL Word : 16 bits of AL Long : 32 bits of AL and AH AH AL Upper 16 bits of A Lower 16 bits of A SP Stack pointer (USP or SSP) PC Program counter PCB Program bank register DTB Data bank register ADB Additional data bank register SSB System stack bank register USB User stack bank register SPB Current stack bank register (SSB or USB) DPR Direct page register brg1 DTB, ADB, SSB, USB, DPR, PCB, SPB brg2 DTB, ADB, SSB, USB, DPR, SPB Ri R0, R1, R2, R3, R4, R5, R6, R7 RWi RW0, RW1, RW2, RW3, RW4, RW5, RW6, RW7 RWj RW0, RW1, RW2, RW3 RLi RL0, RL1, RL2, RL3 dir Compact direct addressing addr16 addr24 ad24 0 to 15 ad24 16 to 23 Direct addressing Physical direct addressing Bit 0 to bit 15 of addr24 Bit 16 to bit 23 of addr24 io imm4 imm8 imm16 imm32 ext (imm8) disp8 disp16 bp I/O area (000000H to 0000FFH) 4-bit immediate data 8-bit immediate data 16-bit immediate data 32-bit immediate data 16-bit data signed and extended from 8-bit immediate data 8-bit displacement 16-bit displacement Bit offset vct4 vct8 Vector number (0 to 15) Vector number (0 to 255) ( )b Bit address rel ear eam rlst 104 Meaning PC relative addressing Effective addressing (codes 00 to 07) Effective addressing (codes 08 to 1F) Register list MB90580C Series Table 3 Code 00 01 02 03 04 05 06 07 Notation R0 R1 R2 R3 R4 R5 R6 R7 RW0 RW1 RW2 RW3 RW4 RW5 RW6 RW7 Effective Address Fields Address format RL0 (RL0) RL1 (RL1) RL2 (RL2) RL3 (RL3) Number of bytes in address extension * Register direct “ea” corresponds to byte, word, and long-word types, starting from the left 08 09 0A 0B @RW0 @RW1 @RW2 @RW3 Register indirect 0C 0D 0E 0F @RW0 + @RW1 + @RW2 + @RW3 + Register indirect with post-increment 10 11 12 13 14 15 16 17 @RW0 + disp8 @RW1 + disp8 @RW2 + disp8 @RW3 + disp8 @RW4 + disp8 @RW5 + disp8 @RW6 + disp8 @RW7 + disp8 Register indirect with 8-bit displacement 18 19 1A 1B @RW0 + disp16 @RW1 + disp16 @RW2 + disp16 @RW3 + disp16 Register indirect with 16-bit displacement 1C 1D 1E 1F @RW0 + RW7 @RW1 + RW7 @PC + disp16 addr16 Register indirect with index Register indirect with index PC indirect with 16-bit displacement Direct address — 0 0 1 2 0 0 2 2 Note : The number of bytes in the address extension is indicated by the “+” symbol in the “#” (number of bytes) column in the tables of instructions. 105 MB90580C Series Table 4 Number of Execution Cycles for Each Type of Addressing (a) Code Operand Number of execution cycles for each type of addressing Number of register accesses for each type of addressing 00 to 07 Ri RWi RLi 08 to 0B @RWj 2 1 0C to 0F @RWj + 4 2 10 to 17 @RWi + disp8 2 1 18 to 1B @RWj + disp16 2 1 1C 1D 1E 1F @RW0 + RW7 @RW1 + RW7 @PC + disp16 addr16 4 4 2 1 2 2 0 0 Listed in tables of instructions Listed in tables of instructions Note : “(a)” is used in the “~” (number of states) column and column B (correction value) in the tables of instructions. Table 5 Compensation Values for Number of Cycles Used to Calculate Number of Actual Cycles Operand (b) byte (c) word (d) long Cycles Access Cycles Access Cycles Access Internal register +0 1 +0 1 +0 2 Internal memory even address Internal memory odd address +0 +0 1 1 +0 +2 1 2 +0 +4 2 4 Even address on external data bus (16 bits) Odd address on external data bus (16 bits) +1 +1 1 1 +1 +4 1 2 +2 +8 2 4 External data bus (8 bits) +1 1 +4 2 +8 4 Notes: • “(b)”, “(c)”, and “(d)” are used in the “~” (number of states) column and column B (correction value) in the tables of instructions. • When the external data bus is used, it is necessary to add in the number of wait cycles used for ready input and automatic ready. Table 6 Correction Values for Number of Cycles Used to Calculate Number of Program Fetch Cycles Instruction Byte boundary Word boundary Internal memory — +2 External data bus (16 bits) — +3 External data bus (8 bits) +3 — Notes: • When the external data bus is used, it is necessary to add in the number of wait cycles used for ready input and automatic ready. • Because instruction execution is not slowed down by all program fetches in actuality, these correction values should be used for “worst case” calculations. 106 MB90580C Series Table 7 Mnemonic # Transfer Instructions (Byte) [41 Instructions] ~ RG B Operation LH AH I S T N Z V C RMW MOV MOV MOV MOV MOV MOV MOV MOV MOV MOVN A, dir A, addr16 A, Ri A, ear A, eam A, io A, #imm8 A, @A A, @RLi+disp8 A, #imm4 3 2 4 3 2 1 2 2 2+ 3+ (a) 3 2 2 2 3 2 10 3 1 1 0 0 1 1 0 0 0 0 2 0 (b) (b) 0 0 (b) (b) 0 (b) (b) 0 byte (A) ← (dir) byte (A) ← (addr16) byte (A) ← (Ri) byte (A) ← (ear) byte (A) ← (eam) byte (A) ← (io) byte (A) ← imm8 byte (A) ← ((A)) byte (A) ← ((RLi)+disp8) byte (A) ← imm4 Z Z Z Z Z Z Z Z Z Z * * * * * * * – * * – – – – – – – – – – – – – – – – – – – – – * – * – * – * – * – * – * – * – * – R * * * * * * * * * * – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – MOVX MOVX MOVX MOVX MOVX MOVX MOVX MOVX MOVX MOVX A, dir A, addr16 A, Ri A, ear A, eam A, io A, #imm8 A, @A A,@RWi+disp8 A, @RLi+disp8 3 2 4 3 2 2 2 2 2+ 3+ (a) 3 2 2 2 3 2 5 2 10 3 0 0 1 1 0 0 0 0 1 2 (b) (b) 0 0 (b) (b) 0 (b) (b) (b) byte (A) ← (dir) byte (A) ← (addr16) byte (A) ← (Ri) byte (A) ← (ear) byte (A) ← (eam) byte (A) ← (io) byte (A) ← imm8 byte (A) ← ((A)) byte (A) ← ((RWi)+disp8) byte (A) ← ((RLi)+disp8) X * X * X * X * X * X * X * X – X * X * – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – * * * * * * * * * * * * * * * * * * * * – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV /MOV dir, A addr16, A Ri, A ear, A eam, A io, A @RLi+disp8, A Ri, ear Ri, eam ear, Ri eam, Ri Ri, #imm8 io, #imm8 dir, #imm8 ear, #imm8 eam, #imm8 @AL, AH @A, T 2 3 1 2 2+ 2 3 2 2+ 2 2+ 2 3 3 3 3+ 3 4 2 2 3+ (a) 3 10 3 4+ (a) 4 5+ (a) 2 5 5 2 4+ (a) 0 0 1 1 0 0 2 2 1 2 1 1 0 0 1 0 (b) (b) 0 0 (b) (b) (b) 0 (b) 0 (b) 0 (b) (b) 0 (b) byte (dir) ← (A) byte (addr16) ← (A) byte (Ri) ← (A) byte (ear) ← (A) byte (eam) ← (A) byte (io) ← (A) byte ((RLi) +disp8) ← (A) byte (Ri) ← (ear) byte (Ri) ← (eam) byte (ear) ← (Ri) byte (eam) ← (Ri) byte (Ri) ← imm8 byte (io) ← imm8 byte (dir) ← imm8 byte (ear) ← imm8 byte (eam) ← imm8 – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – * * * * * * * * * * * * – – * – * * * * * * * * * * * * – – * – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – 2 3 0 (b) byte ((A)) ← (AH) – – – – – * * – – – XCH XCH XCH XCH A, ear A, eam Ri, ear Ri, eam 4 2 2+ 5+ (a) 7 2 2+ 9+ (a) 2 0 4 2 0 2× (b) 0 2× (b) byte (A) ↔ (ear) byte (A) ↔ (eam) byte (Ri) ↔ (ear) byte (Ri) ↔ (eam) Z Z – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – Note : For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,” and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.” 107 MB90580C Series Table 8 Transfer Instructions (Word/Long Word) [38 Instructions] RG B 2 3 3 4 1 1 1 2 2 2 2+ 3+ (a) 2 3 2 3 3 2 2 5 3 10 0 0 0 1 1 0 0 0 0 1 2 (c) (c) 0 0 0 (c) (c) (c) 0 (c) (c) word (A) ← (dir) word (A) ← (addr16) word (A) ← (SP) word (A) ← (RWi) word (A) ← (ear) word (A) ← (eam) word (A) ← (io) word (A) ← ((A)) word (A) ← imm16 – – – – – – – – – word (A) ← ((RWi) +disp8) – word (A) ← ((RLi) +disp8) – MOVW dir, A MOVW addr16, A MOVW SP, A MOVW RWi, A MOVW ear, A MOVW eam, A MOVW io, A MOVW @RWi+disp8, A MOVW @RLi+disp8, A MOVW RWi, ear MOVW RWi, eam MOVW ear, RWi MOVW eam, RWi MOVW RWi, #imm16 MOVW io, #imm16 MOVW ear, #imm16 MOVW eam, #imm16 MOVW @AL, AH /MOVW@A, T 2 3 1 1 2 2+ 2 2 3 2 2+ 2 2+ 3 4 4 4+ 3 4 1 2 2 3+ (a) 3 5 10 3 4+ (a) 4 5+ (a) 2 5 2 4+ (a) 0 0 0 1 1 0 0 1 2 2 1 2 1 1 0 1 0 (c) (c) 0 0 0 (c) (c) (c) (c) (0) (c) 0 (c) 0 (c) 0 (c) word (dir) ← (A) word (addr16) ← (A) word (SP) ← (A) word (RWi) ← (A) word (ear) ← (A) word (eam) ← (A) word (io) ← (A) 2 3 0 (c) XCHW XCHW XCHW XCHW 2 4 2+ 5+ (a) 2 7 2+ 9+ (a) MOVL A, ear MOVL A, eam MOVL A, #imm32 MOVL ear, A MOVL eam, A Mnemonic MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW A, dir A, addr16 A, SP A, RWi A, ear A, eam A, io A, @A A, #imm16 A, @RWi+disp8 A, @RLi+disp8 A, ear A, eam RWi, ear RWi, eam # ~ Operation LH AH I S T N Z V C RMW * * * * * * * – * * * – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – * * * * * * * * * * * * * * * * * * * * * * – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – word ((RWi) +disp8) ← (A) – word ((RLi) +disp8) ← (A) – word (RWi) ← (ear) – word (RWi) ← (eam) – word (ear) ← (RWi) – word (eam) ← (RWi) – word (RWi) ← imm16 – word (io) ← imm16 – word (ear) ← imm16 – word (eam) ← imm16 – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – * * * * * * * * * * * * * * – * – * * * * * * * * * * * * * * – * – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – word ((A)) ← (AH) – – – – – * * – – – 2 0 0 2× (c) 4 0 2 2× (c) word (A) ↔ (ear) word (A) ↔ (eam) word (RWi) ↔ (ear) word (RWi) ↔ (eam) – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – 2 4 2+ 5+ (a) 5 3 2 0 0 0 (d) 0 long (A) ← (ear) long (A) ← (eam) long (A) ← imm32 – – – – – – – – – – – – – – – * * * * * * – – – – – – – – – 2 4 2+ 5+ (a) 2 0 0 (d) long (ear) ← (A) long (eam) ← (A) – – – – – – – – – – * * * * – – – – – – Note : For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,” and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.” 108 MB90580C Series Table 9 Addition and Subtraction Instructions (Byte/Word/Long Word) [42 Instructions] # ~ RG B Operation 2 2 2 2+ 2 2+ 1 2 2+ 1 2 2 2 2+ 2 2+ 1 2 2+ 1 2 5 3 4+ (a) 3 5+ (a) 2 3 4+ (a) 3 2 5 3 4+ (a) 3 5+ (a) 2 3 4+ (a) 3 0 0 1 0 2 0 0 1 0 0 0 0 1 0 2 0 0 1 0 0 0 (b) 0 (b) 0 2× (b) 0 0 (b) 0 0 (b) 0 (b) 0 2× (b) 0 0 (b) 0 byte (A) ← (A) +imm8 byte (A) ← (A) +(dir) byte (A) ← (A) +(ear) byte (A) ← (A) +(eam) byte (ear) ← (ear) + (A) byte (eam) ← (eam) + (A) byte (A) ← (AH) + (AL) + (C) byte (A) ← (A) + (ear) + (C) byte (A) ← (A) + (eam) + (C) Z Z Z Z – Z Z Z Z byte (A) ← (AH) + (AL) + (C) (decimal) Z Z byte (A) ← (A) –imm8 Z byte (A) ← (A) – (dir) Z byte (A) ← (A) – (ear) Z byte (A) ← (A) – (eam) – byte (ear) ← (ear) – (A) – byte (eam) ← (eam) – (A) byte (A) ← (AH) – (AL) – (C) Z byte (A) ← (A) – (ear) – (C) Z byte (A) ← (A) – (eam) – (C) Z byte (A) ← (AH) – (AL) – (C) (decimal) Z 1 2 2+ 3 2 2+ 2 2+ 1 2 2+ 3 2 2+ 2 2+ 2 3 4+ (a) 2 3 5+ (a) 3 4+ (a) 2 3 4+ (a) 2 3 5+ (a) 3 4+ (a) 0 1 0 0 2 0 1 0 0 1 0 0 2 0 1 0 0 0 (c) 0 0 2× (c) 0 (c) 0 0 (c) 0 0 2× (c) 0 (c) word (A) ← (AH) + (AL) word (A) ← (A) +(ear) word (A) ← (A) +(eam) word (A) ← (A) +imm16 word (ear) ← (ear) + (A) word (eam) ← (eam) + (A) word (A) ← (A) + (ear) + (C) word (A) ← (A) + (eam) + (C) word (A) ← (AH) – (AL) word (A) ← (A) – (ear) word (A) ← (A) – (eam) word (A) ← (A) –imm16 word (ear) ← (ear) – (A) word (eam) ← (eam) – (A) word (A) ← (A) – (ear) – (C) word (A) ← (A) – (eam) – (C) A, ear 2 6 A, eam 2+ 7+ (a) A, #imm32 5 4 A, ear 2 6 A, eam 2+ 7+ (a) A, #imm32 5 4 2 0 0 2 0 0 0 (d) 0 0 (d) 0 long (A) ← (A) + (ear) long (A) ← (A) + (eam) long (A) ← (A) +imm32 long (A) ← (A) – (ear) long (A) ← (A) – (eam) long (A) ← (A) –imm32 Mnemonic ADD ADD ADD ADD ADD ADD ADDC ADDC ADDC ADDDC SUB SUB SUB SUB SUB SUB SUBC SUBC SUBC SUBDC A,#imm8 A, dir A, ear A, eam ear, A eam, A A A, ear A, eam A A, #imm8 A, dir A, ear A, eam ear, A eam, A A A, ear A, eam A ADDW A ADDW A, ear ADDW A, eam ADDW A, #imm16 ADDW ear, A ADDW eam, A ADDCW A, ear ADDCW A, eam SUBW A SUBW A, ear SUBW A, eam SUBW A, #imm16 SUBW ear, A SUBW eam, A SUBCW A, ear SUBCW A, eam ADDL ADDL ADDL SUBL SUBL SUBL LH AH I S T N Z V C RMW – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * – – – – – * – – – – – – – – – * – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * – – – – – * – – – – – – – * – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – * * * * * * * * * * * * * * * * * * * * * * * * – – – – – – Note : For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,” and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.” 109 MB90580C Series Table 10 Mnemonic Increment and Decrement Instructions (Byte/Word/Long Word) [12 Instructions] # ~ RG B Operation LH AH I S T N Z V C RMW INC INC ear eam 2 2 2+ 5+ (a) 2 0 0 byte (ear) ← (ear) +1 2× (b) byte (eam) ← (eam) +1 – – – – – – – – – – * * * * * * – – – * DEC DEC ear eam 2 3 2+ 5+ (a) 2 0 0 byte (ear) ← (ear) –1 2× (b) byte (eam) ← (eam) –1 – – – – – – – – – – * * * * * * – – – * INCW INCW ear eam 2 3 2+ 5+ (a) 2 0 0 word (ear) ← (ear) +1 2× (c) word (eam) ← (eam) +1 – – – – – – – – – – * * * * * * – – – * DECW ear DECW eam 2 3 2+ 5+ (a) 2 0 0 word (ear) ← (ear) –1 2× (c) word (eam) ← (eam) –1 – – – – – – – – – – * * * * * * – – – * INCL INCL ear eam 2 7 2+ 9+ (a) 4 0 0 long (ear) ← (ear) +1 2× (d) long (eam) ← (eam) +1 – – – – – – – – – – * * * * * * – – – * DECL DECL ear eam 2 7 2+ 9+ (a) 4 0 0 long (ear) ← (ear) –1 2× (d) long (eam) ← (eam) –1 – – – – – – – – – – * * * * * * – – – * Note : For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,” and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.” Table 11 Mnemonic Compare Instructions (Byte/Word/Long Word) [11 Instructions] # ~ RG B Operation LH AH I S T N Z V C RMW CMP CMP CMP CMP A A, ear A, eam A, #imm8 1 2 2+ 2 1 2 3+ (a) 2 0 1 0 0 0 0 (b) 0 byte (AH) – (AL) byte (A) ← (ear) byte (A) ← (eam) byte (A) ← imm8 – – – – – – – – – – – – – – – – – – – – * * * * * * * * * * * * * * * * – – – – CMPW CMPW CMPW CMPW A 1 A, ear 2 A, eam 2+ A, #imm16 3 1 2 3+ (a) 2 0 1 0 0 0 0 (c) 0 word (AH) – (AL) word (A) ← (ear) word (A) ← (eam) word (A) ← imm16 – – – – – – – – – – – – – – – – – – – – * * * * * * * * * * * * * * * * – – – – CMPL CMPL CMPL A, ear 2 A, eam 2+ A, #imm32 5 6 7+ (a) 3 2 0 0 0 (d) 0 word (A) ← (ear) word (A) ← (eam) word (A) ← imm32 – – – – – – – – – – – – – – – * * * * * * * * * * * * – – – Note : For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,” and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.” 110 MB90580C Series Table 12 Mnemonic Multiplication and Division Instructions (Byte/Word/Long Word) [11 Instructions] # ~ 1 RG B Operation LH AH I S T N Z V C RMW DIVU A 1 * 0 0 word (AH) /byte (AL) – – – – – – – * * – DIVU A, ear 2 *2 1 0 word (A)/byte (ear) – – – – – – – * * – DIVU A, eam 2+ *3 0 *6 word (A)/byte (eam) – – – – – – – * * – *4 1 0 long (A)/word (ear) – – – – – – – * * – DIVUW A, eam 2+ *5 0 *7 long (A)/word (eam) – – – – – – – * * – MULU MULU MULU 0 0 byte (AH) *byte (AL) → word (A) 1 0 byte (A) *byte (ear) → word (A) 0 (b) byte (A) *byte (eam) → word (A) – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – 0 0 word (AH) *word (AL) → long (A) 1 0 word (A) *word (ear) → long (A) 0 (c) word (A) *word (eam) → long (A) – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – DIVUW A, ear 2 A 1 *8 A, ear 2 *9 A, eam 2+ *10 MULUW A 1 *11 MULUW A, ear 2 *12 MULUW A, eam 2+ *13 *1: *2: *3: *4: *5: *6: *7: *8: *9: *10: *11: *12: *13: Quotient → byte (AL) Remainder → byte (AH) Quotient → byte (A) Remainder → byte (ear) Quotient → byte (A) Remainder → byte (eam) Quotient → word (A) Remainder → word (ear) Quotient → word (A) Remainder → word (eam) 3 when the result is zero, 7 when an overflow occurs, and 15 normally. 4 when the result is zero, 8 when an overflow occurs, and 16 normally. 6 + (a) when the result is zero, 9 + (a) when an overflow occurs, and 19 + (a) normally. 4 when the result is zero, 7 when an overflow occurs, and 22 normally. 6 + (a) when the result is zero, 8 + (a) when an overflow occurs, and 26 + (a) normally. (b) when the result is zero or when an overflow occurs, and 2 × (b) normally. (c) when the result is zero or when an overflow occurs, and 2 × (c) normally. 3 when byte (AH) is zero, and 7 when byte (AH) is not zero. 4 when byte (ear) is zero, and 8 when byte (ear) is not zero. 5 + (a) when byte (eam) is zero, and 9 + (a) when byte (eam) is not 0. 3 when word (AH) is zero, and 11 when word (AH) is not zero. 4 when word (ear) is zero, and 12 when word (ear) is not zero. 5 + (a) when word (eam) is zero, and 13 + (a) when word (eam) is not zero. Note : For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,” and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.” 111 MB90580C Series Table 13 Signed Multiplication and Division Instructions (Byte/Word/Long Word) [11 Instructions] Mnemonic # ~ RG B 0 DIV A 2 *1 0 DIV A, ear 2 *2 1 DIV A, eam 2 + *3 0 DIVW A, ear 2 *4 1 DIVW A, eam 2+ *5 0 MULU MULU MULU MULUW MULUW MULUW A 2 A, ear 2 A, eam 2 + A 2 A, ear 2 A, eam 2 + *8 *9 *10 *11 *12 *13 0 1 0 0 1 0 Operation word (AH) /byte (AL) Quotient → byte (AL) Remainder → byte (AH) 0 word (A)/byte (ear) Quotient → byte (A) Remainder → byte (ear) *6 word (A)/byte (eam) Quotient → byte (A) Remainder → byte (eam) 0 long (A)/word (ear) Quotient → word (A) Remainder → word (ear) *7 long (A)/word (eam) Quotient → word (A) Remainder → word (eam) 0 0 (b) 0 0 (c) byte (AH) *byte (AL) → word (A) byte (A) *byte (ear) → word (A) byte (A) *byte (eam) → word (A) word (AH) *word (AL) → long (A) word (A) *word (ear) → long (A) word (A) *word (eam) → long (A) LH AH I S T N Z V C RMW Z – – – – – – * * – Z – – – – – – * * – Z – – – – – – * * – – – – – – – – * * – – – – – – – – * * – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – *1: *2: *3: *4: Set to 3 when the division-by-0, 8 or 18 for an overflow, and 18 for normal operation. Set to 3 when the division-by-0, 10 or 21 for an overflow, and 22 for normal operation. Set to 4 + (a) when the division-by-0, 11 + (a) or 22 + (a) for an overflow, and 23 + (a) for normal operation. Positive dividend: Set to 4 when the division-by-0, 10 or 29 for an overflow, and 30 for normal operation. Negative dividend: Set to 4 when the division-by-0, 11 or 30 for an overflow and 31 for normal operation. *5: Positive dividend: Set to 4 + (a) when the division-by-0, 11 + (a) or 30 + (a) for an overflow, and 31 + (a) for normal operation. Negative dividend: Set to 4 + (a) when the division-by-0, 12 + (a) or 31 + (a) for an overflow, and 32 + (a) for normal operation. *6: When the division-by-0, (b) for an overflow, and 2 × (b) for normal operation. *7: When the division-by-0, (c) for an overflow, and 2 × (c) for normal operation. *8: Set to 3 when byte (AH) is zero, 12 when the result is positive, and 13 when the result is negative. *9: Set to 3 when byte (ear) is zero, 12 when the result is positive, and 13 when the result is negative. *10: Set to 4 + (a) when byte (eam) is zero, 13 + (a) when the result is positive, and 14 + (a) when the result is negative. *11: Set to 3 when word (AH) is zero, 12 when the result is positive, and 13 when the result is negative. *12: Set to 3 when word (ear) is zero, 16 when the result is positive, and 19 when the result is negative. *13: Set to 4 + (a) when word (eam) is zero, 17 + (a) when the result is positive, and 20 + (a) when the result is negative. Notes: • When overflow occurs during DIV or DIVW instruction execution, the number of execution cycles takes two values because of detection before and after an operation. • When overflow occurs during DIV or DIVW instruction execution, the contents of AL are destroyed. • For (a) to (d), refer to “Table 4 Number of Execution Cycles for Effective Address in Addressing Modes” and “Table 5 Correction Values for Number of Cycles for Calculating Actual Number of Cycles.” 112 MB90580C Series Table 14 Mnemonic # ~ Logical 1 Instructions (Byte/Word) [39 Instructions] RG B Operation LH AH I S T N Z V C RMW AND AND AND AND AND A, #imm8 A, ear A, eam ear, A eam, A 2 2 2 3 2+ 4+ (a) 2 3 2+ 5+ (a) 0 1 0 2 0 0 0 (b) 0 2× (b) byte (A) ← (A) and imm8 byte (A) ← (A) and (ear) byte (A) ← (A) and (eam) byte (ear) ← (ear) and (A) byte (eam) ← (eam) and (A) – – – – – – – – – – – – – – – – – – – – – – – – – * * * * * * * * * * R R R R R – – – – – – – – – * OR OR OR OR OR A, #imm8 A, ear A, eam ear, A eam, A 2 2 2 3 2+ 4+ (a) 2 3 2+ 5+ (a) 0 1 0 2 0 0 0 (b) 0 2× (b) byte (A) ← (A) or imm8 byte (A) ← (A) or (ear) byte (A) ← (A) or (eam) byte (ear) ← (ear) or (A) byte (eam) ← (eam) or (A) – – – – – – – – – – – – – – – – – – – – – – – – – * * * * * * * * * * R R R R R – – – – – – – – – * XOR XOR XOR XOR XOR A, #imm8 A, ear A, eam ear, A eam, A 2 2 2 3 2+ 4+ (a) 2 3 2+ 5+ (a) 0 1 0 2 0 0 0 (b) 0 2× (b) byte (A) ← (A) xor imm8 byte (A) ← (A) xor (ear) byte (A) ← (A) xor (eam) byte (ear) ← (ear) xor (A) byte (eam) ← (eam) xor (A) – – – – – – – – – – – – – – – – – – – – – – – – – * * * * * * * * * * R R R R R – – – – – – – – – * NOT NOT NOT A ear eam 1 2 2 3 2+ 5+ (a) 0 2 0 0 byte (A) ← not (A) 0 byte (ear) ← not (ear) 2× (b) byte (eam) ← not (eam) – – – – – – – – – – – – – – – * * * * * * R R R – – – – – * ANDW ANDW ANDW ANDW ANDW ANDW A 1 2 A, #imm16 3 2 A, ear 2 3 A, eam 2+ 4+ (a) ear, A 2 3 eam, A 2+ 5+ (a) 0 0 1 0 2 0 0 0 0 (c) 0 2× (c) word (A) ← (AH) and (A) word (A) ← (A) and imm16 word (A) ← (A) and (ear) word (A) ← (A) and (eam) word (ear) ← (ear) and (A) word (eam) ← (eam) and (A) – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – * * * * * * * * * * * * R R R R R R – – – – – – – – – – – * ORW ORW ORW ORW ORW ORW A 1 2 A, #imm16 3 2 A, ear 2 3 A, eam 2+ 4+ (a) ear, A 2 3 eam, A 2+ 5+ (a) 0 0 1 0 2 0 0 0 0 (c) 0 2× (c) word (A) ← (AH) or (A) word (A) ← (A) or imm16 word (A) ← (A) or (ear) word (A) ← (A) or (eam) word (ear) ← (ear) or (A) word (eam) ← (eam) or (A) – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – * * * * * * * * * * * * R R R R R R – – – – – – – – – – – * XORW XORW XORW XORW XORW XORW A 1 2 A, #imm16 3 2 A, ear 2 3 A, eam 2+ 4+ (a) ear, A 2 3 eam, A 2+ 5+ (a) 0 0 1 0 2 0 0 0 0 (c) 0 2× (c) word (A) ← (AH) xor (A) word (A) ← (A) xor imm16 word (A) ← (A) xor (ear) word (A) ← (A) xor (eam) word (ear) ← (ear) xor (A) word (eam) ← (eam) xor (A) – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – * * * * * * * * * * * * R R R R R R – – – – – – – – – – – * 0 2 0 0 word (A) ← not (A) 0 word (ear) ← not (ear) 2× (c) word (eam) ← not (eam) – – – – – – – – – – – – – – – * * * * * * R R R – – – – – * NOTW A NOTW ear NOTW eam 1 2 2 3 2+ 5+ (a) Note : For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,” and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.” 113 MB90580C Series Table 15 Logical 2 Instructions (Long Word) [6 Instructions] Mnemonic # ~ RG B Operation LH AH I S T N Z V C RMW ANDL A, ear ANDL A, eam 2 2+ 6 7+ (a) 2 0 0 (d) long (A) ← (A) and (ear) long (A) ← (A) and (eam) – – – – – – – – – – * * * * R R – – – – ORL ORL A, ear A, eam 2 2+ 6 7+ (a) 2 0 0 (d) long (A) ← (A) or (ear) long (A) ← (A) or (eam) – – – – – – – – – – * * * * R R – – – – XORL A, ea XORL A, eam 2 2+ 6 7+ (a) 2 0 0 (d) long (A) ← (A) xor (ear) long (A) ← (A) xor (eam) – – – – – – – – – – * * * * R R – – – – Note : For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,” and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.” Table 16 Mnemonic Sign Inversion Instructions (Byte/Word) [6 Instructions] # ~ RG B Operation LH AH I S T N Z V C RMW 2 0 0 byte (A) ← 0 – (A) X – – – – * * * * – – – – – – – – – – – * * * * * * * * – * – – – – – * * * * – – – – – – – – – – – * * * * * * * * – * NEG A 1 NEG NEG ear eam 2 3 2+ 5+ (a) 2 0 NEGW A 1 0 NEGW ear NEGW eam 2 3 2+ 5+ (a) 2 2 0 0 byte (ear) ← 0 – (ear) 2× (b) byte (eam) ← 0 – (eam) 0 word (A) ← 0 – (A) 0 word (ear) ← 0 – (ear) 2× (c) word (eam) ← 0 – (eam) Note : For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,” and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.” Table 17 Mnemonic # ~ RG B NRML A, R0 2 *1 1 0 Normalize Instruction (Long Word) [1 Instruction] Operation LH long (A) ← Shift until first digit is “1” – byte (R0) ← Current shift count AH I S T N Z V C RMW – – – – – * – – – *1: 4 when the contents of the accumulator are all zeroes, 6 + (R0) in all other cases (shift count). Note : For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,” and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.” 114 MB90580C Series Table 18 Mnemonic RORC A ROLC A Shift Instructions (Byte/Word/Long Word) [18 Instructions] # ~ RG B 2 2 2 2 0 0 0 0 Operation LH AH I S T N Z V C RMW byte (A) ← Right rotation with carry byte (A) ← Left rotation with carry – – – – – – – – – – * * * * – – * * – – 2 3 2+ 5+ (a) 2 3 2+ 5+ (a) 2 0 0 2× (b) 2 0 0 2× (b) byte (ear) ← Right rotation with carry byte (eam) ← Right rotation with carry byte (ear) ← Left rotation with carry byte (eam) ← Left rotation with carry – – – – – – – – – – – – – – – – * * * * * * * * – – – – * * * * – * – * 2 2 2 *1 *1 *1 1 1 1 0 0 0 byte (A) ← Arithmetic right barrel shift (A, R0) byte (A) ← Logical right barrel shift (A, R0) byte (A) ← Logical left barrel shift (A, R0) – – – – – – – – * – – * – – – * * * * * * – – – * * * – – – ASRW A LSRW A/SHRW A LSLW A/SHLW A 1 1 1 2 2 2 0 0 0 0 0 0 word (A) ← Arithmetic right shift (A, 1 bit) – – – – – – – – * * * – – * R * – – – * * – – – * * * – – – ASRW A, R0 LSRW A, R0 LSLW A, R0 2 2 2 *1 *1 *1 1 1 1 0 0 0 word (A) ← Arithmetic right barrel shift (A, R0) word (A) ← Logical right barrel shift (A, R0) word (A) ← Logical left barrel shift (A, R0) – – – – – – – – * – – * – – – * * * * * * – – – * * * – – – ASRL A, R0 LSRL A, R0 LSLL A, R0 2 2 2 *2 *2 *2 1 1 1 0 0 0 long (A) ← Arithmetic right shift (A, R0) – – – – – – * – – * – – – * * * * * * – – – * * * – – – RORC ear RORC eam ROLC ear ROLC eam ASR LSR LSL A, R0 A, R0 A, R0 word (A) ← Logical right shift (A, 1 bit) word (A) ← Logical left shift (A, 1 bit) long (A) ← Logical right barrel shift (A, R0) long (A) ← Logical left barrel shift (A, R0) – – – – – – *1: 6 when R0 is 0, 5 + (R0) in all other cases. *2: 6 when R0 is 0, 6 + (R0) in all other cases. Note : For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,” and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.” 115 MB90580C Series Table 19 Mnemonic BZ/BEQ BNZ/BNE BC/BLO BNC/BHS BN rel BP rel BV rel BNV rel BT rel BNT rel BLT rel BGE rel BLE rel BGT rel BLS rel BHI rel BRA rel rel rel rel rel Branch 1 Instructions [31 Instructions] RG B Operation * *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Branch when (Z) = 1 Branch when (Z) = 0 Branch when (C) = 1 Branch when (C) = 0 Branch when (N) = 1 Branch when (N) = 0 Branch when (V) = 1 Branch when (V) = 0 Branch when (T) = 1 Branch when (T) = 0 Branch when (V) xor (N) = 1 Branch when (V) xor (N) = 0 # ~ 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 JMP JMP JMP JMP JMPP JMPP JMPP @A addr16 @ear @eam @ear *3 @eam *3 addr24 1 3 2 2+ 2 2+ 4 2 3 3 4+ (a) 5 6+ (a) 4 0 0 1 0 2 0 0 0 0 0 (c) 0 (d) 0 CALL CALL CALL CALLV CALLP 2 @ear *4 @eam *4 2+ addr16 *5 3 1 #vct4 *5 2 @ear *6 6 7+ (a) 6 7 10 1 0 0 0 2 (c) 2× (c) (c) 2× (c) 2× (c) CALLP @eam *6 2+ 11+ (a) 0 *2 CALLP addr24 *7 4 0 2× (c) *1: *2: *3: *4: *5: *6: *7: 10 LH AH I S T N Z V C RMW – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – Branch when ((V) xor (N)) or (Z) = 1 Branch when ((V) xor (N)) or (Z) = 0 Branch when (C) or (Z) = 1 Branch when (C) or (Z) = 0 Branch unconditionally word (PC) ← (A) word (PC) ← addr16 word (PC) ← (ear) word (PC) ← (eam) word (PC) ← (ear), (PCB) ← (ear +2) word (PC) ← (eam), (PCB) ← (eam +2) word (PC) ← ad24 0 to 15, (PCB) ← ad24 16 to 23 word (PC) ← (ear) word (PC) ← (eam) word (PC) ← addr16 Vector call instruction word (PC) ← (ear) 0 to 15, (PCB) ← (ear) 16 to 23 word (PC) ← (eam) 0 to 15, (PCB) ← (eam) 16 to 23 word (PC) ← addr0 to 15, (PCB) ← addr16 to 23 4 when branching, 3 when not branching. (b) + 3 × (c) Read (word) branch address. W: Save (word) to stack; R: read (word) branch address. Save (word) to stack. W: Save (long word) to W stack; R: read (long word) R branch address. Save (long word) to stack. Note : For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,” and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.” 116 MB90580C Series Table 20 Mnemonic CBNE A, #imm8, rel CWBNE A, #imm16, rel CBNE CBNE ear, #imm8, rel eam, #imm8, rel* 10 CWBNE ear, #imm16, rel CWBNE eam, #imm16, rel*10 Branch 2 Instructions [19 Instructions] # ~ RG B Operation 3 4 1 * *1 0 0 0 0 Branch when byte (A) ≠ imm8 Branch when word (A) ≠ imm16 4 4+ 5 5+ *2 *3 *4 *3 1 0 1 0 0 (b) 0 (c) Branch when byte (ear) ≠ imm8 Branch when byte (eam) ≠ imm8 Branch when word (ear) ≠ imm16 Branch when word (eam) ≠ imm16 *5 2 0 DBNZ ear, rel 3 DBNZ eam, rel 3+ *6 N Z V C RMW – – – – – – * – – – – * * * * * * * – – – – – – – – – – * * * * * * * * * * * * * * * * – – – – Branch when byte (ear) = (ear) – 1, and (ear) ≠ 0 2 2× (b) Branch when byte (eam) = (eam) – 1, and (eam) ≠ 0 – – – – – * * * – – – – – – – * * * – * Branch when word (ear) = (ear) – 1, and (ear) ≠ 0 2× (c) Branch when word (eam) = (eam) – 1, and (eam) ≠ 0 – – – – – * * * – – – – – – – * * * – * Software interrupt Software interrupt Software interrupt Software interrupt Return from interrupt – – – – – – – – – – – – – – * – – – – * – – – – * – – – – – At constant entry, save old frame pointer to stack, set new frame pointer, and allocate local pointer area At constant entry, retrieve old frame pointer from stack. – – – – – – – – – – – – – – – – – – – – Return from subroutine Return from subroutine – – – – – – – – – – – – – – – – – – – – DWBNZ ear, rel 3 *5 2 DWBNZ eam, rel 3+ *6 2 INT INT INTP INT9 RETI #vct8 addr16 addr24 2 3 4 1 1 20 16 17 20 15 0 0 0 0 0 8× (c) 6× (c) 6× (c) 8× (c) *7 LINK #imm8 2 6 0 (c) UNLINK 1 5 0 (c) RET *8 RETP *9 1 1 4 6 0 0 (c) (d) 0 LH AH I – – – – R R R R * S – – – – S S S S * T – – – – – – – – * – – – – * *1: 5 when branching, 4 when not branching *2: 13 when branching, 12 when not branching *3: 7 + (a) when branching, 6 + (a) when not branching *4: 8 when branching, 7 when not branching *5: 7 when branching, 6 when not branching *6: 8 + (a) when branching, 7 + (a) when not branching *7: Set to 3 × (b) + 2 × (c) when an interrupt request occurs, and 6 × (c) for return. *8: Retrieve (word) from stack *9: Retrieve (long word) from stack *10: In the CBNE/CWBNE instruction, do not use the RWj+ addressing mode. Note : For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,” and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.” 117 MB90580C Series Table 21 Other Control Instructions (Byte/Word/Long Word) [28 Instructions] # ~ RG B Operation PUSHW A PUSHW AH PUSHW PS PUSHW rlst 1 1 1 2 4 4 4 *3 0 0 0 *5 (c) (c) (c) *4 POPW POPW POPW POPW A AH PS rlst 1 1 1 2 3 3 4 *2 0 0 0 *5 (c) (c) (c) *4 JCTX @A 1 14 0 AND CCR, #imm8 OR CCR, #imm8 2 2 3 3 0 0 MOV RP, #imm8 MOV ILM, #imm8 2 2 2 2 Mnemonic LH AH I S T N Z V C RMW word (SP) ← (SP) –2, ((SP)) ← (A) word (SP) ← (SP) –2, ((SP)) ← (AH) word (SP) ← (SP) –2, ((SP)) ← (PS) (SP) ← (SP) –2n, ((SP)) ← (rlst) – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – word (A) ← ((SP)), (SP) ← (SP) +2 word (AH) ← ((SP)), (SP) ← (SP) +2 word (PS) ← ((SP)), (SP) ← (SP) +2 (rlst) ← ((SP)), (SP) ← (SP) +2n – – – – * – – – – – – – – – – – – – – – – – * * * * * * * – – – – – – – – – – – – – * * * * * * * – 0 0 byte (CCR) ← (CCR) and imm8 – – byte (CCR) ← (CCR) or imm8 – – * * * * * * * * * * * * * * – – 0 0 0 0 byte (RP) ←imm8 byte (ILM) ←imm8 – – – – – – – – – – – – – – – – – – – – MOVEA RWi, ear 2 3 MOVEA RWi, eam 2+ 2+ (a) MOVEA A, ear 2 1 MOVEA A, eam 2+ 1+ (a) 1 1 0 0 0 0 0 0 word (RWi) ←ear word (RWi) ←eam word(A) ←ear word (A) ←eam – – – – – – * * – – – – – – – – – – – – ADDSP #imm8 ADDSP #imm16 2 3 3 3 0 0 0 0 word (SP) ← (SP) +ext (imm8) word (SP) ← (SP) +imm16 – – – – – – – – – – – – – – – – – – – – MOV MOV 2 2 *1 1 0 0 0 0 byte (A) ← (brgl) byte (brg2) ← (A) Z * – – – – – – – – * * * * – – – – – – 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 No operation – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – NOP ADB DTB PCB SPB NCC CMR A, brgl brg2, A 6× (c) Context switch instruction Prefix code for accessing AD space Prefix code for accessing DT space Prefix code for accessing PC space Prefix code for accessing SP space Prefix code for no flag change Prefix code for common register bank – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – *1: PCB, ADB, SSB, USB, and SPB : 1 state DTB, DPR : 2 states *2: 7 + 3 × (pop count) + 2 × (last register number to be popped), 7 when rlst = 0 (no transfer register) *3: 29 +3 × (push count) – 3 × (last register number to be pushed), 8 when rlst = 0 (no transfer register) *4: Pop count × (c), or push count × (c) *5: Pop count or push count. Note : For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,” and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.” 118 MB90580C Series Table 22 Bit Manipulation Instructions [21 Instructions] # ~ RG B MOVB A, dir:bp MOVB A, addr16:bp MOVB A, io:bp 3 4 3 5 5 4 0 0 0 (b) (b) (b) MOVB dir:bp, A MOVB addr16:bp, A MOVB io:bp, A 3 4 3 7 7 6 0 0 0 SETB dir:bp SETB addr16:bp SETB io:bp 3 4 3 7 7 7 CLRB dir:bp CLRB addr16:bp CLRB io:bp 3 4 3 BBC BBC BBC dir:bp, rel addr16:bp, rel io:bp, rel BBS BBS BBS Mnemonic Operation LH AH I S T N Z V C RMW Z Z Z * * * – – – – – – – – – * * * * * * – – – – – – – – – 2× (b) bit (dir:bp) b ← (A) 2× (b) bit (addr16:bp) b ← (A) 2× (b) bit (io:bp) b ← (A) – – – – – – – – – – – – – – – * * * * * * – – – – – – * * * 0 0 0 2× (b) bit (dir:bp) b ← 1 2× (b) bit (addr16:bp) b ← 1 2× (b) bit (io:bp) b ← 1 – – – – – – – – – – – – – – – – – – – – – – – – – – – * * * 7 7 7 0 0 0 2× (b) bit (dir:bp) b ← 0 2× (b) bit (addr16:bp) b ← 0 2× (b) bit (io:bp) b ← 0 – – – – – – – – – – – – – – – – – – – – – – – – – – – * * * 4 5 4 *1 *1 *2 0 0 0 (b) (b) (b) Branch when (dir:bp) b = 0 Branch when (addr16:bp) b = 0 Branch when (io:bp) b = 0 – – – – – – – – – – – – – – – – – – * * * – – – – – – – – – dir:bp, rel addr16:bp, rel io:bp, rel 4 5 4 *1 *1 *2 0 0 0 (b) (b) (b) Branch when (dir:bp) b = 1 Branch when (addr16:bp) b = 1 Branch when (io:bp) b = 1 – – – – – – – – – – – – – – – – – – * * * – – – – – – – – – SBBS addr16:bp, rel 5 *3 0 2× (b) Branch when (addr16:bp) b = 1, bit = 1 – – – – – – * – – * WBTS io:bp 3 *4 0 *5 Wait until (io:bp) b = 1 – – – – – – – – – – WBTC io:bp 3 *4 0 *5 Wait until (io:bp) b = 0 – – – – – – – – – – *1: *2: *3: *4: *5: byte (A) ← (dir:bp) b byte (A) ← (addr16:bp) b byte (A) ← (io:bp) b 8 when branching, 7 when not branching 7 when branching, 6 when not branching 10 when condition is satisfied, 9 when not satisfied Undefined count Until condition is satisfied Note : For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,” and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.” Table 23 Mnemonic SWAP SWAPW/XCHW A,T EXT EXTW ZEXT ZEXTW Accumulator Manipulation Instructions (Byte/Word) [6 Instructions] # ~ RG B Operation 1 1 1 1 1 1 3 2 1 2 1 1 0 0 0 0 0 0 0 0 0 0 0 0 byte (A) 0 to 7 ↔ (A) 8 to 15 word (AH) ↔ (AL) byte sign extension word sign extension byte zero extension word zero extension LH AH I S T N Z V C RMW – – X – Z – – * – X – Z – – – – – – – – – – – – – – – – – – – – * * R R – – * * * * – – – – – – – – – – – – – – – – – – Note: For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,” and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.” 119 MB90580C Series Table 24 Mnemonic # ~ RG B MOVS/MOVSI MOVSD 2 2 2 * *2 5 * *5 3 * *3 SCEQ/SCEQI SCEQD 2 2 *1 *1 *5 *5 FISL/FILSI 2 6m +6 *5 String Instructions [10 Instructions] Operation LH AH I S T N Z V C RMW Byte transfer @AH+ ← @AL+, counter = RW0 Byte transfer @AH– ← @AL–, counter = RW0 – – – – – – – – – – – – – – – – – – – – *4 *4 Byte retrieval (@AH+) – AL, counter = RW0 Byte retrieval (@AH–) – AL, counter = RW0 – – – – – – – – – – * * * * * * * * – – *3 Byte filling @AH+ ← AL, counter = RW0 – – – – – * * – – – MOVSW/MOVSWI 2 MOVSWD 2 *2 *2 *8 *8 *6 *6 Word transfer @AH+ ← @AL+, counter = RW0 Word transfer @AH– ← @AL–, counter = RW0 – – – – – – – – – – – – – – – – – – – – SCWEQ/SCWEQI SCWEQD 2 2 *1 *1 *8 *8 *7 *7 Word retrieval (@AH+) – AL, counter = RW0 Word retrieval (@AH–) – AL, counter = RW0 – – – – – – – – – – * * * * * * * * – – FILSW/FILSWI 2 6m +6 *8 *6 Word filling @AH+ ← AL, counter = RW0 – – – – – * * – – – m: RW0 value (counter value) n: Loop count *1: 5 when RW0 is 0, 4 + 7 × (RW0) for count out, and 7 × n + 5 when match occurs *2: 5 when RW0 is 0, 4 + 8 × (RW0) in any other case *3: (b) × (RW0) + (b) × (RW0) when accessing different areas for the source and destination, calculate (b) separately for each. *4: (b) × n *5: 2 × (RW0) *6: (c) × (RW0) + (c) × (RW0) when accessing different areas for the source and destination, calculate (c) separately for each. *7: (c) × n *8: 2 × (RW0) Note : For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,” and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.” 120 MB90580C Series ■ ORDERING INFORMATION Part number Package MB90F583CPFV MB90F583CAPFV MB90583CPFV MB90583CAPFV MB90587CPFV MB90587CAPFV 100-pin Plastic LQFP (FPT-100P-M05) MB90F583CPF MB90F583CAPF MB90583CPF MB90583CAPF MB90587CPF MB90587CAPF 100-pin Plastic QFP (FPT-100P-M06) Remarks 121 MB90580C Series ■ PACKAGE DIMENSIONS 100-pin plastic LQFP (FPT-100P-M05) +0.20 16.00±0.20(.630±.008)SQ 75 1.50 –0.10 +.008 14.00±0.10(.551±.004)SQ 76 (Mouting height) .059 –.004 51 50 12.00 (.472) REF 15.00 (.591) NOM Details of "A" part 0.15(.006) INDEX 100 0.15(.006) 26 0.15(.006)MAX LEAD No. 1 "B" 25 0.40(.016)MAX "A" 0.50(.0197)TYP +0.08 0.18 –0.03 +.003 .007 –.001 +0.05 0.08(.003) M 0.127 –0.02 +.002 Details of "B" part .005 –.001 0.10±0.10 (STAND OFF) (.004±.004) 0.10(.004) C 0.50±0.20(.020±.008) 0~10° 2000 FUJITSU LIMITED F100007S-2C-4 Dimensions in mm (inches) 122 MB90580C Series 100-pin plastic QFP (FPT-100P-M06) 23.90±0.40(.941±.016) 3.35(.132)MAX (Mounting height) 0.05(.002)MIN (STAND OFF) 20.00±0.20(.787±.008) 80 51 81 50 14.00±0.20 (.551±.008) 17.90±0.40 (.705±.016) 12.35(.486) REF 16.30±0.40 (.642±.016) INDEX 31 100 "A" LEAD No. 1 30 0.65(.0256)TYP 0.30±0.10 (.012±.004) 0.13(.005) 0.15±0.05(.006±.002) M Details of "A" part 0.25(.010) Details of "B" part "B" 0.10(.004) 18.85(.742)REF 22.30±0.40(.878±.016) C 0.30(.012) 0.18(.007)MAX 0.53(.021)MAX 0 10° 0.80±0.20 (.031±.008) 2000 FUJITSU LIMITED F100008-3C-3 Dimensions in mm (inches) 123 MB90580C Series FUJITSU LIMITED For further information please contact: Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices Shinjuku Dai-Ichi Seimei Bldg. 7-1, Nishishinjuku 2-chome, Shinjuku-ku, Tokyo 163-0721, Japan Tel: +81-3-5322-3347 Fax: +81-3-5322-3386 http://edevice.fujitsu.com/ North and South America FUJITSU MICROELECTRONICS, INC. 3545 North First Street, San Jose, CA 95134-1804, U.S.A. Tel: +1-408-922-9000 Fax: +1-408-922-9179 Customer Response Center Mon. - Fri.: 7 am - 5 pm (PST) Tel: +1-800-866-8608 Fax: +1-408-922-9179 http://www.fujitsumicro.com/ Europe FUJITSU MICROELECTRONICS EUROPE GmbH Am Siebenstein 6-10, D-63303 Dreieich-Buchschlag, Germany Tel: +49-6103-690-0 Fax: +49-6103-690-122 http://www.fujitsu-fme.com/ Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE. LTD. #05-08, 151 Lorong Chuan, New Tech Park, Singapore 556741 Tel: +65-281-0770 Fax: +65-281-0220 http://www.fmap.com.sg/ Korea FUJITSU MICROELECTRONICS KOREA LTD. 1702 KOSMO TOWER, 1002 Daechi-Dong, Kangnam-Gu,Seoul 135-280 Korea Tel: +82-2-3484-7100 Fax: +82-2-3484-7111 F0011 FUJITSU LIMITED Printed in Japan All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. 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