FUJITSU SEMICONDUCTOR DATA SHEET DS05-20905-1E FLASH MEMORY CMOS 64 M (8 M × 8/4 M × 16) BIT Dual Operation MBM29DL64DF-70 ■ DESCRIPTION MBM29DL64DF is a 64 M-bit, 3.0 V-only Flash memory organized as 8 Mbytes of 8 bits each or 4 M words of 16 bits each. The device comes in 48-pin TSOP (1) and 48-ball FBGA packages. This device is designed to be programmed in system with 3.0 V VCC supply. 12.0 V VPP and 5.0 V VCC are not required for write or erase operations. The device can also be reprogrammed in standard EPROM programmers. The device is organized into four physical banks : Bank A, Bank B, Bank C and Bank D, which are considered to be four separate memory arrays operations. This device is the almost identical to Fujitsu’s standard 3 V only Flash memories, with the additional capability of allowing a normal non-delayed read access from a non-busy bank of the array while an embedded write (either a program or an erase) operation is simultaneously taking place on the other bank. (Continued) ■ PRODUCT LINE UP Part No. MBM29DL64DF-70 +0.6 V 3.0 V −0.3 V Power Supply Voltage VCC (V) Max Address Access Time (ns) 70 Max CE Access Time (ns) 70 Max OE Access Time (ns) 30 ■ PACKAGES 48-pin plastic TSOP (1) 48-ball plastic FBGA Marking Side (FPT-48P-M19) (BGA-48P-M13) MBM29DL64DF-70 (Continued) The new design concept called FlexBankTM *1 Architecture is implemented. With this concept the device can execute simultaneous operation between Bank 1, a bank chosen from among the four banks, and Bank 2, a bank consisting of the three remaining banks. This means that any bank can be chosen as Bank 1. (Refer to ■FUNCTIONAL DESCRIPTION for Simultaneous Operation.) The standard device offers access times 70 ns, allowing operation of high-speed microprocessors without the wait. To eliminate bus contention the device has separate chip enable (CE) , write enable (WE) and output enable (OE) controls. This device supports pin and command set compatible with JEDEC standard E2PROMs. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state-machine which controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from 5.0 V and 12.0 V Flash or EPROM devices. The device is programmed by executing the program command sequence. This invokes the Embedded Program AlgorithmTM which is an internal algorithm that automatically times the program pulse widths and verifies proper cell margin. Typically each sector can be programmed and verified in about 0.5 seconds. Erase is accomplished by executing the erase command sequence. This invokes the Embedded Erase AlgorithmTM which is an internal algorithm that automatically preprograms the array if it is not already programmed before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies the proper cell margin. Each sector is typically erased and verified in 0.5 second (if already completely preprogrammed) . The device also features sector erase architecture. The sector mode allows each sector to be erased and reprogrammed without affecting other sectors. The device is erased when shipped from the factory. The device features single 3.0 V power supply operation for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. A low VCC detector automatically inhibits write operations on the loss of power. The end of program or erase is detected by Data Polling of DQ7, by the Toggle Bit feature on DQ6, or the RY/BY output pin. Once the end of a program or erase cycle is completed, the device internally returns to the read mode. The device also has a hardware RESET pin. When this pin is driven low, execution of any Embedded Program Algorithm or Embedded Erase Algorithm is terminated. The internal state machine is then reset to the read mode. The RESET pin may be tied to the system reset circuitry. Therefore if a system reset occurs during the Embedded ProgramTM *2 Algorithm or Embedded EraseTM *2 Algorithm, the device is automatically reset to the read mode and have erroneous data stored in the address locations being programmed or erased. These locations need rewriting after the reset. Resetting the device enables the system’s microprocessor to read the boot-up firmware from the Flash memory. Fujitsu Flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality, reliability, and cost effectiveness. The device memory electrically erases the entire chip or all bits within a sector simultaneously via Fowler-Nordhiem tunneling. The bytes/words are programmed one byte/ word at a time using the EPROM programming mechanism of hot electron injection. *1 : FlexBankTM is a trademark of Fujitsu Limited. *2 : Embedded EraseTM and Embedded ProgramTM are trademarks of Advanced Micro Devices, Inc. 2 MBM29DL64DF-70 ■ FEATURES • 0.17 µm Process Technology • Two-bank Architecture for Simultaneous Read/Program and Read/Erase • FlexBankTM *1 Bank A : 8 Mbit (8 KB × 8 and 64 KB × 15) Bank B : 24 Mbit (64 KB × 48) Bank C : 24 Mbit (64 KB × 48) Bank D : 8 Mbit (8 KB × 8 and 64 KB × 15) Two virtual Banks are chosen from the combination of four physical banks (Refer to “■FUNCTIONAL DESCRIPTION FlexBankTM Architecture”and “Example of Virtual Banks Combination”.) Host system can program or erase in one bank, and then read immediately and simultaneously from the other bank with zero latency between read and write operations. Read-while-erase Read-while-program • Single 3.0 V Read, Program, and Erase Minimized system level power requirements • Compatible with JEDEC-standard Commands Uses the same software commands as E2PROMs • Compatible with JEDEC-standard Worldwide Pinouts 48-pin TSOP (1) (Package suffix : TN − Normal Bend Type) 48-ball FBGA (Package suffix : PBT) • Minimum 100,000 Program/Erase Cycles • High Performance 70 ns maximum access time • Sector Erase Architecture Sixteen 4 Kword and one hundred twenty-six 32 Kword sectors in word mode Sixteen 8 Kbyte and one hundred twenty-six 64 Kbyte sectors in byte mode Any combination of sectors can be concurrently erased. Also supports full chip erase. • HiddenROM Region 256 byte of HiddenROM, accessible through a new “HiddenROM Enable” command sequence Factory serialized and protected to provide a secure electronic serial number (ESN) • WP/ACC Input Pin At VIL allows protection of “outermost” 2 × 8 Kbytes on both ends of boot sectors, regardless of sector group protection/unprotection status At VACC, increases program performance • Embedded EraseTM *2 Algorithms Automatically preprograms and erases the chip or any sector • Embedded ProgramTM *2 Algorithms Automatically programs and verifies data at specified address *1 : FlexBankTM is a trademark of Fujitsu Limited *2 : Embedded EraseTM and Embedded ProgramTM are trademarks of Advanced Micro Devices, Inc. (Continued) 3 MBM29DL64DF-70 (Continued) • Data Polling and Toggle Bit feature for program detection or erase cycle completion • Ready/Busy Output (RY/BY) Hardware method for detection of program or erase cycle completion • Automatic Sleep Mode When addresses remain stable, the device automatically switches itself to low power mode. • Low VCC Write Inhibit ≤ 2.5 V • Program Suspend/Resume Suspends the program operation to allow a read in another byte • Erase Suspend/Resume Suspends the erase operation to allow a read data and/or program in another sector within the same device • Sector Group Protection Hardware method disables any combination of sector groups from program or erase operations • Sector Group Protection Set function by Extended sector group protection command • Fast Programming Function by Extended Command • Temporary Sector Group Unprotection Temporary sector group unprotection via the RESET pin. • In accordance with CFI (Common Flash Memory Interface) 4 MBM29DL64DF-70 ■ PIN ASSIGNMENTS TSOP (1) A15 A14 A13 A12 A11 A10 A9 A8 A19 A20 WE RESET A21 WP/ACC RY/BY A18 A17 A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 (Marking Side) Normal Bend 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 A16 BYTE VSS DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE VSS CE A0 (FPT-48P-M19) (Continued) 5 MBM29DL64DF-70 (Continued) FBGA (TOP VIEW) (Marking side) A6 B6 C6 D6 E6 F6 G6 A13 A12 A14 A15 A16 A5 B5 C5 D5 E5 F5 G5 H5 A9 A8 A10 A11 DQ7 DQ14 DQ13 DQ6 A4 B4 C4 D4 E4 F4 G4 H4 WE RESET A21 A19 DQ5 DQ12 VCC DQ4 A3 B3 C3 D3 E3 F3 G3 H3 RY/BY WP/ ACC A18 A20 DQ2 DQ10 DQ11 DQ3 A2 B2 C2 D2 E2 F2 G2 H2 A7 A17 A6 A5 DQ0 DQ8 DQ9 DQ1 A1 B1 C1 D1 E1 F1 G1 H1 A3 A4 A2 A1 A0 CE OE VSS BYTE DQ15/ A-1 H6 VSS (BGA-48P-M13) ■ PIN DESCRIPTIONS Pin A21 to A0, A-1 Address Input DQ15 to DQ0 Data Input/Output CE Chip Enable OE Output Enable WE Write Enable RESET Hardware Reset Pin/Temporary Sector Group Unprotection RY/BY Ready/Busy Output BYTE Selects 8-bit or 16-bit mode WP/ACC 6 Function Hardware Write Protection/Program Acceleration VCC Device Power Supply VSS Device Ground N.C. No Internal Connection MBM29DL64DF-70 ■ BLOCK DIAGRAM VCC Cell Matrix 8 Mbit (Bank A) A21 to A0 (A-1) Cell Matrix 24 Mbit (Bank B) X-Decoder Y-Gating Bank A address Y-Gating VSS X-Decoder Bank B Address State Control & Command Register RY/BY DQ15 to DQ0 Status Control Bank C Address X-Decoder Cell Matrix 8 Mbit (Bank D) Bank D address Y-Gating X-Decoder Cell Matrix 24 Mbit (Bank C) Y-Gating RESET WE CE OE BYTE WP/ACC DQ15 to DQ0 ■ LOGIC SYMBOL A-1 22 A21 to A0 16 or 8 DQ15 to DQ0 CE OE WE RY/BY RESET BYTE 7 MBM29DL64DF-70 ■ DEVICE BUS OPERATION MBM29DL64DF User Bus Operations Table (BYTE = VIH) CE OE WE Operation Standby A0 A1 A2 A3 A6 A9 DQ15 to DQ0 RESET H X X X X X X X X High-Z H X L L H L L L L L VID Code H X Autoselect Device Code *1 L L H H L L L L VID Code H X Extended Autoselect Device Code *1 L L H L H H H L VID Code H X Autoselect Manufacturer Code * 1 L L H H H H H L VID Code H X 3 L L H A0 A1 A2 A3 A6 A9 DOUT H X Output Disable L H H X X X X X X High-Z H X Write (Program/Erase) L H L A0 A1 A2 A3 A6 A9 DIN H X Enable Sector Group Protection *2, *4 L VID L H L L L VID X H X Verify Sector Group Protection *2, *4 L L H L H L L L VID Code H X Temporary Sector Group Unprotection *5 X X X X X X X X X X VID X Reset (Hardware) /Standby X X X X X X X X X High-Z L X Boot Block Sector Write Protection *6 X X X X X X X X X X X L Read * Legend : L = VIL, H = VIH, X = VIL or VIH, = Pulse input. See “■DC CHARACTERISTICS” for voltage levels. *1 : Manufacturer and device codes are accessed via a command register write sequence. See “ Command Definitions Table”. *2 : Refer to “Sector Group Protection” in ■FUNCTIONAL DESCRIPTION. *3 : WE can be VIL if OE is VIL, OE at VIH initiates the write operations. *4 : VCC = 2.7 V to 3.6 V *5 : Also used for the extended sector group protection. *6 : Protects “outermost” 2 × 4 Kwords on both ends of the boot block sectors (SA0, SA1, SA140, SA141) . 8 WP/ ACC MBM29DL64DF-70 MBM29DL64DF User Bus Operations Table (BYTE = VIL) Operation CE OE WE DQ15/ A-1 A0 A1 A2 A3 A6 A9 DQ7 to DQ0 RESET WP/ ACC Standby H X X X X X X X X X High-Z H X Autoselect Manufacturer Code *1 L L H L L L L L L VID Code H X Autoselect Device Code *1 L L H L H L L L L VID Code H X Extended Autoselect Device Code *1 L L H L L H H H L VID Code H X L L H L H H H H L VID Code H X 3 L L H A-1 A0 A1 A2 A3 A6 A9 DOUT H X Output Disable L H H X X X X X X X High-Z H X Write (Program/Erase) L H L A-1 A0 A1 A2 A3 A6 A9 DIN H X Enable Sector Group Protection *2, *4 L VID L L H L L L VID X H X Verify Sector Group Protection *2, *4 L L H L L H L L L VID Code H X Temporary Sector Group Unprotection *5 X X X X X X X X X X X VID X Reset (Hardware) / Standby X X X X X X X X X X High-Z L X Boot Block Sector Write Protection *6 X X X X X X X X X X X X L Read * Legend : L = VIL, H = VIH, X = VIL or VIH, = Pulse input. See “■DC CHARACTERISTICS” for voltage levels. *1 : Manufacturer and device codes are accessed via command register write sequence. See “Command Definitions Table”. *2 : Refer to “Sector Group Protection” in ■FUNCTIONAL DESCRIPTION. *3 : WE can be VIL if OE is VIL, OE at VIH initiates the write operations. *4 : VCC = 2.7 V to 3.6 V *5 : Also used for extended sector group protection. *6 : Protect “outermost” 2 × 8K bytes on both ends of the boot block sectors (SA0, SA1, SA140, SA141) . 9 MBM29DL64DF-70 MBM29DL64DF Command Definitions Table *1 Bus Write Cycles Req’d Command Sequence Read/ Reset *2 Read/ Reset*2 Word Byte Word Byte 1 3 XXXh 555h AAAh 3 Byte Program Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Word Byte F0h AAh 555h Word Autoselect Fourth Bus First Bus Second Bus Third Bus Fifth Bus Sixth Bus Read/Write Write Cycle Write Cycle Write Cycle Write Cycle Write Cycle Cycle 2AAh 555h AAh 555h AAAh 55h 2AAh AAAh 4 55h 555h AAh 2AAh 555h 55h 555h AAAh (BA) 555h (BA) AAAh 555h AAAh F0h RA*12 *12 RD 90h IA*12 ID*12 A0h PA PD Program Suspend 1 BA B0h Program Resume 1 BA 30h Chip Erase Sector Erase Word Byte Word Byte 6 6 555h AAAh 555h AAAh AAh AAh 2AAh 555h 2AAh 555h 55h 55h 555h AAAh 555h AAAh 80h 80h 555h AAAh 555h AAAh AAh AAh 2AAh 555h 2AAh 555h 55h 555h AAAh 10h 55h SA 30h 1 BA B0h Erase Resume* 1 BA 30h Word Set to Fast Mode Byte 3 20h Word Fast Program *4 Byte 2 Reset from Word Fast Mode Byte *5 2 BA Extended Sector Group Protection *6, *7 3 XXXh Erase Suspend*3 3 AAh 2AAh 555h 55h 555h AAAh PA PD 90h XXXh *11 00h 60h SPA 60h SPA 40h *12 SPA *12 SD 98h 88h XXXh A0h Word Byte Word Query *8 1 Byte HiddenROM Entry*9 555h AAAh (BA) AAh 555h Word Byte (BA) 55h 3 AAAh 2AAh AAh 555h 555h 55h AAAh (Continued) 10 MBM29DL64DF-70 (Continued) Command Sequence Word HiddenROM Program *9, *10 Byte HiddenROM Exit *10 Bus Write Cycles Req’d 4 Fourth Bus First Bus Second Bus Third Bus Fifth Bus Sixth Bus Read/Write Write Cycle Write Cycle Write Cycle Write Cycle Write Cycle Cycle Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data 555h AAAh 555h Word 4 Byte AAh 2AAh 555h 55h 555h 555h AAAh A0h (HRA) PA PD 90h XXXh 00h (HRBA) 2AAh AAh AAAh 55h 555h (HRBA) AAAh *1 : Command combinations not described in “MBM29DL64DF Command Definitions” are illegal. *2 : Both of these reset commands are equivalent. *3 : Erase Suspend and Erase Resume command are valid only during a sector erase operations. *4 : This command is valid during Fast Mode. *5 : The Reset from Fast mode command is required to return to the Read mode when the device is in Fast mode. *6 : This command is valid while RESET = VID (except during HiddenROM mode) . *7 : Sector Group Address (SGA) with (A6, A3, A2, A1, A0) = (0, 0, 0, 1, 0) . *8 : The valid address are A6 to A0. *9 : The HiddenROM Entry command is required prior to the HiddenROM programming. *10 : This command is valid during HiddenROM mode. *11 : The data “F0h” is also acceptable. *12 : Fourth bus cycle becomes read cycle. Notes : • Address bits A21 to A11 = X = “H” or “L” for all address commands except or Program Address (PA) , Sector Address (SA) , Bank Address (BA) and Sector Group Address (SPA) . • Bus operations are defined in “MBM29DL64DF User Bus Operations (BYTE = VIH) ” and “MBM29DL64DF User Bus Operations (BYTE = VIL) ”. • RA = Address of the memory location to be read IA = Autoselect read address that sets both the bank address specified at (A21, A20, A19) and all the other A6, A3, A2, A1, A0 and (A-1) . PA = Address of the memory location to be programmed Addresses are latched on the falling edge of the write pulse. SA = Address of the sector to be erased. The combination of A21, A20, A19, A18, A17, A16, A15, A14, A13 and A12 will uniquely select any sector. BA = Bank Address. Address setted by A21, A20, A19 will select Bank A, Bank B, Bank C and Bank D. • RD = Data read from location RA during read operation. ID = Device code/manufacture code for the address located by IA. PD = Data to be programmed at location PA. Data is latched on the rising edge of write pulse. • SPA = Sector group address to be protected. Set sector group address and (A6, A3, A2, A1, A0) = (0, 0, 0, 1, 0) . • SGA = Sector Group Address. The combination of A21 to A12 will uniquely select any sector group. SD = Sector group protection verify data. Output 01h at protected sector group addresses and output 00h at unprotected sector group addresses. • HRA = Address of the HiddenROM area Word Mode : 000000h to 00007Fh Byte Mode : 000000h to 0000FFh • HRBA = Bank Address of the HiddenROM area (A21 = A20 = A19 = VIL) • The system should generate the following address patterns : Word Mode : 555h or 2AAh to addresses A10 to A0 Byte Mode : AAAh or 555h to addresses A10 to A0, and A-1 • Both Read/Reset commands are functionally equivalent, resetting the device to the read mode. 11 MBM29DL64DF-70 MBM29DL64DF Sector Group Protection Verify Autoselect Codes Table Type A21 to A12 A6 A3 A2 A1 A0 BA*3 VIL VIL VIL VIL VIL BA*3 VIL VIL VIL VIL VIH BA*3 VIL VIH VIH VIH VIL BA*3 VIL VIH VIH VIH VIH VIL VIL VIL VIH VIL Byte Manufacture’s Code Word Byte Device Code Word Byte Extended Device Code*4 Word Byte Word Byte Sector Group Word Addresses Sector Group Protection A-1*1 Code (HEX) VIL 04h X 0004h VIL 7Eh X 227Eh VIL 02h X 2202h VIL 01h X 2201h VIL 01h*2 X 0001h*2 *1 : A-1 is for Byte mode. At Byte mode, DQ14 to DQ8 are High-Z and DQ15 is A-1, the lowest address. *2 : Outputs 01h at protected sector group addresses and outputs 00h at unprotected sector group addresses. *3 : When VID is applied to A9, both Bank 1 and Bank 2 are put into Autoselect mode, which makes simultaneous operation unable to be executed. Consequently, specifying the bank address is not required. However, the bank address needs to be indicated when Autoselect mode is read out at command mode, because then it enables to activate simultaneous operation. *4 : At Word mode, a read cycle at address (BA) 01h (at Byte mode, (BA) 02h) outputs device code. When 227Eh (at Byte mode, 7Eh) is output, it indicates that two additional codes, called Extended Device Codes, will be required. Therefore the system may continue reading out these Extended Device Codes at the address of (BA) 0Eh (at Byte mode, (BA) 1Ch) , as well as at (BA) 0Fh (at Byte mode, (BA) 1Eh) . Extended Autoselect Code Table Type Code DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 04h A-1 HZ HZ HZ HZ HZ HZ HZ 0 0 0 0 0 1 0 0 Manufactur- (B)* er’s Code (W) 0004h 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 Device Code (B)* (W) 227Eh (B)* Extended Device Code 7Eh A-1 02h A-1 (W) 2202h (B)* 0 0 01h A-1 (W) 2201h Sector Group Protection (B)* 0 01h A-1 (W) 0001h 0 HZ HZ HZ HZ HZ 0 1 0 0 0 HZ HZ HZ HZ HZ 0 1 0 0 0 HZ HZ HZ HZ HZ 0 1 0 0 0 HZ HZ HZ HZ HZ 0 0 0 0 0 HZ HZ 1 0 HZ HZ 1 0 HZ HZ 1 0 HZ HZ 0 0 0 1 1 1 1 1 1 0 0 1 1 1 1 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 (B) : Byte mode (W) : Word mode HZ : High-Z * : At Byte mode, DQ14 to DQ8 are High-Z and DQ15 is A-1, the lowest address. 12 MBM29DL64DF-70 ■ FLEXIBLE SECTOR-ERASE ARCHITECTURE Sector Address Table (Bank A) Sector Address Bank Sector Size (Kbytes/ A A A A A A A A A A Kwords) Bank Sector Address ( × 8) Address Range ( × 16) Address Range 21 20 19 18 17 16 15 14 13 12 SA0 0 0 0 0 0 0 0 0 0 0 8/4 000000h to 001FFFh 000000h to 000FFFh SA1 0 0 0 0 0 0 0 0 0 1 8/4 002000h to 003FFFh 001000h to 001FFFh SA2 0 0 0 0 0 0 0 0 1 0 8/4 004000h to 005FFFh 002000h to 002FFFh SA3 0 0 0 0 0 0 0 0 1 1 8/4 006000h to 007FFFh 003000h to 003FFFh SA4 0 0 0 0 0 0 0 1 0 0 8/4 008000h to 009FFFh 004000h to 004FFFh SA5 0 0 0 0 0 0 0 1 0 1 8/4 00A000h to 00BFFFh 005000h to 005FFFh SA6 0 0 0 0 0 0 0 1 1 0 8/4 00C000h to 00DFFFh 006000h to 006FFFh SA7 0 0 0 0 0 0 0 1 1 1 8/4 00E000h to 00FFFFh 007000h to 007FFFh SA8 0 0 0 0 0 0 1 X X X 64/32 010000h to 01FFFFh 008000h to 00FFFFh SA9 0 0 0 0 0 1 0 X X X 64/32 020000h to 02FFFFh 010000h to 017FFFh SA10 Bank SA11 A SA12 0 0 0 0 0 1 1 X X X 64/32 030000h to 03FFFFh 018000h to 01FFFFh 0 0 0 0 1 0 0 X X X 64/32 040000h to 04FFFFh 020000h to 027FFFh 0 0 0 0 1 0 1 X X X 64/32 050000h to 05FFFFh 028000h to 02FFFFh SA13 0 0 0 0 1 1 0 X X X 64/32 060000h to 06FFFFh 030000h to 037FFFh SA14 0 0 0 0 1 1 1 X X X 64/32 070000h to 07FFFFh 038000h to 03FFFFh SA15 0 0 0 1 0 0 0 X X X 64/32 080000h to 08FFFFh 040000h to 047FFFh SA16 0 0 0 1 0 0 1 X X X 64/32 090000h to 09FFFFh 048000h to 04FFFFh SA17 0 0 0 1 0 1 0 X X X 64/32 0A0000h to 0AFFFFh 050000h to 057FFFh SA18 0 0 0 1 0 1 1 X X X 64/32 0B0000h to 0BFFFFh 058000h to 05FFFFh SA19 0 0 0 1 1 0 0 X X X 64/32 0C0000h to 0CFFFFh 060000h to 067FFFh SA20 0 0 0 1 1 0 1 X X X 64/32 0D0000h to 0DFFFFh 068000h to 06FFFFh SA21 0 0 0 1 1 1 0 X X X 64/32 0E0000h to 0EFFFFh 070000h to 077FFFh SA22 0 0 0 1 1 1 1 X X X 64/32 0F0000h to 0FFFFFh 078000h to 07FFFFh Note : The address range is A21 : A-1 if in byte mode (BYTE = VIL) . The address range is A21 : A0 if in word mode (BYTE = VIH) . 13 MBM29DL64DF-70 Sector Address Table (Bank B) Sector Address Bank Sector Size (Kbytes/ A A A A A A A A A A Kwords) Bank Sector Address 14 13 ( × 8) Address Range ( × 16) Address Range 21 20 19 18 17 16 15 12 SA23 0 0 1 0 0 0 0 X X X 64/32 100000h to 10FFFFh 080000h to 087FFFh SA24 0 0 1 0 0 0 1 X X X 64/32 110000h to 11FFFFh 088000h to 08FFFFh SA25 0 0 1 0 0 1 0 X X X 64/32 120000h to 12FFFFh 090000h to 097FFFh SA26 0 0 1 0 0 1 1 X X X 64/32 130000h to 13FFFFh 098000h to 09FFFFh SA27 0 0 1 0 1 0 0 X X X 64/32 140000h to 14FFFFh 0A0000h to 0A7FFFh SA28 0 0 1 0 1 0 1 X X X 64/32 150000h to 15FFFFh 0A8000h to 0AFFFFh SA29 0 0 1 0 1 1 0 X X X 64/32 160000h to 16FFFFh 0B0000h to 0B7FFFh SA30 0 0 1 0 1 1 1 X X X 64/32 170000h to 17FFFFh 0B8000h to 0BFFFFh SA31 0 0 1 1 0 0 0 X X X 64/32 180000h to 18FFFFh 0C0000h to 0C7FFFh SA32 0 0 1 1 0 0 1 X X X 64/32 190000h to 19FFFFh 0C8000h to 0CFFFFh SA33 0 0 1 1 0 1 0 X X X 64/32 1A0000h to 1AFFFFh 0D0000h to 0D7FFFh SA34 0 0 1 1 0 1 1 X X X 64/32 1B0000h to 1BFFFFh 0D8000h to 0DFFFFh SA35 0 0 1 1 1 0 0 X X X 64/32 1C0000h to 1CFFFFh 0E0000h to 0E7FFFh SA36 0 0 1 1 1 0 1 X X X 64/32 1D0000h to 1DFFFFh 0E8000h to 0EFFFFh SA37 Bank SA38 B SA39 0 0 1 1 1 1 0 X X X 64/32 1E0000h to 1EFFFFh 0F0000h to 0F7FFFh 0 0 1 1 1 1 1 X X X 64/32 1F0000h to 1FFFFFh 0F8000h to 0FFFFFh 0 1 0 0 0 0 0 X X X 64/32 200000h to 20FFFFh 100000h to 107FFFh SA40 0 1 0 0 0 0 1 X X X 64/32 210000h to 21FFFFh 108000h to 10FFFFh SA41 0 1 0 0 0 1 0 X X X 64/32 220000h to 22FFFFh 110000h to 117FFFh SA42 0 1 0 0 0 1 1 X X X 64/32 230000h to 23FFFFh 118000h to 11FFFFh SA43 0 1 0 0 1 0 0 X X X 64/32 240000h to 24FFFFh 120000h to 127FFFh SA44 0 1 0 0 1 0 1 X X X 64/32 250000h to 25FFFFh 128000h to 12FFFFh SA45 0 1 0 0 1 1 0 X X X 64/32 260000h to 26FFFFh 130000h to 137FFFh SA46 0 1 0 0 1 1 1 X X X 64/32 270000h to 27FFFFh 138000h to 13FFFFh SA47 0 1 0 1 0 0 0 X X X 64/32 280000h to 28FFFFh 140000h to 147FFFh SA48 0 1 0 1 0 0 1 X X X 64/32 290000h to 29FFFFh 148000h to 14FFFFh SA49 0 1 0 1 0 1 0 X X X 64/32 2A0000h to 2AFFFFh 150000h to 157FFFh SA50 0 1 0 1 0 1 1 X X X 64/32 2B0000h to 2BFFFFh 158000h to 15FFFFh SA51 0 1 0 1 1 0 0 X X X 64/32 2C0000h to 2CFFFFh 160000h to 167FFFh SA52 0 1 0 1 1 0 1 X X X 64/32 2D0000h to 2DFFFFh 168000h to 16FFFFh SA53 0 1 0 1 1 1 0 X X X 64/32 2E0000h to 2EFFFFh 170000h to 177FFFh (Continued) 14 MBM29DL64DF-70 (Continued) Sector Address Bank Sector Size (Kbytes/ A A A A A A A A A A Kwords) Bank Sector Address 14 13 ( × 8) Address Range ( × 16) Address Range 21 20 19 18 17 16 15 12 SA54 0 1 0 1 1 1 1 X X X 64/32 2F0000h to 2FFFFFh 178000h to 17FFFFh SA55 0 1 1 0 0 0 0 X X X 64/32 300000h to 30FFFFh 180000h to 187FFFh SA56 0 1 1 0 0 0 1 X X X 64/32 310000h to 31FFFFh 188000h to 18FFFFh SA57 0 1 1 0 0 1 0 X X X 64/32 320000h to 32FFFFh 190000h to 197FFFh SA58 0 1 1 0 0 1 1 X X X 64/32 330000h to 33FFFFh 198000h to 19FFFFh SA59 0 1 1 0 1 0 0 X X X 64/32 340000h to 34FFFFh 1A0000h to 1A7FFFh SA60 0 1 1 0 1 0 1 X X X 64/32 350000h to 35FFFFh 1A8000h to 1AFFFFh SA61 Bank SA62 B SA63 0 1 1 0 1 1 0 X X X 64/32 360000h to 36FFFFh 1B0000h to 1B7FFFh 0 1 1 0 1 1 1 X X X 64/32 370000h to 37FFFFh 1B8000h to 1BFFFFh 0 1 1 1 0 0 0 X X X 64/32 380000h to 38FFFFh 1C0000h to 1C7FFFh SA64 0 1 1 1 0 0 1 X X X 64/32 390000h to 39FFFFh 1C8000h to 1CFFFFh SA65 0 1 1 1 0 1 0 X X X 64/32 3A0000h to 3AFFFFh 1D0000h to 1D7FFFh SA66 0 1 1 1 0 1 1 X X X 64/32 3B0000h to 3BFFFFh 1D8000h to 1DFFFFh SA67 0 1 1 1 1 0 0 X X X 64/32 3C0000h to 3CFFFFh 1E0000h to 1E7FFFh SA68 0 1 1 1 1 0 1 X X X 64/32 3D0000h to 3DFFFFh 1E8000h to 1EFFFFh SA69 0 1 1 1 1 1 0 X X X 64/32 3E0000h to 3EFFFFh 1F0000h to 1F7FFFh SA70 0 1 1 1 1 1 1 X X X 64/32 3F0000h to 3FFFFFh 1F8000h to 1FFFFFh Note : The address range is A21 : A-1 if in byte mode (BYTE = VIL) . The address range is A21 : A0 if in word mode (BYTE = VIH) . 15 MBM29DL64DF-70 Sector Address Table (Bank C) Sector Address Bank Sector Size (Kbytes/ A A A A A A A A A A Kwords) Bank Sector Address 14 13 ( × 8) Address Range ( × 16) Address Range 21 20 19 18 17 16 15 12 SA71 1 0 0 0 0 0 0 X X X 64/32 400000h to 40FFFFh 200000h to 207FFFh SA72 1 0 0 0 0 0 1 X X X 64/32 410000h to 41FFFFh 208000h to 20FFFFh SA73 1 0 0 0 0 1 0 X X X 64/32 420000h to 42FFFFh 210000h to 217FFFh SA74 1 0 0 0 0 1 1 X X X 64/32 430000h to 43FFFFh 218000h to 21FFFFh SA75 1 0 0 0 1 0 0 X X X 64/32 440000h to 44FFFFh 220000h to 227FFFh SA76 1 0 0 0 1 0 1 X X X 64/32 450000h to 45FFFFh 228000h to 22FFFFh SA77 1 0 0 0 1 1 0 X X X 64/32 460000h to 46FFFFh 230000h to 237FFFh SA78 1 0 0 0 1 1 1 X X X 64/32 470000h to 47FFFFh 238000h to 23FFFFh SA79 1 0 0 1 0 0 0 X X X 64/32 480000h to 48FFFFh 240000h to 247FFFh SA80 1 0 0 1 0 0 1 X X X 64/32 490000h to 49FFFFh 248000h to 24FFFFh SA81 1 0 0 1 0 1 0 X X X 64/32 4A0000h to 4AFFFFh 250000h to 257FFFh SA82 1 0 0 1 0 1 1 X X X 64/32 4B0000h to 4BFFFFh 258000h to 25FFFFh SA83 1 0 0 1 1 0 0 X X X 64/32 4C0000h to 4CFFFFh 260000h to 267FFFh SA84 1 0 0 1 1 0 1 X X X 64/32 4D0000h to 4DFFFFh 268000h to 26FFFFh SA85 1 0 0 1 1 1 0 X X X 64/32 4E0000h to 4EFFFFh 270000h to 277FFFh Bank SA86 C SA87 1 0 0 1 1 1 1 X X X 64/32 4F0000h to 4FFFFFh 278000h to 27FFFFh 1 0 1 0 0 0 0 X X X 64/32 500000h to 50FFFFh 280000h to 287FFFh SA88 1 0 1 0 0 0 1 X X X 64/32 510000h to 51FFFFh 288000h to 28FFFFh SA89 1 0 1 0 0 1 0 X X X 64/32 520000h to 52FFFFh 290000h to 297FFFh SA90 1 0 1 0 0 1 1 X X X 64/32 530000h to 53FFFFh 298000h to 29FFFFh SA91 1 0 1 0 1 0 0 X X X 64/32 540000h to 54FFFFh 2A0000h to 2A7FFFh SA92 1 0 1 0 1 0 1 X X X 64/32 550000h to 55FFFFh 2A8000h to 2AFFFFh SA93 1 0 1 0 1 1 0 X X X 64/32 560000h to 56FFFFh 2B0000h to 2B7FFFh SA94 1 0 1 0 1 1 1 X X X 64/32 570000h to 57FFFFh 2B8000h to 2BFFFFh SA95 1 0 1 1 0 0 0 X X X 64/32 580000h to 58FFFFh 2C0000h to 2C7FFFh SA96 1 0 1 1 0 0 1 X X X 64/32 590000h to 59FFFFh 2C8000h to 2CFFFFh SA97 1 0 1 1 0 1 0 X X X 64/32 5A0000h to 5AFFFFh 2D0000h to 2D7FFFh SA98 1 0 1 1 0 1 1 X X X 64/32 5B0000h to 5BFFFFh 2D8000h to 2DFFFFh SA99 1 0 1 1 1 0 0 X X X 64/32 5C0000h to 5CFFFFh 2E0000h to 2E7FFFh SA100 1 0 1 1 1 0 1 X X X 64/32 5D0000h to 5DFFFFh 2E8000h to 2EFFFFh SA101 1 0 1 1 1 1 0 X X X 64/32 5E0000h to 5EFFFFh 2F0000h to 2F7FFFh SA102 1 0 1 1 1 1 1 X X X 64/32 5F0000h to 5FFFFFh 2F8000h to 2FFFFFh (Continued) 16 MBM29DL64DF-70 (Continued) Sector Address Bank Sector Size (Kbytes/ A A A A A A A A A A Kwords) Bank Sector Address 14 13 ( × 8) Address Range ( × 16) Address Range 21 20 19 18 17 16 15 12 SA103 1 1 0 0 0 0 0 X X X 64/32 600000h to 60FFFFh 300000h to 307FFFh SA104 1 1 0 0 0 0 1 X X X 64/32 610000h to 61FFFFh 308000h to 30FFFFh SA105 1 1 0 0 0 1 0 X X X 64/32 620000h to 62FFFFh 310000h to 317FFFh SA106 1 1 0 0 0 1 1 X X X 64/32 630000h to 63FFFFh 318000h to 31FFFFh SA107 1 1 0 0 1 0 0 X X X 64/32 640000h to 64FFFFh 320000h to 327FFFh SA108 1 1 0 0 1 0 1 X X X 64/32 650000h to 65FFFFh 328000h to 32FFFFh SA109 1 1 0 0 1 1 0 X X X 64/32 660000h to 66FFFFh 330000h to 337FFFh Bank SA110 C SA111 1 1 0 0 1 1 1 X X X 64/32 670000h to 67FFFFh 338000h to 33FFFFh 1 1 0 1 0 0 0 X X X 64/32 680000h to 68FFFFh 340000h to 347FFFh SA112 1 1 0 1 0 0 1 X X X 64/32 690000h to 69FFFFh 348000h to 34FFFFh SA113 1 1 0 1 0 1 0 X X X 64/32 6A0000h to 6AFFFFh 350000h to 357FFFh SA114 1 1 0 1 0 1 1 X X X 64/32 6B0000h to 6BFFFFh 358000h to 35FFFFh SA115 1 1 0 1 1 0 0 X X X 64/32 6C0000h to 6CFFFFh 360000h to 367FFFh SA116 1 1 0 1 1 0 1 X X X 64/32 6D0000h to 6DFFFFh 368000h to 36FFFFh SA117 1 1 0 1 1 1 0 X X X 64/32 6E0000h to 6EFFFFh 370000h to 377FFFh SA118 1 1 0 1 1 1 1 X X X 64/32 6F0000h to 6FFFFFh 378000h to 37FFFFh Note : The address range is A21 : A-1 if in byte mode (BYTE = VIL) . The address range is A21 : A0 if in word mode (BYTE = VIH) . 17 MBM29DL64DF-70 Sector Address Table (Bank D) Sector Address Bank Sector Size (Kbytes/ A A A A A A A A A A Kwords) Bank Sector Address 14 13 ( × 16) Address Range 21 20 19 18 17 16 15 12 SA119 1 1 1 0 0 0 0 X X X 64/32 700000h to 70FFFFh 380000h to 387FFFh SA120 1 1 1 0 0 0 1 X X X 64/32 710000h to 71FFFFh 388000h to 38FFFFh SA121 1 1 1 0 0 1 0 X X X 64/32 720000h to 72FFFFh 390000h to 397FFFh SA122 1 1 1 0 0 1 1 X X X 64/32 730000h to 73FFFFh 398000h to 39FFFFh SA123 1 1 1 0 1 0 0 X X X 64/32 740000h to 74FFFFh 3A0000h to 3A7FFFh SA124 1 1 1 0 1 0 1 X X X 64/32 750000h to 75FFFFh 3A8000h to 3AFFFFh SA125 1 1 1 0 1 1 0 X X X 64/32 760000h to 76FFFFh 3B0000h to 3B7FFFh SA126 1 1 1 0 1 1 1 X X X 64/32 770000h to 77FFFFh 3B8000h to 3BFFFFh SA127 1 1 1 1 0 0 0 X X X 64/32 780000h to 78FFFFh 3C0000h to 3C7FFFh SA128 1 1 1 1 0 0 1 X X X 64/32 790000h to 79FFFFh 3C8000h to 3CFFFFh SA129 Bank SA130 D SA131 1 1 1 1 0 1 0 X X X 64/32 7A0000h to 7AFFFFh 3D0000h to 3D7FFFh 1 1 1 1 0 1 1 X X X 64/32 7B0000h to 7BFFFFh 3D8000h to 3DFFFFh 1 1 1 1 1 0 0 X X X 64/32 7C0000h to 7CFFFFh 3E0000h to 3E7FFFh SA132 1 1 1 1 1 0 1 X X X 64/32 7D0000h to 7DFFFFh 3E8000h to 3EFFFFh SA133 1 1 1 1 1 1 0 X X X 64/32 7E0000h to 7EFFFFh 3F0000h to 3F7FFFh SA134 1 1 1 1 1 1 1 0 0 0 8/4 7F0000h to 7F1FFFh 3F8000h to 3F8FFFh SA135 1 1 1 1 1 1 1 0 0 1 8/4 7F2000h to 7F3FFFh 3F9000h to 3F9FFFh SA136 1 1 1 1 1 1 1 0 1 0 8/4 7F4000h to 7F5FFFh 3FA000h to 3FAFFFh SA137 1 1 1 1 1 1 1 0 1 1 8/4 7F6000h to 7F7FFFh 3FB000h to 3FBFFFh SA138 1 1 1 1 1 1 1 1 0 0 8/4 7F8000h to 7F9FFFh 3FC000h to 3FCFFFh SA139 1 1 1 1 1 1 1 1 0 1 8/4 7FA000h to 7FBFFFh 3FD000h to 3FDFFFh SA140 1 1 1 1 1 1 1 1 1 0 8/4 7FC000h to 7FDFFFh 3FE000h to 3FEFFFh SA141 1 1 1 1 1 1 1 1 1 1 8/4 7FE000h to 7FFFFFh Note : The address range is A21 : A-1 if in byte mode (BYTE = VIL) . The address range is A21 : A0 if in word mode (BYTE = VIH) . 18 ( × 8) Address Range 3FF000h to 3FFFFFh MBM29DL64DF-70 Sector Group Address Table Sector Group A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 Sectors SGA0 0 0 0 0 0 0 0 0 0 0 SA0 SGA1 0 0 0 0 0 0 0 0 0 1 SA1 SGA2 0 0 0 0 0 0 0 0 1 0 SA2 SGA3 0 0 0 0 0 0 0 0 1 1 SA3 SGA4 0 0 0 0 0 0 0 1 0 0 SA4 SGA5 0 0 0 0 0 0 0 1 0 1 SA5 SGA6 0 0 0 0 0 0 0 1 1 0 SA6 SGA7 0 0 0 0 0 0 0 1 1 1 SA7 0 1 1 0 X X X SA8 to SA10 1 1 SGA8 0 0 0 0 0 SGA9 0 0 0 0 1 X X X X X SA11 to SA14 SGA10 0 0 0 1 0 X X X X X SA15 to SA18 SGA11 0 0 0 1 1 X X X X X SA19 to SA22 SGA12 0 0 1 0 0 X X X X X SA23 to SA26 SGA13 0 0 1 0 1 X X X X X SA27 to SA30 SGA14 0 0 1 1 0 X X X X X SA31 to SA34 SGA15 0 0 1 1 1 X X X X X SA35 to SA38 SGA16 0 1 0 0 0 X X X X X SA39 to SA42 SGA17 0 1 0 0 1 X X X X X SA43 to SA46 SGA18 0 1 0 1 0 X X X X X SA47 to SA50 SGA19 0 1 0 1 1 X X X X X SA51 to SA54 SGA20 0 1 1 0 0 X X X X X SA55 to SA58 SGA21 0 1 1 0 1 X X X X X SA59 to SA62 SGA22 0 1 1 1 0 X X X X X SA63 to SA66 SGA23 0 1 1 1 1 X X X X X SA67 to SA70 (Continued) 19 MBM29DL64DF-70 (Continued) Sector Group A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 Sectors SGA24 1 0 0 0 0 X X X X X SA71 to SA74 SGA25 1 0 0 0 1 X X X X X SA75 to SA78 SGA26 1 0 0 1 0 X X X X X SA79 to SA82 SGA27 1 0 0 1 1 X X X X X SA83 to SA86 SGA28 1 0 1 0 0 X X X X X SA87 to SA90 SGA29 1 0 1 0 1 X X X X X SA91 to SA94 SGA30 1 0 1 1 0 X X X X X SA95 to SA98 SGA31 1 0 1 1 1 X X X X X SA99 to SA102 SGA32 1 1 0 0 0 X X X X X SA103 to SA106 SGA33 1 1 0 0 1 X X X X X SA107 to SA110 SGA34 1 1 0 1 0 X X X X X SA111 to SA114 SGA35 1 1 0 1 1 X X X X X SA115 to SA118 SGA36 1 1 1 0 0 X X X X X SA119 to SA122 SGA37 1 1 1 0 1 X X X X X SA123 to SA126 SGA38 1 1 1 1 0 X X X X X SA127 to SA130 0 0 0 1 X X X SA131 to SA133 1 0 SGA39 20 1 1 1 1 1 SGA40 1 1 1 1 1 1 1 0 0 0 SA134 SGA41 1 1 1 1 1 1 1 0 0 1 SA135 SGA42 1 1 1 1 1 1 1 0 1 0 SA136 SGA43 1 1 1 1 1 1 1 0 1 1 SA137 SGA44 1 1 1 1 1 1 1 1 0 0 SA138 SGA45 1 1 1 1 1 1 1 1 0 1 SA139 SGA46 1 1 1 1 1 1 1 1 1 0 SA140 SGA47 1 1 1 1 1 1 1 1 1 1 SA141 MBM29DL64DF-70 Common Flash Memory Interface Code Table Description A6 to A0 DQ15 to DQ0 Query-unique ASCII string “QRY” 10h 11h 12h 0051h 0052h 0059h Primary OEM Command Set 02h : AMD/FJ standard type 13h 14h 0002h 0000h Address for Primary Extended Table 15h 16h 0040h 0000h Alternate OEM Command Set (00h = not applicable) 17h 18h 0000h 0000h Address for Alternate OEM Extended Table 19h 1Ah 0000h 0000h VCC Min (write/erase) DQ7 to DQ4 : 1 V, DQ3 to DQ0 : 100 mV 1Bh 0027h VCC Max (write/erase) DQ7 to DQ4 : 1 V, DQ3 to DQ0 : 100 mV 1Ch 0036h VPP Min voltage 1Dh 0000h 1Eh 0000h Typical timeout per single byte/word write 2 µs 1Fh 0004h Typical timeout for Min size buffer write 2 µs 20h 0000h N 21h 000Ah 22h 0000h 23h 0005h 24h 0000h 25h 0004h Max timeout for full chip erase 2 times typical 26h 0000h Device Size = 2 byte 27h 0017h Flash Device Interface description 02h : ×8 / ×16 28h 29h 0002h 0000h Max number of bytes in multi-byte write = 2N 2Ah 2Bh 0000h 0000h Number of Erase Block Regions within device 2Ch 0003h Erase Block Region 1 Information bit 15 to bit 0 : y = number of sectors bit 31 to bit 16 : z = size (z × 256 bytes) 2Dh 2Eh 2Fh 30h 0007h 0000h 0020h 0000h Erase Block Region 2 Information bit 15 to bit 0 : y = number of sectors bit 31 to bit 16 : z = size (z × 256 bytes) 31h 32h 33h 34h 007Dh 0000h 0000h 0001h VPP Max voltage N N Typical timeout per individual sector erase 2 ms N Typical timeout for full chip erase 2 ms N Max timeout for byte/word write 2 times typical N Max timeout for buffer write 2 times typical N Max timeout per individual sector erase 2 times typical N N (Continued) 21 MBM29DL64DF-70 (Continued) Description A6 to A0 DQ15 to DQ0 Erase Block Region 3 Information bit 15 to bit 0 : y = number of sectors bit 31 to bit 16 : z = size (z × 256 bytes) 35h 36h 37h 38h 0007h 0000h 0020h 0000h Query-unique ASCII string “PRI” 40h 41h 42h 0050h 0052h 0049h Major version number, ASCII 43h 0031h Minor version number, ASCII 44h 0033h Address for command write and process technology DQ1, DQ0 : Address requied for command write (00h : requied) 04h : Required and 0.17 µm technology DQ7 to DQ2 : 0.17 µm process technology 45h 0004h Erase Suspend 02h = To Read & Write 46h 0002h Sector Protection 00h = Not Supported X = Number of sectors per group 47h 0001h Sector Temporary Unprotection 01h = Supported 48h 0001h Sector Protection Algorithm 49h 0004h Dual Operation 00h = Not Supported X = Total number of sectors in all banks except Bank 1 4Ah 0077h 4Bh 0000h 4Ch 0000h 4Dh 0085h 4Eh 0095h 4Fh 0001h Program Suspend 01h = Supported 50h 0001h Bank Organization X = Number of Banks 57h 0004h Bank A Region Information X = Number of sectors in Bank A 58h 0017h Bank B Region Information X = Number of sectors in Bank B 59h 0030h Bank C Region Information X = Number of sectors in Bank C 5Ah 0030h Bank D Region Information X = Number of sectors in Bank D 5Bh 0017h Burst Mode Type 00h = Not Supported Page Mode Type 00h = Not Supported VACC (Acceleration) Supply Minimum DQ7 to DQ4 : 1 V, DQ3 to DQ0 : 100 mV VACC (Acceleration) Supply Maximum DQ7 to DQ4 : 1 V, DQ3 to DQ0 : 100 mV Boot Type 22 MBM29DL64DF-70 ■ FUNCTIONAL DESCRIPTION Simultaneous Operation The device features functions that enable data reading of one memory bank while a program or erase operation is in progress in the other memory bank (simultaneous operation) , in addition to conventional features (read, program, erase, erase-suspend read, and erase-suspend program) . The bank is selected by bank address (A21, A20, A19) with zero latency. The device consists of the following four banks : Bank A : 8 × 8 KB and 15 × 64 KB; Bank B : 48 × 64 KB; Bank C : 48 × 64 KB; Bank D : 8 × 8 KB and 15 × 64 KB. The device can execute simultaneous operations between Bank 1, a bank chosen from among the four banks, and Bank 2, a bank consisting of the three remaining banks (see “FlexBankTM Architecture”.) This is what we call “FlexBank”, for example, the rest of banks B, C and D to let the system read while Bank A is in the process of program (or erase) operation. However the different types of operations for the three banks are not allowed, e.g., Bank A writing, Bank B erasing, and Bank C reading out. With this “FlexBank”, as described in “Example of Virtual Banks Combination”, the system gets to select from four combinations of data volume for Bank 1 and Bank 2, which works well to meet the system requirement. The simultaneous operation cannot execute multifunction mode in the same bank. “Simultaneous Operation” shows the possible combinations for simultaneous operation (refer to “(8) Bank-to-Bank Read/Write Timing Diagram” in ■TIMING DIAGRAM.) FlexBankTM Architecture Table Bank 1 Bank 2 Bank Splits Volume Combination Volume Combination 1 8 Mbit Bank A 56 Mbit Bank B, C, D 2 24 Mbit Bank B 40 Mbit Bank A, C, D 3 24 Mbit Bank C 40 Mbit Bank A, B, D 4 8 Mbit Bank D 56 Mbit Bank A, B, C Example of Virtual Banks Combination Table Bank 1 Bank Splits Volume Combination Bank 2 Sector Size Volume Combination Sector Size Bank B + Bank C + Bank D 8 × 8 Kbyte/4 Kword + 111 × 64 Kbyte/32 Kword 1 8 Mbit Bank A 8 × 8 Kbyte/4 Kword + 56 Mbit 15 × 64 Kbyte/32 Kword 2 16 Mbit Bank A + Bank D 16 × 8 Kbyte/4 Kword + 48 Mbit 30 × 64 Kbyte/32 Kword Bank B + Bank C 96 × 64 Kbyte/32 Kword 16 × 8 Kbyte/4 Kword + 78 × 64 Kbyte/32 Kword 8 × 8 Kbyte/4 Kword + 63 × 64 Kbyte/32 Kword 3 24 Mbit Bank B 48 × 64 Kbyte/32 Kword 40 Mbit Bank A + Bank C + Bank D 4 32 Mbit Bank A + Bank B 8 × 8 Kbyte/4 Kword + 32 Mbit 63 × 64 Kbyte/32 Kword Bank C + Bank D Note : When multiple sector erase over several banks is operated, the system cannot read out of the bank to which a sector being erased belongs. For example, suppose that erasing is taking place at both Bank A and Bank B, neither Bank A nor Bank B is read out They output the sequence flag once they are selected. Meanwhile the system would get to read from either Bank C or Bank D. 23 MBM29DL64DF-70 Simultaneous Operation Table Case Bank 1 Status Bank 2 Status 1 Read mode Read mode 2 Read mode Autoselect mode 3 Read mode Program mode 4 Read mode Erase mode * 5 Autoselect mode Read mode 6 Program mode Read mode 7 Erase mode * Read mode * : By writing erase suspend command on the bank address of sector being erased, the erase operation becomes suspended so that it enables reading from or programming the remaining sectors. Note : Bank 1 and Bank 2 are divided for the sake of convenience at Simultaneous Operation. The Bank consists of 4 banks, Bank A, Bank B, BankC and Bank D. Bank Address (BA) means to specify each of the Banks. Read Mode The device has two control functions required to obtain data at the outputs. CE is the power control and used for a device selection. OE is the output control and used to gate data to the output pins. Address access time (tACC) is equal to the delay from stable addresses to valid output data. The chip enable access time (tCE) is the delay from stable addresses and stable CE to valid data at the output pins. The output enable access time is the delay from the falling edge of OE to valid data at the output pins, assuming the addresses have been stable for at least tACC-tOE time. When reading out data without changing addresses after power-up, it is required to input hardware reset or to change CE pin from “H” to “L” Standby Mode There are two ways to implement the standby mode on the device, one using both the CE and RESET pins, and the other via the RESET pin only. When using both pins, CMOS standby mode is achieved with CE and RESET input held at VCC ± 0.3 V. Under this condition the current consumed is less than 5 µA Max. During Embedded Algorithm operation, VCC active current (ICC2) is required even when CE = “H”. The device can be read with standard access time (tCE) from either of these standby modes. When using the RESET pin only, CMOS standby mode is achieved with RESET input held at VSS ± 0.3 V (CE = “H” or “L”) . Under this condition the current consumed is less than 5 µA Max. Once the RESET pin is set high, the device requires tRH as a wake-up time for output to be valid for read access. During standby mode, the output is in the high impedance state regardless of OE input. Automatic Sleep Mode Automatic sleep mode works to restrain power consumption during read-out of device data. This is useful in applications such as handy terminal which requires low power consumption. To activate this mode, the device automatically switches itself to low power mode when the device addresses remain stable during after 150 ns from data valid. It is not necessary to control CE, WE and OE in this mode. In this mode the current consumed is typically 1 µA (CMOS Level) . During simultaneous operation, VCC active current (ICC2) is required. Since the data are latched during this mode, the data are continuously read out. When the addresses are changed, the mode is automatically canceled and the device reads the data for changed addresses. 24 MBM29DL64DF-70 Output Disable With the OE input at a logic high level (VIH) , output from the device is disabled. This causes the output pins to be in a high impedance state. Autoselect Autoselect mode allows reading out of binary code and identifies its manufacturer and type.It is intended for use by programming equipment for the purpose of automatically matching the device to be programmed with its corresponding programming algorithm. This mode is functional over the entire temperature range of the device. To activate this mode, the programming equipment must force VID on address pin A9. Three identifier bytes may then be sequenced from the device outputs by toggling addresses. All addresses can be either High or Low except A6, A3, A2, A1, A0 and (A-1) See User Bus Operations. The manufacturer and device codes may also be read via the command register, for instances when the device is erased or programmed in a system without access to high voltage on the A9 pin. The command sequence is illustrated in “Command Definitions”. In the command Autoselect mode, the bank addresses BA; (A21, A20, A19) must point to a specific bank during the third write bus cycle of the Autoselect command. Then the Autoselect data will be read from that bank while array data can be read from the other bank. In Word mode, a read cycle from address 00h returns the manufacturer’s code (Fujitsu = 04h) . A read cycle at address 01h outputs device code. When 227Eh is output, it indicates that two additional codes, called Extended Device Codes is required. Therefore the system may continue reading out these Extended Device Codes at addresses of 0Eh and 0Fh. Notice that the above applies to Word mode; the addresses and codes differ from those of Byte mode (refer to “Sector Group Protection Verify Autoselect Codes Table” and “Extended Autoselect Code Table” in ■DEVICE BUS OPERATION. In the case of applying VID on A9, as both Bank 1 and Bank 2 enter Autoselect mode, simultanous operation cannot be executed. Write Device erasure and programming are accomplished via the command register. The contents of the register serve as input to the internal state machine. The state machine output dictates the device function. The command register itself does not occupy any addressable memory location. The register is a latch used to store the commands, along with the address and data information needed to execute the command. The command register is written by bringing WE to VIL, while CE is at VIL and OE is at VIH. Addresses are latched on the falling edge of WE or CE, whichever starts later, while data is latched on the rising edge of WE or CE, whichever starts first. Standard microprocessor write timings are used. Refer to “■AC WRITE CHARACTERISTICS” and Erase/Programming Waveforms for specific timing parameters. Sector Group Protection The device features hardware sector group protection. This feature disables both program and erase operations in any combination of forty eight sector groups of memory. See “Sector Group Address Table”. The user‘s side can use sector group protection using programming equipment. The device is shipped with all sector groups unprotected. To activate it, the programming equipment must force VID on address pin A9 and control pin OE, CE = VIL and A6 = A3 = A2 = A0 = VIL, A1 = VIH. The sector group addresses (A21, A20, A19, A18, A17, A16, A15, A14, A13 and A12) should be set to the sector to be protected. Sector Address Tables (Bank A to Bank D) define the sector address for each of the one hundred forty-two (142) individual sectors, and Sector Group Address Table defines the sector group address for each of the forty eight (48) individual group sectors. Programming of the protection circuitry begins on the falling edge of the WE pulse and is terminated with the rising edge of the same. Sector group addresses must be held constant during the WE pulse. See Sector Group Protection waveforms and algorithms. To verify programming of the protection circuitry, the programming equipment must force VID on address pin A9 with CE and OE at VIL and WE at VIH. Scanning the sector group addresses (A21, A20, A19, A18, A17, A16, A15, A14, A13 and A12) while (A6, A3, A2, A1, A0) = (0, 0, 0, 1, 0) produces a logica “1” code at device output DQ0 for a protected sector. Otherwise the device produces “0” for unprotected sectors. In this mode, the lower order 25 MBM29DL64DF-70 addresses, except for A6, A3, A2, A1 and A0 are DON’T CARES. Address locations with A1 = VIL are reserved for Autoselect manufacturer and device codes. A-1 requires applying to VIL on byte mode. Whether the sector group is protected in the system can be determined by writing an Autoselect command. Performing a read operation at the address location (BA) XX02h, where the higher order addresses (A21, A20, A19, A18, A17, A16, A15, A14, A13, and A12) are the desired sector group address, will produce a logical “1” at DQ0 for a protected sector group. Note that the bank addresses (A21, A20, A19) must be pointing to a specific bank during the third write bus cycle of the Autoselect command. Then the Autoselect data can be read from that bank while array data can still be read from the other bank. To read Autoselect data from the other bank, it must be reset to read mode and then write the Autoselect command to the other bank. See Sector Group Protection Verify Autoselect Codes. Temporary Sector Group Unprotection This feature allows temporary unprotection of previously protected sector groups of the device in order to change data. The Sector Group Unprotection mode is activated by setting the RESET pin to high voltage (VID) . During this mode, formerly protected sector groups can be programmed or erased by selecting the sector group addresses. Once the VID is taken away from the RESET pin, all the previously protected sector groups will be protected again. Refer to “(6) Temporary Sector Group Unprotection Algorithm” in ■FLOW CHRAT. RESET Hardware Reset The device is reset by driving the RESET pin to VIL. The RESET pin works pulse requirement and has to be kept low (VIL) for at least “tRP” in order to properly reset the internal state machine. Any operation in the process of being executed is terminated and the internal state machine is reset to the read mode “tREADY” after the RESET pin is driven low. Furthermore once the RESET pin goes high the device requires an additional “tRH” before it allows read access. When the RESET pin is low, the device will be in the standby mode for the duration of the pulse and all the data output pins are tri-stated. If a hardware reset occurs during a program or erase operation, the data at that particular location is corrupted. Please note that the RY/BY output signal should be ignored during the RESET pulse. See “(11) RESET, RY/BY Timing Diagram” in ■TIMING DIAGRAM for the timing diagram. Refer to “Temporary Sector Group Unprotection” for additional functionality. Byte/Word Configuration BYTE pin selects Byte (8-bit) mode or Word (16-bit) mode for the device. When this pin is driven high, the device operates in Word (16-bit) mode. Data is read and programmed at DQ15 to DQ0. When this pin is driven low, the device operates in Byte (8-bit) mode. In this mode the DQ15/A-1 pin becomes the lowest address bit, and DQ14 to DQ8 bits are tri-stated. However the command bus cycle is always an 8-bit operation and hence commands are written at DQ7 to DQ0 and DQ15 to DQ8 bits are ignored. Refer to Timing Diagram for Word Mode/Byte Mode Configuration. Boot Block Sector Protection The Write Protection function provides a hardware method of protecting certain boot sectors without using VID. This function is one of two provided by the WP/ACC pin. If the system asserts VIL on the WP/ACC pin, the device disables program and erase functions in the two outermost 8 Kbytes on both ends of boot sectors (SA0, SA1, SA140, and SA141) independently of whether those sectors are protected or unprotected using the method described in “Sector Group Protection.” If the system asserts VIH on the WP/ACC pin, the device reverts to whether the two outermost 8 Kbyte on both ends of boot sectors were last set to be protected or unprotected. Sector group protection or unprotection for these four sectors depends on whether they ware last protected or unprotected using the method described in “Sector Group Protection.” 26 MBM29DL64DF-70 Accelerated Program Operation The device offers accelerated program operation which enables programming in high speed. If the system asserts VACC to the WP/ACC pin, the device automatically enters the acceleration mode and the time required for program operation reduces to about 60%. This function is primarily intended to allow high speed programming, so caution is needed as the sector group temporarily becomes unprotected. The system uses a fast program command sequence when programming during acceleration mode. Set command to fast mode and reset command from fast mode are not necessary. When the device enters the acceleration mode, the device is automatically set to fast mode. Therefore the present sequence could be used for programming and detection of completion during acceleration mode. Removing VACC from the WP/ACC pin returns the device to normal operation. Do not remove VACC from WP/ ACC pin while programming. See “(18) Accelerated Program Timing Diagram” in ■TIMING DIAGRAM. Erase operation at Acceleration mode is strictly prohibited. 27 MBM29DL64DF-70 ■ COMMAND DEFINITIONS Device operations are selected by writing specific address and data sequences into the command register. Some commands require Bank Address (BA) input. When command sequences are input into a bank reading, the commands have priority over the reading. ■DEVICE BUS OPERATION table shows the valid register command sequences. Note that the Erase Suspend (B0h) and Erase Resume (30h) commands are valid only while the Sector Erase operation is in progress. Also the Program Suspend (B0h) and Program Resume (30h) commands are valid only while the Program operation is in progress. Furthermore Read/Reset commands are functionally equivalent, resetting the device to the read mode. Note that commands are always written at DQ7 to DQ0 and DQ15 to DQ8 bits are ignored. Read/Reset Command In order to return from Autoselect mode or Exceeded Timing Limits (DQ5 = 1) to Read/Reset mode, the Read/ Reset operation is initiated by writing the Read/Reset command sequence into the command register. Microprocessor read cycles retrieve array data from the memory. The device remains enabled for reads until the command register contents are altered. The device automatically powers-up in the Read/Reset state. In this case a command sequence is not required in order to read data. Standard microprocessor read cycles will retrieve array data. This default value ensures that no spurious alteration of the memory content occurs during the power transition. Refer to “■AC CHARACTERISTICS” and “■TIMING DIAGRAM” for the specific timing parameters. Autoselect Command Flash memories are designed for use in applications where the local CPU alters memory contents. Therefore manufacture and device codes must be accessible while the device resides in the target system. PROM programmers typically access the signature codes by raising A9 to a higher voltage. However multiplexing high voltage onto the address lines is not generally desired system design practice. The device contains Autoselect command operation to supplement traditional PROM programming methodology. The operation is initiated by writing the Autoselect command sequence into the command register. The Autoselect command sequence is initiated first by writing two unlock cycles. This is followed by a third write cycle that contains the bank address (BA) and the Autoselect command. Then the manufacture and device codes can be read from the bank, and actual data from the memory cell can be read from another bank. The higher order address (A21, A20, A19) required for reading out the manufacture and device codes demands the bank address (BA) set at the third write cycle. Following the command write, in WORD mode, a read cycle from address (BA) 00h returns the manufacturer’s code (Fujitsu = 04h) . And a read cycle at address (BA) 01h outputs device code. When 227Eh was output, this indicates that two additional codes, called Extended Device Codes will be required. Therefore the system may continue reading out these Extended Device Codes at the address of (BA) 0Eh, as well as at (BA) 0Fh. Notice that the above applies to WORD mode. The addresses and codes differ from those of BYTE mode (refer to “MBM29DL64DF Sector Group Protection Verify Autoselect Codes” and “Extended Autoselect Code Table” in ■DEVICE BUS OPERATION. ) The sector state (protection or unprotection) will be informed by address (BA) 02h for × 16 ( (BA) 04h for × 8) . Scanning the sector group addresses (A21, A20, A19, A18, A17, A16, A15, A14, A13, and A12) while (A6, A3, A2, A1, A0) = (0, 0, 0, 1, 0) produces a logic “1” at device output DQ0 for a protected sector group. The programming verification should be performed by verifying sector group protection on the protected sector (see User Bus Operations Tables. The manufacture and device codes can be read from the selected bank. To read the manufacture and device codes and sector group protection status from a non-selected bank, it is necessary to write the Read/Reset command sequence into the register. Autoselect command should then be written into the bank to be read. If the software (program code) for Autoselect command is stored in the Flash memory, the device and manufacture codes should be read from the other bank, which does not contain the software. 28 MBM29DL64DF-70 To terminate the operation, write the Read/Reset command sequence into the register. To execute the Autoselect command during the operation, Read/Reset command sequence must be written before the Autoselect command. Byte/Word Programming The device is programmed on a byte-by-byte (or word-by-word) basis. Programming is a four bus cycle operation. There are two “unlock” write cycles. These are followed by the program set-up command and data write cycles. Addresses are latched on the falling edge of CE or WE, whichever happens later, and the data is latched on the rising edge of CE or WE, whichever happens first. The rising edge of CE or WE (whichever happens first) starts programming. Upon executing the Embedded Program Algorithm command sequence, the system is not required to provide further controls or timings. The device automatically provides adequate internally generated program pulses and verify programmed cell margin. The system can determine program operation status by using DQ7 (Data Polling) , DQ6 (Toggle Bit) or RY/BY. The Data Polling and Toggle Bit must be performed at the memory location being programmed. The automatic programming operation is completed when the data on DQ7 is equivalent to data written to this bit at which the device returns to the read mode and addresses are no longer latched (see “Hardware Sequence Flags”) . Therefore the device requires that a valid address to the device be supplied by the system in this particular instance. Hence Data Polling must be performed at the memory location being programmed. If hardware reset occurs during the programming operation, the data being written is not guaranteed. Programming is allowed in any sequence and across sector boundaries. Beware that a data “0” cannot be programmed back to a “1”. Attempting to do so may either hang up the device or result in an apparent success according to the data polling algorithm but a read from Read/Reset mode will show that the data is still “0”. Only erase operations can convert from “0”s to “1”s. “(1) Embedded ProgramTM Algorithm” in ■FLOW CHART illustrates the Embedded ProgramTM Algorithm using typical command strings and bus operations. Program Suspend/Resume The Program Suspend command allows the system to interrupt a program operation so that data can be read from any address. Writing the Program Suspend command (B0h) during the Embedded Program operation immediately suspends the programming. The Program Suspend command is issued during programming operation as well while an erase is suspended. The bank addresses of sector being programmed should be set when writing the Program Suspend command. When the Program Suspend command is written during programming process, the device halts the program operation within 1 µs and updates the status bits. After the program operation is suspended, the system can read data from any address. The data at programsuspended address is not valid. Normal read timing and command definitions apply. After the Program Resume command (30h) is written, the device reverts to programming. The bank addresses of sectors being suspended should be set when writing the Program Resume command. The system can determine the program operation status using the DQ7 or DQ6 status bits, just as in the standard program operation. See “Write Operation Status” for more information. The system may also write the Autoselect command sequence when the device in the Program Suspend mode. The device allows reading Autoselect codes at the addresses within programming sectors, since the codes are not stored in the memory. When the device exits from the Autoselect mode, the device reverts to the Program Suspend mode, and is ready for another valid operation. See “Autoselect Command” for more information. The system must write the Program Resume command (address bits are “Bank Address”) to exit from the Program Suspend mode and continue the programming operation. Further writes of the Resume command are ignored. Another Program Suspend command can be written after the device resumes programming. 29 MBM29DL64DF-70 Chip Erase Chip erase is a six bus cycle operation. There are two “unlock” write cycles. These are followed by writing the “set-up” command. Two more “unlock” write cycles are then followed by the chip erase command. Chip erase does not require the user to program prior to erase. Upon executing the Embedded Erase Algorithm command sequence, the device automatically programs and verifies the entire memory for an all-zero data pattern prior to electrical erase (Preprogram function) . The system is not required to provide any controls or timings during these operations. The system can determine the erase operation status by using DQ7 (Data Polling) , DQ6 (Toggle Bit) or RY/BY. The chip erase begins on the rising edge of the last CE or WE, whichever happens first in the command sequence, and terminates when the data on DQ7 is “1” (see “Write Operation Status” section) , at which the device returns to the read mode. Chip Erase Time : Sector Erase Time × All sectors + Chip Program Time (Preprogramming) “(2) Embedded EraseTM Algorithm” in ■FLOW CHART illustrates the Embedded EraseTM Algorithm using typical command strings and bus operations. Sector Erase Sector erase is a six bus cycle operation. There are two “unlock” write cycles. These are followed by writing the “set-up” command. Two more “unlock” write cycles are then followed by the Sector Erase command. The sector address (any address location within the desired sector) is latched on the falling edge of CE or WE, whichever starts later, while the command (Data = 30h) is latched on the rising edge of CE or WE, whichever starts first. After time-out of “tTOW” from the rising edge of the last sector erase command, the sector erase operation begins. Multiple sectors are erased concurrently by writing the six bus cycle operations on Command Definitions. This sequence is followed by writes of the Sector Erase command to addresses in other sectors desired to be concurrently erased. The time between writes must be less than “tTOW”. Otherwise that command is not accepted and erasure does not start. It is recommended that processor interrupts be disabled during this time to guarantee such condition. The interrupts can reoccur after the last Sector Erase command is written. A time-out of “tTOW” from the rising edge of last CE or WE, whichever starts first, initiates the execution of the Sector Erase command (s) . If another falling edge of CE or WE, whichever starts first occurs within the “tTOW” time-out window, the timer is reset (monitor DQ3 to determine if the sector erase timer window is still open, see section DQ3, Sector Erase Timer) . Resetting the device once execution begins may corrupt the data in the sector. In that case restart the erase on those sectors and allow them to complete. Refer to “Write Operation Status” section for Sector Erase Timer operation. Loading the sector erase buffer may be done in any sequence and with any number of sectors (0 to 141) . Sector erase does not require the user to program the device before erase. The device automatically programs all memory locations in the sector (s) to be erased prior to electrical erase (Preprogram function) . When erasing a sector, the rest remain unaffected. The system is not required to provide any controls or timings during these operations. The system can determine the status of the erase operation by using DQ7 (Data Polling) , DQ6 (Toggle Bit) or RY/BY. The sector erase begins after the “tTOW” time-out from the rising edge of CE or WE, whichever starts first, for the last sector erase command pulse and terminates when the data on DQ7 is “1” (see “Write Operation Status” section) at which the device returns to the read mode. Data polling and Toggle Bit must be performed at an address within any of the sectors being erased. Multiple Sector Erase Time = [Sector Erase Time + Sector Program Time (Preprogramming) ] × Number of Sector Erase In case of multiple sector erase across bank boundaries, a read from the bank (read-while-erase) to which sectors being erased belong cannot be performed. “(2) Embedded EraseTM Algorithm” in ■FLOW CHART illustrates the typical command strings and bus operations. 30 MBM29DL64DF-70 Erase Suspend/Resume The Erase Suspend command allows the user to interrupt Sector Erase operation and then reads data from or programs to a sector not being erased. This command is applicable ONLY during the Sector Erase operation which includes the time-out period for sector erase. Writing the Erase Suspend command (B0h) during the Sector Erase time-out results in immediate termination of the time-out period and suspension of the erase operation. Writing the Erase Resume command (30h) resumes the erase operation. The bank address of sector being erased or erase-suspended should be set when writing the Erase Suspend or Erase Resume command. When the Erase Suspend command is written during the Sector Erase operation, the device takes a maximum of “tSPD” to suspend the erase operation. When the device enters the erase-suspended mode, the RY/BY output pin is at High-Z and the DQ7 is at logic “1”, and DQ6 stops toggling. The user must use the address of the erasing sector for reading DQ6 and DQ7 to determine if the erase operation is suspended. Further writes of the Erase Suspend command are ignored. When the erase operation is suspended, the device defaults to the erase-suspend-read mode. Reading data in this mode is the same as reading from the standard read mode, except that the data must be read from sectors that have not been erase-suspended. Reading successively from the erase-suspended sector while the device is in the erase-suspend-read mode may cause DQ2 to toggle (see the section on “DQ2”) . After entering the erase-suspend-read mode, the user can program the device by writing the appropriate command sequence for Program. This program mode is known as the erase-suspend-program mode. Again it is the same with programming in the regular Program mode, except that the data must be programmed to sectors not being erase-suspended. Reading successively from the erase-suspended sector while the device is in the erasesuspend-program mode may cause DQ2 to toggle. The end of the erase-suspended Program operation is detected by the RY/BY output pin, Data polling of DQ7 or by the Toggle Bit I (DQ6) , which is the same with the regular Program operation. Note that DQ7 must be read from the Program address while DQ6 can be read from any address within bank being erase-suspended. To resume the operation of Sector Erase, the Resume command (30h) should be written to the bank being erase suspended. Any further writes of the Resume command at this point are ignored. Another Erase Suspend command can be written after the chip resumes erasing. Fast Mode Set/Reset Fast Mode function dispenses with the initial two unclock cycles required in the standard program command sequence by writing the Fast Mode command into the command register. In this mode the required bus cycle for programming consists of two bus cycles instead of four in standard program command. Do not write erase command in this mode. The read operation is also executed after exiting from the fast mode. To exit from this mode, write Fast Mode Reset command into the command register. The first cycle must contain the bank address. The VCC active current is required even if CE = VIH during Fast Mode. Fast Programming During Fast Mode, programming is executed with two bus cycle operation. The Embedded Program Algorithm is executed by writing program set-up command (A0h) and data write cycles (PA/PD) . See “(8) Embedded Programming Algorithm for Fast Mode” in ■FLOW CHART. The address of the program set-up command is don’t care. Fast Program command, with the exception of its process taken place at the two bus cycles, emulates the conventional programming so that the programming termination can be detected by Data polling of DQ7, Toggle Bit I (DQ6) and RY/BY output pins. Extended Sector Group Protection In addition to normal sector group protection, the device has Extended Sector Group Protection as extended function. This function enables protection of the sector group by forcing VID on RESET pin and writes a command sequence. Unlike conventional procedures, it is not necessary to force VID and control timing for control pins. The extended sector group protection requires VID on RESET pin only. With this condition the operation is initiated by writing the set-up command (60h) in the command register. Then the sector group addresses pins (A21, A20, A19, A18, A17, A16, A15, A14, A13 and A12) and (A6, A3, A2, A1, A0) = (0, 0, 0, 1, 0) should be set to the sector group to be protected (setting VIL for the other addresses pins is recommended) , and an extended sector group 31 MBM29DL64DF-70 protection command (60h) should be written. A sector group is typically protected in 250 µs. To verify programming of the protection circuitry, the sector group addresses pins (A21, A20, A19, A18, A17, A16, A15, A14, A13 and A12) and (A6, A3, A2, A1, A0) = (0, 0, 0, 1, 0) should be set a command (40h) should be written. Following the command write, a logic “1” at device output DQ0 will produce a protected sector in the read operation. If the output is logic “0”, write the extended sector group protection command (60h) again. To terminate the operation, it is necessary to set RESET pin to VIH. (refer to “(17) Extended Sector Group Protection Timing Diagram” in ■TIMING DIAGRAM and “(7) Extended Sector Group Protection Algorithm” in ■FLOW CHART.) Query (CFI : Common Flash Memory Interface) The CFI (Common Flash Memory Interface) specification outlines device and the host system software interrogation handshake, which allows specific vendor-specified software algorithms to be used for entire families of devices. This allows device-independent, JEDEC ID-independent and forward-and backward-compatible software support for the specified flash device families. Refer to Common Flash Memory Interface Code in detail. The operation is initiated by writing the query command (98h) into the command register. The bank address should be set when writing this command. Then the device information can be read from the bank, and data from the memory cell can be read from the another bank. The higher order address (A21, A20, A19) required for reading out the CFI Codes demands that the bank address (BA) be set at the write cycle. Following the command write, a read cycle from specific address retrieves device information. Note that output data of upper byte (DQ15 to DQ8) is “0” in word mode (16 bit) read. Refer to Common Flash Memory Interface Code. To terminate operation, write the read/reset command sequence into the register. HiddenROM Region The HiddenROM feature provides Flash memory region that the system may access through a new command sequence. This is primarily intended for customers who wish to use an Electronic Serial Number (ESN) in the device with the ESN protected against modification. Once the HiddenROM region is protected, any further modification of that region becomes impossible. This ensures the security of the ESN once the product is shipped to be sold. The HiddenROM region is 256 bytes in length and is stored at the same address of SA0 in Bank A. The device occupies the address of the byte mode 000000h to 0000FFh (word mode 000000h to 00007Fh) . After the system writes the Enter HiddenROM command sequence, the system reads the HiddenROM region by using the addresses normally occupied by the boot sector (particular area of SA0) . That is, the device sends all commands that would normally be sent to the boot sector (particular area of SA0) to the HiddenROM region. This mode of operation continues until the system issues the Exit HiddenROM command sequence, or until power is removed from the device. On power-up, or following a hardware reset, the device reverts to sending commands to the boot sector. When reading the HiddenROM region, either change addresses or change CE pin from “H” to “L”. The same procedure should be taken (changing addresses or CE pin from “H” to “L”) after the system issues the Exit HiddenROM command sequence to read actual memory cell data. HiddenROM Entry Command The device has a HiddenROM area with One Time Protect function. This area is to enter the security code and to remain once set. Programming is allowed in this area until it is protected. However once protection goes on, unprotecting it is not allowed. Therefore extreme caution is required. The HiddenROM area is 256 bytes. This area is normally the “outermost” 8 Kbyte boot block area in Bank A. Therefore write the HiddenROM entry command sequence to enter the HiddenROM area. It is called HiddenROM mode when the HiddenROM area appears. Sectors other than the boot block area SA0 can be read during HiddenROM mode. Read/Program of the HiddenROM area is possible during HiddenROM mode. Write the HiddenROM reset command sequence to exit the HiddenROM mode. The bank address of the HiddenROM should be set on the third cycle of this reset command sequence. In HiddenROM mode, the simultaneous operation cannot be executed multi-function mode between the HiddenROM area and the Bank A. 32 MBM29DL64DF-70 HiddenROM Program Command To program the data to the HiddenROM area, write the HiddenROM program command sequence during HiddenROM mode. This command is the same with the usual program command, except that it needs to write the command during HiddenROM mode. Therefore the detection of completion method is the same, using the DQ7 data polling, DQ6 toggle bit and RY/BY pin. You should pay attention to the address to be programmed. If an address not in the HiddenROM area is selected, the previous data is deleted. HiddenROM Protect Command There are two methods to protect the HiddenROM area. One of them is to write the sector group protect setup command (60h) , set the sector address in the HiddenROM area and (A6, A3, A2, A1, A0) = (0, 0, 0, 1, 0) , and write the sector group protect command (60h) during the HiddenROM mode. The same command sequence is used because it is the same with the extension sector group protect, except that it is in the HiddenROM mode and does not apply high voltage to the RESET pin. Refer to “Extended Sector Group Protection” for details of extension sector group protect setting. The other method is to apply high voltage (VID) to A9 and OE, set the sector address in the HiddenROM area and (A6, A3, A2, A1, A0) = (0, 0, 0, 1, 0) , and apply the write pulse during the HiddenROM mode. To verify the protect circuit, apply high voltage (VID) to A9, specify (A6, A3, A2, A1, A0) = (0, 0, 0, 1, 0) and the sector address in the HiddenROM area, and read. When “1” appears on DQ0, the protect setting is completed. “0” will appear on DQ0 if it is not protected. Apply write pulse again. The same command sequence is used for the above method because other than the HiddenROM mode, it is the same method with the sector group protect previously mentioned. Refer to Secor Group Protection for details of the sector group protect setting. Take note that other sector groups are affected if an address other than those for the HiddenROM area is selected for the sector group address. Pay close attention that once it is protected, protection CANNOT BE CANCELLED. Write Operation Status Details in “Hardware Sequence Flags” are all the status flags which determine the status of the bank for the current mode operation. The read operation from the bank which does not operate Embedded Algorithm returns data of memory cells. These bits offer a method for determining whether an Embedded Algorithm is properly completed. The information on DQ2 is address-sensitive. This means that if an address from an erasing sector is consecutively read, the DQ2 bit will toggle. However, DQ2 will not toggle if an address from a non-erasing sector is consecutively read. This allows users to determine which sectors are in erase. The status flag is not output from banks (non-busy banks) that do not execute Embedded Algorithms. For example a bank (busy bank) is executing an Embedded Algorithm. When the read sequence is [1] < busy bank > , [2] < non-busy bank > , [3] < busy bank > , the DQ6 toggles in the case of [1] and [3]. In case of [2], the data of memory cells are output. In the erase-suspend read mode with the same read sequence, DQ6 will not be toggled in [1] and [3]. In the erase suspend read mode, DQ2 is toggled in [1] and [3]. In case of [2], the data of memory cell is output. 33 MBM29DL64DF-70 Hardware Sequence Flags Table Status Embedded Program Algorithm Embedded Erase Algorithm Erase Suspend Read (Erase Suspended Sector) Erase Erase Suspend Read Suspended (Non-Erase Suspended Sector) In Progress Mode Erase Suspend Program (Non-Erase Suspended Sector) Program Suspend Read Program (Program Suspended Sector) Suspended Program Suspend Read Mode (Non-Program Suspended Sector) Embedded Program Algorithm Embedded Erase Algorithm Exceeded Time Limits Erase Erase Suspend Program Suspended (Non-Erase Suspended Sector) Mode DQ7 DQ6 DQ5 DQ3 DQ2 DQ7 Toggle 0 0 1 0 Toggle 0 1 Toggle *1 1 1 0 0 Toggle Data Data Data Data Data DQ7 Toggle 0 0 1 *2 Data Data Data Data Data Data Data Data Data Data DQ7 Toggle 1 0 1 0 Toggle 1 1 N/A DQ7 Toggle 1 0 N/A *1 : Successive reads from the erasing or erase-suspend sector causes DQ2 to toggle. *2 : Reading from non-erase suspend sector address indicates logic “1” at the DQ2 bit. DQ7 Data Polling The device features Data Polling as a method to indicate the host that the Embedded Algorithms are in progress or completed. During the Embedded Program Algorithm, an attempt to read the device produces reverse data last written to DQ7. Upon completion of the Embedded Program Algorithm, an attempt to read the device produces true data last written to DQ7. During the Embedded Erase Algorithm, an attempt to read the device produces a “0” at the DQ7 output. Upon completion of the Embedded Erase Algorithm, an attempt to read device produces a “1” on DQ7. The flowchart for Data Polling (DQ7) is shown in “(3) Data Polling Algorithm” in ■FLOW CHART. For programming, the Data Polling is valid after the rising edge of the fourth write pulse in the four write pulse sequences. For chip erase and sector erase, the Data Polling is valid after the rising edge of the sixth write pulse in the six write pulse sequences. Data polling also works as a flag to indicate whether the device is in erase-suspend mode. DQ7 goes from “0” to “1” during erase-suspend mode. Notice that to determine DQ7 entering erasesuspend mode, indicate the sector address of sector being erased. Data Polling must be performed at sector addresses of sectors being erased, not protected sectors. Otherwise the status may become invalid. If a program address falls within a protected sector, Data Polling on DQ7 is active for approximately 1 µs, then that bank returns to the read mode. After an erase command sequence is written, if all sectors selected for erasing are protected, Data Polling on DQ7 is active for approximately 400 µs, then the bank returns to read mode. Once the Embedded Algorithm operation is close to being completed, the device data pins (DQ7) may change asynchronously while the output enable (OE) is asserted low. This means that device is driving status information on DQ7 at one instant, and then that byte’s valid data the next. Depending on when the system samples the DQ7 output, it may read the status or valid data. Even if device completes the Embedded Algorithm operation and DQ7 has valid data, data outputs on DQ6 to DQ0 may still be invalid. The valid data on DQ7 to DQ0 is read on successive read attempts. 34 MBM29DL64DF-70 The Data Polling feature is only active during the Embedded Programming Algorithm, Embedded Erase Algorithm, Erase Suspend Mode or sector erase time-out. See Data Polling timing specifications and diagrams. DQ6 Toggle Bit I The device also features the “Toggle Bit I” as a method to indicate to the host system that the Embedded Algorithms are in progress or completed. During Embedded Program or Erase Algorithm cycle, successive attempts to read (CE or OE toggling) data from the busy bank results in DQ6 toggling between one and zero. Once the Embedded Program or Erase Algorithm cycle is completed, DQ6 stops toggling and valid data is read on the next successive attempts. During programming, the Toggle Bit I is valid after the rising edge of the fourth write pulse in the four write pulse sequences. For chip erase and sector erase, the Toggle Bit I is valid after the rising edge of the sixth write pulse in the six write pulse sequences. The Toggle Bit I is active during the sector time out. In Program Operation, if the sector being written to is protected, the toggle bit toggles for about 1 µs and then stops toggling with data unchanged. In erase operation, the device erases all selected sectors except for protected ones. If all selected sectors are protected, the chip toggles the toggle bit for about 400 µs and then drop back into read mode, having data kept remained. Either CE or OE toggling causes DQ6 to toggle. DQ6 determines whether a sector erase is active or is erase-suspended. When a bank is actively erased (that is, the Embedded Erase Algorithm is in progress) , DQ6 toggles. When a bank enters the Erase Suspend mode, DQ6 stops toggling. Successive read cycles during erase-suspend-program cause DQ6 to toggle. To operate toggle bit function properly, CE or OE must be high when bank address is changed. See “(7) AC Waveforms for Toggle Bit I during Embedded Algorithm Operations” (in ■TIMING DIAGRAM) in for the Toggle Bit I timing specifications and diagrams. DQ5 Exceeded Timing Limits DQ5 indicates if the program or erase time exceeds the specified limits (internal pulse count) . Under these conditions DQ5 produces “1”. This is a failure condition indicating that the program or erase cycle was not successfully completed. Data Polling is only operating function of the device under this condition. The CE circuit partially powers down device under these conditions (to approximately 2 mA) . The OE and WE pins control the output disable functions as described in User Bus Operations. The DQ5 failure condition may also appear if the user tries to program a non-blank location without pre-erase. In this case the device locks out and never completes the Embedded Algorithm operation. Hence the system never reads valid data on DQ7 bit and DQ6 never stop toggling. Once the device exceeds timing limits, the DQ5 bit indicates a “1.” Please note that this is not a device failure condition since the device was incorrectly used. If this occurs, reset device with the command sequence. DQ3 Sector Erase Timer After completion of the initial sector erase command sequence, sector erase time-out begins. DQ3 remains low until the time-out is completed. Data Polling and Toggle Bit are valid after the initial sector erase command sequence. If Data Polling or the Toggle Bit I indicates that a valid erase command is written, DQ3 determines whether the sector erase timer window is still open. If DQ3 is high (“1”) the internally controlled erase cycle begins. If DQ3 is low (“0”) , the device accepts additional sector erase commands. To insure the command is accepted, the system software checks the status of DQ3 prior to and following each subsequent Sector Erase command. If DQ3 is high on the second status check, the command may not be accepted. See Hardware Sequence Flags. 35 MBM29DL64DF-70 DQ2 Toggle Bit II This toggle bit II, along with DQ6, determines whether the device is in the Embedded Erase Algorithm or in Erase Suspend. Successive reads from the erasing sector causes DQ2 to toggle during the Embedded Erase Algorithm. If the device is in the erase-suspended-read mode, successive reads from the erase-suspended sector causes DQ2 to toggle. When the device is in the erase-suspended-program mode, successive reads from the non-erase suspended sector indicates a logic “1” at the DQ2 bit. DQ6 is different from DQ2 in that DQ6 toggles only when the standard program or Erase, or Erase Suspend Program operation is in progress. These two status bits, along with that of DQ7, operate as follows : For example DQ2 and DQ6 determine if the erase-suspend-read mode is in progress. (DQ2 toggles while DQ6 does not.) See also “Toggle Bit Status” table and “DQ2 vs.DQ6” waveform. Furthermore DQ2 determines which sector is being erased. At the erase mode, DQ2 toggles if this bit is read from an erasing sector. To operate toggle bit function properly, CE or OE must be high when bank address is changed. Reading Toggle Bits DQ6/DQ2 Whenever the system initially begins reading toggle bit status, it must read DQ7 to DQ0 at least twice in a row to determine whether a toggle bit is on. Typically the system would note and store the value of the toggle bit after the first read. After the second read, the system compares the new value of the toggle bit with the first. If the toggle bit is not toggling, this indicates that the device completes the program or erase operation. The system reads array data on DQ7 to DQ0 on the following read cycle. However if after the initial two read cycles, the system determines that the toggle bit is still on, the system also should note whether the value of DQ5 is high (see the section on “DQ5”) . If it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as DQ5 went high. If the toggle bit is no longer toggling, the device successfully completes the program or erase operation. If it is still toggling, the device does not complete the operation successfully, and the system must write the reset command to return to reading array data. The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 has not gone high. The system continues to monitor the toggle bit and DQ5 through successive read cycles, determining the status as described in the previous paragraph. Alternatively the system chooses to perform other system tasks. In this case the system must start at the beginning of the algorithm to determine the status of the operation. Toggle Bit Status Table DQ7 DQ6 DQ2 DQ7 Toggle 1 Erase 0 Toggle Toggle*1 Erase-Suspend Read (Erase-Suspended Sector) 1 1 Toggle DQ7 Toggle 1*2 Mode Program Erase-Suspend Program *1 : Successive reads from the erasing or erase-suspend sector cause DQ2 to toggle. *2 : Reading from the non-erase suspend sector address indicates logic “1” at the DQ2 bit. RY/BY Ready/Busy The device provides a RY/BY open-drain output pin as a way to indicate that Embedded Algorithms are either in progress or have been completed. When output is low the device is busy with either a program or erase 36 MBM29DL64DF-70 operation. If output is high, the device is ready to accept any read/write or erase operation. If the device is placed in an Erase Suspend mode, RY/BY output is high. During programming, the RY/BY pin is driven low after the rising edge of the fourth write pulse. During an erase operation, the RY/BY pin is driven low after the rising edge of the sixth write pulse. RY/BY pin indicates busy condition during RESET pulse. Refer to “(10) RY/BY Timing Diagram during Program/Erase Operation Timing Diagram” and “(11) RESET, RY/BY Timing Diagram” in ■TIMING DIAGRAM. RY/BY pin is pulled high in standby mode. Since this is an open-drain output, Pull-up resistor needs to be connected to VCC; multiples of devices may be connected to the host system via more than one RY/BY pin in parallel. Data Protection The device offers protection against accidental erasure or programming caused by spurious system level signals that may exist during power transitions. During power-up the device automatically resets the internal state machine in Read mode. With its control register architecture, alteration of memory contents only occurs after successful completion of specific multi-bus cycle command sequences. The device also incorporates several features to prevent inadvertent write cycles resulting from VCC power-up and power-down transitions or system noise. Low VCC Write Inhibit To avoid initiation of a write cycle during VCC power-up and power-down, the write cycle is locked out for VCC less than VLKO. If VCC < VLKO, the command register is disabled and all internal program/erase circuits are disabled. Under this condition the device resets to the read mode. Subsequent writes are ignored until the VCC level goes higher than VLKO. It is the user’s responsibility to ensure that the control pins are logically correct to prevent unintentional writes when VCC is above VLKO. If the Embedded Erase Algorithm is interrupted, the intervened erasing sector (s) is (are) not valid. Write Pulse “Glitch” Protection Noise pulses of less than 3 ns (typical) on OE, CE or WE does not initiate write cycle. Logical Inhibit Writing is prohibited by holding any one of OE = VIL, CE = VIH or WE = VIH. To initiate a write cycle CE and WE must be logical zero while OE is a logical one. Power-Up Write Inhibit Power-up of the device with WE = CE = VIL and OE = VIH does not accept commands on the rising edge of WE. Internal state machine is automatically reset to the read mode on power-up. Sector Group Protection Device user is able to protect each sector group individually to store and protect data. Protection circuit voids both program and erase command that are addressed to protect sectors. Any commands to program or erase addressed to protected sector are ignored (see ■FUNCTIONAL DESCRIPTION, Sector Group Protection) . 37 MBM29DL64DF-70 ■ ABSOLUTE MAXIMUM RATINGS Parameter Rating Symbol Unit Min Max Tstg −55 +125 °C TA −40 +85 °C VIN, VOUT −0.5 VCC + 0.5 V Power Supply Voltage *1 VCC −0.5 +4.0 V A9, OE, and RESET *1,*3 VIN −0.5 +13.0 V 1, 4 VACC −0.5 +10.5 V Storage Temperature Ambient Temperature with Power Applied Voltage with Respect to Ground All pins except A9, OE, and RESET *1,*2 WP/ACC * * *1: Voltage is defined on the basis of VSS = GND = 0 V. *2: Minimum DC voltage on input or I/O pins is −0.5 V. During voltage transitions, input or I/O pins may undershoot VSS to −2.0 V for periods of up to 20 ns. Maximum DC voltage on input or I/O pins is VCC + 0.5 V. During voltage transitions, input or I/O pins may overshoot to VCC + 2.0 V for periods of up to 20 ns. *3: Minimum DC input voltage on A9, OE and RESET pins is −0.5 V. During voltage transitions, A9, OE and RESET pins may undershoot VSS to −2.0 V for periods of up to 20 ns. Voltage difference between input and supply voltage (VIN - VCC) does not exceed +9.0 V. Maximum DC input voltage on A9, OE and RESET pins is +13.0 V which may overshoot to +14.0 V for periods of up to 20 ns. *4: Minimum DC input voltage on WP/ACC pin is −0.5 V. During voltage transitions, WP/ACC pin may undershoot VSS to −2.0 V for periods of up to 20 ns. Maximum DC input voltage on WP/ACC pin is +10.5 V which may overshoot to +12.0 V for periods of up to 20 ns when Vcc is applied. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. ■ RECOMMENDED OPERATING CONDITIONS Parameter Symbol Value Min Max Unit Ambient Temperature TA −40 +85 °C Power Supply Voltage* VCC +2.7 +3.6 V * : Voltage is defined on the basis of VSS = GND = 0 V. Note: Operating ranges define those limits between which the proper device function is guaranteed. WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. 38 MBM29DL64DF-70 ■ MAXIMUM OVERSHOOT/MAXIMUM UNDERSHOOT +0.6 V 20 ns 20 ns −0.5 V −2.0 V 20 ns Maximum Undershoot Waveform 20 ns VCC + 2.0 V VCC + 0.5 V +2.0 V 20 ns 20 ns Maximum Overshoot Waveform 1 20 ns +14.0 V +13.0 V VCC + 0.5 V 20 ns 20 ns Note : Applicable for A9, OE and RESET. Maximum Overshoot Waveform 2 39 MBM29DL64DF-70 ■ DC CHARACTERISTICS Parameter Symbol Value Conditions Min Typ Max Input Leakage Current ILI VIN = VSS to VCC, VCC = VCC Max −1.0 +1.0 µA Output Leakage Current ILO VOUT = VSS to VCC, VCC = VCC Max −1.0 +1.0 µA A9, OE, RESET Inputs Leakage Current ILIT VCC = VCC Max, A9, OE, RESET = 12.5 V +35 µA WP/ACC Accelerated Program Current ILIA VCC = VCC Max, WP/ACC = VACC Max 20 mA Byte 16 Word 18 Byte 4 Word 4 VCC Active Current * 1 ICC1 CE = VIL, OE = VIH, f = 5 MHz CE = VIL, OE = VIH, f = 1 MHz mA mA VCC Active Current *2 ICC2 CE = VIL, OE = VIH 30 mA VCC Current (Standby) ICC3 VCC = VCC Max, CE = VCC ± 0.3 V, RESET = VCC ± 0.3 V, WP/ACC = VCC ± 0.3 V 1 5 µA VCC Current (Standby, Reset) ICC4 VCC = VCC Max, RESET = VSS ± 0.3 V 1 5 µA VCC Current (Automatic Sleep Mode) *5 ICC5 VCC = VCC Max, CE = VSS ± 0.3 V, RESET = VCC ± 0.3 V VIN = VCC ± 0.3 V or VSS ± 0.3 V 1 5 µA VCC Active Current *6 (Read-While-Program) ICC6 CE = VIL, OE = VIH Byte 46 Word 48 VCC Active Current *6 (Read-While-Erase) ICC7 CE = VIL, OE = VIH Byte 46 Word 48 VCC Active Current (Erase-Suspend-Program) ICC8 CE = VIL, OE = VIH 40 mA Input Low Level VIL −0.5 0.6 V Input High Level VIH 2.0 VCC + 0.3 V Voltage for Autoselect and Sector Protection (A9, OE, RESET) *3,*4 VID 11.5 12 12.5 V Voltage for WP/ACC Sector Protection/Unprotection and Program Acceleration *4 VACC 8.5 9.0 9.5 V Output Low Voltage Level VOL IOL = 4 mA, VCC = VCC Min 0.45 V VOH1 IOH = −2.0 mA, VCC = VCC Min 2.4 V VOH2 IOH = −100 µA Output High Voltage Level Low VCC Lock-Out Voltage VLKO mA mA VCC − 0.4 V 2.3 2.4 2.5 V *1 : ICC current listed includes both the DC operating current and the frequency dependent component. *2 : ICC active while Embedded Algorithm (program or erase) is in progress. *3 : This timing is only for Sector Group Protection Operation and Autoselect mode. *4 : Applicable for only VCC. *5 : Automatic sleep mode enables the low power mode when addresses remain stable for 150 ns. *6 : Embedded Algorithm (program or erase) is in progress (@5 MHz.) 40 Unit MBM29DL64DF-70 ■ AC CHARACTERISTICS • Read Only Operations Characteristics Symbol Parameter JEDEC Standard Read Cycle Time tAVAV tRC Address to Output Delay tAVQV Chip Enable to Output Delay Condition Value (Note) Unit Min Max 70 ns tACC CE = VIL OE = VIL 70 ns tELQV tCE OE = VIL 70 ns Output Enable to Output Delay tGLQV tOE 30 ns Chip Enable to Output High-Z tEHQZ tDF 25 ns Output Enable to Output High-Z tGHQZ tDF 25 ns Output Hold Time From Addresses, CE or OE, Whichever Occurs First tAXQX tOH 0 ns RESET Pin Low to Read Mode tREADY 20 µs CE to BYTE Switching Low or High tELFL tELFH 5 ns Note : Test Conditions : Output Load : 30 pF (MBM29DL64DF-70) Input rise and fall times : 5 ns Input pulse levels : 0.0 V or VCC Timing measurement reference level Input : 0.5 × VCC Output : 0.5 × VCC 3.3 V 1N3064 or Equivalent 2.7 kΩ Device Under Test 6.2 kΩ CL Diodes = 1N3064 or Equivalent Notes: CL = 30 pF including jig capacitance (MBM29DL64DF-70) In case of CL = 100 pF, the device can be operated at an access time of 80 ns. Test Conditions 41 MBM29DL64DF-70 • Write/Erase/Program Operations Symbol Parameter Value Unit JEDEC Standard Min Typ Max Write Cycle Time tAVAV tWC 70 ns Address Setup Time tAVWL tAS 0 ns tASO 12 ns tWLAX tAH 30 ns tAHT 0 ns Data Setup Time tDVWH tDS 25 ns Data Hold Time tWHDX tDH 0 ns tOEH 0 ns 10 ns CE High During Toggle Bit Polling tCEPH 20 ns OE High During Toggle Bit Polling tOEPH 20 ns Read Recover Time Before Write tGHWL tGHWL 0 ns Read Recover Time Before Write tGHEL tGHEL 0 ns CE Setup Time tELWL tCS 0 ns WE Setup Time tWLEL tWS 0 ns CE Hold Time tWHEH tCH 0 ns WE Hold Time tEHWH tWH 0 ns Write Pulse Width tWLWH tWP 35 ns CE Pulse Width tELEH tCP 35 ns Write Pulse Width High tWHWL tWPH 20 ns CE Pulse Width High tEHEL tCPH 20 ns tWHWH1 tWHWH1 4 µs 6 µs tWHWH2 tWHWH2 0.5 s VCC Setup Time tVCS 50 µs Rise Time to VID *2 tVIDR 500 ns tVACCR 500 ns tVLHT 4 µs tWPP 100 µs Address Setup Time to OE Low During Toggle Bit Polling Address Hold Time Address Hold Time from CE or OE High During Toggle Bit Polling Output Enable Hold Time Read Toggle and Data Polling Byte Programming Operation Sector Erase Operation * Word 1 Rise Time to VACC *3 Voltage Transition Time * Write Pulse Width * 2 2 (Continued) 42 MBM29DL64DF-70 (Continued) Parameter Symbol Value Unit JEDEC Standard Min Typ Max OE Setup Time to WE Active *2 tOESP 4 µs CE Setup Time to WE Active *2 tCSP 4 µs Recover Time from RY/BY tRB 0 ns RESET Pulse Width tRP 500 ns RESET High Level Period Before Read tRH 200 ns BYTE Switching Low to Output High-Z tFLQZ 25 ns BYTE Switching High to Output Active tFHQV 70 ns Program/Erase Valid to RY/BY Delay tBUSY 90 ns Delay Time from Embedded Output Enable tEOE 70 ns Erase Time-out Time tTOW 50 µs Erase Suspend Transition Time tSPD 20 µs *1 : Does not include preprogramming time. *2 : For Sector Group Protection operation. *3 : For Accelerated Program operation only. 43 MBM29DL64DF-70 ■ ERASE AND PROGRAMMING PERFORMANCE Limits Parameter Unit Min Typ Max Sector Erase Time 0.5 2.0 s Word Programming Time 6.0 100 µs Byte Programming Time 4.0 80 µs Chip Programming Time 200 s 100,000 cycle Program/Erase Cycle Comments Excludes programming time prior to erasure Excludes system-level overhead Excludes system-level overhead Notes : Typical Erase conditions TA = + 25 °C, VCC = 2.9 V Typical Program conditions TA = + 25 °C, VCC = 2.9 V, Data = Checker ■ TSOP (1) PIN CAPACITANCE Parameter Input Capacitance Symbol CIN Condition Value Unit Typ Max VIN = 0 6.0 10.0 pF Output Capacitance COUT VOUT = 0 8.5 12.0 pF Control Pin Capacitance CIN2 VIN = 0 8.0 11.0 pF WP/ACC Pin Capacitance CIN3 VIN = 0 9.0 12.0 pF Notes : • Test conditions TA = + 25 °C, f = 1.0 MHz • DQ15/A-1 pin capacitance is stipulated by output capacitance. ■ FBGA PIN CAPACITANCE Parameter Input Capacitance Symbol CIN Condition Unit Typ Max VIN = 0 6.0 10.0 pF Output Capacitance COUT VOUT = 0 8.5 12.0 pF Control Pin Capacitance CIN2 VIN = 0 8.0 11.0 pF WP/ACC Pin Capacitance CIN3 VIN = 0 9.0 12.0 pF Notes : • Test conditions TA = + 25 °C, f = 1.0 MHz • DQ15/A-1 pin capacitance is stipulated by output capacitance. 44 Value MBM29DL64DF-70 ■ TIMING DIAGRAM • Key to Switching Waveforms WAVEFORM INPUTS OUTPUTS Must Be Steady Will Be Steady May Change from H to L Will Change from H to L May Change from L to H Will Change from L to H "H" or "L": Any Change Permitted Changing, State Unknown Does Not Apply Center Line is HighImpedance "Off" State (1) Read Operation Timing Diagram tRC Address Address Stable tACC CE tOE tDF OE tOEH WE tCE High-Z Outputs tOH Outputs Valid High-Z 45 MBM29DL64DF-70 (2) Hardware Reset/Read Operation Timing Diagram tRC Address Address Stable tACC CE tRH tRP tRH tCE RESET tOH High-Z Outputs Outputs Valid (3) Alternate WE Controlled Program Operation Timing Diagram 3rd Bus Cycle Data Polling 555h Address tWC PA tAS PA tRC tAH CE tCS tCH tCE OE tGHWL tWP tOE tWPH tWHWH1 WE tOH tDF tDS tDH Data A0h PD DQ7 DOUT Notes: • PA is address of the memory location to be programmed. • PD is data to be programmed at word address. • DQ7 is the output of the complement of the data written to the device. • DOUT is the output of the data written to the device. • Figure indicates the last two bus cycles out of four bus cycle sequence. • These waveforms are for the × 16 mode. 46 DOUT MBM29DL64DF-70 (4) Alternate CE Controlled Program Operation Timing Diagram 3rd Bus Cycle Data Polling 555h Address tWC PA tAS PA tAH WE tWS tWH OE tGHEL tCP tCPH tWHWH1 CE tDS tDH Data A0h PD DQ7 DOUT Notes: • PA is address of the memory location to be programmed. • PD is data to be programmed at word address. • DQ7 is the output of the complement of the data written to the device. • DOUT is the output of the data written to the device. • Figure indicates the last two bus cycles out of four bus cycle sequence. • These waveforms are for the × 16 mode. 47 MBM29DL64DF-70 (5) Chip/Sector Erase Operation Timing Diagram 555h Address 2AAh tWC tAS 555h 555h 2AAh SA* tAH CE tCS tCH OE tWP tGHWL tWPH WE tDS tDH AAh 10h for Chip Erase 55h 80h AAh 55h Data 10h/ 30h tVCS VCC * : SA is the sector address for Sector Erase. Addresses = 555h (Word) for Chip Erase. Note : These waveforms are for the × 16 mode. The addresses differ from the × 8 mode. (6) Data Polling during Embedded Algorithm Operation Timing Diagram CE tCH tDF tOE OE tOEH WE tCE * DQ7 Data DQ7 DQ7 = Valid Data High-Z tWHWH1 or 2 DQ6 to DQ0 DQ6 to DQ0 = Output Flag Data tBUSY DQ6 to DQ0 Valid Data tEOE RY/BY * : DQ7 = Valid Data (the device has completed the Embedded operation) . 48 High-Z MBM29DL64DF-70 (7) AC Waveforms for Toggle Bit I during Embedded Algorithm Operations Address tAHT tAHT tAS tASO CE tCEPH WE tOEPH tOEH tOEH OE tDH tOE tCE * DQ6/DQ2 Data Toggle Data Toggle Data Toggle Data Stop Toggling Output Valid tBUSY RY/BY * : DQ6 stops toggling (the device has completed the Embedded operation) . 49 MBM29DL64DF-70 (8) Bank-to-Bank Read/Write Timing Diagram Address Read Command Read Command Read Read tRC tWC tRC tWC tRC tRC BA1 BA2 (555h) BA1 BA2 (PA) BA1 BA2 (PA) tAS tACC tAH tAS tAHT tCE CE tOE tCEPH OE tGHWL tDF tOEH tWP WE tDS Valid Output DQ tDH Valid Intput (A0h) tDF Valid Output Valid Intput (PD) Valid Output Status Note : This is example of Read for Bank 1 and Embedded Algorithm (program) for Bank 2. BA1 : Address corresponding to Bank 1 BA2 : Address corresponding to Bank 2 (9) DQ2 vs. DQ6 Enter Embedded Erasing WE Erase Suspend Erase Enter Erase Suspend Program Erase Suspend Read DQ6 DQ2* Toggle DQ2 and DQ6 with OE or CE * : DQ2 is read from the erase-suspended sector. 50 Erase Suspend Program Erase Resume Erase Suspend Read Erase Erase Complete MBM29DL64DF-70 (10) RY/BY Timing Diagram during Program/Erase Operation Timing Diagram CE Rising edge of the last WE signal WE Entire programming or erase operations RY/BY tBUSY (11) RESET, RY/BY Timing Diagram WE RESET tRP tRB RY/BY tREADY (12) Timing Diagram for Word Mode Configuration CE tCE BYTE Data Output (DQ7 to DQ0) DQ14 to DQ0 tELFH DQ15/A-1 Data Output (DQ14 to DQ0) tFHQV A-1 DQ15 51 MBM29DL64DF-70 (13) Timing Diagram for Byte Mode Configuration CE BYTE DQ14 to DQ0 tELFL Data Output (DQ7 to DQ0) Data Output (DQ14 to DQ0) tACC DQ15/A-1 A-1 DQ15 tFLQZ (14) BYTE Timing Diagram for Write Operations Falling edge of the last write signal CE or WE Input Valid BYTE tAS 52 tAH MBM29DL64DF-70 (15) Sector Group Protection Timing Diagram A21, A20, A19 A18, A17, A16 A15, A14, A13 A12 SPAX SPAY A6, A3, A2, A0 A1 VID VIH A9 VID VIH OE tVLHT tVLHT tVLHT tVLHT tWPP WE tOESP tCSP CE 01h Data tVCS tOE VCC SPAX : Sector Group Address to be protected SPAY : Next Sector Group Address to be protected Note : A-1 is VIL on byte mode. 53 MBM29DL64DF-70 (16) Temporary Sector Group Unprotection Timing Diagram VCC tVIDR tVCS tVLHT VID VIH RESET CE WE tVLHT Program or Erase Command Sequence RY/BY Unprotection Period 54 tVLHT MBM29DL64DF-70 (17) Extended Sector Group Protection Timing Diagram VCC tVCS RESET tVLHT tVIDR tWC Address tWC SPAX SPAX SPAY A6, A3, A2, A0 A1 CE OE TIME-OUT tWP WE Data 60h 60h 40h 01h 60h tOE SPAX : Sector Group Address to be protected SPAY : Next Sector Group Address to be protected TIME-OUT : Time-Out window = 250 µs (Min) 55 MBM29DL64DF-70 (18) Accelerated Program Timing Diagram VCC tVACCR tVCS tVLHT VACC VIH WP/ACC CE WE tVLHT Program Command Sequence RY/BY Acceleration Period 56 tVLHT MBM29DL64DF-70 ■ FLOW CHART (1) Embedded ProgramTM Algorithm EMBEDDED ALGORITHM Start Write Program Command Sequence (See Below) Data Polling No Increment Address No Verify Data ? Yes Embedded Program Algorithm in program Last Address ? Yes Programming Completed Program Command Sequence (Address/Command): 555h/AAh 2AAh/55h 555h/A0h Program Address/Program Data Note : The sequence is applied for × 16 mode. 57 MBM29DL64DF-70 (2) Embedded EraseTM Algorithm EMBEDDED ALGORITHM Start Write Erase Command Sequence (See Below) Data Polling No Data = FFh ? Yes Embedded Erase Algorithm in progress Erasure Completed Chip Erase Command Sequence (Address/Command): Individual Sector/Multiple Sector Erase Command Sequence (Address/Command): 555h/AAh 555h/AAh 2AAh/55h 2AAh/55h 555h/80h 555h/80h 555h/AAh 555h/AAh 2AAh/55h 2AAh/55h 555h/10h Sector Address /30h Sector Address /30h Sector Address /30h Note : The sequence is applied for × 16 mode. 58 Additional sector erase commands are optional. MBM29DL64DF-70 (3) Data Polling Algorithm VA = Address for programming = Any of the sector addresses within the sector being erased during sector erase or multiple sector erases operation. = Any of the sector addresses within the sector not being protected during chip erase operation. Start Read Byte (DQ7 to DQ0) Addr. = VA DQ7 = Data? Yes No No DQ5 = 1? Yes Read Byte (DQ7 to DQ0) Addr. = VA DQ7 = Data? * No Fail Yes Pass * : DQ7 is rechecked even if DQ5 = “1” because DQ7 may change simultaneously with DQ5. 59 MBM29DL64DF-70 (4) Toggle Bit Algorithm Start Read DQ7 to DQ0 Addr. = VA VA = Bank address being executed Embedded Algorithm. *1 Read DQ7 to DQ0 Addr. = VA DQ6 = Toggle? No Yes No DQ5 = 1? Yes *1, *2 Read DQ7 to DQ0 Addr. = VA *1, *2 Read DQ7 to DQ0 Addr. = VA DQ6 = Toggle? No Yes Program/Erase Operation Not Complete.Write Reset Command Program/Erase Operation Complete *1 : Read toggle bit twice to determine whether it is toggling. *2 : Recheck toggle bit because it may stop toggling as DQ5 changes to “1”. 60 MBM29DL64DF-70 (5) Sector Group Protection Algorithm Start Setup Sector Group Addr. A21, A20, A19, A18, A17, A16, A15, A14, A13, A12 ( ) PLSCNT = 1 OE = VID, A9 = VID CE = VIL, RESET = VIH A6 = A3 = A2 = A0 = VIL, A1 = VIH Activate WE Pulse Increment PLSCNT Time out 100 µs WE = VIH, CE = OE = VIL (A9 should remain VID) Read from Sector Group = SPA, A1 = VIH * ( AAddr. 6 = A3 = A2 = A0 = VIL ) No PLSCNT = 25? Yes Remove VID from A9 Write Reset Command No Data = 01h? Yes Protect Another Sector Group? Yes No Device Failed Remove VID from A9 Write Reset Command Sector Group Protection Completed * : A-1 is VIL in byte mode. 61 MBM29DL64DF-70 (6) Temporary Sector Group Unprotection Algorithm Start RESET = VID *1 Perform Erase or Program Operations RESET = VIH Temporary Sector Group Unprotection Completed *2 *1 : All protected sector groups are unprotected. *2 : All previously protected sector groups are reprotected. 62 MBM29DL64DF-70 (7) Extended Sector Group Protection Algorithm Start RESET = VID Wait to 4 µs Device is Operating in Temporary Sector Group Unprotection Mode No Extended Sector Group Protection Entry? Yes To Setup Sector Group Protection Write XXXh/60h PLSCNT = 1 To Protect Secter Group Write 60h to Secter Address (A6 = A3 = A2 = A0 = VIL, A1 = VIH) Time out 250 µs To Verify Sector Group Protection Write 40h to Secter Address (A6 = A3 = A2 = A0 = VIL, A1 = VIH) Increment PLSCNT Read from Sector Group Address (Addr. = SPA, A1 = VIH, A6 = A3 = A2 = A0 = VIL) No Setup Next Sector Group Address PLSCNT = 25? Yes Remove VID from RESET Write Reset Command No Data = 01h? Yes Yes Protect Other Sector Group? No Remove VID from RESET Write Reset Command Device Failed Sector Group Protection Completed 63 MBM29DL64DF-70 (8) Embedded Programming Algorithm for Fast Mode FAST MODE ALGORITHM Start 555h/AAh Set Fast Mode 2AAh/55h 555h/20h XXXh/A0h Program Address/Program Data In Fast Program Data Polling Verify Data? No Yes Increment Address No Last Address? Yes Programming Completed (BA) XXXh/90h Reset Fast Mode XXXh/F0h Note : The sequence is applied for × 16 mode. 64 MBM29DL64DF-70 ■ ORDERING INFORMATION MBM29DL64D F 70 TN PACKAGE TYPE TN = 48-Pin Thin Small Outline Package (TSOP) Normal Bend PBT = 48-Ball Fine pitch Ball Grid Array Package (FBGA) SPEED OPTION See Product Selector Guide DEVICE REVISION DEVICE NUMBER/DESCRIPTION MBM29DL64D 64 Mega-bit (8 M × 8-Bit or 4 M × 16-Bit) Flash Memory 3.0 V-only Read, Program, and Erase Part No. MBM29DL64DF70TN MBM29DL64DF70PBT Package Access Time (ns) 48-pin plastic TSOP (1) (FPT-48P-M19) Normal Bend 70 48-pin plastic FBGA (BGA-48P-M13) 70 Remarks 65 MBM29DL64DF-70 ■ PACKAGE DIMENSIONS Note 1) * : Values do not include resin protrusion. Resin protrusion and gate protrusion are +0.15 (.006) Max (each side) . Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder. 48-pin plastic TSOP (1) (FPT-48P-M19) LEAD No. 1 48 INDEX Details of "A" part 0.25(.010) 0~8˚ 0.60±0.15 (.024±.006) 24 25 * 12.00±0.20 20.00±0.20 (.787±.008) * 18.40±0.20 (.724±.008) "A" 0.10(.004) (.472±.008) +0.10 1.10 –0.05 +.004 .043 –.002 (Mounting height) +0.03 0.17 –0.08 +.001 .007 –.003 C 0.10±0.05 (.004±.002) (Stand off height) 0.50(.020) 0.22±0.05 (.009±.002) 0.10(.004) M 2003 FUJITSU LIMITED F48029S-c-6-7 Dimensions in mm (inches) Note : The values in parentheses are reference values. (Continued) 66 MBM29DL64DF-70 (Continued) 48-pin plastic FBGA (BGA-48P-M13) +0.15 9.00±0.20(.354±.008) +.006 1.05 –0.10 .041 –.004 (Mounting height) 0.38±0.10(.015±.004) (Stand off) 5.60(.220) 0.80(.031)TYP 6 5 8.00±0.20 (.315±.008) 4 4.00(.157) 3 INDEX 2 1 H C0.25(.010) G F E D 48-ø0.45±0.10 (48-ø.018±.004) C B A ø0.08(.003) M 0.10(.004) C 2001 FUJITSU LIMITED B48013S-c-3-2 Dimensions in mm (inches) Note : The values in parentheses are reference values. 67 MBM29DL64DF-70 FUJITSU LIMITED All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of Fujitsu semiconductor device; Fujitsu does not warrant proper operation of the device with respect to use based on such information. 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