FUJITSU MBM29XL12DF-80

TM
SPANSION Flash Memory
Data Sheet
September 2003
TM
This document specifies SPANSION memory products that are now offered by both Advanced Micro Devices and
Fujitsu. Although the document is marked with the name of the company that originally developed the specification,
these products will be offered to customers of both AMD and Fujitsu.
Continuity of Specifications
There is no change to this datasheet as a result of offering the device as a SPANSION
revisions will occur when appropriate, and changes will be noted in a revision summary.
TM
product. Future routine
Continuity of Ordering Part Numbers
AMD and Fujitsu continue to support existing part numbers beginning with "Am" and "MBM". To order these
products, please use only the Ordering Part Numbers listed in this document.
For More Information
Please contact your local AMD or Fujitsu sales office for additional information about SPANSION
solutions.
TM
memory
FUJITSU SEMICONDUCTOR
DATA SHEET
DS05-20901-1E
PAGE MODE FLASH MEMORY
CMOS
128M (8M × 16/4M × 32) BIT
MBM29XL12DF-70/80
■ DESCRIPTION
The MBM29XL12DF is 128M-bit, 3.0 V-only Page mode and dual operation Flash memory organized as 8M words
by 16 bits or 4M words by 32 bits. The device is offered in 90-pin SSOP and 96-ball FBGA packages. This device
is designed to be programmed in-system with the standard system 3.0 V Vcc supply. 12.0 V Vpp and 5.0 V Vcc
are not required for program or erase operations. The device can also be reprogrammed in standard EPROM
programmers.
(Continued)
■ PRODUCT LINEUP
Part No.
Ordering Part Number Suffix
MBM29XL12DF
70
80
3.0 to 3.6
2.7 to 3.1
Max Random Address Access Time (ns)
70
80
Max Page Address Access Time (ns)
25
30
Max CE Access Time (ns)
70
80
Max OE Access Time (ns)
25
30
VCC (V)
■ PACKAGES
90-pin plastic SSOP
96-ball plastic FBGA
(FPT-90P-M01)
(BGA-96P-M02)
MBM29XL12DF-70/80
(Continued)
The device provides truly high performance non-volatile Flash memory solution. The device offers fast page
access times of 25 ns and 30 ns with random access times of 70 ns and 80 ns, allowing operation of high-speed
microprocessors without wait states. To eliminate bus contention the device has separate chip enable (CE), write
enable (WE), and output enable (OE) controls. The page size is 8 words or 4 double words.
The dual operation function provides simultaneous operation by dividing the memory space into four banks. The
device can improve overall system performance by allowing a host system to program or erase in one bank,
then immediately and simultaneously read from the other bank with zero latency. This releases the system from
waiting for the completion of program or erase operations.
The device is command set compatible with JEDEC standard E2PROMs. Commands are written to the command
register using standard microprocessor write timings. Register contents serve as input to an internal statemachine which controls the erase and programming circuitry. Write cycles also internally latch addresses and
data needed for the program and erase operations. Reading data out of the device is similar to reading from 5.0
V and 12.0 V Flash or EPROM devices.
The device is programmed by executing the program command sequence. This will invoke the Embedded
ProgramTM Algorithm which is an internal algorithm that automatically times the program pulse widths and verifies
proper cell margins. Typically, each 32K words sector can be programmed and verified in about 0.3 seconds.
Erase is accomplished by executing the erase command sequence. This will invoke the Embedded EraseTM
Algorithm which is an internal algorithm that automatically preprograms the array if it is not already programmed
before executing the erase operation. During erase, the device automatically times the erase pulse widths and
verifies proper cell margins.
Any individual sector is typically erased and verified in 0.5 seconds. (If already preprogrammed.)
The device also features a sector erase architecture. The sector mode allows each sector to be erased and
reprogrammed without affecting other sectors. The device is erased when shipped from the factory.
The device features single 3.0 V power supply operation for both read and write functions. Internally generated
and regulated voltages are provided for the program and erase operations. A low VCC detector automatically
inhibits program and erase operations on the loss of power. The end of program or erase is detected by Data
Polling of DQ7, by the Toggle Bit feature on DQ6, output pin. Once the end of a program or erase cycle has been
completed, the device internally resets to the read mode.
Fujitsu’s Flash technology combines years of Flash memory manufacturing experience to produce the highest
levels of quality, reliability, and cost effectiveness. The device memory electrically erases all bits within a sector
simultaneously via Fowler-Nordhiem tunneling. The words are programmed one word at a time using the EPROM
programming mechanism of hot electron injection.
2
MBM29XL12DF-70/80
■ FEATURES
• 0.17 µm Process Technology
• Single 3.0 V Read, Program and Erase
Minimized system level power requirements
• Simultaneous Read/Write (Program and Erase) Operations (Dual Bank)
• FlexBankTM *1
Bank A: 16 Mbit (4K words ×8 and 32K words ×31)
Bank B: 48 Mbit (32K words ×96)
Bank C: 48 Mbit (32K words ×96)
Bank D: 16 Mbit (4K words ×8 and 32K words ×31)
• High Performance Page Mode
25 ns maximum page access time at VCC = 3.0 V to 3.6 V(70 ns random access time)
30 ns maximum page access time at VCC = 2.7 V to 3.1 V(80 ns random access time)
• 8 Words Page (×
×16) / 4 Double Words Page (×
×32) Size
• Compatible with JEDEC-Standard Commands
Uses same software commands as E2PROMs
• Compatible with JEDEC-standard World-wide Pinouts
90-pin SSOP (Package Suffix : PFV)
96-ball FBGA (Package Suffix : PBT)
• Minimum 100,000 Program/Erase Cycles
• Sector Erase Architecture
Eight 4K words, two hundred fifty -four 32K words, and eight 4K words sectors
Any combination of sectors can be concurrently erased. Also supports full chip erase
• Dual Boot Block
16 by 4K words bootblock sectors, 8 at the top of the address range and 8 at the bottom of the address range
• HiddenROM Region
128 words of HiddenROM region by using device address of word mode 000000h to 00007Fh (double word
mode: 000000h to 00003Fh) accessible through a “HiddenROM Enable” command sequence
Factory serialized and protected to provide a secure electronic serial number (ESN)
• Write Protect Pin (WP)
Write Protect (WP) function allows protection of “outermost” 2×
× 4K words on both ends of boot sectors,
regardless of sector protection/unprotection status
• Accelerate Pin (ACC)
At VACC, increases program performance
• Embedded EraseTM *2 Algorithms
Automatically preprograms and erases the chip or any sector
• Embedded ProgramTM *2 Algorithms
Automatically programs and verifies data at specified address
• Data Polling and Toggle Bit Feature for detection of program or erase cycle completion
• Ready/Busy Output (RY/BY)
Hardware method for detection of program or erase cycle completion
• Automatic Sleep Mode
When addresses remain stable, the device automatically switches itself to low power mode.
• Low VCC Write Inhibit ≤ VLKO
(Continued)
3
MBM29XL12DF-70/80
(Continued)
• Program Suspend/Resume
Suspends the program operation to allow a read in another word
• Erase Suspend/Resume
Suspends the erase operation to allow a read data and/or program in another sector within the same device
• In accordance with CFI (Common Flash Memory Interface)
• Hardware Reset Pin (RESET)
Hardware method to reset the device for reading array data
• New Sector Protection
Persistent Sector Protection
Password Sector Protection
• Hardware Sector Group Protection
Hardware method disables any combination of sectors from program or erase operation
*1: FlexBankTM is a trademark of Fujitsu Limited, Japan.
*2: Embedded EraseTM and Embedded ProgramTM are trademarks of Advanced Micro Devices, Inc.
4
MBM29XL12DF-70/80
■ PIN ASSIGNMENTS
SSOP
(TOP VIEW)
N.C.
N.C.
N.C.
RESET
RY/BY
A0
A1
A2
A3
A4
A5
VCC
DQ0
DQ16
DQ1
DQ17
Vss
VCC
DQ2
DQ18
DQ3
DQ19
DQ4
DQ20
DQ5
DQ21
Vss
VCC
DQ6
DQ22
DQ7
DQ23
Vss
A6
A7
A8
A9
A10
A11
A12
N.C.
N.C.
N.C.
N.C.
N.C.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
N.C.
N.C.
ACC
WP
WE
N.C.
A21
A20
DW/W
OE
CE
Vss
DQ31/A-1
DQ15
DQ30
DQ14
Vss
VCC
DQ29
DQ13
DQ28
DQ12
DQ27
DQ11
DQ26
DQ10
Vss
VCC
DQ25
DQ9
DQ24
DQ8
VCC
A19
A18
A17
A16
A15
A14
A13
N.C.
N.C.
N.C.
N.C.
N.C.
(FPT-90P-M01)
(Continued)
5
MBM29XL12DF-70/80
(Continued)
FBGA
(TOP VIEW)
Marking Side
A11
B11
C11
P11
Q11
R11
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
E10
F10
G10
H10
J10
K10
L10
M10
DQ30
VCC
DQ13
DQ12
DQ27
DQ26
VCC
DQ9
D9
E9
F9
G9
H9
J9
K9
L9
M9
N9
CE
VSS
DQ15
DQ29
DQ28
DQ11
VSS
DQ24
VCC
A19
D8
E8
F8
G8
H8
J8
K8
L8
M8
N8
A20
DW/W
OE
DQ14
VSS
DQ10
DQ25
A18
A17
A16
F7
G7
H7
D7
E7
WE
N.C.
D6
E6
RESET ACC
A21 DQ31/A-1 N.C.
J7
K7
L7
M7
N7
N.C.
DQ8
A15
A14
A13
F6
G6
H6
J6
K6
L6
M6
N6
WP
RY/BY
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
D5
E5
F5
G5
H5
J5
K5
L5
M5
N5
A1
A2
A3
A0
DQ2
N.C.
A12
A11
A9
A10
D4
E4
F4
G4
H4
J4
K4
L4
M4
N4
A4
A5
DQ0
DQ16
DQ18
DQ5
DQ21
A8
A6
A7
E3
F3
G3
H3
J3
K3
L3
M3
N3
VCC
DQ1
VSS
DQ19
DQ4
DQ6
DQ7
DQ23
VSS
F2
G2
H2
J2
K2
L2
M2
DQ17
VCC
DQ3
DQ20
VSS
VCC
DQ22
A1
B1
C1
P1
Q1
R1
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
(BGA-96P-M02)
6
MBM29XL12DF-70/80
■ PIN DESCRIPTIONS
MBM29XL12DF Pin Configuration
Pin
Function
A21 to A0, A-1
Address Inputs
DQ31 to DQ0
Data Inputs/Outputs
CE
Chip Enable
OE
Output Enable
WE
Write Enable
RESET
Hardware Reset / Temporary Sector Group Unprotection
RY/BY
Ready/Busy Output
DW / W
Selects 32-bit or 16-bit mode
WP
Hardware Write Protection
ACC
Program Acceleration
N.C.
Pin Not Connected Internally
VSS
Device Ground
VCC
Device Power Supply
7
MBM29XL12DF-70/80
■ BLOCK DIAGRAM
Cell Matrix
16 Mbit
(Bank A)
A21 to A0, A-1
Cell Matrix
48 Mbit
(Bank B)
X-Decoder
Y-Gating
Bank A
address
Y-Gating
VCC
VSS
X-Decoder
Bank B Address
State
Control
&
Command
Register
RY/BY
DQ31
to
DQ0
Status
Control
Bank C Address
X-Decoder
Cell Matrix
16 Mbit
(Bank D)
Bank D
address
Y-Gating
X-Decoder
Cell Matrix
48 Mbit
(Bank C)
■ LOGIC SYMBOL
A-1
22
A21 to A0
32 or 16
DQ31 to DQ0
RESET
CE
OE
WE
DW/W
WP
ACC
8
RY/BY
Y-Gating
RESET
WE
CE
OE
DW/W
WP
ACC
DQ15 to DQ0
MBM29XL12DF-70/80
■ DEVICE BUS OPERATION
MBM29XL12DF User Bus Operations Table (DW/W = VIL)
Operation
CE OE WE WP
DQ31
A0
/A-1
A1
A2
A3
A4
A5
A6
A9
DQ15 to
RESET
DQ0*7
Autoselect Manufacturer
Code *1
L
L
H
X
L
L
L
L
L
X
X
L
VID
Code
H
Autoselect Device Code *1
L
L
H
X
L
H
L
L
L
X
X
L
VID
Code
H
Extended Autoselect Device
Code *1
L
L
H
X
L
L
H
H
H
X
X
L
VID
Code
H
L
L
H
X
L
H
H
H
H
X
X
L
VID
Code
H
Read *3
L
L
H
X
A-1
A0
A1
A2
A3
A4
A5
A6
A9
DOUT
H
Standby
H
X
X
X
X
X
X
X
X
X
X
X
X
High-Z
H
Output Disable
L
H
H
X
X
X
X
X
X
X
X
X
X
High-Z
H
Write (Program/Erase)
L
H
L
X
A-1
A0
A1
A2
A3
A4
A5
A6
A9
DIN
H
Enable Sector Group
Protection *2,*4
L
VID
X
L
L
H
L
H
H
H
L
VID
X
H
Verify Sector Group
Protection *2, *4
L
L
H
H
L
L
H
L
H
H
H
L
VID
Code
H
Boot Block Sector Write
Protection *5
X
X
X
L
X
X
X
X
X
X
X
X
X
X
H
Temporary Sector Group
Unprotection *6
X
X
X
H
X
X
X
X
X
X
X
X
X
X
VID
Reset
X
X
X
X
X
X
X
X
X
X
X
X
X
High-Z
L
Legend: L = VIL, H = VIH, X = VIL or VIH,
= Pulse input. See "■DC CHARACTERISTICS" for voltage levels.
*1 : Manufacturer and device codes may also be accessed via a command register write sequence.
See "MBM29XL12DF Command Definitions Table".
*2 : Refer to section on "Sector Group Protection".
*3 : WE can be VIL if OE is VIL, OE at VIH initiates the program and erase operations.
*4 : VCC = 3.0 V to 3.6 V for 70 ns random access time
VCC = 2.7 V to 3.1 V for 80 ns random access time
*5 : Protects “outermost” 2 × 4K words on both end of the boot block sectors. (SA0, SA1, SA268, and SA269)
*6 : Also used for "Extended Sector Group Protection".
*7 : DQ30 to DQ16 = X (VIL or VIH)
9
MBM29XL12DF-70/80
MBM29XL12DF User Bus Operations Table (DW/W = VIH)
Operation
CE OE WE
WP
A0
A1
A2
A3
A4
A5
A6
A9
DQ31 to
RESET
DQ0
Autoselect Manufacturer
Code *1
L
L
H
X
L
L
L
L
X
X
L
VID
Code
H
Autoselect Device Code *1
L
L
H
X
H
L
L
L
X
X
L
VID
Code
H
Extended Autoselect Device
Code *1
L
L
H
X
L
H
H
H
X
X
L
VID
Code
H
L
L
H
X
H
H
H
H
X
X
L
VID
Code
H
L
L
H
X
A0
A1
A2
A3
A4
A5
A6
A9
DOUT
H
Standby
H
X
X
X
X
X
X
X
X
X
X
X
High-Z
H
Output Disable
L
H
H
X
X
X
X
X
X
X
X
X
High-Z
H
Write (Program/Erase)
L
H
L
X
A0
A1
A2
A3
A4
A5
A6
A9
DIN
H
Enable Sector Group
Protection *2,*4
L
VID
X
L
H
L
H
H
H
L
VID
X
H
Verify Sector Group
Protection *2, *4
L
L
H
H
L
H
L
H
H
H
L
VID
Code
H
Boot Block Sector Write
Protection *5
X
X
X
L
X
X
X
X
X
X
X
X
X
H
Temporary Sector Group
Unprotection *6
X
X
X
H
X
X
X
X
X
X
X
X
X
VID
Reset
X
X
X
X
X
X
X
X
X
X
X
X
High-Z
L
Read *
3
Legend: L = VIL, H = VIH, X = VIL or VIH,
= Pulse input. See "■DC CHARACTERISTICS" for voltage levels.
*1 : Manufacturer and device codes may also be accessed via a command register write sequence.
See "MBM29XL12DF Command Definitions Table".
*2 : Refer to section on "Sector Group Protection".
*3 : WE can be VIL if OE is VIL, OE at VIH initiates the program and erase operations.
*4 : VCC = 3.0 V to 3.6 V for 70 ns random access time
VCC = 2.7 V to 3.1 V for 80 ns random access time
*5 : Protects “outermost” 2 × 4K words on both end of the boot block sectors. (SA0, SA1, SA268, and SA269)
*6 : Also used for "Extended Sector Group Protection".
10
MBM29XL12DF-70/80
MBM29XL12DF Command Definitions Table
Bus
Second
Bus Fifth Bus
Seventh
First Bus
Third Bus Fourth
Sixth Bus
Write Write
Bus
Read/Write Write
Bus
Cycle
Write
Cycle
Cycle
Write
Cycle
CyWrite Cycle
Cycle
Write Cycle
cles
Req’d Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data
Command
Sequence
Read/Reset *1
Read/Reset
*1
Autoselect
2
DW
W
DW
4
3
W
Program
Chip Erase
Sector Erase
DW
W
DW
W
DW
W
XXXh F0h
555h
AAAh
555h
AAh
AAh
AAAh
4
6
6
555h
AAAh
555h
AAAh
555h
AAAh
AAh
AAh
AAh
RA
—
—
—
—
—
—
—
—
—
F0h
RA
RD
—
—
—
—
—
—
2AAh
(BA)
555h
55h
90h
—
—
—
—
—
—
—
—
555h
AAAh
PA
PD
—
—
—
—
—
—
10h
—
—
2AAh
555h
2AAh
555h
2AAh
555h
2AAh
555h
RD
55h
55h
55h
55h
—
555h
AAAh
555h
AAAh
555h
AAAh
555h
AAAh
A0h
80h
80h
555h
AAAh
555h
AAAh
AAh
AAh
2AAh
555h
2AAh
555h
55h
555h
AAAh
55h
SA
30h
—
—
Program/Erase
Suspend
1
BA
B0h
—
—
—
—
—
—
—
—
—
—
—
—
Program/Erase
Resume
1
BA
30h
—
—
—
—
—
—
—
—
—
—
—
—
20h
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
SGA
SD
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
88h
—
—
—
—
—
—
—
—
(HRA)
PD
PA
—
—
—
—
—
—
90h XXXh 00h
—
—
—
—
—
—
Set to Fast
Mode
DW
Fast
Program *2
DW
W
W
3
2
DW
Reset from
2
Fast Mode * W
2
Extended
Sector
Group
Protection*3
4
555h
AAAh
XXXh
XXXh
BA
BA
AAh
A0h
90h
2AAh
555h
PA
55h
PD
XXXh F0h
XXXh
*6
555h
AAAh
DW
XXXh 60h SGA 60h SGA 40h
W
DW
Query *4
1
W
HiddenROM DW
Entry
W
3
HiddenROM DW
Program *5
W
4
HiddenROM DW
Exit *5
W
4
(BA)
55h
(BA)
55h
555h
AAAh
555h
AAAh
555h
AAAh
98h
AAh
AAh
AAh
—
2AAh
555h
2AAh
555h
2AAh
555h
—
55h
55h
55h
—
555h
AAAh
555h
AAAh
555h
AAAh
A0h
(Continued)
11
MBM29XL12DF-70/80
(Continued)
Bus
Second
Bus
Seventh
First Bus
Third Bus Fourth
Fifth Bus
Sixth Bus
Write Write
Bus
Read/Write Write
Bus
Cycle
Write
Cycle
Cycle
Write
Cycle
CyWrite Cycle
Cycle
Write Cycle
cles
Req’d Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data
Command
Sequence
HiddenROM DW
Protect *5
W
6
AAAh
AAh
555h
DW
Password
Program *7
555h
4
W
2AAh
555h
55h
55h
555h
AAAh
AAAh
RD
(0)
—
—
—
—
—
—
—
—
—
—
60h OPBP 68h OPBP 48h XXXh
XX0h PD0
555h
2AAh
AAh
555h
XX1h PD1
38h
AAAh
XX0h PD0
XX1h PD1
—
—
XX2h PD2
XX3h PD3
Password
Unlock
DW
5
555h
W
7
AAAh
Password
Verify
DW
W
Password
DW
Mode Locking
W
Bit Program
Persistent
DW
Sector
Protection
Mode Locking W
Bit Program
PPB
Program
PPB Verify
W
DW
W
All PPB
Erase *8
DW
PPB Lock
Bit Set
DW
PPB Lock
Bit Verify
DW
DPB Write
DPB Erase
DPB/PPB
Verify
12
DW
W
W
3
W
DW
W
DW
W
AAAh
AAh
555h
6
AAAh
6
6
4
6
3
4
4
4
4
AAAh
555h
AAAh
555h
2AAh
555h
2AAh
555h
55h
55h
555h
55h
AAh
555h
2AAh
555h
2AAh
AAAh
555h
AAAh
28h XX0h PD0 XX1h PD1
C8h PWA PWD
—
60h
PL
—
XX2h PD2 XX3h PD3
—
—
—
—
48h XXh
RD
(0)
AAAh
—
—
60h SPML 68h SPML 48h XXh
RD
(0)
—
—
PL
68h
555h
2AAh
AAh
555h
555h
2AAh
AAh
555h
W
DW
555h
AAh
55h
55h
AAAh
555h
AAAh
555h
60h
(SGA)
WP
68h
(SGA)
WP
48h
XX
RD
(0)
—
—
58h
SA
RD
(0)
—
—
—
—
—
—
60h
EP
60h
EP
40h
XX
RD
(0)
—
—
78h
—
—
—
—
—
—
—
—
(BA)
555h
AAh
55h
58h
AAAh
AAAh
555h
SA
RD
(1)
—
—
—
—
—
—
48h
SA
X1h
—
—
—
—
—
—
48h
SA
X0h
—
—
—
—
—
—
(BA)
555h
AAh
55h
58h
AAAh
AAAh
555h
SA
RD
(0)
—
—
—
—
—
—
AAAh
555h
AAAh
555h
AAAh
AAh
AAh
AAh
555h
555h
AAAh
555h
AAAh
555h
555h
2AAh
555h
2AAh
555h
55h
55h
55h
AAAh
555h
AAAh
555h
AAAh
2AAh
AAh
AAh
2AAh
555h
2AAh
555h
2AAh
55h
55h
555h
AAAh
555h
AAAh
MBM29XL12DF-70/80
Legend :
= Address of the memory location to be read
= Address of the memory location to be programmed
Addresses are latched on the falling edge of the write pulse.
SA
= Address of the sector
BA
= Bank Address
RD
= Data read from location RA during read operation.
PD
= Data to be programmed at location PA. Data is latched on the rising edge of write pulse.
SGA = Sector group address to be protected. Set sector group address and (A6, A5, A4, A3, A2, A1, A0)
= (0, 1, 1, 1, 0, 1, 0)
SD
= Sector group protection verify data. Output 01h at protected sector group addresses and output
00h at unprotected sector group addresses.
HRA = Address of the HiddenROM area(Double Word Mode: 000000h to 00003Fh)
(Word Mode
: 000000h to 00007Fh)
RD(0) = DQ0 data, RD(1) = DQ1 data. PPB Lock bit is read on DQ1 and PPB or DPB are read on DQ0.
If set, DQ0/DQ1=1. If cleared, DQ0/DQ1=0.
OPBP = (A6, A5, A4, A3, A2, A1, A0) is (X, 0, 1, 1, 0, 1, 0)
64 bit Password Data
PD0 to PD1 : Double Word Mode
PD0 to PD3 : Word Mode
PWA/PWD = Password Address/Password Data
PL
= Password Locking Address (A6, A5, A4, A3, A2, A1, A0) is (X, 0, 0, 1, 0, 1, 0)
SPML = Persistent Protection Mode Locking (A6, A5, A4, A3, A2, A1, A0) is (X, 0, 1, 0, 0, 1, 0)
WP = PPB Program (A6, A5, A4, A3, A2, A1, A0) is (0, 1, 1, 1, 0, 1, 0)
EP
= PPB Erase (A6, A5, A4, A3, A2, A1, A0) is (1, 1, 1, 1, 0, 1, 0)
RA
PA
*1 : Both of these reset commands are equivalent.
*2 : This command is valid during Fast Mode.
*3 : This command is valid while RESET = VID.
*4 : The valid addresses are A6 to A0.
*5 : This command is valid during HiddenROM mode.
*6 : The data “00h” is also acceptable.
*7 : Data before fourth cycle also need to be programmed repearting from first cycle to third cycle.
*8 : RD(0) of the sixth cycle shows PPB erase status. When RD(0) is "1", programming must be repeated
from the beginning of first cycle to the fourth cycle; both fifth and the sixth validate full completion of erase.
Notes : • Address bits A21 to A11 = X = “H” or “L” for all address commands except for PA, SA, BA, SGA, OPBP,
PWA, PL, SPML, WP.
• Bus operations are defined in "MBM29XL12DF User Bus Operations Table (DW/W = VIL)" and
"MBM29XL12DF User Bus Operations Table (DW/W = VIH)".
• The system should generate the following address patterns:
DW (Double Word) Mode : 555h or 2AAh to addresses A10 to A0
W (Word) Mode
: AAAh or 555h to addresses A10 to A0, A-1
• Both Read/Reset commands are functionally equivalent, resetting the device to the read mode.
• Command combinations not described in “Command Definitions Table” are illegal.
13
MBM29XL12DF-70/80
MBM29XL12DF Autoselect Codes Table
Type
Manufacture’s Code
Device
Code
Double Word
Word
Double Word
Extended
Device
Code*4
Word
Double Word
Word
PPB Protection
A21 to A11
A6
A5
A4
A3
A2
A1
A0
A-1*1
Code (HEX)
BA*3
VIL
x
x
VIL
VIL
VIL
VIL
VIL
04h
BA*3
VIL
x
x
VIL
VIL
VIL
VIH
x
2222227Eh
VIL
227Eh
BA*3
VIL
x
x
VIH
VIH
VIH
VIL
x
2222220Dh
VIL
220Dh
BA*3
VIL
x
x
VIH
VIH
VIH
VIH
x
22222200h
VIL
2200h
Sector
Group
Addresses
VIL
VIH
VIH
VIH
VIL
VIH
VIL
VIL
01h*2
*1 : A-1 is for word mode.
*2 : Sector Group can be protected by "Sector Group Protection", "Extended Sector Group Protection" and
"New Sector Protection(PPB Protection)". Outputs 01h at protected PPB addresses and outputs 00h at
unprotected PPB addresses.
*3 : When VID is applied to A9, both Bank 1 and Bank 2 are put into Autoselect mode, which makes simutaneous
operation unable to be executed. Consequently, specifying the bank address is not required. However, the bank
address needs to be indicated when Autoselect mode is read out at command mode, because then it enables
to activate simultaneous operation.
*4 : At double word mode, a read cycle at address (BA) 01h (at word mode,02h) outputs device code.
When 222227Eh (at word mode,227Eh) is output, it indicates that two additional codes, called Extended
Device Codes, will be required. Therefore the system may continue reading out these Extended
Device Codes at the address of (BA) 0Eh (at word mode,1Ch), as well as at (BA) 0Fh (at word mode, 1Eh).
14
MBM29XL12DF-70/80
Exteneded Auteselect Code Table
Type
Code DQ31 DQ30 DQ29 DQ28 DQ27 DQ26 DQ25 DQ24 DQ23 DQ22 DQ21 DQ20 DQ19 DQ18 DQ17 DQ16
Manufacturer’s
Code
04h
A-1/0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
2222
227Eh
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
A-1
HZ
HZ
HZ
HZ
HZ
HZ
HZ
HZ
HZ
HZ
HZ
HZ
HZ
HZ
HZ
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
(W) 220Dh A-1
HZ
HZ
HZ
HZ
HZ
HZ
HZ
HZ
HZ
HZ
HZ
HZ
HZ
HZ
HZ
2222
2200h
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
A-1
HZ
HZ
HZ
HZ
HZ
HZ
HZ
HZ
HZ
HZ
HZ
HZ
HZ
HZ
HZ
(DW)
Device Code
(W) 227Eh
(DW)
Extended
Device Code
(DW)
2222
220Dh
(W) 2200h
PPB Protection
01h
A-1/0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PPB Unprotection
00h
A-1/0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Type
Code DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0
Manufacturer’s
Code
04h
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
(DW)
2222
227Eh
0
0
1
0
0
0
1
0
0
1
1
1
1
1
1
0
(W)
227Eh
0
0
1
0
0
0
1
0
0
1
1
1
1
1
1
0
(DW)
2222
220Dh
0
0
1
0
0
0
1
0
0
0
0
0
1
1
0
1
0
0
1
0
0
0
1
0
0
0
0
0
1
1
0
1
0
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0
2200h
0
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0
PPB Protection *
01h
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
PPB Unprotection *
00h
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Device Code
(W) 220Dh
Extended
Device Code
2222
(DW)
(W)
2200h
HZ
: High-Z
(DW) : Double Word mode
(W)
: Word mode
* : In word mode, DQ30 to DQ16 become "High-Z" and DQ31 becomes Lowest address "A-1".
15
MBM29XL12DF-70/80
Sector Address Tables (Bank A)
Sector Address
Bank Sector
Bank
Address
A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11
Bank
A
16
Sector
Size
(KW /
KDW)
(× 16)
Address Range
(× 32)
Address Range
SA0
0
0
0
0
0
0
0
0
0
0
0
4/2
000000h to 000FFFh
000000h to 0007FFh
SA1
0
0
0
0
0
0
0
0
0
0
1
4/2
001000h to 001FFFh
000800h to 000FFFh
SA2
0
0
0
0
0
0
0
0
0
1
0
4/2
002000h to 002FFFh
001000h to 0017FFh
SA3
0
0
0
0
0
0
0
0
0
1
1
4/2
003000h to 003FFFh
001800h to 001FFFh
SA4
0
0
0
0
0
0
0
0
1
0
0
4/2
004000h to 004FFFh
002000h to 0027FFh
SA5
0
0
0
0
0
0
0
0
1
0
1
4/2
005000h to 005FFFh
002800h to 002FFFh
SA6
0
0
0
0
0
0
0
0
1
1
0
4/2
006000h to 006FFFh
003000h to 0037FFh
SA7
0
0
0
0
0
0
0
0
1
1
1
4/2
007000h to 007FFFh
003800h to 003FFFh
SA8
0
0
0
0
0
0
0
1
X
X
X
32/16
008000h to 00FFFFh
004000h to 007FFFh
SA9
0
0
0
0
0
0
1
0
X
X
X
32/16
010000h to 017FFFh
008000h to 00BFFFh
SA10
0
0
0
0
0
0
1
1
X
X
X
32/16
018000h to 01FFFFh
00C000h to 00FFFFh
SA11
0
0
0
0
0
1
0
0
X
X
X
32/16
020000h to 027FFFh
010000h to 013FFFh
SA12
0
0
0
0
0
1
0
1
X
X
X
32/16
028000h to 02FFFFh
014000h to 017FFFh
SA13
0
0
0
0
0
1
1
0
X
X
X
32/16
030000h to 037FFFh
018000h to 01BFFFh
SA14
0
0
0
0
0
1
1
1
X
X
X
32/16
038000h to 03FFFFh
01C000h to 01FFFFh
SA15
0
0
0
0
1
0
0
0
X
X
X
32/16
040000h to 047FFFh
020000h to 023FFFh
SA16
0
0
0
0
1
0
0
1
X
X
X
32/16
048000h to 04FFFFh
024000h to 027FFFh
SA17
0
0
0
0
1
0
1
0
X
X
X
32/16
050000h to 057FFFh
028000h to 02BFFFh
SA18
0
0
0
0
1
0
1
1
X
X
X
32/16
058000h to 05FFFFh
02C000h to 02FFFFh
SA19
0
0
0
0
1
1
0
0
X
X
X
32/16
060000h to 067FFFh
030000h to 033FFFh
SA20
0
0
0
0
1
1
0
1
X
X
X
32/16
068000h to 06FFFFh
034000h to 037FFFh
SA21
0
0
0
0
1
1
1
0
X
X
X
32/16
070000h to 077FFFh
038000h to 03BFFFh
SA22
0
0
0
0
1
1
1
1
X
X
X
32/16
078000h to 07FFFFh
03C000h to 03FFFFh
SA23
0
0
0
1
0
0
0
0
X
X
X
32/16
080000h to 087FFFh
040000h to 043FFFh
SA24
0
0
0
1
0
0
0
1
X
X
X
32/16
088000h to 08FFFFh
044000h to 047FFFh
SA25
0
0
0
1
0
0
1
0
X
X
X
32/16
090000h to 097FFFh
048000h to 04BFFFh
SA26
0
0
0
1
0
0
1
1
X
X
X
32/16
098000h to 09FFFFh
04C000h to 04FFFFh
SA27
0
0
0
1
0
1
0
0
X
X
X
32/16
0A0000h to 0A7FFFh
050000h to 053FFFh
SA28
0
0
0
1
0
1
0
1
X
X
X
32/16
0A8000h to 0AFFFFh
054000h to 057FFFh
SA29
0
0
0
1
0
1
1
0
X
X
X
32/16
0B0000h to 0B7FFFh
058000h to 05BFFFh
SA30
0
0
0
1
0
1
1
1
X
X
X
32/16
0B8000h to 0BFFFFh
05C000h to 05FFFFh
SA31
0
0
0
1
1
0
0
0
X
X
X
32/16
0C0000h to 0C7FFFh
060000h to 063FFFh
SA32
0
0
0
1
1
0
0
1
X
X
X
32/16
0C8000h to 0CFFFFh
064000h to 067FFFh
SA33
0
0
0
1
1
0
1
0
X
X
X
32/16
0D0000h to 0D7FFFh
068000h to 06BFFFh
SA34
0
0
0
1
1
0
1
1
X
X
X
32/16
0D8000h to 0DFFFFh
06C000h to 06FFFFh
SA35
0
0
0
1
1
1
0
0
X
X
X
32/16
0E0000h to 0E7FFFh
070000h to 073FFFh
SA36
0
0
0
1
1
1
0
1
X
X
X
32/16
0E8000h to 0EFFFFh
074000h to 077FFFh
SA37
0
0
0
1
1
1
1
0
X
X
X
32/16
0F0000h to 0F7FFFh
078000h to 07BFFFh
SA38
0
0
0
1
1
1
1
1
X
X
X
32/16
0F8000h to 0FFFFFh
07C000h to 07FFFFh
MBM29XL12DF-70/80
Bank Sector
Bank
Address
A21 A20 A19
Bank
B
Sector Address Tables (Bank B)
Sector Address
Sector
Size
(× 16)
(KW /
Address Range
A18 A17 A16 A15 A14 A13 A12 A11 KDW)
(× 32)
Address Range
SA39
0
0
1
0
0
0
0
0
X
X
X
32/16
100000h to 107FFFh
080000h to 083FFFh
SA40
0
0
1
0
0
0
0
1
X
X
X
32/16
108000h to 10FFFFh
084000h to 087FFFh
SA41
0
0
1
0
0
0
1
0
X
X
X
32/16
110000h to 117FFFh
088000h to 08BFFFh
SA42
0
0
1
0
0
0
1
1
X
X
X
32/16
118000h to 11FFFFh
08C000h to 08FFFFh
SA43
0
0
1
0
0
1
0
0
X
X
X
32/16
120000h to 127FFFh
090000h to 093FFFh
SA44
0
0
1
0
0
1
0
1
X
X
X
32/16
128000h to 12FFFFh
094000h to 097FFFh
SA45
0
0
1
0
0
1
1
0
X
X
X
32/16
130000h to 137FFFh
098000h to 09BFFFh
SA46
0
0
1
0
0
1
1
1
X
X
X
32/16
138000h to 13FFFFh
09C000h to 09FFFFh
SA47
0
0
1
0
1
0
0
0
X
X
X
32/16
140000h to 147FFFh
0A0000h to 0A3FFFh
SA48
0
0
1
0
1
0
0
1
X
X
X
32/16
148000h to 14FFFFh
0A4000h to 0A7FFFh
SA49
0
0
1
0
1
0
1
0
X
X
X
32/16
150000h to 157FFFh
0A8000h to 0ABFFFh
SA50
0
0
1
0
1
0
1
1
X
X
X
32/16
158000h to 15FFFFh
0AC000h to 0AFFFFh
SA51
0
0
1
0
1
1
0
0
X
X
X
32/16
160000h to 167FFFh
0B0000h to 0B3FFFh
SA52
0
0
1
0
1
1
0
1
X
X
X
32/16
168000h to 16FFFFh
0B4000h to 0B7FFFh
SA53
0
0
1
0
1
1
1
0
X
X
X
32/16
170000h to 177FFFh
0B8000h to 0BBFFFh
SA54
0
0
1
0
1
1
1
1
X
X
X
32/16
178000h to 17FFFFh
0BC000h to 0BFFFFh
SA55
0
0
1
1
0
0
0
0
X
X
X
32/16
180000h to 187FFFh
0C0000h to 0C3FFFh
SA56
0
0
1
1
0
0
0
1
X
X
X
32/16
188000h to 18FFFFh
0C4000h to 0C7FFFh
SA57
0
0
1
1
0
0
1
0
X
X
X
32/16
190000h to 197FFFh
0C8000h to 0CBFFFh
SA58
0
0
1
1
0
0
1
1
X
X
X
32/16
198000h to 19FFFFh
0CC000h to 0CFFFFh
SA59
0
0
1
1
0
1
0
0
X
X
X
32/16
1A0000h to 1A7FFFh
0D0000h to 0D3FFFh
SA60
0
0
1
1
0
1
0
1
X
X
X
32/16
1A8000h to 1AFFFFh
0D4000h to 0D7FFFh
SA61
0
0
1
1
0
1
1
0
X
X
X
32/16
1B0000h to 1B7FFFh
0D8000h to 0DBFFFh
SA62
0
0
1
1
0
1
1
1
X
X
X
32/16
1B8000h to 1BFFFFh
0DC000h to 0DFFFFh
SA63
0
0
1
1
1
0
0
0
X
X
X
32/16
1C0000h to 1C7FFFh
0E0000h to 0E3FFFh
SA64
0
0
1
1
1
0
0
1
X
X
X
32/16
1C8000h to 1CFFFFh
0E4000h to 0E7FFFh
SA65
0
0
1
1
1
0
1
0
X
X
X
32/16
1D0000h to 1D7FFFh
0E8000h to 0EBFFFh
SA66
0
0
1
1
1
0
1
1
X
X
X
32/16
1D8000h to 1DFFFFh
0EC000h to 0EFFFFh
SA67
0
0
1
1
1
1
0
0
X
X
X
32/16
1E0000h to 1E7FFFh
0F0000h to 0F3FFFh
SA68
0
0
1
1
1
1
0
1
X
X
X
32/16
1E8000h to 1EFFFFh
0F4000h to 0F7FFFh
SA69
0
0
1
1
1
1
1
0
X
X
X
32/16
1F0000h to 1F7FFFh
0F8000h to 0FBFFFh
SA70
0
0
1
1
1
1
1
1
X
X
X
32/16
1F8000h to 1FFFFFh
0FC000h to 0FFFFFh
SA71
0
1
0
0
0
0
0
0
X
X
X
32/16
200000h to 207FFFh
100000h to 103FFFh
SA72
0
1
0
0
0
0
0
1
X
X
X
32/16
208000h to 20FFFFh
104000h to 107FFFh
SA73
0
1
0
0
0
0
1
0
X
X
X
32/16
210000h to 217FFFh
108000h to 10BFFFh
SA74
0
1
0
0
0
0
1
1
X
X
X
32/16
218000h to 21FFFFh
10C000h to 10FFFFh
SA75
0
1
0
0
0
1
0
0
X
X
X
32/16
220000h to 227FFFh
110000h to 113FFFh
SA76
0
1
0
0
0
1
0
1
X
X
X
32/16
228000h to 22FFFFh
114000h to 117FFFh
SA77
0
1
0
0
0
1
1
0
X
X
X
32/16
230000h to 237FFFh
118000h to 11BFFFh
(Continued)
17
MBM29XL12DF-70/80
Sector Address
Bank Sector
Bank
Address
A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11
Bank
B
Sector
Size
(KW /
KDW)
(× 16)
Address Range
(× 32)
Address Range
SA78
0
1
0
0
0
1
1
1
X
X
X
32/16
238000h to 23FFFFh
11C000h to 11FFFFh
SA79
0
1
0
0
1
0
0
0
X
X
X
32/16
240000h to 247FFFh
120000h to 123FFFh
SA80
0
1
0
0
1
0
0
1
X
X
X
32/16
248000h to 24FFFFh
124000h to 127FFFh
SA81
0
1
0
0
1
0
1
0
X
X
X
32/16
250000h to 257FFFh
128000h to 12BFFFh
SA82
0
1
0
0
1
0
1
1
X
X
X
32/16
258000h to 25FFFFh
12C000h to 12FFFFh
SA83
0
1
0
0
1
1
0
0
X
X
X
32/16
260000h to 267FFFh
130000h to 133FFFh
SA84
0
1
0
0
1
1
0
1
X
X
X
32/16
268000h to 26FFFFh
134000h to 137FFFh
SA85
0
1
0
0
1
1
1
0
X
X
X
32/16
270000h to 277FFFh
138000h to 13BFFFh
SA86
0
1
0
0
1
1
1
1
X
X
X
32/16
278000h to 27FFFFh
13C000h to 13FFFFh
SA87
0
1
0
1
0
0
0
0
X
X
X
32/16
280000h to 287FFFh
140000h to 143FFFh
SA88
0
1
0
1
0
0
0
1
X
X
X
32/16
288000h to 28FFFFh
144000h to 147FFFh
SA89
0
1
0
1
0
0
1
0
X
X
X
32/16
290000h to 297FFFh
148000h to 14BFFFh
SA90
0
1
0
1
0
0
1
1
X
X
X
32/16
298000h to 29FFFFh
14C000h to 14FFFFh
SA91
0
1
0
1
0
1
0
0
X
X
X
32/16
2A0000h to 2A7FFFh
150000h to 153FFFh
SA92
0
1
0
1
0
1
0
1
X
X
X
32/16
2A8000h to 2AFFFFh
154000h to 157FFFh
SA93
0
1
0
1
0
1
1
0
X
X
X
32/16
2B0000h to 2B7FFFh
158000h to 15BFFFh
SA94
0
1
0
1
0
1
1
1
X
X
X
32/16
2B8000h to 2BFFFFh
15C000h to 15FFFFh
SA95
0
1
0
1
1
0
0
0
X
X
X
32/16
2C0000h to 2C7FFFh
160000h to 163FFFh
SA96
0
1
0
1
1
0
0
1
X
X
X
32/16
2C8000h to 2CFFFFh
164000h to 167FFFh
SA97
0
1
0
1
1
0
1
0
X
X
X
32/16
2D0000h to 2D7FFFh
168000h to 16BFFFh
SA98
0
1
0
1
1
0
1
1
X
X
X
32/16
2D8000h to 2DFFFFh
16C000h to 16FFFFh
SA99
0
1
0
1
1
1
0
0
X
X
X
32/16
2E0000h to 2E7FFFh
170000h to 173FFFh
SA100
0
1
0
1
1
1
0
1
X
X
X
32/16
2E8000h to 2EFFFFh
174000h to 177FFFh
SA101
0
1
0
1
1
1
1
0
X
X
X
32/16
2F0000h to 2F7FFFh
178000h to 17BFFFh
SA102
0
1
0
1
1
1
1
1
X
X
X
32/16
2F8000h to 2FFFFFh
17C000h to 17FFFFh
SA103
0
1
1
0
0
0
0
0
X
X
X
32/16
300000h to 307FFFh
180000h to 183FFFh
SA104
0
1
1
0
0
0
0
1
X
X
X
32/16
308000h to 30FFFFh
184000h to 187FFFh
SA105
0
1
1
0
0
0
1
0
X
X
X
32/16
310000h to 317FFFh
188000h to 18BFFFh
SA106
0
1
1
0
0
0
1
1
X
X
X
32/16
318000h to 31FFFFh
18C000h to 18FFFFh
SA107
0
1
1
0
0
1
0
0
X
X
X
32/16
320000h to 327FFFh
190000h to 193FFFh
SA108
0
1
1
0
0
1
0
1
X
X
X
32/16
328000h to 32FFFFh
194000h to 197FFFh
SA109
0
1
1
0
0
1
1
0
X
X
X
32/16
330000h to 337FFFh
198000h to 19BFFFh
SA110
0
1
1
0
0
1
1
1
X
X
X
32/16
338000h to 33FFFFh
19C000h to 19FFFFh
SA111
0
1
1
0
1
0
0
0
X
X
X
32/16
340000h to 347FFFh
1A0000h to 1A3FFFh
SA112
0
1
1
0
1
0
0
1
X
X
X
32/16
348000h to 34FFFFh
1A4000h to 1A7FFFh
SA113
0
1
1
0
1
0
1
0
X
X
X
32/16
350000h to 357FFFh
1A8000h to 1ABFFFh
SA114
0
1
1
0
1
0
1
1
X
X
X
32/16
358000h to 35FFFFh
1AC000h to 1AFFFFh
SA115
0
1
1
0
1
1
0
0
X
X
X
32/16
360000h to 367FFFh
1B0000h to 1B3FFFh
SA116
0
1
1
0
1
1
0
1
X
X
X
32/16
368000h to 36FFFFh
1B4000h to 1B7FFFh
(Continued)
18
MBM29XL12DF-70/80
(Continued)
Sector Address
Bank Sector
Bank
Address
A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11
Bank
B
Sector
Size
(KW /
KDW)
(× 16)
Address Range
(× 32)
Address Range
SA117
0
1
1
0
1
1
1
0
X
X
X
32/16
370000h to 377FFFh
1B8000h to 1BBFFFh
SA118
0
1
1
0
1
1
1
1
X
X
X
32/16
378000h to 37FFFFh
1BC000h to 1BFFFFh
SA119
0
1
1
1
0
0
0
0
X
X
X
32/16
380000h to 387FFFh
1C0000h to 1C3FFFh
SA120
0
1
1
1
0
0
0
1
X
X
X
32/16
388000h to 38FFFFh
1C4000h to 1C7FFFh
SA121
0
1
1
1
0
0
1
0
X
X
X
32/16
390000h to 397FFFh
1C8000h to 1CBFFFh
SA122
0
1
1
1
0
0
1
1
X
X
X
32/16
398000h to 39FFFFh
1CC000h to 1CFFFFh
SA123
0
1
1
1
0
1
0
0
X
X
X
32/16
3A0000h to 3A7FFFh
1D0000h to 1D3FFFh
SA124
0
1
1
1
0
1
0
1
X
X
X
32/16
3A8000h to 3AFFFFh
1D4000h to 1D7FFFh
SA125
0
1
1
1
0
1
1
0
X
X
X
32/16
3B0000h to 3B7FFFh
1D8000h to 1DBFFFh
SA126
0
1
1
1
0
1
1
1
X
X
X
32/16
3B8000h to 3BFFFFh
1DC000h to 1DFFFFh
SA127
0
1
1
1
1
0
0
0
X
X
X
32/16
3C0000h to 3C7FFFh
1E0000h to 1E3FFFh
SA128
0
1
1
1
1
0
0
1
X
X
X
32/16
3C8000h to 3CFFFFh
1E4000h to 1E7FFFh
SA129
0
1
1
1
1
0
1
0
X
X
X
32/16
3D0000h to 3D7FFFh
1E8000h to 1EBFFFh
SA130
0
1
1
1
1
0
1
1
X
X
X
32/16
3D8000h to 3DFFFFh
1EC000h to 1EFFFFh
SA131
0
1
1
1
1
1
0
0
X
X
X
32/16
3E0000h to 3E7FFFh
1F0000h to 1F3FFFh
SA132
0
1
1
1
1
1
0
1
X
X
X
32/16
3E8000h to 3EFFFFh
1F4000h to 1F7FFFh
SA133
0
1
1
1
1
1
1
0
X
X
X
32/16
3F0000h to 3F7FFFh
1F8000h to 1FBFFFh
SA134
0
1
1
1
1
1
1
1
X
X
X
32/16
3F8000h to 3FFFFFh
1FC000h to 1FFFFFh
19
MBM29XL12DF-70/80
Sector Address Tables (Bank C)
Sector Address
Bank Sector
Bank
Address
A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11
Bank
C
Sector
Size
(KW /
KDW)
(× 16)
Address Range
(× 32)
Address Range
SA135
1
0
0
0
0
0
0
0
X
X
X
32/16
400000h to 407FFFh
200000h to 203FFFh
SA136
1
0
0
0
0
0
0
1
X
X
X
32/16
408000h to 40FFFFh
204000h to 207FFFh
SA137
1
0
0
0
0
0
1
0
X
X
X
32/16
410000h to 417FFFh
208000h to 20BFFFh
SA138
1
0
0
0
0
0
1
1
X
X
X
32/16
418000h to 41FFFFh
20C000h to 20FFFFh
SA139
1
0
0
0
0
1
0
0
X
X
X
32/16
420000h to 427FFFh
210000h to 213FFFh
SA140
1
0
0
0
0
1
0
1
X
X
X
32/16
428000h to 42FFFFh
214000h to 217FFFh
SA141
1
0
0
0
0
1
1
0
X
X
X
32/16
430000h to 437FFFh
218000h to 21BFFFh
SA142
1
0
0
0
0
1
1
1
X
X
X
32/16
438000h to 43FFFFh
21C000h to 21FFFFh
SA143
1
0
0
0
1
0
0
0
X
X
X
32/16
440000h to 447FFFh
220000h to 223FFFh
SA144
1
0
0
0
1
0
0
1
X
X
X
32/16
448000h to 44FFFFh
224000h to 227FFFh
SA145
1
0
0
0
1
0
1
0
X
X
X
32/16
450000h to 457FFFh
228000h to 22BFFFh
SA146
1
0
0
0
1
0
1
1
X
X
X
32/16
458000h to 45FFFFh
22C000h to 22FFFFh
SA147
1
0
0
0
1
1
0
0
X
X
X
32/16
460000h to 467FFFh
230000h to 233FFFh
SA148
1
0
0
0
1
1
0
1
X
X
X
32/16
468000h to 46FFFFh
234000h to 237FFFh
SA149
1
0
0
0
1
1
1
0
X
X
X
32/16
470000h to 477FFFh
238000h to 23BFFFh
SA150
1
0
0
0
1
1
1
1
X
X
X
32/16
478000h to 47FFFFh
23C000h to 23FFFFh
SA151
1
0
0
1
0
0
0
0
X
X
X
32/16
480000h to 487FFFh
240000h to 243FFFh
SA152
1
0
0
1
0
0
0
1
X
X
X
32/16
488000h to 48FFFFh
244000h to 247FFFh
SA153
1
0
0
1
0
0
1
0
X
X
X
32/16
490000h to 497FFFh
248000h to 24BFFFh
SA154
1
0
0
1
0
0
1
1
X
X
X
32/16
498000h to 49FFFFh
24C000h to 24FFFFh
SA155
1
0
0
1
0
1
0
0
X
X
X
32/16
4A0000h to 4A7FFFh
250000h to 253FFFh
SA156
1
0
0
1
0
1
0
1
X
X
X
32/16
4A8000h to 4AFFFFh
254000h to 257FFFh
SA157
1
0
0
1
0
1
1
0
X
X
X
32/16
4B0000h to 4B7FFFh
258000h to 25BFFFh
SA158
1
0
0
1
0
1
1
1
X
X
X
32/16
4B8000h to 4BFFFFh
25C000h to 25FFFFh
SA159
1
0
0
1
1
0
0
0
X
X
X
32/16
4C0000h to 4C7FFFh
260000h to 263FFFh
SA160
1
0
0
1
1
0
0
1
X
X
X
32/16
4C8000h to 4CFFFFh
264000h to 267FFFh
SA161
1
0
0
1
1
0
1
0
X
X
X
32/16
4D0000h to 4D7FFFh
268000h to 26BFFFh
SA162
1
0
0
1
1
0
1
1
X
X
X
32/16
4D8000h to 4DFFFFh
26C000h to 26FFFFh
SA163
1
0
0
1
1
1
0
0
X
X
X
32/16
4E0000h to 4E7FFFh
270000h to 273FFFh
SA164
1
0
0
1
1
1
0
1
X
X
X
32/16
4E8000h to 4EFFFFh
274000h to 277FFFh
SA165
1
0
0
1
1
1
1
0
X
X
X
32/16
4F0000h to 4F7FFFh
278000h to 27BFFFh
SA166
1
0
0
1
1
1
1
1
X
X
X
32/16
4F8000h to 4FFFFFh
27C000h to 27FFFFh
SA167
1
0
1
0
0
0
0
0
X
X
X
32/16
500000h to 507FFFh
280000h to 283FFFh
SA168
1
0
1
0
0
0
0
1
X
X
X
32/16
508000h to 50FFFFh
284000h to 287FFFh
SA169
1
0
1
0
0
0
1
0
X
X
X
32/16
510000h to 517FFFh
288000h to 28BFFFh
SA170
1
0
1
0
0
0
1
1
X
X
X
32/16
518000h to 51FFFFh
28C000h to 28FFFFh
SA171
1
0
1
0
0
1
0
0
X
X
X
32/16
520000h to 527FFFh
290000h to 293FFFh
SA172
1
0
1
0
0
1
0
1
X
X
X
32/16
528000h to 52FFFFh
294000h to 297FFFh
SA173
1
0
1
0
0
1
1
0
X
X
X
32/16
530000h to 537FFFh
298000h to 29BFFFh
(Continued)
20
MBM29XL12DF-70/80
Sector Address
Bank Sector
Bank
Address
A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11
Bank
C
Sector
Size
(KW /
KDW)
(× 16)
Address Range
(× 32)
Address Range
SA174
1
0
1
0
0
1
1
1
X
X
X
32/16
538000h to 53FFFFh
29C000h to 29FFFFh
SA175
1
0
1
0
1
0
0
0
X
X
X
32/16
540000h to 547FFFh
2A0000h to 2A3FFFh
SA176
1
0
1
0
1
0
0
1
X
X
X
32/16
548000h to 54FFFFh
2A4000h to 2A7FFFh
SA177
1
0
1
0
1
0
1
0
X
X
X
32/16
550000h to 557FFFh
2A8000h to 2ABFFFh
SA178
1
0
1
0
1
0
1
1
X
X
X
32/16
558000h to 55FFFFh
2AC000h to 2AFFFFh
SA179
1
0
1
0
1
1
0
0
X
X
X
32/16
560000h to 567FFFh
2B0000h to 2B3FFFh
SA180
1
0
1
0
1
1
0
1
X
X
X
32/16
568000h to 56FFFFh
2B4000h to 2B7FFFh
SA181
1
0
1
0
1
1
1
0
X
X
X
32/16
570000h to 577FFFh
2B8000h to 2BBFFFh
SA182
1
0
1
0
1
1
1
1
X
X
X
32/16
578000h to 57FFFFh
2BC000h to 2BFFFFh
SA183
1
0
1
1
0
0
0
0
X
X
X
32/16
580000h to 587FFFh
2C0000h to 2C3FFFh
SA184
1
0
1
1
0
0
0
1
X
X
X
32/16
588000h to 58FFFFh
2C4000h to 2C7FFFh
SA185
1
0
1
1
0
0
1
0
X
X
X
32/16
590000h to 597FFFh
2C8000h to 2CBFFFh
SA186
1
0
1
1
0
0
1
1
X
X
X
32/16
598000h to 59FFFFh
2CC000h to 2CFFFFh
SA187
1
0
1
1
0
1
0
0
X
X
X
32/16
5A0000h to 5A7FFFh
2D0000h to 2D3FFFh
SA188
1
0
1
1
0
1
0
1
X
X
X
32/16
5A8000h to 5AFFFFh
2D4000h to 2D7FFFh
SA189
1
0
1
1
0
1
1
0
X
X
X
32/16
5B0000h to 5B7FFFh
2D8000h to 2DBFFFh
SA190
1
0
1
1
0
1
1
1
X
X
X
32/16
5B8000h to 5BFFFFh
2DC000h to 2DFFFFh
SA191
1
0
1
1
1
0
0
0
X
X
X
32/16
5C0000h to 5C7FFFh
2E0000h to 2E3FFFh
SA192
1
0
1
1
1
0
0
1
X
X
X
32/16
5C8000h to 5CFFFFh
2E4000h to 2E7FFFh
SA193
1
0
1
1
1
0
1
0
X
X
X
32/16
6D0000h to 5D7FFFh
2E8000h to 2EBFFFh
SA194
1
0
1
1
1
0
1
1
X
X
X
32/16
6D8000h to 5DFFFFh
2EC000h to 2EFFFFh
SA195
1
0
1
1
1
1
0
0
X
X
X
32/16
5E0000h to 5E7FFFh
2F0000h to 2F3FFFh
SA196
1
0
1
1
1
1
0
1
X
X
X
32/16
5E8000h to 5EFFFFh
2F4000h to 2F7FFFh
SA197
1
0
1
1
1
1
1
0
X
X
X
32/16
5F0000h to 5F7FFFh
2F8000h to 2FBFFFh
SA198
1
0
1
1
1
1
1
1
X
X
X
32/16
5F8000h to 5FFFFFh
2FC000h to 2FFFFFh
SA199
1
1
0
0
0
0
0
0
X
X
X
32/16
600000h to 607FFFh
300000h to 303FFFh
SA200
1
1
0
0
0
0
0
1
X
X
X
32/16
608000h to 60FFFFh
304000h to 307FFFh
SA201
1
1
0
0
0
0
1
0
X
X
X
32/16
610000h to 617FFFh
308000h to 30BFFFh
SA202
1
1
0
0
0
0
1
1
X
X
X
32/16
618000h to 61FFFFh
30C000h to 30FFFFh
SA203
1
1
0
0
0
1
0
0
X
X
X
32/16
620000h to 627FFFh
310000h to 313FFFh
SA204
1
1
0
0
0
1
0
1
X
X
X
32/16
628000h to 62FFFFh
314000h to 317FFFh
SA205
1
1
0
0
0
1
1
0
X
X
X
32/16
630000h to 637FFFh
318000h to 31BFFFh
SA206
1
1
0
0
0
1
1
1
X
X
X
32/16
638000h to 63FFFFh
31C000h to 31FFFFh
SA207
1
1
0
0
1
0
0
0
X
X
X
32/16
640000h to 647FFFh
320000h to 323FFFh
SA208
1
1
0
0
1
0
0
1
X
X
X
32/16
648000h to 64FFFFh
324000h to 327FFFh
SA209
1
1
0
0
1
0
1
0
X
X
X
32/16
650000h to 657FFFh
328000h to 32BFFFh
SA210
1
1
0
0
1
0
1
1
X
X
X
32/16
658000h to 65FFFFh
32C000h to 32FFFFh
SA211
1
1
0
0
1
1
0
0
X
X
X
32/16
660000h to 667FFFh
330000h to 333FFFh
SA212
1
1
0
0
1
1
0
1
X
X
X
32/16
668000h to 66FFFFh
334000h to 337FFFh
(Continued)
21
MBM29XL12DF-70/80
(Continued)
Sector Address
Bank Sector
Bank
Address
A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11
Bank
C
22
Sector
Size
(KW /
KDW)
(× 16)
Address Range
(× 32)
Address Range
SA213
1
1
0
0
1
1
1
0
X
X
X
32/16
670000h to 677FFFh
338000h to 33BFFFh
SA214
1
1
0
0
1
1
1
1
X
X
X
32/16
678000h to 67FFFFh
33C000h to 33FFFFh
SA215
1
1
0
1
0
0
0
0
X
X
X
32/16
680000h to 687FFFh
340000h to 343FFFh
SA216
1
1
0
1
0
0
0
1
X
X
X
32/16
688000h to 68FFFFh
344000h to 347FFFh
SA217
1
1
0
1
0
0
1
0
X
X
X
32/16
690000h to 697FFFh
348000h to 34BFFFh
SA218
1
1
0
1
0
0
1
1
X
X
X
32/16
698000h to 69FFFFh
34C000h to 34FFFFh
SA219
1
1
0
1
0
1
0
0
X
X
X
32/16
6A0000h to 6A7FFFh
350000h to 353FFFh
SA220
1
1
0
1
0
1
0
1
X
X
X
32/16
6A8000h to 6AFFFFh
354000h to 357FFFh
SA221
1
1
0
1
0
1
1
0
X
X
X
32/16
6B0000h to 6B7FFFh
358000h to 35BFFFh
SA222
1
1
0
1
0
1
1
1
X
X
X
32/16
8B8000h to 6BFFFFh
35C000h to 35FFFFh
SA223
1
1
0
1
1
0
0
0
X
X
X
32/16
6C0000h to 6C7FFFh
360000h to 363FFFh
SA224
1
1
0
1
1
0
0
1
X
X
X
32/16
6C8000h to 6CFFFFh
364000h to 367FFFh
SA225
1
1
0
1
1
0
1
0
X
X
X
32/16
6D0000h to 6D7FFFh
368000h to 36BFFFh
SA226
1
1
0
1
1
0
1
1
X
X
X
32/16
6D8000h to 6DFFFFh
36C000h to 36FFFFh
SA227
1
1
0
1
1
1
0
0
X
X
X
32/16
6E0000h to 6E7FFFh
370000h to 373FFFh
SA228
1
1
0
1
1
1
0
1
X
X
X
32/16
6E8000h to 6EFFFFh
374000h to 377FFFh
SA229
1
1
0
1
1
1
1
0
X
X
X
32/16
6F0000h to 6F7FFFh
378000h to 37BFFFh
SA230
1
1
0
1
1
1
1
1
X
X
X
32/16
6F8000h to 6FFFFFh
37C000h to 37FFFFh
MBM29XL12DF-70/80
Sector Address Tables (Bank D)
Sector Address
Bank Sector
Bank
Address
A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11
Bank
D
Sector
Size
(KW /
KDW)
(× 16)
Address Range
(× 32)
Address Range
SA231
1
1
1
0
0
0
0
0
X
X
X
32/16
700000h to 707FFFh
380000h to 383FFFh
SA232
1
1
1
0
0
0
0
1
X
X
X
32/16
708000h to 70FFFFh
384000h to 387FFFh
SA233
1
1
1
0
0
0
1
0
X
X
X
32/16
710000h to 717FFFh
388000h to 38BFFFh
SA234
1
1
1
0
0
0
1
1
X
X
X
32/16
718000h to 71FFFFh
38C000h to 38FFFFh
SA235
1
1
1
0
0
1
0
0
X
X
X
32/16
720000h to 727FFFh
390000h to 393FFFh
SA236
1
1
1
0
0
1
0
1
X
X
X
32/16
728000h to 72FFFFh
394000h to 397FFFh
SA237
1
1
1
0
0
1
1
0
X
X
X
32/16
730000h to 737FFFh
398000h to 39BFFFh
SA238
1
1
1
0
0
1
1
1
X
X
X
32/16
738000h to 73FFFFh
39C000h to 39FFFFh
SA239
1
1
1
0
1
0
0
0
X
X
X
32/16
740000h to 747FFFh
3A0000h to 3A3FFFh
SA240
1
1
1
0
1
0
0
1
X
X
X
32/16
748000h to 74FFFFh
3A4000h to 3A7FFFh
SA241
1
1
1
0
1
0
1
0
X
X
X
32/16
750000h to 757FFFh
3A8000h to 3ABFFFh
SA242
1
1
1
0
1
0
1
1
X
X
X
32/16
758000h to 75FFFFh
3AC000h to 3AFFFFh
SA243
1
1
1
0
1
1
0
0
X
X
X
32/16
760000h to 767FFFh
3B0000h to 3B3FFFh
SA244
1
1
1
0
1
1
0
1
X
X
X
32/16
768000h to 76FFFFh
3B4000h to 3B7FFFh
SA245
1
1
1
0
1
1
1
0
X
X
X
32/16
770000h to 777FFFh
3B8000h to 3BBFFFh
SA246
1
1
1
0
1
1
1
1
X
X
X
32/16
778000h to 77FFFFh
3BC000h to 3BFFFFh
SA247
1
1
1
1
0
0
0
0
X
X
X
32/16
780000h to 787FFFh
3C0000h to 3C3FFFh
SA248
1
1
1
1
0
0
0
1
X
X
X
32/16
788000h to 78FFFFh
3C4000h to 3C7FFFh
SA249
1
1
1
1
0
0
1
0
X
X
X
32/16
790000h to 797FFFh
3C8000h to 3CBFFFh
SA250
1
1
1
1
0
0
1
1
X
X
X
32/16
798000h to 79FFFFh
3CC000h to 3CFFFFh
SA251
1
1
1
1
0
1
0
0
X
X
X
32/16
7A0000h to 7A7FFFh
3D0000h to 3D3FFFh
SA252
1
1
1
1
0
1
0
1
X
X
X
32/16
7A8000h to 7AFFFFh
3D4000h to 3D7FFFh
SA253
1
1
1
1
0
1
1
0
X
X
X
32/16
7B0000h to 7B7FFFh
3D8000h to 3DBFFFh
SA254
1
1
1
1
0
1
1
1
X
X
X
32/16
7B8000h to 7BFFFFh
3DC000h to 3DFFFFh
SA255
1
1
1
1
1
0
0
0
X
X
X
32/16
7C0000h to 7C7FFFh
3E0000h to 3E3FFFh
SA256
1
1
1
1
1
0
0
1
X
X
X
32/16
7C8000h to 7CFFFFh
3E4000h to 3E7FFFh
SA257
1
1
1
1
1
0
1
0
X
X
X
32/16
7D0000h to 7D7FFFh
3E8000h to 3EBFFFh
SA258
1
1
1
1
1
0
1
1
X
X
X
32/16
7D8000h to 7DFFFFh
3EC000h to 3EFFFFh
SA259
1
1
1
1
1
1
0
0
X
X
X
32/16
7E0000h to 7E7FFFh
3F0000h to 3F3FFFh
SA260
1
1
1
1
1
1
0
1
X
X
X
32/16
7E8000h to 7EFFFFh
3F4000h to 3F7FFFh
SA261
1
1
1
1
1
1
1
0
X
X
X
32/16
7F0000h to 7F7FFFh
3F8000h to 3FBFFFh
SA262
1
1
1
1
1
1
1
1
0
0
0
4/2
7F8000h to 7F8FFFh
3FC000h to 3FC7FFh
SA263
1
1
1
1
1
1
1
1
0
0
1
4/2
7F9000h to 7F9FFFh
3FC800h to 3FCFFFh
SA264
1
1
1
1
1
1
1
1
0
1
0
4/2
7FA000h to 7FAFFFh
3FD000h to 3FD7FFh
SA265
1
1
1
1
1
1
1
1
0
1
1
4/2
7FB000h to 7FBFFFh
3FD800h to 3FDFFFh
SA266
1
1
1
1
1
1
1
1
1
0
0
4/2
7FC000h to 7FCFFFh
3FE000h to 3FE7FFh
SA267
1
1
1
1
1
1
1
1
1
0
1
4/2
7FD000h to 7FDFFFh
3FE800h to 3FEFFFh
SA268
1
1
1
1
1
1
1
1
1
1
0
4/2
7FE000h to 7FEFFFh
3FF000h to 3FF7FFh
SA269
1
1
1
1
1
1
1
1
1
1
1
4/2
7FF000h to 7FFFFFh
3FF800h to 3FFFFFh
23
MBM29XL12DF-70/80
Sector Group Address Table
Sector Group
A21
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
Sectors
SGA0
0
0
0
0
0
0
0
0
0
0
0
SA0
SGA1
0
0
0
0
0
0
0
0
0
0
1
SA1
SGA2
0
0
0
0
0
0
0
0
0
1
0
SA2
SGA3
0
0
0
0
0
0
0
0
0
1
1
SA3
SGA4
0
0
0
0
0
0
0
0
1
0
0
SA4
SGA5
0
0
0
0
0
0
0
0
1
0
1
SA5
SGA6
0
0
0
0
0
0
0
0
1
1
0
SA6
SGA7
0
0
0
0
0
0
0
0
1
1
1
SA7
0
1
1
0
X
X
X
SA8 to SA10
1
1
SGA8
0
0
0
0
0
0
SGA9
0
0
0
0
0
1
X
X
X
X
X
SA11 to SA14
SGA10
0
0
0
0
1
0
X
X
X
X
X
SA15 to SA18
SGA11
0
0
0
0
1
1
X
X
X
X
X
SA19 to SA22
SGA12
0
0
0
1
0
0
X
X
X
X
X
SA23 to SA26
SGA13
0
0
0
1
0
1
X
X
X
X
X
SA27 to SA30
SGA14
0
0
0
1
1
0
X
X
X
X
X
SA31 to SA34
SGA15
0
0
0
1
1
1
X
X
X
X
X
SA35 to SA38
SGA16
0
0
1
0
0
0
X
X
X
X
X
SA39 to SA42
SGA17
0
0
1
0
0
1
X
X
X
X
X
SA43 to SA46
SGA18
0
0
1
0
1
0
X
X
X
X
X
SA47 to SA50
SGA19
0
0
1
0
1
1
X
X
X
X
X
SA51 to SA54
SGA20
0
0
1
1
0
0
X
X
X
X
X
SA55 to SA58
SGA21
0
0
1
1
0
1
X
X
X
X
X
SA59 to SA62
SGA22
0
0
1
1
1
0
X
X
X
X
X
SA63 to SA66
SGA23
0
0
1
1
1
1
X
X
X
X
X
SA67 to SA70
SGA24
0
1
0
0
0
0
X
X
X
X
X
SA71 to SA74
SGA25
0
1
0
0
0
1
X
X
X
X
X
SA75 to SA78
SGA26
0
1
0
0
1
0
X
X
X
X
X
SA79 to SA82
SGA27
0
1
0
0
1
1
X
X
X
X
X
SA83 to SA86
SGA28
0
1
0
1
0
0
X
X
X
X
X
SA87 to SA90
SGA29
0
1
0
1
0
1
X
X
X
X
X
SA91 to SA94
SGA30
0
1
0
1
1
0
X
X
X
X
X
SA95 to SA98
SGA31
0
1
0
1
1
1
X
X
X
X
X
SA99 to SA102
SGA32
0
1
1
0
0
0
X
X
X
X
X
SA103 to SA106
(Continued)
24
MBM29XL12DF-70/80
Sector Group
A21
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
Sectors
SGA33
0
1
1
0
0
1
X
X
X
X
X
SA107 to SA110
SGA34
0
1
1
0
1
0
X
X
X
X
X
SA111 to SA114
SGA35
0
1
1
0
1
1
X
X
X
X
X
SA115 to SA118
SGA36
0
1
1
1
0
0
X
X
X
X
X
SA119 to SA122
SGA37
0
1
1
1
0
1
X
X
X
X
X
SA123 to SA126
SGA38
0
1
1
1
1
0
X
X
X
X
X
SA127 to SA130
SGA39
0
1
1
1
1
1
X
X
X
X
X
SA131 to SA134
SGA40
1
0
0
0
0
0
X
X
X
X
X
SA135 to SA138
SGA41
1
0
0
0
0
1
X
X
X
X
X
SA139 to SA142
SGA42
1
0
0
0
1
0
X
X
X
X
X
SA143 to SA146
SGA43
1
0
0
0
1
1
X
X
X
X
X
SA147 to SA150
SGA44
1
0
0
1
0
0
X
X
X
X
X
SA151 to SA154
SGA45
1
0
0
1
0
1
X
X
X
X
X
SA155 to SA158
SGA46
1
0
0
1
1
0
X
X
X
X
X
SA159 to SA162
SGA47
1
0
0
1
1
1
X
X
X
X
X
SA163 to SA166
SGA48
1
0
1
0
0
0
X
X
X
X
X
SA167 to SA170
SGA49
1
0
1
0
0
1
X
X
X
X
X
SA171 to SA174
SGA50
1
0
1
0
1
0
X
X
X
X
X
SA175 to SA178
SGA51
1
0
1
0
1
1
X
X
X
X
X
SA179 to SA182
SGA52
1
0
1
1
0
0
X
X
X
X
X
SA183 to SA186
SGA53
1
0
1
1
0
1
X
X
X
X
X
SA187 to SA190
SGA54
1
0
1
1
1
0
X
X
X
X
X
SA191 to SA194
SGA55
1
0
1
1
1
1
X
X
X
X
X
SA195 to SA198
SGA56
1
1
0
0
0
0
X
X
X
X
X
SA199 to SA202
SGA57
1
1
0
0
0
1
X
X
X
X
X
SA203 to SA206
SGA58
1
1
0
0
1
0
X
X
X
X
X
SA207 to SA210
SGA59
1
1
0
0
1
1
X
X
X
X
X
SA211 to SA214
SGA60
1
1
0
1
0
0
X
X
X
X
X
SA215 to SA218
SGA61
1
1
0
1
0
1
X
X
X
X
X
SA219 to SA222
SGA62
1
1
0
1
1
0
X
X
X
X
X
SA223 to SA226
SGA63
1
1
0
1
1
1
X
X
X
X
X
SA227 to SA230
SGA64
1
1
1
0
0
0
X
X
X
X
X
SA231 to SA234
SGA65
1
1
1
0
0
1
X
X
X
X
X
SA235 to SA238
SGA66
1
1
1
0
1
0
X
X
X
X
X
SA239 to SA242
SGA67
1
1
1
0
1
1
X
X
X
X
X
SA243 to SA246
(Continued)
25
MBM29XL12DF-70/80
(Continued)
Sector Group
A21
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
Sectors
SGA68
1
1
1
1
0
0
X
X
X
X
X
SA247 to SA250
SGA69
1
1
1
1
0
1
X
X
X
X
X
SA251 to SA254
SGA70
1
1
1
1
1
0
X
X
X
X
X
SA255 to SA258
0
0
0
1
X
X
X
SA259 to SA261
1
0
SGA71
26
1
1
1
1
1
1
SGA72
1
1
1
1
1
1
1
1
0
0
0
SA262
SGA73
1
1
1
1
1
1
1
1
0
0
1
SA263
SGA74
1
1
1
1
1
1
1
1
0
1
0
SA264
SGA75
1
1
1
1
1
1
1
1
0
1
1
SA265
SGA76
1
1
1
1
1
1
1
1
1
0
0
SA266
SGA77
1
1
1
1
1
1
1
1
1
0
1
SA267
SGA78
1
1
1
1
1
1
1
1
1
1
0
SA268
SGA79
1
1
1
1
1
1
1
1
1
1
1
SA269
MBM29XL12DF-70/80
Common Flash Memory Interface Code
Description
A6 to A0
DQ15 to DQ0
Query-unique ASCII string “QRY”
10h
11h
12h
0051h
0052h
0059h
Primary OEM Command Set
02h: AMD/FJ standard type
13h
14h
0002h
0000h
Address for Primary Extended Table
15h
16h
0040h
0000h
Alternate OEM Command Set (00h = not applicable)
17h
18h
0000h
0000h
Address for Alternate OEM Extended Table
19h
1Ah
0000h
0000h
VCC Min (write/erase)DQ7 to DQ4=1V, DQ3 to DQ0=100 mV
1Bh
0027h
VCC Max (write/erase)DQ7 to DQ4=1V, DQ3 to DQ0=100 mV
1Ch
0036h
VPP Min voltage
1Dh
0000h
1Eh
0000h
Typical timeout per single byte/word write 2 µs
1Fh
0004h
Typical timeout for Min size buffer write 2 µs
20h
0000h
N
21h
000Ah
Typical timeout for full chip erase 2 ms
22h
0000h
Max timeout for byte/word write 2 times typical µs
23h
0005h
Max timeout for buffer write 2 times typical µs
24h
0000h
25h
0004h
26h
0000h
Device Size = 2 byte
27h
0018h
Flash Device Interface description
05h: ×16 / ×32
28h
29h
0005h
0000h
Max number of byte in multi-byte write = 2N
2Ah
2Bh
0000h
0000h
Number of Erase Block Regions within device
2Ch
0003h
Erase Block Region 1 Information
bit 15 to 0: y = number of sectors
bit 31 to 16: z = size
(z × 256 bytes)
2Dh
2Eh
2Fh
30h
0007h
0000h
0020h
0000h
Erase Block Region 2 Information
bit 15 to 0: y = number of sectors
bit 31 to 16: z = size
(z × 256 bytes)
31h
32h
33h
34h
00FDh
0000h
0000h
0001h
Erase Block Region 3 Information
bit 15 to 0: y = number of sectors
bit 31 to 16: z = size
(z × 256 bytes)
35h
36h
37h
38h
0007h
0000h
0020h
0000h
VPP Max voltage
N
N
Typical timeout per individual sector erase 2 ms
N
N
N
N
Max timeout per individual sector erase 2 times typical ms
N
Max timeout for full chip erase 2 times typical ms
N
(Continued)
27
MBM29XL12DF-70/80
(Continued)
Description
28
A6 to A0
DQ15 to DQ0
Erase Block Region 4 Information
bit 15 to 0: y = number of sectors
bit 31 to 16: z = size
(z × 256 bytes)
39h
3Ah
3Bh
3Ch
0000h
0000h
0000h
0000h
Query-unique ASCII string “PRI”
40h
41h
42h
0050h
0052h
0049h
Major version number, ASCII
43h
0031h
Minor version number, ASCII
44h
0033h
Address Sensitive Unlock
04h = Required and 0.17µm technology
45h
0004h
Erase Suspend
02h = To Read & Write
46h
0002h
Sector Protection
00h = Not Supported
X = Number of sectors in per group
47h
0001h
Sector Temporary Unprotection
01h = Supported
48h
0001h
Sector Protection Algorithm
49h
0007h
Dual Operation
00h = Not Supported,
X = Total number of sectors in all Banks except Bank A
4Ah
00E7h
Burst Mode Type
00h = Not Supported
4Bh
0000h
Page Mode Type
02h = 8 Word Page
4Ch
0002h
VACC (Acceleration) Supply Minimum
DQ7 to DQ4=1V, DQ3 to DQ0=100 mV
4Dh
00B5h
VACC (Acceleration) Supply Maximum
DQ7 to DQ4=1V, DQ3 to DQ0=100 mV
4Eh
00C5h
Boot Type
4Fh
0001h
Program Suspend,
01h = Supported
50h
0001h
Bank Organization
X = Number of Banks
57h
0004h
Bank A Region Information X = Number of sectors in Bank A
58h
0027h
Bank B Region Information X = Number of sectors in Bank B
59h
0060h
Bank C Region Information X = Number of sectors in Bank C
5Ah
0060h
Bank D Region Information X = Number of sectors in Bank D
5Bh
0027h
MBM29XL12DF-70/80
■ FUNCTIONAL DESCRIPTION
Simultaneous Operation
The device features functions that enable data reading from one memory bank while a program or erase operation
is in progress in the other memory bank (simultaneous operation) , in addition to conventional features (read,
program, erase, erase-suspend read, and erase-suspend program) . The bank is selected by bank address
( A21, A20, A19 ) with zero latency. The device consists of the following four banks :
Bank A : 8 × 4KW and 31× 32KW; Bank B : 96 × 32 KW; Bank C : 96 ×32KW; Bank D : 8 × 4KW and 31 × 32KW.
The device can execute simultaneous operations between Bank 1, a bank chosen from among the four banks,
and Bank 2, a bank consisting of the three remaining banks. See “FlexBankTM Architecture” below. This is what
we call “FlexBank”, for example the rest of banks B, C and D to let the system read while Bank A is in the process
of program (or erase) operation. However the different types of operations for the three banks are not allowed,
e.g. Bank A programming, Bank B erasing, and Bank C reading out. With this “FlexBank”, as described in
“Example of Virtual Banks Combination”, the system gets to select from four combinations of data volume for
Bank 1 and Bank 2, which works well to meet the system requirement. The simultaneous operation cannot
execute multi-function mode in the same bank. Refer to “Bank-to-Bank Read/Write(Program and Erase) Timing
Diagram”.
FlexBankTM Architecture
Bank 1
Bank 2
Bank
Splits
Bank Size
Combination
Bank Size
Combination
1
16 Mbit
Bank A
112 Mbit
Bank B, C, D
2
48 Mbit
Bank B
80 Mbit
Bank A, C, D
3
48 Mbit
Bank C
80 Mbit
Bank A, B, D
4
16 Mbit
Bank D
112 Mbit
Bank A, B, C
Example of Virtual Banks Combination
Bank
Splits
Bank 1
Bank
Size
Combination of
Memory Bank
Bank 2
Sector Sizes
Bank
Size
Combination of
Memory Bank
Sector Sizes
8 × 4K words,
223 × 32K words
1
16 Mbit
Bank A
8 × 4K words,
31 × 32K words
112 Mbit
Bank B
+
Bank C
+
Bank D
2
32 Mbit
Bank A
+
Bank D
16 × 4K words,
62 × 32K words
96 Mbit
Bank B
+
Bank C
192 × 32K words
16 × 4K words,
158 × 32K words
8 × 4K words,
127 × 32Kwords
3
48 Mbit
Bank B
96 × 32K words
80 Mbit
Bank A
+
Bank C
+
Bank D
4
64 Mbit
Bank A
+
Bank B
8 × 4K words,
127 × 32Kwords
64 Mbit
Bank C
+
Bank D
Note : When multiple sector erase over several banks is operated, the system cannot read out of the bank to which
a sector being erased belongs. For example, suppose that erasing is taking place at both Bank A and Bank B,
neither Bank A nor Bank B is read out they output the sequence flag once they are selected.
Meanwhile the system would get to read from either Bank C or Bank D.
29
MBM29XL12DF-70/80
Simultaneous Operation
Case
Bank 1 Status
Bank 2 Status
1
Read mode
Read mode
2
Read mode
Autoselect mode
3
Read mode
Program mode
4
Read mode
Erase mode
5
Autoselect mode
Read mode
6
Program mode
Read mode
7
Erase mode
Read mode
Note : Bank 1 and Bank 2 are divided for the sake of convenience at Simultaneous Operation. The Bank consists
of 4 banks, Bank A, Bank B, BankC and Bank D. Bank Address (BA) means to specify each of the Banks.
Read Mode
The device has two control functions required to obtain data at the outputs. CE is the power control and used
for a device selection. OE is the output control and used to gate data to the output pins if a device is selected.
Address access time (tACC) is equal to the delay from stable addresses to valid output data. The chip enable
access time (tCE) is the delay from stable addresses and stable CE to valid data at the output pins. The output
enable access time is the delay from the falling edge of OE to valid data at the output pins. Assuming the
addresses have been stable for at least tACC - tOE time. When reading out a data without changing addresses
after power-up, input hardware reset or to change CE pin from “H” or “L”.
Page Mode Read
The device is capable of fast Page mode read and are compatible with the Page mode Mask ROM read operation.
This mode provides faster read access speed for random locations within a page. The Page size of the device
is 8 words or 4 double words, within the appropriate Page being selected by the higher address bits A21 to A2
and the LSB bits A1 to A0 (in the double word mode) and A1 to A-1(in the word mode) determining the specific
double word or word within that page. This is an asynchronous operation with the microprocessor supplying the
specific double word or word location.
The random or initial page access is equal to tACC and subsequent Page read access (as long as the locations
specified by the microprocessor fall within that Page) is equivalent to tPACC. Here again, CE selects the device
and OE is the output control and used to gate data to the output pins if the device is selected. Fast Page mode
accesses are obtained by keeping A21 to A2 constant and changing A1 to A0 to select the specific double word
or changing A1 to A-1 to select the specific word, within that page.
Standby Mode
There are two ways to implement the standby mode on the device, one using both the CE and RESET pins, and
the other via the RESET pin only.
When using both pins, CMOS standby mode is achieved with CE and RESET input held at VCC±0.3 V. Under
this condition the current consumed is less than 5 µA Max. During Embedded Algorithm operation, VCC active
current (ICC2) is required even when CE=“H”. The device can be read with standard access time (tCE) from either
of these standby modes.
When using the RESET pin only, CMOS standby mode is achieved with RESET input held at VSS±0.3 V (CE=“H”
or “L”) . Under this condition the current consumed is less than 5 µA Max. Once the RESET pin is set high, the
device requires tRH as a wake-up time for output to be valid for read access.
During standby mode, the output is in the high impedance state regardless of OE input.
30
MBM29XL12DF-70/80
Automatic Sleep Mode
Automatic sleep mode works to restrain power consumption during read-out of the device data. This is useful
in the application such as a handy terminal which requires low power consumption.
To activate this mode, the device automatically switches itself to low power mode when addresses remain stable
during access time of 150 ns. It is not necessary to control CE, WE, and OE on this mode. The current consumed
is typically 1 µA (CMOS Level).
During simultaneous operation, VCC active current (ICC2) is required.
Since the data are latched during this mode, the data are continuously read out. When the addresses are
changed, the mode is automatically canceled and the device reads the data for changed addresses.
Output Disable
With the OE input is at logic high level (VIH), output from the device is disabled. This causes the output pins to
be in a high impedance state.
Autoselect
Autoselect mode allows reading out of a binary code and identifies its manufacturer and type.It is intended for
use by programming equipment for the purpose of automatically matching the device to be programmed with
its corresponding programming algorithm. This mode is functional over the entire temperature range of the device.
To activate this mode, the programming equipment must force VID on address pin A9. Three identifier bytes may
then be sequenced from the device outputs by toggling addresses. All addresses are DON’T CARES except A6
to A0.
The manufacturer and device codes may also be read via the command register, for instances when the device
is erased or programmed in a system without access to high voltage on the A9 pin. The command sequence is
illustrated in “Command Definitions Table” of ■DEVICE BUS OPERATIONS.
In the command Autoselect mode, the bank addresses BA (A21, A20, A19) must point to a specific bank during
the third write bus cycle of the Autoselect command. Then the Autoselect data are read from that bank while
array data can be read from the other bank.
A read cycle from address 00h returns the manufacturer’s code (Fujitsu=04h) . A read cycle from address 01h
(at word mode, 02h) outputs device code. When 2222227Eh (at word mode, 227Eh) is output, it indicates that
two additional codes, called Extended Device Codes is required. Therefore the system may continue reading
out these Extended Device Codes at addresses of 0Eh (at word mode, 1Ch) and 0Fh (at word mode, 1Eh).
Refer to “Autoselect Codes Table” and “Extended Autoselect Code Table” in ■DEVICE BUS OPERATION.
In the case of applying VID on A9, because both Bank 1 and Bank 2 enter Autoselect mode, simultanous operation
cannot be executed.
Write
Device erase and programming are accomplished via the command register. The contents of the register serve
as input to the internal state machine. The state machine output dictates the device function.
The command register itself does not occupy any addressable memory location. The register is a latch used to
store the commands, along with the address and data information needed to execute the command. The command register is written by bringing WE to VIL, while CE is at VIL and OE is at VIH. Addresses are latched on the
falling edge of WE or CE, whichever starts later, while data is latched on the rising edge of WE or CE, whichever
starts first. Standard microprocessor write timings are used.
Refer to AC Write Characteristics and the Erase/Programming Waveforms for specific timing parameters.
31
MBM29XL12DF-70/80
Double Word/Word Configuration
DW/W pin selects double word (32-bit) mode or word (16-bit) mode for the device. When this pin is driven high,
device operates in the double word (32-bit) mode. Data is read and programmed at DQ31 to DQ0. When this pin
is driven low, device operates in word (16-bit) mode. Under this mode, DQ31/A-1 pin becomes the lowest address
bit, and DQ30 to DQ16 bits are tri-stated. However, the command bus cycle is always an 16-bit operation and
hence commands are written at DQ15 to DQ0 and DQ31 to DQ16 bits are ignored. Refer to “Double Word Mode
Configuration Timing Diagram”,“Word Mode Configuration Timing Diagram” and “DW/W Diagram for Write Operations” in “■TIMING DIAGRAM”.
Accelerated Program Operation
The device offers accelerated program operation which enables the programming in high speed. If the system
asserts VACC to the ACC pin, the device automatically enters the acceleration mode and the time required for
program operation will reduce to about 60%. This function is primarily intended to allow high speed program,
so caution is needed as the sector group becomes temporarily unprotected.
The system uses fast program command sequence when programming during acceleration mode. Set command
to fast mode and reset command from fast mode are not necessary. When the device enters the acceleration
mode, the device automatically set to fast mode. Therefore the present sequence is used for programming and
detection of completion during acceleration mode.
Removing VACC from the ACC pin and applying VIL or VIH returns the device to normal operation. Do not remove
VACC from ACC pin while programming. See “Accelerated Program Timing Diagram”.
RESET
Hardware Reset
The device may be reset by driving the RESET pin to VIL. The RESET pin has a pulse requirement and has to
be kept low (VIL) for at least “tRP” in order to properly reset the internal state machine. Any operation in the process
of being executed is terminated and the internal state machine is reset to the read mode “tREADY” after the RESET
pin is driven low. Furthermore once the RESET pin goes high the device requires an additional “tRH” before it
allows read access. When the RESET pin is low, the device is in the standby mode for the duration of the pulse
and all the data output pins are tri-stated. If a hardware reset occurs during a program or erase operation, the
data at that particular location are corrupted. Please note that the RY/BY output signal should be ignored during
the RESET pulse. See “RESET, RY/BY Timing Diagram”.
HiddenROM Region
Unlike previous flash memory devices, the MBM29XL12DF allows simultaneous operation while the HiddenROM
is enabled. However, there are a number of restrictions associated with simultaneous operation and device
operation when the HiddenROM is enabled:
(1) The HiddenROM is not available for reading while the Password Unlock, any PPB program/erase operation,
or Password programming are in progress. Reading to any location in the Bank A will return the status of
these operations until these operations have completed execution.
(2) Writing the corresponding Sector Protect latch associated with the overlaid bootblock sector results in the
Sector Protect latch NOT being updated. This is only accomplished when the HiddenROM is not enabled.
(3) Reading the corresponding DPB associated with the overlaid bootblock sector results in reading invalid data
when the PPB Lock/DPB Verify command is issued. This function is only accomplished when
the HiddenROM is not enabled.
(4) All commands are available for execution when the HiddenROM is enabled except the following list. Issuing
the following commands while the HiddenROM is enabled results in the command being ignored.
— CFI
— Set to Fast Mode
— Fast Program
— Reset from Fast Mode
— Program and Sector Erase Suspend
— Program and Sector Erase Resume
32
MBM29XL12DF-70/80
(5) Executing the Sector Erase command is permitted when the HiddenROM is enabled, however, there is no
provision for erasing the HiddenROM with the Sector Erase command, regardless of the protection status.
The Sector Erase command will erase all other sectors when the HiddenROM is enabled. Erasing the
HiddenROM with the Embedded Algorithm is accomplished by issuing the Chip Erase command. If the
HiddenROM is the only sector requiring erasure, set the Sector Protect latches for the remaining sectors
prior to issuing the Chip Erase command.
(6) Executing the HiddenROM Entry command during program or erase suspend mode is allowed. Since the
Sector Erase/Program Resume command is disabled while the HiddenROM is enabled, the user cannot
resume programming or erase of the HiddenROM in place of the overlaid boot block sector.
HiddenROM Protection Bit
The HiddenROM Protection Bit prevents programming of the HiddenROM memory area. Once set, the HiddenROM memory area contents are non-modifiable.
33
MBM29XL12DF-70/80
<Protection>
The MBM29XL12DF features several levels of sector protection, which can disable both the program and erase
operations in certain sectors or sector groups:
(1) Write Protect (WP)[Hardware Protection]
The device features a hardware protection option using a write protect pin that prevents programming or erasing,
regardless of the state of the sector’s Persistent or Dynamic Protection Bits. The WP pin is associated with the
“outermost” 2 × 4K words on both ends of boot sectors. The WP pin has no effect on any other sector. When
WP is taken to VIL, program and erase operations of the “outermost” 2 × 4K words sectors on both end are
disabled. By taking WP back to VIH, the “outermost” 2 × 4K words sectors are enabled for program and erase
operations, depending upon the status of the individual sector Persistent or Dynamic Protection Bits. If either of
the two outermost sectors Persistent or Dynamic Protection Bits are programmed, program or erase operations
are inhibited. If the sector Persistent or Dynamic Protection Bits are both erased, the two sectors are available
for programming or erasing as long as WP remains at VIH. The user must hold the WP pin at either VIH or VIL
during the entire program or erase operation of the “outermost” two sectors on both end of boot sectors.
(2)Sector Group Protection [Software Protection]
The device features hardware sector group protection. This feature disables both program and erase operations
in any number of sector groups. The sector group protection feature is enabled using programming equipment
at the user’s site. The device is shipped with all sector groups unprotected.
To activate this mode, the programming equipment must force VID on address pin A9 and control pin OE, CE =
VIL, (A6, A5, A4, A3, A2, A1,A0) = (0, 1, 1, 1, 0, 1, 0). The sector addresses pins (A21, A20, A19, A18, A17, A16, A15, A14,
A13, A12, and A11) should be set to the sector group to be protected. Programming of the protection circuitry
begins on the falling edge of the WE pulse and is terminated with the rising edge of the same. Sector addresses
must be held constant during the WE pulse. See Sector Group Protection waveforms and algorithms.
To verify programming of the protection circuitry, the programming equipment must force VID on address pin A9
with CE and OE at VIL and WE at VIH. Scanning the sector addresses (A21, A20, A19, A18, A17, A16, A15, A14, A13,
A12, and A11) while (A6, A5, A4, A3, A2, A1,A0) = (0, 1, 1, 1, 0, 1, 0) produces logic “1” at device output DQ0 for a
protected sector. Otherwise the device produces logic "0" for an unprotected sector group. A-1 = VIL is required
in word mode.
It is also possible to determine if a sector group is protected in the system by writing an Autoselect command.
Performing a read operation at the address location XX02h, where the higher order addresses pins (A21, A20,
A19, A18, A17, A16, A15, A14, A13, A12, and A11) represents the sector group address will produce a logical “1” at DQ0
for a protected sector. See "User Bus Operations" for Autoselect codes.
(3) Extended Sector Group Protection [Software Protection]
In addition to normal sector group protection, the device has Extended Sector Group Protection as extended
function. This function enables protection of the sector group by forcing VID on RESET pin and writes a command
sequence. Unlike conventional procedures, it is not necessary to force VID and control timing for control pins.
The only RESET pin requires VID for sector group protection in this mode. The extended sector group protection
requires VID on RESET pin. With this condition, the operation is initiated by writing the set-up command (60h)
in the command register. Then the sector group addresses pins (A21, A20, A19, A18, A17, A16, A15, A14, A13, A12, and
A11) and (A6, A5, A4, A3, A2, A1, A0) = (0, 1, 1, 1, 0, 1, 0) should be set to the sector group to be protected (setting
VIL for the other addresses pins is recommended) , and an extended sector group protection command (60h)
should be written. A sector group is typically protected in 250 µs. To verify programming of the protection circuitry,
the sector group addresses pins (A21, A20, A19, A18, A17, A16, A15, A14, A13, A12, and A11) and (A6, A5, A4, A3, A2, A1,
A0) = (0, 1, 1, 1, 0, 1, 0) should be set a command (40h) should be written. Following the command write, logic
“1” at device output DQ0 produces a protected sector in the read operation. If the output is logic “0”, write the
extended sector group protection command (60h) again. To terminate the operation, it is necessary to set RESET
pin to VIH. Refer to. Extended Sector Group Protection waveforms and algorithm.
34
MBM29XL12DF-70/80
(4) New Sector Protection [Software Protection]
A command sector protection method that replaces the old VID controlled protection method in future. However
MBM29XL12DF supports both VID protection and Persistent Sector Protection. Both Protect supported as a shift
period.
The Persistent Sector Protection and the old VID controlled protection can go back each other until Persistent
Protection Lock Bit is settled.
a) Persistent Protection Bit (PPB)
A single Persistent (non-volatile) Protection Bit is assigned to a maximum four sectors (see the sector address
tables for specific sector protection groupings). All 4 K words boot-block sectors have individual sector Persistent
Protection Bits (PPBs) for greater flexibility. Each PPB is individually modifiable through the PPB Write Command.
Note: If a PPB requires erasure, all of the sector PPBs must first be preprogrammed prior to PPB erasing. All
PPBs erase in parallel, unlike programming where individual PPBs are programmable. It is the responsibility of
the user to perform the preprogramming operation. Otherwise, an already erased sector PPBs has the potential
of being over-erased. There is no hardware mechanism to prevent sector PPBs over-erasure.
b) Dynamic Protection Bit (DPB)
A volatile protection bit is assigned for each sector. After power-up or hardware reset, the contents of all DPBs
is “0”. Each DPB is individually modifiable through the DPB Write Command.
When the parts are first shipped, the PPBs are cleared, the DPBs are cleared, and PPB Lock is defaulted to
power up in the cleared state - meaning the PPBs are changeable.
When the device is first powered on the DPBs power up cleared (sectors not protected). The Protection State
for each sector is determined by the logical OR of the PPB and the DPB related to that sector. For the sectors
that have the PPBs cleared, the DPBs control whether or not the sector is protected or unprotected. By issuing
the DPB Write/Erase command sequences, the DPBs will be set or cleared, thus placing each sector in the
protected or unprotected state. These are the so-called Dynamic Locked or Unlocked states. They are called
dynamic states because it is very easy to switch back and forth between the protected and unprotected conditions.
This allows software to easily protect sectors against inadvertent changes yet does not prevent the easy removal
of protection when changes are needed. The DPBs maybe set or cleared as often as needed.
PPB vs DPB
The PPBs allow for a more static, and difficult to change, level of protection. The PPBs retain their state across
power cycles because they are Non-Volatile. Individual PPBs are set with a command but must all be cleared
as a group through a complex sequence of program and erasing commands. The PPBs are also limited to 100
erase cycles.
The PBB Lock bit adds an additional level of protection. Once all PPBs are programmed to the desired settings,
the PPB Lock may be set to “1”. Setting the PPB Lock disables all program and erase commands to the NonVolatile PPBs. In effect, the PPB Lock Bit locks the PPBs into their current state. The only way to clear the PPB
Lock is to go through a power cycle. System boot code can determine if any changes to the PPB are needed
e.g. to allow new system code to be downloaded. If no changes are needed then the boot code can set the PBB
Lock to disable any further changes to the PBBs during system operation.
The WP write protect pin adds a final level of hardware protection to the two outermost 4K words on both ends
of boot sectors. When this pin is low it is not possible to change the contents of these two sectors. These sectors
generally hold system boot code. So, the WP pin can prevent any changes to the boot code that could override
the choices made while setting up sector protection during system initialization.
It is possible to have sectors that have been persistently locked, and sectors that are left in the dynamic state.
The sectors in the dynamic state are all unprotected. If there is a need to protect some of them, a simple DPB
Write command sequence is all that is necessary. The DPB write/erase command for the dynamic sectors switch
the DPBs to signify protected and unprotected, respectively. If there is a need to change the status of the
persistently locked sectors, a few more steps are required. First, the PPB Lock bit must be disabled by either
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MBM29XL12DF-70/80
putting the device through a power-cycle, or hardware reset. The PPBs can then be changed to reflect the
desired settings. Setting the PPB lock bit once again will lock the PPBs, and the device operates normally again.
Note: to achieve the best protection, it’s recommended to execute the PPB lock bit set command early in the
boot code, and protect the boot code by holding WP = VIL.
DPB
PPB
PPB Lock
Sector State
0
0
0
Unprotected—PPB and DPB are changeable
1
0
0
Protected—PPB and DPB and DPB are changeable
0
1
0
Protected—PPB and DPB and DPB are changeable
1
1
0
Protected—PPB and DPB and DPB are changeable
0
0
1
Unprotected—PPB not changeable, DPB is
changeable
1
0
1
Protected—PPB not changeable, DPB is changeable
0
1
1
Protected—PPB not changeable, DPB is changeable
1
1
1
Protected—PPB not changeable, DPB is changeable
The above table contains all possible combinations of the DPB, PPB, and PPB lock relating to the status of the
sector.
In summary, if the PPB is set, and the PPB lock is set, the sector is protected and the protection can not be
removed until the next power cycle clears the PBB lock. If the PPB is cleared, the sector can be dynamically
locked or unlocked. The DPB then controls whether or not the sector is protected or unprotected.
If the user attempts to program or erase a protected sector, the device ignores the command and returns to read
mode. A program command to a protected sector enables status polling for approximately 1 µs before the device
returns to read mode without having modified the contents of the protected sector. An erase command to a
protected sector enables status polling for approximately 50 µs after which the device returns to read mode
without having erased the protected sector.
The programming of the DPB, PPB, and PPB lock for a given sector can be verified by writing a DPB/PPB/PPB
lock verify command to the device.
–DPB/PPB Status
The programming of the DPB/PPB for a given sector can be verified by writing a DPB/PPB status verify command
to the device.
–PPB Lock Bit Status
The programming of the PPB Lock Bit for a given sector can be verified by writing a PPB Lock Bit status verify
command to the device.
c) Persistent Protection Bit Lock (PPB Lock)
• PPB Locked
• PPB Locked with Password
A highly sophisticated protection method that requires a password before changes to certain sectors or sector
groups are permitted.
All parts default to operate in the Persistent Sector Protection mode. The customer must then choose if the
Persistent or Password Protection method is most desirable. There are two one-time programmable non-volatile
bits that define which sector protection method will be used. If the customer decides to continue using the
Persistent Sector Protection method, they must set the Persistent Sector Protection Mode Locking Bit. This will
permanently set the part to operate only using Persistent Sector Protection. If the customer decides to use the
password protection method, they must set the Password Mode Locking Bit. This will permanently set the part
to operate only using password sector protection.
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MBM29XL12DF-70/80
It is important to remember that setting either the Persistent Sector Protection Mode Locking Bit or the Password
Mode Locking Bit permanently selects the protection mode. It is not possible to switch between the two methods
once a locking bit has been set. It is important that one mode is explicitly selected when the device is first
programmed, rather than relying on the default mode alone. This is so that it is not possible for a system program
or virus to later set the Password Mode Locking Bit, which would cause an unexpected shift from the default
Persistent Sector Protection Mode into the Password Protection Mode.
The WP Hardware Protection feature is always available, independent of the software managed protection
method chosen.
A global volatile bit. When set to “1”, the PPBs cannot be changed. When cleared (“0”), the PPBs are changeable.
There is only one PPB Lock bit per device. The PPB Lock is cleared after power-up or hardware reset. There is
no command sequence to unlock the PPB Lock.
The Persistent Protection Bit (PPB) Lock is a volatile bit that reflects the state of the Password Mode Locking
Bit after power-up reset. If the Password Mode Locking Bit is set, which indicates the device is in Password
Protection Mode, the PPB Lock Bit is also set after a hardware reset (RESET asserted) or a power-up reset.
The ONLY means for clearing the PPB Lock Bit in Password Protection Mode is to issue the Password Unlock
command. Successful execution of the Password Unlock command clears the PPB Lock Bit, allowing for sector
PPBs modifications. Asserting RESET, taking the device through a power-on reset, or issuing the PPB Lock Bit
Set command sets the PPB Lock Bit back to a “1”.
If the Password Mode Locking Bit is not set, indicating Persistent Sector Protection Mode, the PPB Lock Bit is
cleared after power-up or hardware reset. The PPB Lock Bit is set by issuing the PPB Lock Bit Set command.
Once set the only means for clearing the PPB Lock Bit is by issuing a hardware or power-up reset. The Password
Unlock command is ignored in Persistent Sector Protection Mode.
-Password and Password Mode Locking Bit
In order to select the Password sector protection scheme, the customer must first program the password. Fujitsu
recommends that the password be somehow correlated to the unique Electronic Serial Number (ESN) of the
particular flash device. Each ESN is different for every flash device; therefore each password should be different
for every flash device. While programming in the password region, the customer may perform Password Verify
operations.
Once the desired password is programmed in, the customer must then set the Password Mode Locking Bit. This
operation achieves two objectives:
(1) It permanently sets the device to operate using the Password Protection Mode. It is not possible to reverse
this function.
(2) It also disables all further commands to the password region. All program, and read operations are ignored.
Both of these objectives are important, and if not carefully considered, may lead to unrecoverable errors.
The user must be sure that the Password Protection method is desired when setting the Password Mode
Locking Bit. More importantly, the user must be sure that the password is correct when the Password Mode
Locking Bit is set. Due to the fact that read operations are disabled, there is no means to verify what the
password is afterwards. If the password is lost after setting the Password Mode Locking Bit, there will be
no way to clear the PPB Lock bit.
The Password Mode Locking Bit, once set, prevents reading the 64-bit password on the DQ bus and further
password programming. The Password Mode Locking Bit is not erasable. Once Password Mode Locking Bit is
programmed, the Persistent Sector Protection Locking Bit is disabled from programming, guaranteeing that no
changes to the protection scheme are allowed.
64-bit Password
The 64-bit Password is located in its own memory space and is accessible through the use of the Password
Program and Verify commands (see “Password Verify Command”). The password function works in conjunction
with the Password Mode Locking Bit, which when set, prevents the Password Verify command from reading the
contents of the password on the pins of the device.
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MBM29XL12DF-70/80
-Persistent Sector Protection Mode Locking Bit
Like the password mode locking bit, a Persistent Sector Protection mode locking bit exists to guarantee that the
device remain in software sector protection. Once set, the Persistent Sector Protection locking bit prevents
programming of the password protection mode locking bit. This guarantees that a hacker could not place the
device in password protection mode.
(5) Temporary Sector Group Unprotection
This feature allows temporary unprotection of previously protected sector groups of the device in order to change
data. The Sector Group Unprotection mode is activated by setting the RESET pin to high voltage (VID). During
this mode, formerly protected sector groups can be programmed or erased by selecting the sector group addresses. Once the VID is taken away from the RESET pin, all the previously protected sector groups will be
protected again. While PPB Lock is set, this device cannot enter the Temporary Sector Group Unprotection mode.
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MBM29XL12DF-70/80
■ COMMAND DEFINITIONS
Device operations are selected by writing specific address and data sequences into the command register. Some
commands require Bank Address (BA) input. When command sequences are input into bank reading, the
commands have priority over the reading. "MBM29XL12DF Command Definitions Table" in ■DEVICE BUS
OPERATION shows the valid register command sequences. Note that the Erase Suspend (B0h) and Erase
Resume (30h) commands are valid only while the Sector Erase operation is in progress. Also the Program
Suspend (B0h) and Program Resume (30h) commands are valid only while the Program operation is in progress.
Moreover, Read/Reset commands are functionally equivalent, resetting the device to the read mode. Please
note that commands are always written at DQ15 to DQ0 and DQ31 to DQ16 bits are ignored.
Read/Reset Command
In order to return from Autoselect mode or Exceeded Timing Limits (DQ5 = 1) to Read/Reset mode, verify mode
of secter protect commands, the Read/Reset operation is initiated by writing the Read/Reset command sequence
into the command register. Microprocessor read cycles retrieve array data from the memory. The device remains
enabled for reads until the command register contents are altered.
The device automatically powers-up in the Read/Reset state. In this case, a command sequence is not required
to read data. Standard microprocessor read cycles retrieve array data. This default value ensures that no spurious
alteration of the memory content occurs during the power transition. Refer to the AC Read Characteristics and
Waveforms for specific timing parameters.
Autoselect Command
Flash memories are intended for use in applications where the local CPU alters memory contents. Therefore
manufacture and device codes must be accessible while the device resides in the target system. PROM programmers typically access the signature codes by raising A9 to a higher voltage. However multiplexing high
voltage onto the address lines is not generally desired system design practice.
The device contains Autoselect command operation to supplement traditional PROM programming methodology.
The operation is initiated by writing the Autoselect command sequence into the command register.
The Autoselect command sequence is initiated first by writing two unlock cycles. This is followed by a third write
cycle that contains the bank address (BA) and the Autoselect command. Then the manufacture and device
codes can be read from the bank, and actual data from the memory cell can be read from another bank. The
higher order address (A21, A20, A19) required for reading out the manufacture and device codes demands the
bank address (BA) set at the third write cycle.
Following the command write, a read cycle from address (BA) 00h returns the manufacturer’s code (Fujitsu=04h).
And, at double word mode, a read cycle at address (BA) 01h (at word mode, 02h) outputs device code. When
2222227Eh (at word mode, 227Eh) is output, this indicates that two additional codes, called Extended Device
Codes will be required. Therefore the system may continue reading out these Extended Device Codes at the
address of (BA) 0Eh (at word mode, 1Ch), as well as at (BA) 0Fh (at word mode, 1Eh). Refer to "MBM29XL12DF
Autoselect Codes Table" and "Exteneded Auteselect Code Table" in ■DEVICE BUS OPERATION.
The sector state (PPB protection or PPB unprotection) is informed by address (SA) XX02h . Scanning the sector
group addresses (A21, A20, A19, A18, A17, A16, A15, A14, A13, A12 and A11) while(A6, A5, A4, A3, A2, A1,A0) = (0, 1, 1,
1, 0, 1, 0) produces logic “1” at device output DQ0 for a protected sector group. The programming verification
should be performed by verifying sector group protection on the protected sector. See "MBM29XL12DF User
Bus Operations Table (DW/W = VIL)" and "MBM29XL12DF User Bus Operations Table (DW/W = VIH)" in ■DEVICE
BUS OPERATION.
The manufacture and device codes can be read from the selected bank. To read the manufacture and device
codes and sector protection status from a non-selected bank, it is necessary to write the Read/Reset command
sequence into the register. Autoselect command should then be written into the bank to be read.
If the software (program code) for Autoselect command is stored in the Flash memory, the device and manufacture codes should be read from the other bank, which does not contain the software.
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MBM29XL12DF-70/80
To terminate the operation, it is necessary to write the Read/Reset command sequence into the register. To
execute the Autoselect command during the operation, Read/Reset command sequence must be written before
the Autoselect command.
Word/Double Word Programming Command
The device is programmed on word-by-word basis (or double word-by-double word). Programming is a four bus
cycle operation. There are two “unlock” write cycles. These are followed by the program set-up command and
data write cycles. Addresses are latched on the falling edge of CE or WE, whichever happens later, and the data
is latched on the rising edge of CE or WE, whichever happens first. The rising edge of CE or WE (whichever
happens first) starts programming. Upon executing the Embedded Program Algorithm command sequence, the
system is not required to provide further controls or timings. The device automatically provides adequate internally generated program pulses and verify programmed cell margin.
The system can determine the status of the program operation by using DQ7 (Data Polling), DQ6 (Toggle Bit) or
RY/BY. The Data Polling and Toggle Bit must be performed at the memory location being programmed.
The automatic programming operation is completed when the data on DQ7 is equivalent to data written to this
bit at which device returns to the read mode and addresses are no longer latched. See "Hardware Sequence
Flags". Therefore the device requires that a valid address to the device be supplied by the system in this particular
instance. Hence Data Polling must be performed at the memory location being programmed.
Any commands written to the chip during this period are ignored. If hardware reset occurs during the programming
operation, the data being written is not guaranteed.
Programming is allowed in any sequence and across sector boundaries. Beware that a data “0” cannot be
programmed back to a “1”. Attempting to do so may either hang up the device or result in an apparent success
according to the data polling algorithm but a read from Read/Reset mode will show that the data is still “0”. Only
erase operations can convert from “0”s to “1”s.
Refer to "Embedded ProgramTM Algorithm" using typical command strings and bus operations.
Program Suspend/Resume Command
The Program Suspend command allows the system to interrupt a program operation so that data can be read
from any address. Writing the Program Suspend command (B0h) during the Embedded Program operation
immediately suspends the programming. The Program Suspend command may also be issued during a programming operation while an erase is suspended. The bank addresses of sector being programmed should be
set when writing the Program Suspend command.
When the Program Suspend command is written during a programming process, the device halts the program
operation within 1 µs and updates the status bits.
After the program operation has been suspended, the system can read data from any address. The data at
program-suspended address is not valid. Normal read timing and command definitions apply.
After the Program Resume command (30h) is written, the device reverts to programming. The bank addresses
of sectors being suspended should be set when writing the Program Resume command. The system can
determine the program operation status using the DQ7 or DQ6 status bits, just as in the standard program
operation. See “Write Operation Status” for more information.
The system may also write the Autoselect command sequence in the Program Suspend mode. The device allows
reading Autoselect codes at the addresses within programming sectors, since the codes are not stored in the
memory. When the device exits from the Autoselect mode, the device reverts to the Program Suspend mode,
and is ready for another valid operation. See “Autoselect Command Sequence” for more information.
The system must write the Program Resume command (address bits are “Bank Address”) to exit from the
Program Suspend mode and continue programming operation. Further writes of the Resume command are
ignored. Another Program Suspend command can be written after the device resumes programming.
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MBM29XL12DF-70/80
Chip Erase Command
Chip erase is a six-bus cycle operation. There are two “unlock” write cycles. These are followed by writing the
“set-up” command. Two more “unlock” write cycles are then followed by the chip erase command.
Chip erase does not require the user to program prior to erase. Upon executing the Embedded Erase Algorithm
command sequence the device automatically programs and verifies the entire memory for an all zero data pattern
prior to electrical erase. (Preprogram Function) The system is not required to provide any controls or timings
during these operations.
The system can determine the erase operation status by using DQ7 (Data Polling), or DQ6 (Toggle Bit). The chip
erase begins on the rising edge of the last CE or WE, whichever happens first in the command sequence and
terminates when the data on DQ7 is “1” (See "Write Operation Status" section.) at which the device returns to
read the mode.
Chip Erase Time: Sector Erase Time × All sectors + Chip Program Time (Preprogramming)
Refer to "Embedded EraseTM Algorithm" for typical command strings and bus operations.
Sector Erase Command
Sector erase is a six bus cycle operation. There are two “unlock” write cycles. These are followed by writing the
“set-up” command. Two more “unlock” write cycles are then followed by the Sector Erase command. The sector
address (any address location within the desired sector) is latched on the falling edge of CE or WE whichever
starts later, while the command (Data = 30h) is latched on the rising edge of CE or WE whichever states first.
After time-out of “tTOW” from the rising edge of the last sector erase command, the sector erase operation will begin.
Multiple sectors are erased concurrently by writing the six bus cycle operations on "MBM29XL12DF Command
Definitions Table" in ■DEVICE BUS OPERATION. This sequence is followed with writes of the Sector Erase
command to addresses in other sectors desired to be concurrently erased. The time between writes must be
less than “tTOW” otherwise that command is not accepted and erasure does not start. It is recommended that
processor interrupts be disabled during this time to guarantee this condition. The interrupts can be re-enabled
after the last Sector Erase command is written. A time-out of “tTOW” from the rising edge of last CE or WE whichever
starts first initiates the execution of the Sector Erase command(s). If another falling edge of CE or WE, whichever
starts first occurs within the “tTOW” time-out window the timer is reset. (Monitor DQ3 to determine if the sector
erase timer window is still open, see section DQ3, "Sector Erase Timer".) Any command other than Sector Erase
or Erase Suspend during this time-out period will reset the device to the read mode, ignoring the previous
command string. Resetting the device once execution has begun may corrupt the data in the sector. In that case
restart the erase on those sectors and allow them to complete. Refer to "Write Operation Status" section for
Sector Erase Timer operation. Loading the sector erase buffer may be done in any sequence and with any
number of sectors.
Sector erase does not require the user to program prior to erase. The device automatically programs all memory
locations in the sector(s) to be erased prior to electrical erase (Preprogram function). When erasing a sector or
sectors the remaining unselected sectors are not affected. The system is not required to provide any controls
or timings during these operations.
The system can determine the status of the erase operation by using DQ7 (Data Polling), or DQ6 (Toggle Bit).
The sector erase begins after the “tTOW” time out from the rising edge of CE or WE whichever starts first for the
last sector erase command pulse and terminates when the data on DQ7 is “1” at which time the device returns
to the read mode. See "Write Operation Status" section. Data polling and Toggle Bit must be performed at an
address within any of the sectors being erased.
Multiple Sector Erase Time; [Sector Erase Time + Sector Program Time (Preprogramming)] × Number of Sector
Erase.
In case of multiple sector erase across bank boundaries, a read from the bank (read-while-erase) to which
sectors being erased belong cannot be performed.
Refer to "Embedded EraseTM Algorithm" for typical command strings and bus operations.
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MBM29XL12DF-70/80
Erase Suspend/Resume Command
The Erase Suspend command allows the user to interrupt a Sector Erase operation and then perform data reads
from or programs to a sector not being erased. This command is applicable ONLY during the Sector Erase
operation which includes the time-out period for sector erase. The Erase Suspend command is ignored during
the Chip Erase operation. Writting the Erase Suspend command (B0h) during the Sector Erase time-out results
in immediate termination of the time-out period and suspension of the erase operation.
Writing the Erase Resume command (30h) resumes the erase operation. The addresses are “DON’T CARES”
when writting the Erase Suspend or Erase Resume command.When the Erase Suspend command is written
during the Sector Erase operation, the device takes a maximum of “tSPD” to suspend the erase operation. When
the device has entered the erase-suspended mode, the DQ7 bit is at logic “1”, and DQ6 stops toggling. The user
must use the address of the erasing sector for reading DQ6 and DQ7 to determine if the erase operation is
suspended. Further writes of the Erase Suspend command are ignored.
When the erase operation is suspended, the device defaults to the erase-suspend-read mode. Reading data in
this mode is the same as reading from the standard read mode except that the data must be read from sectors
that have not been erase-suspended. Successively reading from the erase-suspended sector while the device
is in the erase-suspend-read mode causes DQ2 to toggle. See the section on DQ2.
After entering the erase-suspend-read mode, the user can program the device by writing the appropriate command sequence for program. This program mode is known as the erase-suspend-program mode. Again, programming in this mode is the same as programming in the regular program mode except that the data must be
programmed to sectors that are not erase-suspended. Successively reading from the erase-suspended sector
while the device is in the erase-suspend-program mode causes DQ2 to toggle. The end of the erase-suspended
program operation is detected by the Data polling of DQ7 or by the Toggle Bit I (DQ6) which is the same as the
regular program operation. Note that DQ7 must be read from the program address while DQ6 can be read from
any address.
To resume the operation of Sector Erase, the Resume command (30h) should be written. Any further writes of
the Resume command at this point is ignored. Another Erase Suspend command is written after the chip resumes
erasing.
Fast Mode
Fast Mode function dispenses with the initial two unlock cycles required in the standard program command
sequence writing Fast Mode command into the command register. In this mode the required bus cycle for
programming is two cycles instead of four bus cycles in standard program command. The read operation is also
executed after exiting this mode. During the Fast mode, do not write any commands other than the Fast program/
Fast mode reset command. To exit this mode, write Fast Mode Reset command into the command register.
Refer to "Embedded Program Algorithm for Fast Mode". The VCC active current is required even CE = VIH during
Fast Mode.
Fast Programming
During Fast Mode, the programming can be executed with two bus cycles operation. The Embedded Program
Algorithm is executed by writing program set-up command (A0h) and data write cycles (PA/PD). Refer to "Embedded Program Algorithm for Fast Mode".
Query (CFI:Common Flash Memory Interface)
The CFI (Common Flash Memory Interface) specification outlines device and host system software interrogation
handshake which allows specific vendor-specified software algorithms to be used for entire families of device.
This allows device-independent, JEDEC ID-independent, and forward- and backward-compatible software support for the specified flash device families. Refer to "Common Flash Memory Interface Code" in ■FLEXIBLE
SECTOR-ERASE ARCHITECTURE in detail.
The operation is initiated by writing the query command (98h) into the command register. Following the command
write, a read cycle from specific address retrives device information. Please note that output data of upper byte
(DQ31 to DQ16) is “0” in word mode (16 bit) read. To terminate operation, write the Read/Reset command
sequence into the register.
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MBM29XL12DF-70/80
HiddenROM Entry Command
The device has a HiddenROM area with One Time Protect function. This area is to enter the security code and
to unable the change of the code once set. Program/erase is possible in this area until it is protected. However
once it is protected, it is impossible to unprotect. Therefore extreme caution is required.
HiddenROM area is 128 words in Bank A. This area is normally the “outermost” 8K words boot block area.
Therefore, write the HiddenROM entry command sequence to enter the HiddenROM area. It is called HiddenROM mode when the HiddenROM area appears.
The following commands are permitted after issuing the HiddenROM Entry command:
1. Autoselect
2. Password Program
3. Password Verify
4. Password Unlock
5. Read/Reset
6. Program
7. Chip and Sector Erase
8. HiddenROM Protection Bit Program
9. PPB Program
10. All PPB Erase
11. PPB Lock Bit Set
12. DPB Write
13. DPB/PPB/PPB Lock Bit Verify
14. HiddenROM Exit
The following commands are unavailable when the HiddenROM is enabled. Issuing the following commands
while the HiddenROM is enabled results in the command being ignored.
1. CFI
2. Set to Fast Mode
3. Fast Program
4. Reset from Fast Mode
5. Program and Sector Erase Suspend
6. Program and Sector Erase Resume
The HiddenROM Entry command is allowed when the device is in either program or erase suspend modes. If
the HiddenROM is enabled, the program or erase suspend command is ignored. This prevents resuming either
programming or erase on the HiddenROM if the overlayed sector is undergoing programming or erase. It is the
responsibility of the software to resume the program or erase of a suspended program or erase after exiting the
HiddenROM.
Executing any of the PPB program/erase commands, or Password Unlock command results in the Bank A
returning the status of these operations while they are in progress, thus making the HiddenROM unavailable for
reading. If the HiddenROM is enabled while the DPB command is issued, the DPB for the overlayed sector is
not updated. Reading the DPB status using the PPB Lock Bit/DPB verify command when the HiddenROM is
enabled returns invalid data.
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MBM29XL12DF-70/80
HiddenROM Program Command
To program the data to the HiddenROM area, write the HiddenROM program command sequence during HiddenROM mode. This command is the same as the program command in usual except to write the command
during HiddenROM mode. Therefore the detection of completion method is the same as using the DQ7 data
polling, and DQ6 toggle bit. Need to pay attention to the address to be programmed. If the address other than
the HiddenROM area is selected to program, data of the address are changed.
HiddenROM Protect Command
The method to protect the HiddenROM is to apply high voltage (VID) to A9 and OE, set the sector address in the
HiddenROM area and (A6, A5, A4, A3, A2, A1, A0) = (0, 1, 1, 1, 0, 1, 0), and apply the write pulse during the
HiddenROM mode. To verify the protect circuit, apply high voltage (VID) to A9, specify (A6, A5, A4, A3, A2, A1, A0)
= (0, 0, 1, 1, 0, 1, 0) and the sector address in the HiddenROM area, and read. When “1” appears on DQ0, the
protect setting is completed. “0” appears on DQ0 if it is not protected. Please apply write pulse agian. The same
command sequence could be used for the above method because other than the HiddenROM mode, it is the
same as the sector protect in the past.
And the device has also HiddenROM protect command without VID. See "MBM29XL12DF Command Definitions
Table" in ■DEVICE BUS OPERATION.
Other sector will be effected if the address other than those for HiddenROM area is selected for the sector
address, so please be carefull. Once it is protected, protection can not be cancelled, so please pay the closest
attention.
Another method to protect is to issue HiddenROM Protection Bit Program Command. This is able to protect
HiddenROM area by command only.
Password Program Command
The Password Program Command permits programming the password that is used as part of the hardware
protection scheme. The actual password is 64-bits long. In word mode, 4 Password Program commands (In
double word mode. 2 Password Program commands)are required to program the password. The user must enter
the unlock cycle, password program command (38h) and the program address/data for each portion of the
password when programming. There are no provisions for entering the 2-cycle unlock cycle, the password
program command, and all the password data. There is no special addressing order required for programming
the password. Also, when the password is undergoing programming, Simultaneous Operation is disabled. Read
operations to any memory location will return the programming status. Once programming is complete, the user
must issue a Read/Reset command to return the device to normal operation. Once the Password is written and
verified, the Password Mode Locking Bit must be set in order to prevent verification. The Password Program
Command is only capable of programming “0”s. Programming a “1” after a cell is programmed as a “0” results
in a time-out by the Embedded Program Algorithm with the cell remaining as a “0”. The password is all F’s when
shipped from the factory. All 64-bit password combinations are valid as a password.
Password Programming is permitted if the HiddenROM is enabled.
Password Verify Command
The Password Verify Command is used to verify the Password. The Password is verifiable only when the Password
Mode Locking Bit is not programmed. If the Password Mode Locking Bit is programmed and the user attempts
to verify the Password, the device will always drive all F’s onto the DQ data bus.
The Password Verify command is permitted if the HiddenROM is enabled. Also, the device will not operate in
Simultaneous Operation when the Password Verify command is executed. Only the password is returned regardless of the bank address. The lower two address bits (A1:A0) are valid during the Password Verify. Writing
the Read/Reset command returns the device back to normal operation.
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MBM29XL12DF-70/80
Password Protection Mode Locking Bit Program Command
The Password Protection Mode Locking Bit Program Command programs the Password Protection Mode Locking
Bit, which prevents further verifies or updates to the Password. Once programmed, the Password Protection
Mode Locking Bit cannot be erase. If the Password Protection Mode Locking Bit is verified as program without
margin, the Password Protection Mode Locking Bit Program command can be executed to improve the program
margin. Once the Password Protection Mode Locking Bit is programmed, the Persistent Sector Protection Locking
Bit program circuitry is disabled, thereby forcing the device to remain in the Password Protection mode. Exiting
the Mode Locking Bit Program command is accomplished by writing the Read/Reset command.
The Password Protection Mode Locking Bit Program command is permitted if the HiddenROM is enabled.
Persistent Sector Protection Mode Locking Bit Program Command
The Persistent Sector Protection Mode Locking Bit Program Command programs the Persistent Sector Protection
Mode Locking Bit, which prevents the Password Mode Locking Bit from ever being programmed. If the Persistent
Sector Protection Mode Locking Bit is verified as programmed without margin, the Persistent Sector Protection
Mode Locking Bit Program Command should be reissued to improve program margin. By disabling the program
circuitry of the Password Mode Locking Bit, the device is forced to remain in the Persistent Sector Protection
mode of operation, once this bit is set. Exiting the Persistent Protection Mode Locking Bit Program command is
accomplished by writing the Read/Reset command.
The Persistent Sector Protection Mode Locking Bit Program command is permitted if the HiddenROM is enabled.
PPB Lock Bit Set Command
The PPB Lock Bit Set command is used to set the PPB Lock bit if it is cleared either at reset or if the Password
Unlock command was successfully executed. There is no PPB Lock Bit Clear command. Once the PPB Lock
Bit is set, it cannot be cleared unless the device is taken through a power-on clear or the Password Unlock
command is executed. Upon setting the PPB Lock Bit, the PPBs are latched into the DPBs. If the Password
Mode Locking Bit is set, the PPB Lock Bit status is reflected as set, even after a power-on reset cycle. Exiting
the PPB Lock Bit Set command is accomplished by writing the Read/Reset command.
The PPB Lock Bit Set command is permitted if the HiddenROM is enabled.
DPB Write(Erase) Command
The DPB Write command is used to set or clear a DPB for a given sector. The high order address bits (A21 to
A11) are issued at the same time as the code 01h or 00h on DQ7 to DQ0. All other DQ data bus pins are ignored
during the data write cycle. The DPBs are modifiable at any time, regardless of the state of the PPB or PPB
Lock Bit. The DPBs are cleared at power-up or hardware reset.Exiting the DPB Write command is accomplished
by writing the Read/Reset command.
The DPB Write command is permitted if the HiddenROM is enabled.
DPB /PPB Verify command
DPB/PPB verify command is uesed to verify the status of several sectors.
Scanning the sector addresses (SA) will produce a logical "1" at the device output DQ0 for a protected sector.
Otherwise the device will produce "0" at DQ0 for the sector which is not protected.
The DPB/PPB verify erify command is permitted if the HiddenROM is enabled.
PPB Lock Bit Verify command
PPB Lock Bit verify command is used to verify the status of a PPB Lock Bit.
A logical "1" at the device output DQ1 indicates that the PPB Lock Bit is set.
If PPB Lock Bit is not set, DQ1 will output"0".The PPB Lock Bit verify command is permitted if the HiddenROM
is enabled.
45
MBM29XL12DF-70/80
Password Unlock Command
The Password Unlock command is used to clear the PPB Lock Bit so that the PPBs can be unlocked for
modification, thereby allowing the PPBs to become accessible for modification. The exact password must be
entered in order for the unlocking function to occur. This command cannot be issued any faster than 2 µs at a
time to prevent a hacker from running through the all 64-bit combinations in an attempt to correctly match a
password. If the command is issued before the 2 µs execution window for each portion of the unlock, the command
will be ignored.
The Password Unlock function is accomplished by writing Password Unlock command and data to the device to
perform the clearing of the PPB Lock Bit. A0 and A1 are used to determine the 16 bit data quantity is used to
match separated 16 bits. Writing the Password Unlock command is address order specific. In other words, the
lowers address A1:A0 = 00, the next cycle command is to A1:A0 = 01, then to A1:A0 = 10, and finally to A1:A0 =
11. Writing out of sequence results in the Password Unlock not returning a match with the password and the
PPB Lock Bit remains set.
Once the Password Unlock command is entered, the RY/BY pin goes LOW indicating that the device is busy.
Also, reading the Bank A results in the DQ6 pin toggling, indicating that the Password Unlock function is in
progress. Reading the other bank returns actual array data. Approximately 1µs is required for each portion of
the unlock. Once the first portion of the password unlock completes (RY/BY is not driven and DQ6 does not
toggle when read), the next cycle is issued, only this time with the next part of the password. Seven cycles
Password Unlock commands are required to successfully clear the PPB Lock Bit. As with the first Password
Unlock command, the RY/BY signal goes LOW and reading the device results in the DQ6 pin toggling on
successive read operations until complete. It is the responsibility of the microprocessor to keep track of the
number of Password Unlock cycles, the order, and when to read the PPB Lock bit to confirm successful password
unlock.
The Password Unlock command is permitted if the HiddenROM is enabled.
PPB Program Command
The PPB Program command is used to program, or set, a given PPB. Each PPB is individually programmed
(but is bulk erased with the other PPBs). The specific sector address (A21 to A11) are written at the same time
as the program command 60h with A6 = 0. If the PPB Lock Bit is set and the corresponding PPB is set for the
sector, the PPB Program command will not execute and the command will time-out without programming the PPB.
After programming a PPB, two additional cycles are needed to determine whether the PPB has been programmed
with margin. If the PPB has been programmed without margin, the program command should be reissued to
improve the program margin.
The PPB Program command is permitted if the HiddenROM is enabled. The PPB Program command does not
follow the Embedded Program algorithm.
All PPB Erase Command
The All PPB Erase command is used to erase all PPBs in bulk. There is no means for individually erasing a
specific PPB. Unlike the PPB program, no specific sector address is required. However, when the PPB erase
command is written (60h) and A6 = 1, all Sector PPBs are erased in parallel. If the PPB Lock Bit is set the ALL
PPB Erase command will not execute and the command will time-out without erasing the PPBs. After erasing
the PPBs, two additional cycles are needed to determine whether the PPB has been erased with margin. If the
PPBs has been erased with-out margin, the erase command should be reissued to improve the program margin.
It is the responsibility of the user to preprogram all PPBs prior to issuing the All PPB Erase command. If the user
attempts to erase a cleared PPB, over-erasure may occur making it difficult to program the PPB at a later time.
Also note that the total number of PPB program/erase cycles is limited to 100 cycles. Cycling the PPBs beyond
100 cycles is not guaranteed.
The All PPB Erase command is permitted if the HiddenROM is enabled.
46
MBM29XL12DF-70/80
Write Operation Status
Detailed in “Hardware Sequence Flags” are all the status flags which can determine the status of the bank for
the current mode operation. The read operation from the bank which doesn’t operate Embedded Algorithm
returns data of memory cells. These bits offer a method for determining whether an Embedded Algorithm is
properly completed. The information on DQ2 is address-sensitive. This means that if an address from an erasing
sector is consecutively read, the DQ2 bit will toggle. However, DQ2 will not toggle if an address from a non-erasing
sector is consecutively read. This allows users to determine which sectors are in erase and which are not.
The status flag is not output from banks (non-busy banks) which do not execute Embedded Algorithms. For
example, a bank (busy bank) is executing an Embedded Algorithm. When the read sequence is [1] < busy
bank >, [2] < non-busy bank >, [3] < busy bank >, the DQ6 toggles in the case of [1] and [3]. In case of [2], the
data of memory cells are output. In the erase-suspend read mode with the same read sequence, DQ6 will not
be toggled in [1] and [3].
Hardware Sequence Flags
DQ7
DQ6
DQ5
DQ3
DQ2
DQ7
Toggle
0
0
1
0
Toggle
0
1
Toggle*1
1
1
0
0
Toggle
Erase Suspend Read
(Non-Erase Suspended Sector)
Data
Data
Data
Data
Data
Erase Suspend Program
(Non-Erase Suspended Sector)
DQ7
Toggle
0
0
1*2
Program Suspend Read
(Program Suspended Sector)
Data
Data
Data
Data
Data
Program Suspend Read
(Non-Program Suspended Sector)
Data
Data
Data
Data
Data
DQ7
Toggle
1
0
1
0
Toggle
1
1
N/A
DQ7
Toggle
1
0
N/A
Status
Embedded Program Algorithm
Embedded Erase Algorithm
Erase Suspend Read
(Erase Suspended Sector)
Erase
Suspended
In Progress Mode
Program
Suspended
Mode
Embedded Program Algorithm
Embedded Erase Algorithm
Exceeded
Time Limits Erase
Erase Suspend Program
Suspended
(Non-Erase Suspended Sector)
Mode
*1: Successive reads from the erasing or erase-suspend sector will cause DQ2 to toggle.
*2: Reading from non-erase suspend sector address will indicate logic “1” at the DQ2 bit.
Notes: • DQ0 and DQ1 are reserve pins for future use.
• DQ4 is limited to Fujitsu internal use.
DQ7
Data Polling
The device features Data Polling as a method to indicate to the host that the Embedded Algorithms are in
progress or completed. During the Embedded Program Algorithm, an attempt to read the device will produce a
complement of data last written to DQ7. Upon completion of the Embedded Program Algorithm, an attempt to
read the device will produce true data last written to DQ7. During the Embedded Erase Algorithm, an attempt to
read the device will produce a “0” at the DQ7 output. Upon completion of the Embedded Erase Algorithm, an
attempt to read device will produce a “1” on DQ7. The flowchart for Data Polling (DQ7) is shown in “Data Polling
Algorithm”.
47
MBM29XL12DF-70/80
For programming, the Data Polling is valid after the rising edge of the fourth write pulse in the four write pulse
sequences.
For chip erase and sector erase, the Data Polling is valid after the rising edge of the sixth write pulse in the six
write pulse sequences. Data Polling must be performed at sector addresses of sectors being erased, not protected sectors. Otherwise the status may become invalid.
If a program address falls within a protected sector, Data Polling on DQ7 is active for approximately 1 µs, then
that bank returns to the read mode. After an erase command sequence is written, if all sectors selected for
erasing are protected, Data Polling on DQ7 is active for approximately 400 µs, then the bank returns to read mode.
Once the Embedded Algorithm operation is close to being completed, the device data pins (DQ7) may change
asynchronously while the output enable (OE) is asserted low. This means that device is driving status information
on DQ7 at one instant, and then that byte’s valid data at the next instant. Depending on when the system samples
the DQ7 output, it may read the status or valid data. Even if device has completed the Embedded Algorithm
operation and DQ7 has a valid data, data outputs on DQ0 to DQ6 may still be invalid. The valid data on DQ0 to
DQ7 will be read on successive read attempts.
The Data Polling feature is active only during the Embedded Programming Algorithm, Embedded Erase Algorithm
or sector erase time-out. See “Toggle Bit Status” and “Data Polling during Embedded Algorithm Operation Timing
Diagram”.
DQ6
Toggle Bit I
The device also features the “Toggle Bit I” as a method to indicate to the host system that the Embedded
Algorithms are in progress or completed.
During Embedded Program or Erase Algorithm cycle, successive attempts to read (OE toggling) data from the
busy bank will result in DQ6 toggling between one and zero. Once the Embedded Program or Erase Algorithm
cycle is completed, DQ6 will stop toggling and valid data will be read on the next successive attempts. During
programming, the Toggle Bit I is valid after the rising edge of the fourth write pulse in the four write pulse
sequences. For chip erase and sector erase, the Toggle Bit I is valid after the rising edge of the sixth write pulse
in the six write pulse sequences. The Toggle Bit I is active during the sector time out.
In programming, if the sector being written is protected, the toggle bit will toggle for about 1 µs and then stop
toggling with data unchanged. In erase, the device will erase all selected sectors except for protected ones. If
all selected sectors are protected, the chip will toggle the toggle bit for about 400 µs and then drop back into
read mode, having data kept remained.
Either CE or OE toggling will cause DQ6 to toggle. In addition, an Erase Suspend/Resume command will cause
DQ6 to toggle.
The system can use DQ6 to determine whether a sector is actively erased or is erase-suspended. When a bank
is actively erased (that is, the Embedded Erase Algorithm is in progress) , DQ6 toggles. When a bank enters the
Erase Suspend mode, DQ6 stops toggling. Successive read cycles during erase-suspend-program cause DQ6
to toggle.
To operate toggle bit function properly, CE or OE must be high when bank address is changed.
See “AC Wavefrom for Toggle Bit I during Embedded Algorithm Operations”.
DQ5
Exceeded Timing Limits
DQ5 will indicate if the program or erase time has exceeded the specified limits (internal pulse count) . Under
these conditions DQ5 will produce “1”. This is a failure condition indicating that the program or erase cycle was
not successfully completed. Data Polling is only operating function of the device under this condition. The CE
circuit will partially power down device under these conditions (to approximately 2 mA) . The OE and WE pins
will control the output disable functions as described in "MBM29XL12DF User Bus Operations Table (DW/W =
VIL)" and "MBM29XL12DF User Bus Operations Table (DW/W = VIH)" in ■DEVICE BUS OPERATION.
48
MBM29XL12DF-70/80
The DQ5 failure condition may also appear if a user tries to program a non-blank location without pre-erase. In
this case the device locks out and never completes the Embedded Algorithm operation. Hence, the system never
reads valid data on DQ7 bit and DQ6 never stop toggling. Once the device has exceeded timing limits, the DQ5
bit will indicate a “1.” Please note that this is not a device failure condition since the device was incorrectly used.
If this occurs, reset device with the command sequence.
DQ3
Sector Erase Timer
After completion of the initial sector erase command sequence, sector erase time-out begins. DQ3 will remain
low until the time-out is completed. Data Polling and Toggle Bit are valid after the initial sector erase command
sequence.
If Data Polling or the Toggle Bit I indicates that a valid erase command has been written, DQ3 may be used to
determine whether the sector erase timer window is still open. If DQ3 is high (“1”) the internally controlled erase
cycle has begun. If DQ3 is low (“0”) , the device will accept additional sector erase commands. To insure the
command has been accepted, the system software should check the status of DQ3 prior to and following each
subsequent Sector Erase command. If DQ3 were high on the second status check, the command may not have
been accepted.
See “Hardware Sequence Flags”.
DQ2
Toggle Bit II
This toggle bit II, along with DQ6, can be used to determine whether the device is in the Embedded Erase
Algorithm or in Erase Suspend.
Successive reads from the erasing sector will cause DQ2 to toggle during the Embedded Erase Algorithm. If the
device is in the erase-suspended-read mode, successive reads from the erase-suspended sector will cause
DQ2 to toggle. When the device is in the erase-suspended-program mode, successive reads from the non-erase
suspended sector will indicate a logic “1” at the DQ2 bit.
DQ6 is different from DQ2 in that DQ6 toggles only when the standard program or Erase, or Erase Suspend
Program operation is in progress. The behavior of these two status bits, along with that of DQ7, is summarized
as follows :
For example, DQ2 and DQ6 can be used together to determine if the erase-suspend-read mode is in progress.
(DQ2 toggles while DQ6 does not.) See also “Toggle Bit Status” and "DQ2 vs DQ6".
Furthermore DQ2 can also be used to determine which sector is being erased. At the erase mode, DQ2 toggles
if this bit is read from an erasing sector.
To operate toggle bit function properly, CE or OE must be high when bank address is changed.
Reading Toggle Bits DQ6/DQ2
Whenever the system initially begins reading toggle bit status, it must read DQ7 to DQ0 at least twice in a row
to determine whether a toggle bit is toggling. Typically a system would note and store the value of the toggle bit
after the first read. After the second read, the system would compare the new value of the toggle bit with the
first. If the toggle bit is not toggling, the device has completed the program or erase operation. The system can
read array data on DQ7 to DQ0 on the following read cycle.
However, if, after the initial two read cycles, the system determines that the toggle bit is still toggling, the system
also should note whether the value of DQ5 is high (see the section on DQ5) . If it is, the system should then
determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as DQ5
went high. If the toggle bit is no longer toggling, the device has successfully completed the program or erase
operation. If it is still toggling, the device did not complete the operation successfully, and the system must write
the reset command to return to reading array data.
The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 has not
gone high. The system may continue to monitor the toggle bit and DQ5 through successive read cycles, determining the status as described in the previous paragraph. Alternatively, it may choose to perform other system
49
MBM29XL12DF-70/80
tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine the
status of the operation. Refer to “Toggle Bit Algorithm”.
Toggle Bit Status
DQ7
DQ6
DQ2
DQ7
Toggle
1
Erase
0
Toggle
Toggle *
Erase-Suspend Read
(Erase-Suspended Sector)
1
1
Toggle
DQ7
Toggle
1*
Mode
Program
Erase-Suspend Program
* : Successive reads from the erasing or erase-suspend sector will cause DQ2 to toggle. Reading from non-erase
suspend sector address will indicate logic “1” at the DQ2 bit.
RY/BY (Ready/Busy Pin)
The device provides a RY/BY open-drain output pin as a way to indicate to the host system that Embedded
Algorithms are either in progress or have been completed. If output is low, the device is busy with either a program
or erase operation. If output is high, the device is ready to accept any read/write or erase operation. If the device
is placed in an Erase Suspend mode, RY/BY output will be high.
During programming, the RY/BY pin is driven low after the rising edge of the fourth write pulse. During an erase
operation, the RY/BY pin is driven low after the rising edge of the sixth write pulse. The RY/BY pin will indicate
a busy condition during RESET pulse. Refer to the following detailed timing diagrams. The RY/BY pin is pulled
high in standby mode.
Since this is an open-drain output, RY/BY pins can be tied together in parallel with a pull-up resistor to VCC.
Data Protection
The device is designed to offer protection against accidental erasure or programming caused by spurious system
level signals that may exist during power transitions. During power up device automatically resets internal state
machine to Read mode. Also, with its control register architecture, alteration of memory contents only occurs
after successful completion of specific multi-bus cycle command sequence.
Device also incorporates several features to prevent inadvertent write cycles resulting from VCC power-up and
power-down transitions or system noise.
Low VCC Write Inhibit
To avoid initiation of a write cycle during VCC power-up and power-down, a write cycle is locked out for VCC less
than VLKO (Min). If VCC < VLKO, the command register is disabled and all internal program/erase circuits are disabled.
Under this condition, the device will reset to the read mode. Subsequent writes will be ignored until the VCC level
is greater than VLKO. It is the users responsibility to ensure that the control pins are logically correct to prevent
unintentional writes when VCC is above VLKO (Min).
If the Embedded Erase Algorithm is interrupted, there is possibility that the erasing sector(s) can not be used.
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE, CE, or WE will not initiate a write cycle.
Logical Inhibit
Writing is inhibited by holding any one of OE = VIL, CE = VIH, or WE = VIH. To initiate a write cycle, CE and WE
must be a logical zero while OE is a logical one.
Power-up Write Inhibit
Power-up of the device with WE = CE = VIL and OE = VIH will not accept commands on the rising edge of WE.
The internal state machine is automatically reset to read mode on power-up.
50
MBM29XL12DF-70/80
■ ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Rating
Unit
Min
Max
Tstg
–55
+125
°C
TA
–40
+85
°C
VIN, VOUT
–0.5
VCC+0.5
V
Power Supply Voltage *1, *2
VCC
–0.5
+4.0
V
A9, OE, RESET and ACC *1, *3
VIN
–0.5
+13.0
V
Storage Temperature
Ambient Temperature with Power Applied
Voltage with Respect to Ground. All pins except
A9, OE, RESET and ACC *1, *2
*1 : Voltage is defined on the basis of VSS=GND=0V.
*2 : Minimum DC voltage on input or l/O pins is –0.5 V. During voltage transitions, inputs or I/O pins may
undershoot VSS to –2.0 V for periods of up to 20 ns. Maximum DC voltage on input or l/O pins is
VCC +0.5 V. During voltage transitions,inputs may overshoot to VCC +2.0 V for periods of up to 20 ns.
*3 : Minimum DC input voltage on A9, OE, RESET and ACC pins is –0.5 V. During voltage transitions, A9, OE,
RESET and ACC pins may undershoot VSS to –2.0 V for periods of up to 20 ns. Voltage difference between input
and supply voltage (VIN – VCC) does not exceed +9.0 V. Maximum DC input voltage on A9, OE, RESET and
ACC pins is +13.0 V which may overshoot to +14.0V for periods of up to 20 ns.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
■ RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
Ambient Temperature
TA
Power Supply Voltage *
VCC
Part No.
Value
Unit
Min
Max
MBM29XL12DF-70/80
–40
+85
°C
MBM29XL12DF-70
+3.0
+3.6
V
MBM29XL12DF-80
+2.7
+3.1
V
* : Voltage is defined on the basis of VSS=GND=0V.
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
51
MBM29XL12DF-70/80
■ MAXIMUM OVERSHOOT / MAXIMUM UNDERSHOOT
+0.8 V
20 ns
20 ns
–0.5 V
–2.0 V
20 ns
Maximum Undershoot Waveform
20 ns
VCC +2.0 V
VCC +0.5 V
+2.0 V
20 ns
20 ns
Maximum Overshoot Waveform 1
20 ns
+14.0 V
+13.0 V
VCC +0.5 V
20 ns
20 ns
Note: This waveform is applied for A9, OE, RESET, and ACC.
Maximum Overshoot Waveform 2
52
MBM29XL12DF-70/80
■ DC CHARACTERISTICS
Value
Parameter
Symbol
Conditions
Unit
Min
Typ
Max
Input Leakage Current
ILI
VIN = VSS to VCC, VCC = VCC Max
–1.0
—
+1.0
µA
Output Leakage Current
ILO
VOUT = VSS to VCC, VCC = Vcc Max
–1.0
—
+1.0
µA
A9, OE, RESET, ACC Inputs
Leakage Current
ILIT
VCC = VCC Max,
A9, OE, RESET, ACC= 12.5V
—
—
35
µA
ACC Accelerated Program Current
ILIA
VCC = VCC Max,
ACC = VACC Max
—
—
20
mA
CE = VIL, OE = VIH
f = 10MHz
—
—
70
mA
CE = VIL, OE = VIH
f = 5MHz
—
—
35
mA
1
VCC Active Current *
(Initial/Random Read)
ICC1
VCC Active Current *2
ICC2
CE = VIL, OE = VIH
—
—
35
mA
VCC Current (Standby)
ICC3
VCC = VCC Max, CE = VCC ±0.3 V,
RESET =VCC ±0.3 V,
WP = VCC ±0.3 V
—
1
5
µA
VCC Current (Standby,Reset)
ICC4
VCC = VCC Max,
RESET =VSSQ ±0.3 V
—
1
5
µA
VCC Current (Page Mode) *3
ICC5
CE = VIL, OE = VIH,
f = 40MHz
—
—
15
mA
VCC Current
(Automatic Sleep Mode) *4
ICC6
VCC = VCC Max, CE = VSS ±0.3 V,
RESET =VCC ±0.3 V
VIN = VCC ±0.3 V or VSS ±0.3 V
—
1
5
µA
VCC Active Current*6
(Read-While-Program)
ICC7
CE = VIL, OE = VIH
—
—
50
mA
VCC Active Current*6
(Read-While-Erase)
ICC8
CE = VIL, OE = VIH
—
—
50
mA
VCC Active Current*6
(Erase-Suspend-Program)
ICC9
CE = VIL, OE = VIH
—
—
35
mA
(Continued)
53
MBM29XL12DF-70/80
(Continued)
Value
Parameter
Symbol
Conditions
Unit
Min
Typ
Max
Input Low Voltage
VIL
—
−0.5
—
0.6
V
Input High Voltage *5
VIH
—
VCC−0.2
—
VCC+0.3
V
Voltage for Auteselect and Sector
Protection(A9, OE, RESET)*7
VID
—
11.5
12.0
12.5
V
Voltage for ACC Program
Acceleration
VACC
—
11.5
12.0
12.5
V
Output Low Voltage
VOL
IOL = 4.0 mA, VCC = VCC Min
—
—
0.45
V
VOH1
IOH = –2.0 mA, VCC = VCC Min
VCC−0.4
—
—
V
VOH2
IOH = –100 µA, VCC = VCC Min
VCC−0.2
—
—
V
VLKO
—
2.3
2.4
2.5
V
Output High Voltage
Low VCC Lock-Out Voltage
*1 : lCC current listed includes both the DC operating current and the frequency dependent component.
*2 : lCC active while Embedded Algorithm (Program or Erase) is in progress.
*3 : Addresses except A1, A0, (A-1) are fixed.
*4 : Automatic sleep mode enables the low power mode when address remain stable for 150 ns.
*5 : About VIH Min , it should be applied larger voltage.
*6 : Embedded Algorithm (Program or Erase) is in progress.(@5 MHz)
*7 : VID is only for Sector Group Protection operation and Autoselect mode.
54
MBM29XL12DF-70/80
■ AC CHARACTERISTICS
• Read Only Operations Characteristics
Value *
Symbol
Parameter
Condition
JEDEC
Standard
Read Cycle Time
tAVAV
tRC
Address to Output Delay
tAVQV
tACC
Page Read Cycle Time
—
tPRC
Page Address to Output Delay
—
tPACC
Chip Enable to Output Delay
tELQV
tCE
Output Enable to Output Delay
tGLQV
tOE
Chip Enable to Output High-Z
tEHQZ
Output Enable to Output High-Z
70
80
Unit
Min
Max
Min
Max
70
—
80
—
ns
—
70
—
80
ns
25
—
30
—
ns
CE = VIL
OE = VIL
—
25
—
30
ns
OE = VIL
—
70
—
80
ns
—
—
25
—
30
ns
tDF
—
—
25
—
30
ns
tGHQZ
tDF
—
—
25
—
30
ns
Output Hold Time From Address,
CE or OE,
Whichever Occurs First
tAXQX
tOH
—
4
—
5
—
ns
RESET Pin Low to Read Mode
—
tREADY
—
—
20
—
20
ns
—
CE = VIL
OE = VIL
—
* : Test Conditions :
Output Load: VCC = 2.7 V to 3.1 V :1 TTL gate and 30pF (MBM29XL12DF-70/80)
Input rise and fall times: 5 ns
Input pulse levels: 0.0 V or VCC
Timing measurement reference level
Input: 0.5 × VCC
Output: 0.5 × VCC
55
MBM29XL12DF-70/80
• Write (Erase/Program) Operations
Value
Symbol
Parameter
JEDEC Standard
70
80
Unit
Min
Typ
Max
MIn
Typ
Max
Write Cycle Time
tAVAV
tWC
70
—
—
80
—
—
ns
Address Setup Time
tAVWL
tAS
0
—
—
0
—
—
ns
—
tASO
12
—
—
12
—
—
ns
tWLAX
tAH
45
—
—
45
—
—
ns
—
tAHT
0
—
—
0
—
—
ns
Data Setup Time
tDVWH
tDS
35
—
—
45
—
—
ns
Data Hold Time
tWHDX
tDH
0
—
—
0
—
—
ns
0
—
—
0
—
—
ns
—
tOEH
10
—
—
10
—
—
ns
CE High During Toggle Bit Polling
—
tCEPH
20
—
—
20
—
—
ns
OE High During Toggle Bit Polling
—
tOEPH
20
—
—
20
—
—
ns
Read Recover Time Before Write
tGHWL
tGHWL
0
—
—
0
—
—
ns
Read Recover Time Before Write
tGHEL
tGHEL
0
—
—
0
—
—
ns
CE Setup Time
tELWL
tCS
0
—
—
0
—
—
ns
WE Setup Time
tWLEL
tWS
0
—
—
0
—
—
ns
CE Hold Time
tWHEH
tCH
0
—
—
0
—
—
ns
WE Hold Time
tEHWH
tWH
0
—
—
0
—
—
ns
Write Pulse Width
tWLWH
tWP
35
—
—
35
—
—
ns
CE Pulse Width
tELEH
tCP
35
—
—
35
—
—
ns
Write Pulse Width High
tWHWL
tWPH
30
—
—
30
—
—
ns
CE Pulse Width High
tEHEL
tCPH
30
—
—
30
—
—
ns
—
12
—
—
12
—
tWHWH1
tWHWH1
—
6
—
—
6
—
tWHWH2
tWHWH2
—
0.5
—
—
0.5
—
s
VCC Setup Time
—
tVCS
50
—
—
50
—
—
µs
Rise Time to VID *2
—
tVIDR
500
—
—
500
—
—
ns
—
tVACCR
500
—
—
500
—
—
ns
—
tVLHT
4
—
—
4
—
—
µs
—
tWPP
100
—
—
100
—
—
µs
OE Setup Time to WE Active*2
—
tOESP
4
—
—
4
—
—
µs
2
—
tCSP
4
—
—
4
—
—
µs
Address Setup Time to OE Low During
Toggle Bit Polling
Address Hold Time
Address Hold Time from CE or OE High
During Toggle Bit Polling
Output Enable Hold
Time
Read
Toggle and Data Polling
Programming Operation
Double Word
Word
Sector Erase Operation*1
ACC 3
Rise Time to V
*
Voltage Transition Time *
2
Write Pulse Width*2
CE Setup Time to WE Active*
µs
(Continued)
56
MBM29XL12DF-70/80
(Continued)
Value
Symbol
Parameter
JEDEC Standard
70
80
Unit
Min
Typ
Max
Min
Typ
Max
Recover Time from RY/BY
—
tRB
0
—
—
0
—
—
ns
RESET Pulse Width
—
tRP
500
—
—
500
—
—
ns
RESET High Level Period Before Read
—
tRH
200
—
—
200
—
—
ns
Program/Erase Valid to RY/BY
Delay
—
tBUSY
—
—
90
—
—
90
ns
Delay Time from Embedded Output Enable
—
tEOE
—
—
70
—
—
80
ns
Erase Time-out Time
—
tTOW
50
—
—
50
—
—
µs
Erase Suspend Transition Time
—
tSPD
—
—
20
—
—
20
µs
DW/W Switching Low to Output High-Z
—
tFLQZ
—
—
30
—
—
30
ns
DW/W Switching High to Output Active
—
tFHQV
70
—
—
80
—
—
ns
*1 : This does not include the preprogramming time.
*2 : This timing is for Sector Group Protection operation.
*3 : This timing is limited for Accelerated Program operation only.
57
MBM29XL12DF-70/80
■ ERASE AND PROGRAMMING PERFORMANCE
Value
Parameter
Min
Typ
Max
Sector Erase Time
—
0.5
2
Double Word Programming Time
—
12
150
Unit
Comments
s
Excludes programming time
prior to erase
µs
Excludes system-level
overhead
Excludes system-level
overhead
Word Programming Time
—
6
100
Chip Programming Time
—
50.3
200
s
100,000
—
—
cycle
Erase/Program Cycle
—
Notes : • Typical Erase Conditions: TA = +25°C, VCC = 2.9 V
• Typical Program Conditions: TA = +25°C, VCC = 2.9 V, Data = Checker
■ SSOP PIN CAPACITANCE
Parameter
Symbol
Input Capacitance
CIN
Test Setup
Value
Unit
Typ
Max
VIN = 0
7.0
10.0
pF
Output Capacitance
COUT
VOUT = 0
6.0
12.0
pF
Control Pin Capacitance
CIN2
VIN = 0
7.5
11.0
pF
Typ
Max
Unit
Notes : • Test Conditions: TA = +25°C, f = 1.0 MHz
• DQ31/A-1 pin capacitance is stipulated by Output Capacitance.
■ FBGA PIN CAPACITANCE
Parameter
Test Setup
Input Capacitance
CIN
VIN = 0
TBD
TBD
pF
Output Capacitance
COUT
VOUT = 0
TBD
TBD
pF
Control Pin Capacitance
CIN2
VIN = 0
TBD
TBD
pF
Note :
58
Symbol
• Test Conditions: TA = +25°C, f = 1.0 MHz
• DQ31/A-1 pin capacitance is stipulated by Output Capacitance.
MBM29XL12DF-70/80
■ TIMING DIAGRAM
• Key to Switching Waveforms
WAVEFORM
INPUTS
OUTPUTS
Must Be
Steady
Will Be
Steady
May
Change
from H to L
Will Be
Change
from H to L
May
Change
from L to H
Will Be
Change
from L to H
“H” or “L”:
Any Change
Permitted
Changing,
State
Unknown
Does Not
Apply
Center Line is
HighImpedance
“Off” State
tRC
Address
Address Stable
tACC
CE
tOE
tDF
OE
tOEH
WE
tCE
Outputs
High-Z
tOH
Output Valid
High-Z
Read Operation Timing Diagram
59
MBM29XL12DF-70/80
A21 to A2
Same Page Address
A1 to A0
(A-1)
Aa
Ab
Ac
tRC
tPRC
tPRC
Ad
tACC
tCE
CE
OE
tOEH
tOE
tDF
WE
High-Z
Outputs
tPACC
tPACC
tPACC
tOH
tOH
tOH
Da
Db
Dc
tOH
Dd
Page Read Operation Timing Diagram
tRC
Address
Address Stable
tACC
CE
tRH
tRP
tRH
tCE
RESET
tOH
Outputs
High-Z
Outputs Valid
Hardware Reset/Read Operation Timing Diagram
60
MBM29XL12DF-70/80
CE
Rising edge of the last WE signal
WE
Entire program or
erase operations
RY/BY
tBUSY
RY/BY Timing Diagram during Program/Erase Operation Timing Diagram
WE
RESET
tRP
tRB
RY/BY
tREADY
RESET, RY/BY Timing Diagram
61
MBM29XL12DF-70/80
3rd Bus Cycle
Data Polling
555h
Address
PA
tWC
tAS
PA
tRC
tAH
CE
tCH
tCS
tCE
OE
tGHWL
tWP
tWPH
tOE
tWHWH1
WE
tDS
Data
A0h
tDF
tDH
PD
DQ7
DOUT
tOH
DOUT
Notes: • PA is address of the memory location to be programmed.
• PD is data to be programmed at word address (x16 mode).
• DQ7 is the output of the complement of the data written to the device.
• DOUT is the output of the data written to the device.
• Figure indicates last two bus cycles out of four bus cycle sequence.
• These waveforms are for the ×32 mode. (The addresses differ from ×16 mode.)
Alternate WE Controlled Program Operation Timing Diagram
62
MBM29XL12DF-70/80
3rd Bus Cycle
Address
Data Polling
PA
555h
tWC
tAS
PA
tAH
WE
tWS
tWH
OE
tGHEL
tCP
tCPH
tWHWH1
CE
tDS
Data
A0h
tDH
PD
DQ7
DOUT
Notes: • PA is address of the memory location to be programmed.
• PD is data to be programmed at word address (x16 mode).
• DQ7 is the output of the complement of the data written to the device.
• DOUT is the output of the data written to the device.
• Figure indicates last two bus cycles out of four bus cycle sequence.
• These waveforms are for the ×32 mode. (The addresses differ from ×16 mode.)
Alternate CE Controlled Program Operation Timing Diagram
63
MBM29XL12DF-70/80
Address
2AAh
555h
tWC
tAS
555h
555h
SA*
2AAh
tAH
CE
tCS
tCH
OE
tGHWL
tWP
tWPH
tDS
tDH
WE
AAh
Data
10h for Chip Erase
55h
80h
AAh
55h
10h/
30h
tVCS
VCC
* : SA is the sector address for Sector Erase. Address = 555h (Double Word). AAAh (Word) for
Chip Erase.
Note : These waveforms are for the ×32 mode. (The addresses differ from ×16 mode.)
Chip/Sector Erase Operation Timing Diagram
64
MBM29XL12DF-70/80
CE
t CH
t OE
t DF
OE
t OEH
WE
t CE
*
Data
DQ7
DQ7 =
Valid Data
DQ7
High-Z
t WHWH1 or 2
DQ6 to DQ0
Data
DQ6 to DQ0 = Output Flag
DQ6 to DQ0
Valid Data
High-Z
t EOE
* : DQ7 = Valid Data (The device has completed the Embedded operation.)
Data Polling during Embedded Algorithm Operation Timing Diagram
65
MBM29XL12DF-70/80
Address
tAHT tASO
tAHT tAS
CE
tCEPH
WE
tOEPH
tOEH
tOEH
OE
tDH
DQ 6/DQ2
tOE
Toggle
Data
Data
tCE
Toggle
Data
Toggle
Data
*
Stop
Toggling
tBUSY
RY/BY
*: DQ6 stops toggling (The device has completed the Embedded operation.)
AC Waveforms for Toggle Bit I during Embedded Algorithm Operations
66
Output
Valid
MBM29XL12DF-70/80
Read
Command
Read
Command
Read
Read
tRC
tWC
tRC
tWC
tRC
tRC
BA1
BA2
(555h)
BA1
BA2
(PA)
BA1
BA2
(PA)
Address
tAS
tACC
tAH
tAS
tAHT
tCE
CE
tOE
tCEPH
OE
tGHWL
tDF
tOEH
tWP
WE
tDS
Valid
Output
DQ
tDH
Valid
Intput
(A0h)
tDF
Valid
Output
Valid
Intput
(PD)
Valid
Output
Status
Note : This is example of Read for Bank 1 and Embedded Algorithm (program) for Bank 2.
BA1 : Address corresponding to Bank 1
BA2 : Address corresponding to Bank 2
Bank-to-Bank Read / Write(Program and Erase) Timing Diagram
Enter
Embedded
Erase
WE
Erase
Suspend
Erase
Enter Erase
Suspend Program
Erase Suspend
Read
Erase
Suspend
Program
Erase
Resume
Erase Suspend
Read
Erase
Erase
Complete
DQ6
DQ2 *
Toggle
DQ2 and DQ6
with OE or CE
* : DQ2 is read from the erase-suspended sector.
DQ2 vs. DQ6
67
MBM29XL12DF-70/80
CE
tCE
DW/W
Data Output
(DQ15 to DQ0)
DQ30 to DQ0
tELFH
Data Output
(DQ30 to DQ0)
tFHQV
DQ31/A-1
DQ31
A-1
Double Word Mode Configuration Timing Diagram
CE
DW/W
tELFL
DQ30 to DQ0
Data Output
(DQ15 to DQ0)
Data Output
(DQ30 to DQ0)
tACC
DQ31/A-1
DQ31
A-1
tFLQZ
Word Mode Configuration Timing Diagram
Falling edge of the last write signal
CE or WE
Input
Valid
DW/W
tSET
(tAS)
tHOLD (tAH)
DW/W Timing Diagram for Write Operations
68
MBM29XL12DF-70/80
Address
(A21 to A11)
SPAX
SPAY
A6, A2, A0
A5, A4, A3, A1
VID
VIH
A9
tVLHT
VID
VIH
OE
tVLHT
tVLHT
tVLHT
tWPP
WE
tOESP
tCSP
CE
01h
Data
tOE
tVCS
VCC
SPAX : Sector Group Address to be protected
SPAY : Next Sector Group Address to be protected
Note : A-1 is VIL in word mode.
Sector Group Protection Timing Diagram
69
MBM29XL12DF-70/80
VCC
tVIDR
tVCS
tVLHT
VID
VIH
RESET
CE
WE
tVLHT
Program Command Sequence
RY/BY
Unprotection period
Temporary Sector Group Unprotection Timing Diagram
70
tVLHT
MBM29XL12DF-70/80
VCC
tVCS
RESET
VID
VIH
tVLHT
tVIDR
tWC
Address
tWC
SGAX
SGAX
SGAY
A6, A2, A0
A5, A4,
A3, A1
CE
OE
TIME-OUT
tWP
WE
Data
60h
60h
40h
01h
60h
tOE
SGAX : Sector Group Address to be protected
SGAY : Next Sector Group Address to be protected
TIME-OUT : Time-Out window = 250 µs (Min)
Extended Sector Group Protection Timing Diagram
71
MBM29XL12DF-70/80
VCC
tVACCR
tVCS
tVLHT
VACC
VIH
ACC
CE
WE
tVLHT
Program Command Sequence
Acceleration period
Accelerated Program Timing Diagram
72
tVLHT
MBM29XL12DF-70/80
EMBEDDED ALGORITHM
Start
Write Program Command
Sequence
(See Below)
Data Polling Device
Embedded
Program
Algorithm
in progress
No
Verify Data
?
Yes
Increment Address
No
Last Address
?
Yes
Programming Completed
Program Command Sequence (Address/Command):
555h/AAh
2AAh/55h
555h/A0h
Program Address/Program Data
Notes : • The sequence is applied for ×32 mode.
• The addresses differ from ×16 mode.
Embedded ProgramTM Algorithm
73
MBM29XL12DF-70/80
EMBEDDED ALGORITHM
Start
Write Erase Command
Sequence
(See Below)
Data Polling or Toggle Bit
from Device
No
Data = FFh
?
Embedded
Erase
Algorithm
in progress
Yes
Erasure Completed
Chip Erase Command Sequence
(Address/Command):
Individual Sector/Multiple Sector
Erase Command Sequence
(Address/Command):
555h/AAh
555h/AAh
2AAh/55h
2AAh/55h
555h/80h
555h/80h
555h/AAh
555h/AAh
2AAh/55h
2AAh/55h
555h/10h
Sector Address/30h
Sector Address/30h
Additional sector
erase commands
are optional.
Sector Address/30h
Note : The sequence is applied for ×32 mode.
The addresses differ from ×16 mode.
Embedded EraseTM Algorithm
74
MBM29XL12DF-70/80
VA = Address for programming
= Any of the sector addresses
within the sector being erased
during sector erase or multiple
sector erase operation.
= Any of the sector addresses
within the sector not being
protected during chip erase
operation.
Start
Read
DQ7 to DQ0
Addr. = VA
DQ7 = Data?
Yes
No
No
DQ5 = 1?
Yes
Read
DQ7 to DQ0
Addr. = VA
DQ7 = Data?
*
Yes
No
Fail
Pass
* : DQ7 is rechecked even if DQ5 = “1” because DQ7 may change simultaneously with DQ5.
Data Polling Algorithm
75
MBM29XL12DF-70/80
VA = Bank address being excuted
Embedded Algorithm
Start
Read
DQ7 to DQ0
Addr. = VA
*1
Read
DQ7 to DQ0
Addr. = VA
*1
DQ6
= Toggle?
No
Yes
No
DQ5 = 1?
Yes
Read DQ7 to DQ0
Addr. = VA
Read DQ7 to DQ0
Addr. = VA
DQ6
= Toggle?
*1, *2
*1, *2
No
Yes
Program/Erase
Operation Not
Complete, Write
Reset Command
Program/Erase
Operation Complete
*1 : Read toggle bit twice to determine whether it is toggling.
*2 : Recheck toggle bit because it may stop toggling as DQ5 changes to “1”.
Toggle Bit Algorithm
76
MBM29XL12DF-70/80
Start
Setup Sector Group Addr.
(A21, A20, A19, A18, A17,
A16, A15, A14, A13, A12)
PLSCNT = 1
OE = VID, A9 = VID,
CE = VIL, RESET = VIH
A6 = A2 = A0 = VIL,
A5 = A4 = A3 = A1 = VIH
Activate WE Pulse
Time out 100 µs
Increment PLSCNT
WE = V IH, CE = OE = V IL
(A9 should remain VID)
Read from Sector Group
(Addr. = SPA,
A6 = A2 = A0 = VIL,
A5 = A4 = A3 = A1 = VIH ) *
No
No
PLSCNT = 25?
Yes
Data = 01h?
Yes
Yes
Remove VID from A9
Write Reset Command
Protect Another Sector
Group ?
No
Device Failed
Remove VID from A9
Write Reset Command
Sector Group Protection
Completed
* : A-1 is VIL in word mode.
Sector Group Protection Algorithm
77
MBM29XL12DF-70/80
Start
RESET = VID
*1
Perform Erase or
Program Operation
RESET = VIH
Temporary Sector Group
Unprotection Completed
*2
*1 : All protected sector groups are unprotected.
*2 : All previously protected sector groups are reprotected once again.
Temporary Sector Group Unprotection Algorithm
78
MBM29XL12DF-70/80
Start
RESET = VID
Wait to 4 µs
Device is Operating in
Temporary Sector Group
Unprotection Mode
No
Extended Sector Group
Protection Entry?
Yes
To Setup Sector Group Protection
Write XXXh/60h
PLSCNT = 1
(
To Protect Sector Group
Write 60h to SGA
A6 = A2 = A0 = VIL,
A5 = A4 = A3 = A1 =VIH
)
Time out 250 µs
To Verify Sector Group Protection
Write 40h to SGA
A6 = A2 = A0 = VIL,
A5 = A4 = A3 = A1=VIH
Increment PLSCNT
(
)
Read from Sector Group Address
(Addr. = SGA,
A6 = A2 = A0 = VIL,
A5 = A4 = A3 = A1 = VIH)*
No
Setup Next SGA
PLSCNT = 25?
Yes
Remove VID from RESET
Write Reset Command
No
Data = 01h?
Yes
Yes
Protect Other Sector
Group?
No
Remove VID from RESET
Write Reset Command
Device Failed
Sector Group Protection
Completed
* : A-1 is VIL in word mode.
Extended Sector Group Protection Algorithm
79
MBM29XL12DF-70/80
FAST MODE ALGORITHM
Start
555h/AAh
Set Fast Mode
2AAh/55h
555h/20h
XXXh/A0h
Program Address/Program Data
Data Polling Device
Verify Data?
No
In Fast Program
Yes
No
Increment Address
Last Address
?
Yes
Programming Completed
BA/90h
Reset Fast Mode
XXXh/F0h
Embedded Program Algorithm for Fast Mode
80
MBM29XL12DF-70/80
Start
HiddenROM Entry
PPB Program
Operation
DQ 0 = 1?
No
Yes
HiddenROM Exit
Yes
HiddenROM Exit
Protect Another
?
No
PPB Protection
Completed
PPB Protection Algorithm
81
MBM29XL12DF-70/80
Start
HiddenROM Entry
DPB Program
Operation
Yes
Protect Another
?
No
HiddenROM Exit
DPB Protection Algorithm
82
MBM29XL12DF-70/80
Start
Start
HiddenROM Entry
Read Auto-select
DPB/PPB & PPB
Lock Bit Status
Command
PPB Bit Status
DQ0 = 0
(Unprotected)
DQ0 = 1
(Protected)
DPB/PPB
PPB lock bit
PPB Protection Status
DQ0 = 0
(Unprotected)
DQ0 = 1
(Protected)
Note: This output indicates
the “OR” between DPB
and PPB
DQ1 = 0
(Unprotected)
DQ1 = 1
(Protected)
Note: This output indicates
PPB lock bit
DPB/PPB & PPB Lock Bit Status
Protection Status
83
MBM29XL12DF-70/80
Start
Addr. = AAAh
Data = AAh
HiddenROM Entry
Addr. = 555h
Data = 55h
repeat
4-times
Password Program
Operation *
Addr. = AAAh
Data = 38h
Addr. = XX0h to XX3h
Data = PD0 to PD3
* : Password Program (word mode)
Password Mode Set
84
Password Verify
HiddenROM Exit
MBM29XL12DF-70/80
Password Mode Choice Method
Start
Password Program
Password Protection
Mode
Bit Program
Password Verify
Correct?
Reset Command
Yes
No
No (Time out)
Reset Command
DQ0 = 0?
Yes
Reset Command
Program Complete
Password Sector Protect Algorithm
85
MBM29XL12DF-70/80
PPB Lock Clear in Password Mode
Start
Password Unlock
Password Unlock
No (Time out)
RY/BY = H?
Yes
No
DPB/PPB/PPB Lock
Bit Status
DQ0 = 1?
Yes
Password/Unlock
Complete
All PPB Erase
Reset Command
No (Time out)
DQ0 = 0?
Yes
Program Complete
PPB Lock Bit Clear in Password Mode
86
Reset Command
MBM29XL12DF-70/80
■ ORDERING INFORMATION
MBM29XL12D
F
70
PFV
PACKAGE TYPE
PFV = 90-pin Shrink Outline L-leaded Package
(SSOP)
PBT = 96-ball Fine Pitch Ball Grid Array
Package (FBGA)
SPEED OPTION
See "Product Selector Guide".
DEVICE REVISION
DEVICE NUMBER/DESCRIPTION
MBM29XL12D
128 Mega-bit (8M × 16-Bit or 4M × 32-Bit) Page Mode Flash Memory
3.0 V-only Read, Program, and Erase
Part Number
Package
Access Time (ns)
MBM29XL12DF 70PFV
MBM29XL12DF 80PFV
90-pin plastic SSOP
(FPT-90P-M01)
70
80
MBM29XL12DF 70PBT
MBM29XL12DF 80PBT
96-ball plastic FBGA
(BGA-96P-M02)
70
80
Remarks
87
MBM29XL12DF-70/80
■ PACKAGE DIMENSIONS
Note 1) *1 : These dimensions include resin protrusion.
Note 2) *2 : These dimensions do not include resin protrusion.
Note 3) Pins width and pins thickness include plating thickness.
Note 4) Pins width do not include tie bar cutting remainder.
90-pin plastic SSOP
(FPT-90P-M01)
*1 23.70±0.30(.933±.012)
90
1.80±0.10
(Mounting height)
(.071±.004)
0.55±0.10
(Stand off)
(.022±.004)
46
"A"
16.00±0.30
(.630±.012)
*213.30±0.20
(.524±.008)
INDEX
1
Details of "A" part
45
0.50(.020)
0.22±0.05
(.009±.002)
0.08(.003)
M
0.17
.007
+0.05
–0.03
+.002
–.001
0˚~8˚
+0.12
0.88 –0.15
+.005
.035 –.006
0.25(.010)
0.08(.003)
C
2003 FUJITSU LIMITED F90001S-c-2-2
Dimensions in mm (inches)
Note : The values in parentheses are reference values.
(Continued)
88
MBM29XL12DF-70/80
(Continued)
96-ball plastic FBGA
(BGA-96P-M02)
+0.15
1.05 –0.10
14.50±0.10(.571±.004)
+.006
(Mounting height)
.041 –.004
0.38±0.10
(Stand off)
(.015±.004)
0.40(.016)
REF
0.80(.031)
REF
B
0.40(.016)
REF
0.80(.031)
REF
11
10
9
8
7
6
5
4
3
2
1
A
9.50±0.10
(.374±.004)
0.10(.004) S
R Q P N M L K J H G F E D C B A
INDEX AREA
S
INDEX SIDE
96-ø0.45±0.05
(96-ø.018±.002)
C
0.08(.003)
M
S A B
2003 FUJITSU LIMITED B96002S-c-1-1
Dimensions in mm (inches)
Note : The values in parentheses are reference values.
89
MBM29XL12DF-70/80
FUJITSU LIMITED
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