HD74ALVCH16269 12-bit to 24-bit Registered Bus Transceivers with 3-state Outputs ADE-205-136 (Z) Preliminary 1st. Edition May 1996 Description The HD74ALVCH16269 is used in applications where two separate ports must be multiplexed onto, or demultiplexed from, a single port. The device is particularly suitable as an interface between synchronous DRAMs and high speed microprocessors. Data is stored in the internal B port registers on the low to high transition of the clock (CLK) input when the appropriate clock enable (CLKENA) inputs are low. Proper control of these inputs allows two sequential 12-bit words to be presented as a 24-bit word on the B port. For data transfer in the B to A direction, a single storage register is provided. The select (SEL) line selects 1B or 2B data for the A outputs. The register on the A output permits the fastest possible data transfer, thus extending the period that the data is valid on the bus. The control terminals are registered so that all transactions are synchronous with CLK. Data flow is controlled by the active low output enables (OEA, OEB1, OEB2). Active bus hold circuitry is provided to hold unused or floating data inputs at a valid logic level. Features • VCC = 2.3 V to 3.6 V • Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C) • Typical VOH undershoot > 2.0 V (@VCC = 3.3 V, Ta = 25°C) • High output current ±24 mA (@VCC = 3.0 V) • Bus hold on data inputs eliminates the need for external pullup / pulldown resistors HD74ALVCH16269 Function Table Inputs Outputs CLK OEA OEB A 1B, 2B ↑ H H Z Z ↑ H L Z Active ↑ L H Active Z ↑ L L Active Active Output enable Inputs CLKENA1 Outputs CLKENA2 CLK A 1B 2B *1 H H X X 1B0 2B0 L X ↑ L L X L X ↑ H H X X L ↑ L X L X L ↑ H X H *1 A-to-B storage (OEB = L) Inputs Output A CLK SEL 1B 2B X H X X A0 *1 X L X X A0 *1 ↑ H L X L ↑ H H X H ↑ L X L L ↑ L X H H B-to-A storage (OEA = L) H : High level L : Low level X : Immaterial Z : High impedance ↑ : Low to high transition Note: 1. Output level before the indicated steady state input conditions were established. HD74ALVCH16269 Pin Arrangement 56 OEB2 OEA 1 OEB1 2 55 CLKENA2 2B3 3 54 2B4 GND 4 53 GND 2B2 5 52 2B5 2B1 6 VCC 7 51 2B6 A1 8 49 2B7 A2 9 48 2B8 A3 10 47 2B9 50 VCC GND 11 46 GND A4 12 45 2B10 A5 13 44 2B11 A6 14 43 2B12 A7 15 42 1B12 A8 16 41 1B11 A9 17 40 1B10 GND 18 39 GND A10 19 38 1B9 A11 20 37 1B8 A12 21 36 1B7 VCC 22 35 VCC 1B1 23 34 1B6 1B2 24 33 1B5 GND 25 32 GND 1B3 26 31 1B4 30 CLKENA1 NC 27 SEL 28 29 CLK (Top view) HD74ALVCH16269 Absolute Maximum Ratings Item Supply voltage Input voltage *1, 2 Symbol Ratings Unit VCC –0.5 to 4.6 V VI –0.5 to 4.6 V –0.5 to VCC +0.5 Output voltage *1, 2 Conditions Except I/O ports I/O ports VO –0.5 to VCC +0.5 V Input clamp current I IK –50 mA VI < 0 Output clamp current I OK ±50 mA VO < 0 or VO > VCC Continuous output current IO ±50 mA VO = 0 to VCC TSSOP ±100 Maximum power dissipation at Ta = 55°C (in still air) *3 PT 1 W Storage temperature Tstg –65 to 150 °C Notes: Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. 1. The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed. 2. This value is limited to 4.6 V maximum. 3. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils. Recommended Operating Conditions Item Symbol Min Max Unit Supply voltage VCC 2.3 3.6 V Input voltage VI 0 VCC V Output voltage VO 0 VCC V High level output current I OH — –12 mA — –12 VCC = 2.7 V — –24 VCC = 3.0 V — 12 — 12 VCC = 2.7 V — 24 VCC = 3.0 V Low level output current I OL mA Input transition rise or fall rate ∆t / ∆v 0 10 ns / V Operating temperature Ta –40 85 °C Note: Unused control inputs must be held high or low to prevent them from floating. Conditions VCC = 2.3 V VCC = 2.3 V HD74ALVCH16269 Logic Diagram 29 CLK C1 2 OEB1 1D C1 56 OEB2 1D 30 CLKENA1 55 CLKENA2 C1 28 SEL 1D 1 OEA 1D C1 A1 8 C1 G1 1 1 1D CE C1 1D CE C1 1D 1 of 12 Channels 23 6 1B1 2B1 HD74ALVCH16269 Electrical Characteristics (Ta = –40 to 85°C) Item Symbol VCC (V) *1 Input voltage VIH VIL Output voltage VOH Min Max Unit 2.3 to 2.7 1.7 — V 2.7 to 3.6 2.0 — 2.3 to 2.7 — 0.7 2.7 to 3.6 — 0.8 I OH = –100 µA Min to Max VCC–0.2 — 2.3 2.0 — I OH = –6 mA, VIH = 1.7 V 2.3 1.7 — I OH = –12 mA, VIH = 1.7 V 2.7 2.2 — I OH = –12 mA, VIH = 2.0 V 3.0 2.4 — I OH = –12 mA, VIH = 2.0 V 3.0 2.0 — I OH = –24 mA, VIH = 2.0 V Min to Max — 0.2 I OL = 100 µA 2.3 — 0.4 I OL = 6 mA, VIL = 0.7 V 2.3 — 0.7 I OL = 12 mA, VIL = 0.7 V 2.7 — 0.4 I OL = 12 mA, VIL = 0.8 V 3.0 — 0.55 I OL = 24 mA, VIL = 0.8 V I IN 3.6 — ±5 I IN (hold) 2.3 45 — VIN = 0.7 V 2.3 –45 — VIN = 1.7 V 3.0 75 — VIN = 0.8 V 3.0 –75 — VIN = 2.0 V 3.6 — ±500 VIN = 0 to 3.6 V I OZ 3.6 — ±10 µA VOUT = VCC or GND Quiescent supply current I CC 3.6 — 40 µA VIN = VCC or GND 3.0 to 3.6 — 750 µA VIN = one input at (VCC–0.6) V, other inputs at V CC or GND VOL Input current Off state output current *2 ∆I CC V Test Conditions µA VIN = VCC or GND Notes: 1. For conditions shown as Min or Max, use the appropriate values under recommended operating conditions. 2. For I/O ports, the parameter I OZ includes the input leakage current. HD74ALVCH16269 Switching Characteristics (Ta = –40 to 85°C) Item Symbol VCC (V) Min Typ Max Unit 2.5±0.2 135 — — MHz 2.7 135 — — 3.3±0.3 135 — — t PLH 2.5±0.2 1.0 — 8.8 t PHL 2.7 — — 7.3 3.3±0.3 1.0 — 6.2 2.5±0.2 1.0 — 7.0 2.7 — — 5.8 3.3±0.3 1.0 — 5.0 t ZH 2.5±0.2 1.0 — 8.4 t ZL 2.7 — — 6.7 3.3±0.3 1.0 — 6.1 2.5±0.2 1.0 — 8.1 2.7 — — 6.2 3.3±0.3 1.0 — 5.9 t HZ 2.5±0.2 1.4 — 8.3 t LZ 2.7 — — 6.9 3.3±0.3 1.0 — 6.1 2.5±0.2 1.5 — 7.7 2.7 — — 6.8 3.3±0.3 1.0 — 5.6 Maximum clock frequency f max Propagation delay time Output enable time Output disable time ns FROM (Input) TO (Output) CLK B A ns CLK B A ns CLK B A Input capacitance CIN 3.3 — 3.5 — pF Control inputs Output capacitance CIN / O 3.3 — 9.0 — pF A or B ports HD74ALVCH16269 Item Symbol VCC (V) Min Typ Max Unit FROM (Input) Setup time t su 2.5±0.2 2.0 — — ns A data before CLK↑ 2.7 2.0 — — 3.3±0.3 1.7 — — 2.5±0.2 2.2 — — 2.7 2.1 — — 3.3±0.3 1.8 — — 2.5±0.2 1.6 — — 2.7 1.6 — — 3.3±0.3 1.3 — — 2.5±0.2 1.0 — — CLKENA1 or 2.7 1.2 — — CLKENA2 before CLK↑ 3.3±0.3 0.9 — — 2.5±0.2 1.5 — — 2.7 1.6 — — 3.3±0.3 1.3 — — 2.5±0.2 0.7 — — 2.7 0.6 — — 3.3±0.3 0.6 — — 2.5±0.2 0.7 — — 2.7 0.6 — — 3.3±0.3 0.6 — — 2.5±0.2 1.1 — — 2.7 0.7 — — 3.3±0.3 0.7 — — 2.5±0.2 1.0 — — CLKENA1 or 2.7 0.8 — — CLKENA2 after CLK↑ 3.3±0.3 1.1 — — 2.5±0.2 0.8 — — 2.7 0.8 — — 3.3±0.3 0.8 — — 2.5±0.2 3.3 — — 2.7 3.3 — — 3.3±0.3 3.3 — — Hold time Pulse width th tw B data before CLK↑ SEL before CLK↑ OE before CLK↑ ns A data after CLK↑ B data after CLK↑ SEL aftrer CLK↑ OE after CLK↑ ns CLK “H” or “L” HD74ALVCH16269 • Test Circuit See under table 500 Ω S1 OPEN GND *1 C L = 50 pF 500 Ω Load Circuit for Outputs Symbol t PLH / t PHL t su / t h / t w t ZH/ t HZ t ZL / t LZ Vcc=2.5±0.2V Vcc=2.7V, 3.3±0.3V OPEN OPEN GND GND 4.6 V 6.0 V Note: 1. C L includes probe and jig capacitance. HD74ALVCH16269 • Waveforms – 1 tf tr 90 % Input VIH 90 % Vref Vref 10 % 10 % GND t PHL t PLH VOH Output Vref Vref VOL • Waveforms – 2 tr VIH 90 % Vref Timing Input 10 % tsu GND th VIH Data Input Vref Vref GND tw VIH Input Vref Vref GND HD74ALVCH16269 • Waveforms – 3 Output Control tf tr VIH 90 % 90 % Vref Vref 10 % t ZL 10 % GND t LZ ≈VOH1 Vref Waveform - A t ZH Waveform - B VOL + 0.3 V t HZ VOH – 0.3 V Vref VOL VOH ≈VOL1 TEST VIH Vref VOH1 VOL1 Vcc=2.5±0.2V Vcc=2.7V, 3.3±0.3V 2.3 V 2.7 V 1.2 V 2.3 V 1.5 V 3.0 V GND GND Notes: 1. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Zo = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. 2. Waveform – A is for an output with internal conditions such that the output is low except when disabled by the output control. 3. Waveform – B is for an output with internal conditions such that the output is high except when disabled by the output control. 4. The output are measured one at a time with one transition per measurement. HD74ALVCH16269 Package Dimensions Unit : mm +0.3 14.00 –0.1 29 6.10 +0.3 –0.1 56 1 0.50 28 0.20 +0.1 –0.05 0.08 M 8.10 ± 0.3 0.40 Max 0.15 ± 0.05 0.10 0.05 ± 0.05 1.2 Max 10° Max 0.50 ± 0.1 Hitachi code EIAJ code JEDEC code TTP-56D — — Cautions 1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual property rights, in connection with use of the information contained in this document. 2. Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. 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Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as failsafes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the Hitachi product. 5. This product is not designed to be radiation resistant. 6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Hitachi. 7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor products. Hitachi, Ltd. Semiconductor & Integrated Circuits. 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