HITACHI HD74ALVCH162821

HD74ALVCH162821
3.3-V 20-bit Bus Interface Flip Flops with 3-state Outputs
ADE-205-186A (Z)
2nd. Edition
September 1997
Description
The HD74ALVCH162821 can be used as two 10-bit flip flops or one 20-bit flip flop. The 20 flip flops are
edge triggered D-type flip flops. On the positive transition of the clock (CLK) input, the device provides
true data at the Q outputs. A buffered output enable (OE) input can be used to place the ten outputs in
either a normal logic state (high or low level) or a high impedance state. In the high impedance state, the
outputs neither load nor drive the bus lines significantly. The high impedance state and increased drive
provide the capability to drive bus line without need for interface or pullup components. The output enable
(OE) input does not affect the internal operations of the flip flops. Old data can be retained or new data can
be entered while the outputs are in the high impedance state. Active bus hold circuitry is provided to hold
unused or floating data inputs at a valid logic level. All outputs, which are designed to sink up to 12 mA,
include 26 Ω resistors to reduce overshoot and undershoot.
Features
• VCC = 2.3 V to 3.6 V
• Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C)
• Typical VOH undershoot > 2.0 V (@VCC = 3.3 V, Ta = 25°C)
• High output current ±12 mA (@VCC = 3.0 V)
• Bus hold on data inputs eliminates the need for external pullup / pulldown resistors
• All outputs have equivalent 26 Ω series resistors, so no external resistors are required.
HD74ALVCH162821
Function Table
Inputs
Output Q
OE
CLK
D
L
↑
H
H
L
↑
L
L
L
H or L
X
Q0 *1
H
X
X
Z
H : High level
L : Low level
X : Immaterial
Z : High impedance
↑ : Low to high transition
Note: 1. Output level before the indicated steady state input conditions were established.
2
HD74ALVCH162821
Pin Arrangement
1OE 1
56 1CLK
1Q1 2
55 1D1
1Q2 3
54 1D2
GND 4
53 GND
1Q3 5
52 1D3
1Q4 6
VCC 7
51 1D4
1Q5 8
49 1D5
1Q6 9
48 1D6
1Q7 10
47 1D7
GND 11
46 GND
1Q8 12
45 1D8
1Q9 13
44 1D9
1Q10 14
43 1D10
2Q1 15
42 2D1
2Q2 16
41 2D2
2Q3 17
40 2D3
GND 18
39 GND
2Q4 19
38 2D4
2Q5 20
37 2D5
2Q6 21
36 2D6
VCC 22
35 VCC
2Q7 23
34 2D7
2Q8 24
33 2D8
GND 25
32 GND
2Q9 26
31 2D9
2Q10 27
30 2D10
2OE 28
29 2CLK
50 VCC
(Top view)
3
HD74ALVCH162821
Absolute Maximum Ratings
Item
Symbol
Ratings
Unit
VCC
–0.5 to 4.6
V
VI
–0.5 to 4.6
V
VO
–0.5 to VCC +0.5
V
Input clamp current
I IK
–50
mA
VI < 0
Output clamp current
I OK
±50
mA
VO < 0 or VO > VCC
Continuous output current
IO
±50
mA
VO = 0 to VCC
VCC, GND current / pin
I CC or IGND
±100
mA
Maximum power dissipation
at Ta = 55°C (in still air) *3
PT
1
W
Storage temperature
Tstg
–65 to 150
°C
Input voltage
*1
Output voltage
Notes:
*1, 2
Conditions
TSSOP
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage
to the device. These are stress ratings only, and functional operation of the device at these or
any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute maximum rated conditions for extended periods may affect device
reliability.
1. The input and output negative voltage ratings may be exceeded if the input and output clamp
current ratings are observed.
2. This value is limited to 4.6 V maximum.
3. The maximum package power dissipation is calculated using a junction temperature of 150°C
and a board trace length of 750 mils.
Recommended Operating Conditions
Item
Symbol
Min
Max
Unit
Supply voltage
VCC
2.3
3.6
V
Input voltage
VI
0
VCC
V
Output voltage
VO
0
VCC
V
High level output current
I OH
—
–6
mA
—
–8
VCC = 2.7 V
—
–12
VCC = 3.0 V
—
6
—
8
VCC = 2.7 V
—
12
VCC = 3.0 V
Low level output current
I OL
mA
Input transition rise or fall rate
∆t / ∆v
0
10
ns / V
Operating temperature
Ta
–40
85
°C
Note: Unused control inputs must be held high or low to prevent them from floating.
4
Conditions
VCC = 2.3 V
VCC = 2.3 V
HD74ALVCH162821
Logic Diagram
1OE
1CLK
1
56
1 of 10
Channels
1D1
55
C1
2
1Q1
1D
To nine other channels
2OE
2CLK
28
29
1 of 10
Channels
2D1
42
C1
15
2Q1
1D
To nine other channels
5
HD74ALVCH162821
Electrical Characteristics (Ta = –40 to 85°C)
Item
Symbol VCC (V) *1
Input voltage
VIH
VIL
Output voltage
VOH
Min
Max
Unit
2.3 to 2.7
1.7
—
V
2.7 to 3.6
2.0
—
2.3 to 2.7
—
0.7
2.7 to 3.6
—
0.8
I OH = –100 µA
Min to Max VCC–0.2
—
2.3
1.9
—
I OH = –4 mA, VIH = 1.7 V
2.3
1.7
—
I OH = –6 mA, VIH = 1.7 V
3.0
2.4
—
I OH = –6 mA, VIH = 2.0 V
2.7
2.0
—
I OH = –8 mA, VIH = 2.0 V
3.0
2.0
—
I OH = –12 mA, VIH = 2.0 V
Min to Max —
0.2
I OL = 100 µA
2.3
—
0.4
I OL = 4 mA, VIL = 0.7 V
2.3
—
0.55
I OL = 6 mA, VIL = 0.7 V
3.0
—
0.55
I OL = 6 mA, VIL = 0.8 V
2.7
—
0.6
I OL = 8 mA, VIL = 0.8 V
3.0
—
0.8
I OL = 12 mA, VIL = 0.8 V
I IN
3.6
—
±5
I IN (hold)
2.3
45
—
VIN = 0.7 V
2.3
–45
—
VIN = 1.7 V
3.0
75
—
VIN = 0.8 V
3.0
–75
—
VIN = 2.0 V
3.6
—
±500
VIN = 0 to 3.6 V
I OZ
3.6
—
±10
µA
VOUT = VCC or GND
Quiescent supply current I CC
3.6
—
40
µA
VIN = VCC or GND
3.0 to 3.6
—
750
µA
VIN = one input at (VCC–0.6)
V,
other inputs at V CC or GND
VOL
Input current
Off state output current
*2
∆I CC
V
Test Conditions
µA
VIN = VCC or GND
Notes: 1. For conditions shown as Min or Max, use the appropriate values under recommended operating
conditions.
2. For I/O ports, the parameter I OZ includes the input leakage current.
6
HD74ALVCH162821
Switching Characteristics (Ta = –40 to 85°C)
Item
Symbol VCC (V)
Min
Typ
Max
Unit
2.5±0.2
150
—
—
MHz
2.7
150
—
—
3.3±0.3
150
—
—
t PLH
2.5±0.2
1.0
—
6.9
t PHL
2.7
—
—
6.0
3.3±0.3
1.0
—
5.1
t ZH
2.5±0.2
1.0
—
7.6
t ZL
2.7
—
—
6.9
3.3±0.3
1.0
—
5.7
t HZ
2.5±0.2
1.4
—
6.4
t LZ
2.7
—
—
5.5
3.3±0.3
1.0
—
5.1
2.5±0.2
4.4
—
—
2.7
3.9
—
—
3.3±0.3
3.4
—
—
2.5±0.2
0
—
—
2.7
0
—
—
3.3±0.3
0
—
—
2.5±0.2
3.3
—
—
2.7
3.3
—
—
3.3±0.3
3.3
—
—
3.3
—
3.5
—
3.3
—
6.0
—
3.3
—
7.0
—
Maximum clock frequency f max
Propagation delay time
Output enable time
Output disable time
Setup time
Hold time
Pulse width
Input capacitance
Output capacitance
t su
th
tw
CIN
CO
FROM
(Input)
TO
(Output)
ns
CLK
Q
ns
OE
Q
ns
OE
Q
ns
ns
ns
pF
Control inputs
Data inputs
pF
7
HD74ALVCH162821
• Test Circuit
See under table
500 Ω
S1
OPEN
GND
*1
C L = 50 pF
500 Ω
Load Circuit for Outputs
Symbol
t PLH / t PHL
t su / t h / t w
t ZH/ t HZ
t ZL / t LZ
Vcc=2.5±0.2V
Vcc=2.7V,
3.3±0.3V
OPEN
OPEN
GND
GND
4.6 V
6.0 V
Note: 1. C L includes probe and jig capacitance.
8
HD74ALVCH162821
• Waveforms – 1
tf
tr
90 %
Input
VIH
90 %
Vref
Vref
10 %
10 %
GND
t PHL
t PLH
VOH
Output
Vref
Vref
VOL
• Waveforms – 2
tr
VIH
90 %
Vref
Timing Input
10 %
tsu
GND
th
VIH
Data Input
Vref
Vref
GND
tw
VIH
Input
Vref
Vref
GND
9
HD74ALVCH162821
• Waveforms – 3
Output
Control
tf
tr
VIH
90 %
90 %
Vref
Vref
10 %
t ZL
10 %
GND
t LZ
≈VOH1
Vref
Waveform - A
t ZH
Waveform - B
VOL + 0.3 V
t HZ
VOH – 0.3 V
Vref
VOL
VOH
≈VOL1
TEST
VIH
Vref
VOH1
VOL1
Vcc=2.5±0.2V
Vcc=2.7V,
3.3±0.3V
2.3 V
2.7 V
1.2 V
2.3 V
1.5 V
3.0 V
GND
GND
Notes: 1. All input pulses are supplied by generators having the following characteristics:
PRR ≤ 10 MHz, Zo = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
2. Waveform – A is for an output with internal conditions such that the output is low
except when disabled by the output control.
3. Waveform – B is for an output with internal conditions such that the output is high
except when disabled by the output control.
4. The output are measured one at a time with one transition per measurement.
10
HD74ALVCH162821
Package Dimensions
Unit : mm
+0.3
14.00 –0.1
29
6.10 +0.3
–0.1
56
28
0.15 ± 0.05
0.08 M
0.40 Max
0.10
1.20 max
0.20 +0.1
–0.05
0.50
0.05 Min
1
8.10 ± 0.3
10° Max
0.50 ± 0.1
Hitachi code
EIAJ code
JEDEC code
TTP-56D
—
—
11
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