HD74ALVCH162721 3.3-V 20-bit Flip Flops with 3-state Outputs ADE-205-184B (Z) 3rd. Edition December 1999 Description The HD74ALVCH162721’s twenty flip flops are edge triggered D-type flip flops with qualified clock storage. On the positive transition of the clock (CLK) input, the device provides true data at the Q outputs, provided that the clock enable (CLKEN) input is low. If CLKEN is high, no data is stored. A buffered output enable (OE) input can be used to place the twenty outputs in either a normal logic state (high or low level) or a high impedance state. In the high impedance state, the outputs neither load nor drive the bus lines significantly. The high impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components. The output enable (OE) input does not affect the internal operation of the flip flops. Old data can be retained or new data can be entered while the outputs are in the high impedance state. Active bus hold circuitry is provided to hold unused or floating data inputs at a valid logic level. All outputs, which are designed to sink up to 12 mA, include 26 Ω resistors to reduce overshoot and undershoot. Features • VCC = 2.3 V to 3.6 V • Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C) • Typical VOH undershoot > 2.0 V (@VCC = 3.3 V, Ta = 25°C) • High output current ±12 mA (@V CC = 3.0 V) • Bus hold on data inputs eliminates the need for external pullup / pulldown resistors • All outputs have equivalent 26 Ω series resistors, so no external resistors are required. HD74ALVCH162721 Function Table Inputs Output Q OE CLKEN CLK D L H X X Q0 *1 L L ↑ H H L L ↑ L L L L L or H X Q0 *1 H X X X Z H : High level L : Low level X : Immaterial Z : High impedance ↑ : Low to high transition Note: 1. Output level before the indicated steady state input conditions were established. 2 HD74ALVCH162721 Pin Arrangement OE 1 56 CLK Q1 2 55 D1 Q2 3 54 D2 53 GND GND 4 Q3 5 52 D3 Q4 6 VCC 7 51 D4 Q5 8 49 D5 Q6 9 48 D6 Q7 10 47 D7 50 VCC GND 11 46 GND Q8 12 45 D8 Q9 13 44 D9 Q10 14 43 D10 Q11 15 42 D11 Q12 16 41 D12 Q13 17 40 D13 GND 18 39 GND Q14 19 38 D14 Q15 20 37 D15 Q16 21 36 D16 VCC 22 35 VCC Q17 23 34 D17 Q18 24 33 D18 GND 25 32 GND Q19 26 31 D19 Q20 27 30 D20 29 CLKEN NC 28 (Top view) 3 HD74ALVCH162721 Absolute Maximum Ratings Item Symbol Ratings Unit VCC –0.5 to 4.6 V VI –0.5 to 4.6 V VO –0.5 to VCC +0.5 V Input clamp current I IK –50 mA VI < 0 Output clamp current I OK ±50 mA VO < 0 or VO > VCC Continuous output current IO ±50 mA VO = 0 to VCC VCC, GND current / pin I CC or IGND ±100 mA Maximum power dissipation at Ta = 55°C (in still air) *3 PT 1 W Storage temperature Tstg –65 to 150 °C Supply voltage Input voltage *1 Output voltage Notes: *1, 2 Conditions TSSOP Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. 1. The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed. 2. This value is limited to 4.6 V maximum. 3. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils. Recommended Operating Conditions Item Symbol Min Max Unit Supply voltage VCC 2.3 3.6 V Input voltage VI 0 VCC V Output voltage VO 0 VCC V High level output current I OH — –6 mA — –8 VCC = 2.7 V — –12 VCC = 3.0 V — 6 — 8 VCC = 2.7 V — 12 VCC = 3.0 V Low level output current I OL mA Input transition rise or fall rate ∆t / ∆v 0 10 ns / V Operating temperature Ta –40 85 °C Note: Unused control inputs must be held high or low to prevent them from floating. 4 Conditions VCC = 2.3 V VCC = 2.3 V HD74ALVCH162721 Logic Diagram OE CLK CLKEN D1 1 56 29 55 CE C1 1D 2 Q1 To nineteen other channels 5 HD74ALVCH162721 Electrical Characteristics (Ta = –40 to 85°C) Item Symbol VCC (V) *1 Input voltage VIH VIL Output voltage VOH Min Max Unit 2.3 to 2.7 1.7 — V 2.7 to 3.6 2.0 — 2.3 to 2.7 — 0.7 2.7 to 3.6 — 0.8 I OH = –100 µA Min to Max VCC–0.2 — 2.3 1.9 — I OH = –4 mA, VIH = 1.7 V 2.3 1.7 — I OH = –6 mA, VIH = 1.7 V 3.0 2.4 — I OH = –6 mA, VIH = 2.0 V 2.7 2.0 — I OH = –8 mA, VIH = 2.0 V 3.0 2.0 — I OH = –12 mA, VIH = 2.0 V Min to Max — 0.2 I OL = 100 µA 2.3 — 0.4 I OL = 4 mA, VIL = 0.7 V 2.3 — 0.55 I OL = 6 mA, VIL = 0.7 V 3.0 — 0.55 I OL = 6 mA, VIL = 0.8 V 2.7 — 0.6 I OL = 8 mA, VIL = 0.8 V 3.0 — 0.8 I OL = 12 mA, VIL = 0.8 V I IN 3.6 — ±5 I IN (hold) 2.3 45 — VIN = 0.7 V 2.3 –45 — VIN = 1.7 V 3.0 75 — VIN = 0.8 V 3.0 –75 — VIN = 2.0 V 3.6 — ±500 VIN = 0 to 3.6 V I OZ 3.6 — ±10 µA VOUT = VCC or GND Quiescent supply current I CC 3.6 — 40 µA VIN = VCC or GND 3.0 to 3.6 — 750 µA VIN = one input at (VCC–0.6) V, other inputs at V CC or GND VOL Input current Off state output current *2 ∆I CC V Test Conditions µA VIN = VCC or GND Notes: 1. For conditions shown as Min or Max, use the appropriate values under recommended operating conditions. 2. For I/O ports, the parameter I OZ includes the input leakage current. 6 HD74ALVCH162721 Switching Characteristics (Ta = –40 to 85°C) Item Symbol VCC (V) Min Typ Max Unit 2.5±0.2 150 — — MHz 2.7 150 — — 3.3±0.3 150 — — t PLH 2.5±0.2 1.0 — 6.7 t PHL 2.7 1.0 — 6.2 3.3±0.3 1.0 — 5.3 t ZH 2.5±0.2 1.0 — 7.2 t ZL 2.7 1.0 — 7.0 3.3±0.3 1.0 — 5.8 t HZ 2.5±0.2 1.0 — 6.3 t LZ 2.7 1.0 — 5.4 3.3±0.3 1.0 — 5.0 2.5±0.2 4.0 — — 2.7 3.6 — — 3.3±0.3 3.1 — — 2.5±0.2 3.4 — — 2.7 3.1 — — 3.3±0.3 2.7 — — 2.5±0.2 0 — — 2.7 0 — — 3.3±0.3 0 — — 2.5±0.2 0 — — 2.7 0 — — 3.3±0.3 0 — — 2.5±0.2 3.3 — — 2.7 3.3 — — 3.3±0.3 3.3 — — Maximum clock frequency f max Propagation delay time Output enable time Output disable time Setup time Hold time Pulse width t su th tw FROM (Input) TO (Output) ns CLK Q ns OE Q ns OE Q ns Data before CLK↑ CLKEN before CLK↑ ns Data after CLK↑ CLKEN after CLK↑ ns Input capacitance CIN 3.3 — 3.5 — pF Output capacitance CO 3.3 — 7.0 — pF 7 HD74ALVCH162721 • Test Circuit See under table 500 Ω S1 OPEN GND *1 C L = 50 pF 500 Ω Load Circuit for Outputs Symbol t PLH / t PHL t su / t h / t w t ZH/ t HZ t ZL / t LZ Vcc=2.5±0.2V Vcc=2.7V, 3.3±0.3V OPEN OPEN GND GND 4.6 V 6.0 V Note: 1. C L includes probe and jig capacitance. 8 HD74ALVCH162721 • Waveforms – 1 tf tr 90 % Input VIH 90 % Vref Vref 10 % 10 % GND t PHL t PLH VOH Output Vref Vref VOL • Waveforms – 2 tr VIH 90 % Vref Timing Input 10 % tsu GND th VIH Data Input Vref Vref GND tw VIH Input Vref Vref GND 9 HD74ALVCH162721 • Waveforms – 3 Output Control tf tr VIH 90 % 90 % Vref Vref 10 % t ZL 10 % GND t LZ ≈VOH1 Vref Waveform - A t ZH Waveform - B VOL + 0.3 V t HZ VOH – 0.3 V Vref VOL VOH ≈VOL1 TEST VIH Vref VOH1 VOL1 Vcc=2.5±0.2V Vcc=2.7V, 3.3±0.3V 2.3 V 2.7 V 1.2 V 2.3 V 1.5 V 3.0 V GND GND Notes: 1. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Zo = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. 2. Waveform – A is for an output with internal conditions such that the output is low except when disabled by the output control. 3. Waveform – B is for an output with internal conditions such that the output is high except when disabled by the output control. 4. The output are measured one at a time with one transition per measurement. 10 HD74ALVCH162721 Package Dimensions Unit : mm +0.3 14.00 –0.1 29 6.10 +0.3 –0.1 56 28 0.15 ± 0.05 0.08 M 0.40 Max 0.10 1.20 max 0.20 +0.1 –0.05 0.50 0.05 Min 1 8.10 ± 0.3 10° Max 0.50 ± 0.1 Hitachi code EIAJ code JEDEC code TTP-56D — — 11 HD74ALVCH162721 Cautions 1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual property rights, in connection with use of the information contained in this document. 2. Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However, contact Hitachi’s sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as failsafes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the Hitachi product. 5. This product is not designed to be radiation resistant. 6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Hitachi. 7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor products. Hitachi, Ltd. Semiconductor & Integrated Circuits. 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Ltd. 16 Collyer Quay #20-00 Hitachi Tower Singapore 049318 Tel: 535-2100 Fax: 535-1533 Hitachi Asia Ltd. Taipei Branch Office 3F, Hung Kuo Building. No.167, Tun-Hwa North Road, Taipei (105) Tel: <886> (2) 2718-3666 Fax: <886> (2) 2718-8180 Hitachi Asia (Hong Kong) Ltd. Group III (Electronic Components) 7/F., North Tower, World Finance Centre, Harbour City, Canton Road, Tsim Sha Tsui, Kowloon, Hong Kong Tel: <852> (2) 735 9218 Fax: <852> (2) 730 0281 Telex: 40815 HITEC HX Copyright ' Hitachi, Ltd., 1999. All rights reserved. Printed in Japan. 12