HD74HC646/HD74HC648 Octal Bus Transceivers/Registers with Multiplexed 3-state outputs Description Six control inputs enable this device to be used as a latched transceiver, unlatched transceiver or a combination of both. As a latched transceiver, data from one bus is stored for later retrieval by the other bus. Alternately real time bus data (unlatched) may be directly transferred from one bus to another. Circuit operation is determined by the Control G, Direction, Clock AB, Clock BA, Select AB, Select BA control inputs. The enable input, Contorl G, controls whether any bus outputs are enabled. The direction control Direction (DIR), determines which bus is enabled, and hence the direction data flows: The Select AB, Select BA inputs cotrol whether the latched data (stored in D type flip-flops), or the bus data (from other bus input pins) is transferred. Each set of flip-flops has its own clock Clock AB and Clock BA, for storing data. Data is latched on the rising edge of the clock. Features • • • • • High Speed Operation: tpd (Bus to Bus) = 14 ns typ (CL = 50 pF) High Output Current: Fanout of 15 LSTTL Loads Wide Operating Voltage: VCC = 2 to 6 V Low Input Current: 1 µA max Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C) HD74HC646/HD74HC648 Function Table Inputs Select Data I/O Data I/O Operation or Function Direction BA AB AB BA A1 thru A8 B1 thru B8 HD74HC646 HD74HC648 H X X X Z (Input) Z (Input) Isolation Isolation H X H H Z (Input) Z (Input) Store A & B data Store A & B data L L X X X L Output Z (Input) B real-time data to A bus B real-time data to A bus L L H H X H Output Z (Input) B stored data to A bus B stored data to A bus L L L L X H Output Z (Input) B stored data to A bus B stored data to A bus L H X X L X Z (Input) Output A real-time data to B bus A real-time data to B bus L H H H H X Z (Input) Output A stored data to B bus A stored data to B bus L H L L H X Z (Input) Output A stored data to B bus A stored data to B bus X Bus A X Real-time transfer Bus B to Bus A 2 Bus B G Bus A Clock Bus B Control Real-time transfer Bus A to Bus B Storage from A, B, or A and B Bus B Bus A Bus B Bus A HD74HC646/HD74HC648 Transfer stored data to A or B Pin Arrangement Clock AR 1 24 VCC Select AB 2 23 Clock BA Direciton 3 22 Select BA A1 4 21 Control G A2 5 20 B1 A3 6 19 B2 A4 7 18 B3 A5 8 17 B4 A6 9 16 B5 A7 10 15 B6 A8 11 14 B7 GND 12 13 B8 (Top view) 3 HD74HC646/HD74HC648 Absolute Maximum Ratings Item Symbol Rating Unit Supply voltage range VCC –0.5 to +7.0 V Input voltage VIN –0.5 to VCC + 0.5 V Output voltage VOUT –0.5 to VCC + 0.5 V Output current I OUT ±35 mA DC current drain per VCC , GND I CC, I GND ±75 mA DC input diode current I IK ±20 mA DC output diode current I OK ±20 mA Power Dissipation per package PT 500 mW Storage temperature Tstg –65 to +150 °C Logic Diagram HD74HC646 x7 VCC Q CBA CBA A1 D VCC D Q CAB CAB B1 CAB CBA SAB DIR SBA G 4 HD74HC646/HD74HC648 HD74HC648 x7 VCC Q CBA CBA A1 D VCC D Q CAB CAB B1 CAB CBA SAB DIR SBA G 5 HD74HC646/HD74HC648 DC Characteristics Ta = –40 to +85°C Ta = 25°C Item Symbol VCC (V) Min Typ Max Min Max Unit Input voltage VIH 2.0 1.5 — — 1.5 — V 4.5 3.15 — — 3.15 — 6.0 4.2 — — 4.2 — 2.0 — — 0.5 — 0.5 4.5 — — 1.35 — 1.35 6.0 — — 1.8 — 1.8 2.0 1.9 2.0 — 1.9 — 4.5 4.4 4.5 — 4.4 — 6.0 5.9 6.0 — 5.9 — 4.5 4.18 — — 4.13 — I OH = –6 mA 6.0 5.68 — — 5.63 — I OH = –7.8 mA 2.0 — 0.0 0.1 — 0.1 4.5 — 0.0 0.1 — 0.1 6.0 — 0.0 0.1 — 0.1 4.5 — — 0.26 — 0.33 I OL = 6 mA 6.0 — — 0.26 — 0.33 I OL = 7.8 mA VIL Output voltage VOH VOL Test Conditions V V V Vin = VIH or VIL I OH = –20 µA Vin = VIH or VIL I OL = 20 µA Off-state output current I OZ 6.0 — — ±0.5 — ±5.0 µA Vin = VIH or VIL, Vout = VCC or GND Input current Iin 6.0 — — ±0.1 — ±1.0 µA Vin = VCC or GND Quiescent supply current I CC 6.0 — — 4.0 40 µA Vin = VCC or GND, Iout = 0 µA 6 — HD74HC646/HD74HC648 AC Characteristics (CL = 50 pF, Input tr = tf = 6 ns) Ta = –40 to +85°C Ta = 25°C Item Symbol VCC (V) Min Typ Max Min Max Unit Test Conditions Maximum clock f max 2.0 — — 5 — 4 ns Clock AB to B or 4.5 — — 27 — 21 6.0 — — 32 — 25 Propagation delay t PLH 2.0 — — 170 — 215 time 4.5 — 14 34 — 43 6.0 — — 29 — 37 t PLH 2.0 — — 150 — 190 t PHL 4.5 — 14 30 — 38 6.0 — — 26 — 33 t PLH 2.0 — — 220 — 275 t PHL 4.5 — 18 44 — 55 6.0 — — 37 — 47 t PLH 2.0 — — 170 — 215 t PHL 4.5 — 15 34 — 43 6.0 — — 29 — 37 t PLH 2.0 — — 170 — 215 t PHL 4.5 — 16 34 — 43 6.0 — — 29 — 37 frequency t PHL Output enable t ZH 2.0 — — 150 — 190 time t ZL 4.5 — 17 30 — 38 6.0 — — 26 — 33 Output disable t LZ 2.0 — — 150 — 190 time t HZ 4.5 — 20 30 — 38 6.0 — — 26 — 33 2.0 100 — — 125 — 4.5 20 3 — 25 — 6.0 17 — — 21 — 2.0 5 — — 5 — 4.5 5 0 — 5 — 6.0 5 — — 5 — Setup time Hold time t su th Clock BA to A ns A or B input to B or A output (HD74HC646 only) ns A or B input to B or A output (HD74HC648 only) ns Clock BA or Clock AB input to A or B output ns Select BA or Select AB input to A or B output, with A or B high ns Select BA or Select AB input to A or B output, with A or B low ns Control G input or Direction to A or B output ns Control G input to A or B output ns ns 7 HD74HC646/HD74HC648 AC Characteristics (CL = 50 pF, Input tr = tf = 6 ns) (cont) Ta = –40 to +85°C Ta = 25°C Item Symbol VCC (V) Min Typ Max Min Max Unit Pulse width tw 2.0 80 — — 100 — ns 4.5 16 5 — 20 — 6.0 14 — — 17 — Output rise/fall t TLH 2.0 — — 60 — 75 time t THL 4.5 — 4 12 — 15 6.0 — — 10 — 13 — — 5 10 — 10 Input capacitance 8 Cin ns pF Test Conditions Unit: mm 13 13.4 15.0 Max 24 31.6 32.5 Max 12 1.2 15.24 0.48 ± 0.10 0.51 Min 2.54 ± 0.25 5.70 Max 2.13 Max 2.54 Min 1 + 0.11 0.25 – 0.05 0° – 15° Hitachi Code JEDEC EIAJ Weight (reference value) DP-24 Conforms Conforms 3.1 g Cautions 1. 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