HOLTEK HT48R06A-1

Preliminary
HT48R06A-1
8-Bit OTP Microcontroller
Features
·
·
·
·
·
·
·
·
·
Operating voltage:
fSYS=4MHz: 3.3V~5.5V
fSYS=8MHz: 4.5V~5.5V
13 bidirectional I/O lines
An interrupt input shared with an I/O line
8-bit programmable timer/event counter with
overflow interrupt and 8-stage prescaler
On-chip crystal and RC oscillator
Watchdog timer
1024´14 program memory PROM
64´8 data memory RAM
Buzzer driving pair and PFD supported
·
·
·
·
·
·
·
·
·
Halt function and wake-up feature reduce
power consumption
Up to 0.5ms instruction cycle with 8MHz
system clock at VDD=5V
Allinstructionsinoneortwomachinecycles
14-bit table read instruction
Two-level subroutine nesting
Bit manipulation instruction
63 powerful instructions
Low voltage reset function
18-pin DIP/SOP package
General Description
ous subsystem controllers. A halt feature is
included to reduce power consumption.
The device is an 8-bit high performance
RISC-like microcontroller designed for multiple I/O product applications. The device is particularly suitable for use in products such as
remote controllers, fan/light controllers, washing machine controllers, scales, toys and vari-
The program and option memories can be electrically programmed, making the microcontroller suitable for use in product development.
1
February 25, 2000
Preliminary
HT48R06A-1
Block Diagram
IN T /P C 0
In te rru p t
C ir c u it
S T A C K 0
P ro g ra m
R O M
P ro g ra m
C o u n te r
M
T M R
S T A C K 1
IN T C
U
P r e s c a le r
P C 1
S Y S C L K /4
In s tr u c tio n
R e g is te r
M
M P
U
D A T A
M e m o ry
X
W D T S
W D T P r e s c a le r
P C C
W D T
M
U
X
R C
P O R T C
O S C
P C 0 ~ P C 1
P C
M U X
In s tr u c tio n
D e c o d e r
B Z /B Z
P B C
S T A T U S
A L U
P A C
S
S
C 1
P O R T B
P B
S h ifte r
T im in g
G e n e ra to r
O S
R E
V D
V S
Y S
T M R C
P C 0
O S C 2
fS
T M R /P C 1
X
O p tio n
P R O M
A C C
P A
P O R T A
P B 0 ~ P B 2
P A 0 ~ P A 7
D
Pin Assignment
P A 3
1
1 8
P A 4
P A 2
2
1 7
P A 5
P A 1
3
1 6
P A 6
P A 0
4
1 5
P A 7
P B 2
5
1 4
O S C 2
P B 1 /B Z
6
1 3
O S C 1
P B 0 /B Z
7
1 2
V D D
V S S
8
1 1
R E S
P C 0 /IN T
9
1 0
P C 1 /T M R
H T 4 8 R 0 6 A -1
1 8 D IP /S O P
2
February 25, 2000
Preliminary
HT48R06A-1
Pin Description
Pin No.
4~1
18~15
Pin Name
PA0~PA7
I/O
I/O
ROM Code
Option
Description
Pull-high*
Wake-up
Bidirectional 8-bit input/output port. Each bit can be
configured as wake-up input by ROM code option.
Software instructions determine the CMOS output or
schmitt trigger input with a pull-high resistor (determined by pull-high options).
Bidirectional 3-bit input/output port. Software instructions determine the CMOS output or schmitt
trigger input with a pull-high resistor (determined by
pull-high options).
The PB0 and PB1 are pin-shared with the BZ and BZ,
respectively. Once the PB0 and PB1 are selected as
buzzer driving outputs, the output signals come from
an internal PFD generator (shared with timer/event
counter).
7
6
5
PB0/BZ
PB1/BZ
PB2
I/O
Pull-high*
I/O or
BZ/BZ
8
VSS
¾
¾
9
10
PC0/INT
PC1/TMR
11
Negative power supply, ground
Bidirectional I/O lines. Software instructions determine the CMOS output or SCHMITT trigger input
with a pull-high resistor (determined by pull-high options). The external interrupt and timer input are
pin-shared with the PC0 and PC1, respectively. The
external interrupt input is activated on a high to low
transition.
I/O
Pull-high*
RES
I
¾
Schmitt trigger reset input. Active low
12
VDD
¾
¾
Positive power supply
13
14
OSC1
OSC2
I
O
Crystal
or RC
OSC1, OSC2 are connected to an RC network or Crystal (determined by ROM code option) for the internal
system clock. In the case of RC operation, OSC2 is the
output terminal for 1/4 system clock.
* All pull-high resistors are controlled by an option bit.
Absolute Maximum Ratings
Supply Voltage ...............VSS-0.3V to VSS+5.5V
Storage Temperature.................-50°C to 125°C
Input Voltage .................VSS-0.3V to VDD+0.3V
Operating Temperature ..............-40°C to 85°C
Note: These are stress ratings only. Stresses exceeding the range specified under "Absolute Maximum Ratings" may cause substantial damage to the device. Functional operation of this device
at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
3
February 25, 2000
Preliminary
HT48R06A-1
D.C. Characteristics
Symbol
Parameter
Ta=25°C
Test Conditions
VDD
Conditions
Min.
Typ.
Max.
Unit
VDD1
Operating Voltage
¾
fSYS=4MHz
3.3
¾
5.5
V
VDD2
Operating Voltage
¾
fSYS=8MHz
4.5
¾
5.5
V
IDD1
Operating Current
(Crystal OSC)
3.3V
¾
1
2
mA
¾
2
4
mA
IDD2
Operating Current
(RC OSC)
3.3V
¾
1
2
mA
¾
2
4
mA
IDD3
Operating Current
(Crystal OSC)
¾
5
10
mA
ISTB1
Standby Current
(WDT Enabled)
3.3V
¾
¾
5
mA
¾
¾
10
mA
ISTB2
Standby Current
(WDT Disabled)
3.3V
¾
¾
1
mA
¾
¾
2
mA
VIL1
3.3V
Input Low Voltage for
I/O Ports, TMR and INT 5V
¾
0
¾
0.2VDD
V
¾
0
¾
0.2VDD
V
VIH1
Input High Voltage for 3.3V
I/O Ports, TMR and INT 5V
¾
0.8VDD
¾
VDD
V
¾
0.8VDD
¾
VDD
V
VIL3
Input Low Voltage
(RES)
3.3V
¾
0
¾
0.4VDD
V
5V
¾
0
¾
0.4VDD
V
VIH3
Input High Voltage
(RES)
3.3V
¾
0.9VDD
¾
VDD
V
5V
¾
0.9VDD
¾
VDD
V
VLVR
Low Voltage Reset
¾
¾
3.1
3.2
3.3
V
IOL
I/O Port Sink Current
3.3V VOL=0.1VDD
4
8
¾
mA
VOL=0.1VDD
10
20
¾
mA
IOH
I/O Port Source
Current
3.3V VOH=0.9VDD
-2
-4
¾
mA
VOH=0.9VDD
-5
-10
¾
mA
RPH
Pull-high Resistance
5V
5V
5V
5V
5V
5V
5V
No load, fSYS=4MHz
No load, fSYS=4MHz
No load, fsys=8MHz
No load, system Halt
No load, system Halt
3.3V
¾
40
60
80
kW
5V
¾
10
30
50
kW
4
February 25, 2000
Preliminary
HT48R06A-1
A.C. Characteristics
Symbol
Parameter
Ta=25°C
Test Conditions
Min.
Typ.
¾
400
¾
4000
kHz
5V
¾
400
¾
8000
kHz
3.3V
¾
400
¾
4000
kHz
5V
¾
400
¾
4000
kHz
3.3V
¾
0
¾
4000
kHz
5V
¾
0
¾
4000
kHz
3.3V
¾
43
86
168
ms
5V
¾
35
65
130
ms
11
22
43
ms
9
17
35
ms
¾
1024
¾
tSYS
VDD
Conditions
3.3V
Max. Unit
fSYS1
System Clock
(Crystal OSC)
fSYS2
System Clock (RC OSC)
fTIMER
Timer I/P Frequency (TMR)
tWDTOSC
Watchdog Oscillator
tWDT1
Watchdog Time-out Period
(RC)
tWDT2
Watchdog Time-out Period
(System Clock)
¾
tRES
External Reset Low Pulse
Width
¾
¾
1
¾
¾
ms
tSST
System Start-up Timer
Period
¾
Power-up, reset or
wake-up from Halt
¾
1024
¾
tSYS
tINT
Interrupt Pulse Width
¾
¾
1
¾
¾
ms
3.3V Without WDT
5V prescaler
Without WDT
prescaler
5
February 25, 2000
Preliminary
HT48R06A-1
Functional Description
When executing a jump instruction, conditional
skip execution, loading PCL register, subroutine call, initial reset, internal interrupt, external interrupt or return from subroutine, the PC
manipulates the program transfer by loading
the address corresponding to each instruction.
Execution flow
The system clock for the microcontroller is derived from either a crystal or an RC oscillator.
The system clock is internally divided into four
non-overlapping clocks. One instruction cycle
consists of four system clock cycles.
The conditional skip is activated by instructions. Once the condition is met, the next instruction, fetched during the current
instruction execution, is discarded and a
dummy cycle replaces it to get the proper instruction. Otherwise proceed with the next instruction.
Instruction fetching and execution are
pipelined in such a way that a fetch takes an instruction cycle while decoding and execution
takes the next instruction cycle. However, the
pipelining scheme causes each instruction to effectively execute in a cycle. If an instruction
changes the program counter, two cycles are required to complete the instruction.
The lower byte of the program counter (PCL) is
a readable and writable register (06H). Moving
data into the PCL performs a short jump. The
destination will be within 256 locations.
Program counter - PC
The program counter (PC) controls the sequence in which the instructions stored in program PROM are executed and its contents
specify full range of program memory.
When a control transfer takes place, an additional dummy cycle is required.
Program memory - PROM
After accessing a program memory word to fetch
an instruction code, the contents of the program
counter are incremented by one. The program
counter then points to the memory word containing the next instruction code.
S y s te m
C lo c k
T 1
T 2
T 3
T 4
The program memory is used to store the program instructions which are to be executed. It
also contains data, table, and interrupt entries,
and is organized into 1024´14 bits, addressed
by the program counter and table pointer.
T 1
T 2
T 3
T 4
T 1
T 2
T 3
T 4
O S C 2 ( R C o n ly )
P C
P C
F e tc h IN S T (P C )
E x e c u te IN S T (P C -1 )
P C + 1
F e tc h IN S T (P C + 1 )
E x e c u te IN S T (P C )
P C + 2
F e tc h IN S T (P C + 2 )
E x e c u te IN S T (P C + 1 )
Execution flow
6
February 25, 2000
Preliminary
Certain locations in the program memory are
reserved for special usage:
0 0 0 H
This area is reserved for program initialization. After chip reset, the program always begins execution at location 000H.
E x te r n a l In te r r u p t S u b r o u tin e
0 0 8 H
· Location 004H
T im e r /E v e n t C o u n te r In te r r u p t S u b r o u tin e
P ro g ra m
M e m o ry
n 0 0 H
This area is reserved for the external interrupt service program. If the INT input pin is
activated, the interrupt is enabled and the
stack is not full, the program begins execution
at location 004H.
L o o k - u p T a b le ( 2 5 6 w o r d s )
n F F H
· Location 008H
L o o k - u p T a b le ( 2 5 6 w o r d s )
3 F F H
1 4 b its
This area is reserved for the timer/event counter interrupt service program. If a timer interrupt results from a timer/event counter
overflow, and if the interrupt is enabled and the
stack is not full, the program begins execution
at location 008H.
N o te : n ra n g e s fro m
0 to 3
Program memory
the lower-order byte in the table is
well-defined, the other bits of the table word
are transferred to the lower portion of TBLH,
and the remaining 2 bits are read as "0". The
Table Higher-order byte register (TBLH) is
read only. The table pointer (TBLP) is a
read/write register (07H), which indicates the
table location. Before accessing the table, the
location must be placed in TBLP. The TBLH
is read only and cannot be restored. If the
main routine and the ISR (Interrupt Service
· Table location
Any location in the PROM space can be used
as look-up tables. The instructions "TABRDC
[m]" (the current page, 1 page=256 words)
and "TABRDL [m]" (the last page) transfer
the contents of the lower-order byte to the
specified data memory, and the higher-order
byte to TBLH (08H). Only the destination of
Mode
D e v ic e In itia liz a tio n P r o g r a m
0 0 4 H
· Location 000H
HT48R06A-1
Program Counter
*9
*8
*7
*6
*5
*4
*3
*2
*1
*0
Initial Reset
0
0
0
0
0
0
0
0
0
0
External Interrupt
0
0
0
0
0
0
0
1
0
0
Timer/Event Counter Overflow
0
0
0
0
0
0
1
0
0
0
Skip
PC+2
Loading PCL
*9
*8
@7
@6
@5
@4
@3
@2
@1
@0
Jump, Call Branch
#9
#8
#7
#6
#5
#4
#3
#2
#1
#0
Return from Subroutine
S9
S8
S7
S6
S5
S4
S3
S2
S1
S0
Program counter
Note: *9~*0: Program counter bits
S9~S0: Stack register bits
#9~#0: Instruction code bits
@7~@0: PCL bits
7
February 25, 2000
Preliminary
ited. When the stack pointer is decremented (by
RET or RETI), the interrupt will be serviced.
This feature prevents stack overflow allowing
the programmer to use the structure more easily. In a similar case, if the stack is full and a
"CALL" is subsequently executed, stack overflow occurs and the first entry will be lost (only
the most recent 2 return addresses are stored).
Routine) both employ the table read instruction, the contents of the TBLH in the main
routine are likely to be changed by the table
read instruction used in the ISR. Errors can
occur. In other words, using the table read instruction in the main routine and the ISR simultaneously should be avoided. However, if
the table read instruction has to be applied in
both the main routine and the ISR, the interrupt is supposed to be disabled prior to the table read instruction. It will not be enabled
until the TBLH has been backed up. All table
related instructions require two cycles to complete the operation. These areas may function
as normal program memory depending upon
the requirements.
Data memory - RAM
The data memory is designed with 81´8 bits.
The data memory is divided into two functional groups: special function registers and
general purpose data memory (64´8). Most are
read/write, but some are read only.
The special function registers include the indirect addressing register (00H), timer/event
counter (TMR;0DH), timer/event counter control register (TMRC;0EH), program counter
lower-order byte register (PCL;06H), memory
pointer register (MP;01H), accumulator
(ACC;05H), table pointer (TBLP;07H), table
higher-order byte register (TBLH;08H), status
register (STATUS;0AH), interrupt control register (INTC;0BH), watchdog timer option setting register (WDTS;09H), I/O registers
(PA;12H, PB;14H, PC;16H) and I/O control
registers (PAC;13H, PBC;15H, PCC;17H). The
remaining space before the 40H is reserved for
future expanded usage and reading these locations will get "00H". The general purpose data
memory, addressed from 40H to 7FH, is used
for data and control information under instruction commands.
Stack register - STACK
This is a special part of the memory which is
used to save the contents of the program counter (PC) only. The stack is organized into 2 levels and is neither part of the data nor part of the
program space, and is neither readable nor
writable. The activated level is indexed by the
stack pointer (SP) and is neither readable nor
writeable. At a subroutine call or interrupt acknowledgment, the contents of the program
counter are pushed onto the stack. At the end of
a subroutine or an interrupt routine, signaled
by a return instruction (RET or RETI), the program counter is restored to its previous value
from the stack. After a chip reset, the SP will
point to the top of the stack.
If the stack is full and a non-masked interrupt
takes place, the interrupt request flag will be
recorded but the acknowledgment will be inhibInstruction
HT48R06A-1
Table Location
*9
*8
*7
*6
*5
*4
*3
*2
*1
*0
TABRDC [m]
P9
P8
@7
@6
@5
@4
@3
@2
@1
@0
TABRDL [m]
1
1
@7
@6
@5
@4
@3
@2
@1
@0
Table location
Note: *9~*0: Table location bits
P9, P8: Current program counter bits
@7~@0: Table pointer bits
8
February 25, 2000
Preliminary
All of the data memory areas can handle arithmetic, logic, increment, decrement and rotate
operations directly. Except for some dedicated
bits, each bit in the data memory can be set and
reset by "SET [m].i" and "CLR [m].i". They are
also indirectly accessible through memory
pointer register (MP;01H).
HT48R06A-1
0 0 H
In d ir e c t A d d r e s s in g R e g is te r
0 1 H
M P
0 2 H
0 3 H
0 4 H
0 5 H
Indirect addressing register
Location 00H is an indirect addressing register
that is not physically implemented. Any
read/write operation of [00H] accesses data memory pointed to by MP (01H). Reading location 00H
itself indirectly will return the result 00H. Writing indirectly results in no operation.
A C C
0 6 H
P C L
0 7 H
T B L P
0 8 H
T B L H
0 9 H
W D T S
0 A H
S T A T U S
0 B H
IN T C
0 C H
0 D H
T M R
0 E H
T M R C
S p e c ia l P u r p o s e
D A T A M E M O R Y
0 F H
1 0 H
The memory pointer register MP (01H) is a 7-bit
register. The bit 7 of MP is undefined and reading
will return the result 1 . Any writing operation
to MP will only transfer the lower 7-bit data to
MP.
1 1 H
Accumulator
The accumulator is closely related to ALU operations. It is also mapped to location 05H of the
data memory and can carry out immediate data
operations. The data movement between two
data memory locations must pass through the
accumulator.
1 2 H
P A
1 3 H
P A C
1 4 H
P B
1 5 H
P B C
1 6 H
P C
1 7 H
P C C
1 8 H
1 9 H
: U n u s e d
1 A H
R e a d a s "0 0 "
1 B H
1 C H
1 D H
1 E H
1 F H
2 0 H
Arithmetic and logic unit - ALU
This circuit performs 8-bit arithmetic and logic
operations. The ALU provides the following functions:
3 F H
4 0 H
G e n e ra l P u rp o s e
D A T A M E M O R Y
(6 4 B y te s )
Arithmetic operations (ADD, ADC, SUB, SBC,
DAA)
7 F H
· Logic operations (AND, OR, XOR, CPL) Rota-
RAM mapping
tion (RL, RR, RLC, RRC)
· Increment and Decrement (INC, DEC)
· Branch decision (SZ, SNZ, SIZ, SDZ ....)
watchdog time-out flag (TO). It also records the
status information and controls the operation
sequence.
The ALU not only saves the results of a data operation but also changes the status register.
With the exception of the TO and PD flags,
bits in the status register can be altered by
instructions like most other registers. Any
data written into the status register will not
change the TO or PD flag. In addition opera-
Status register - STATUS
This 8-bit register (0AH) contains the zero flag
(Z), carry flag (C), auxiliary carry flag (AC),
overflow flag (OV), power down flag (PD), and
9
February 25, 2000
Preliminary
HT48R06A-1
the other interrupts will be blocked (by clearing
the EMI bit). This scheme may prevent any further interrupt nesting. Other interrupt requests may happen during this interval but
only the interrupt request flag is recorded. If a
certain interrupt requires servicing within the
service routine, the EMI bit and the corresponding bit of INTC may be set to allow interrupt
nesting. If the stack is full, the interrupt request
will not be acknowledged, even if the related interrupt is enabled, until the SP is decremented.
If immediate service is desired, the stack must
be prevented from becoming full.
tions related to the status register may give
different results from those intended. The
TO flag can be affected only by system
power-up, a WDT time-out or executing the
"CLR WDT" or "HALT" instruction. The PD
flag can be affected only by executing the
"HALT" or "CLR WDT" instruction or a system power-up.
The Z, OV, AC and C flags generally reflect the
status of the latest operations.
In addition, on entering the interrupt sequence
or executing the subroutine call, the status register will not be pushed onto the stack automatically. If the contents of the status are
important and if the subroutine can corrupt the
status register, precautions must be taken to
save it properly.
All these kinds of interrupts have a wake-up capability. As an interrupt is serviced, a control
transfer occurs by pushing the program counter
onto the stack, followed by a branch to a subroutine at specified location in the program
memory. Only the program counter is pushed
onto the stack. If the contents of the register or
status register (STATUS) are altered by the interrupt service program which corrupts the desired control sequence, the contents should be
saved in advance.
Interrupt
The device provides an external interrupt and
internal timer/event counter interrupts. The
Interrupt Control Register (INTC;0BH) contains the interrupt control bits to set the enable/disable and the interrupt request flags.
External interrupts are triggered by a high to
low transition of INT and the related interrupt
Once an interrupt subroutine is serviced, all
Labels
Bits
Function
C
0
C is set if the operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation; otherwise C is cleared. C
is also affected by a rotate through carry instruction.
AC
1
AC is set if the operation results in a carry out of the low nibbles in addition or no
borrow from the high nibble into the low nibble in subtraction; otherwise AC is
cleared.
Z
2
Z is set if the result of an arithmetic or logic operation is zero; otherwise Z is
cleared.
OV
3
OV is set if the operation results in a carry into the highest-order bit but not a
carry out of the highest-order bit, or vice versa; otherwise OV is cleared.
PD
4
PD is cleared by system power-up or executing the "CLR WDT" instruction. PD
is set by executing the "HALT" instruction.
TO
5
TO is cleared by system power-up or executing the "CLR WDT" or "HALT" instruction. TO is set by a WDT time-out.
¾
6
Undefined, read as "0"
¾
7
Undefined, read as "0"
Status register
10
February 25, 2000
Preliminary
following table shows the priority that is applied. These can be masked by resetting the
EMI bit.
request flag (EIF; bit 4 of INTC) will be set.
When the interrupt is enabled, the stack is not
full and the external interrupt is active, a subroutine call to location 04H will occur. The interrupt request flag (EIF) and EMI bits will be
cleared to disable other interrupts.
No. Interrupt Source Priority Vector
The internal timer/event counter interrupt is
initialized by setting the timer/event counter
interrupt request flag (TF; bit 5 of INTC),
caused by a timer overflow. When the interrupt
is enabled, the stack is not full and the TF bit is
set, a subroutine call to location 08H will occur.
The related interrupt request flag (TF) will be
reset and the EMI bit cleared to disable further
interrupts.
INTC
(0BH)
External Interrupt
1
04H
b
Timer/event
Counter Overflow
2
08H
It is recommended that a program does not
use the "CALL subroutine" within the interrupt subroutine. Interrupts often occur in an
unpredictable manner or need to be serviced
immediately in some applications. If only one
stack is left and enabling the interrupt is not
well controlled, the original control sequence will
Interrupts, occurring in the interval between
the rising edges of two consecutive T2 pulses,
will be serviced on the latter of the two T2
pulses, if the corresponding interrupts are enabled. In the case of simultaneous requests the
Bit No.
a
The timer/event counter interrupt request flag
(TF), external interrupt request flag (EIF), enable timer/event counter bit (ETI), enable external interrupt bit (EEI) and enable master
interrupt bit (EMI) constitute an interrupt control register (INTC) which is located at 0BH in
the data memory. EMI, EEI, ETI are used to
control the enabling/disabling of interrupts.
These bits prevent the requested interrupt
from being serviced. Once the interrupt request
flags (TF, EIF) are set, they will remain in the
INTC register until the interrupts are serviced
or cleared by a software instruction.
During the execution of an interrupt subroutine,
other interrupt acknowledgments are held until
the "RETI" instruction is executed or the EMI
bit and the related interrupt control bit are set to
1 (of course, if the stack is not full). To return
from the interrupt subroutine, "RET" or "RETI"
may be invoked. RETI will set the EMI bit to enable an interrupt service, but RET will not.
Register
HT48R06A-1
Label
Function
0
EMI
Controls the master (global) interrupt
(1= enabled; 0= disabled)
1
EEI
Controls the external interrupt
(1= enabled; 0= disabled)
2
ETI
Controls the timer/event counter interrupt
(1= enabled; 0= disabled)
3
¾
4
EIF
External interrupt request flag
(1= active; 0= inactive)
5
TF
Internal timer/event counter request flag
(1= active; 0= inactive)
6
¾
Unused bit, read as "0"
7
¾
Unused bit, read as "0"
Unused bit, read as "0"
INTC register
11
February 25, 2000
Preliminary
OSC1 and OSC2 is needed to provide the feedback and phase shift required for the oscillator,
and no other external components are required.
Instead of a crystal, a resonator can also be connected between OSC1 and OSC2 to get a frequency reference, but two external capacitors
in OSC1 and OSC2 are required (If the oscillating frequency is less than 1MHz).
be damaged once the "CALL" operates in the interrupt subroutine.
Oscillator configuration
There are two oscillator circuits in the
microcontroller.
V
O S C 1
D D
4 7 0 p F
O S C 2
C r y s ta l O s c illa to r
fS Y S /4
N M O S O p e n D r a in
The WDT oscillator is a free running on-chip RC
oscillator, and no external components are required. Even if the system enters the power down
mode, the system clock is stopped, but the WDT
oscillator still works with a period of approximately 65ms/5V. The WDT oscillator can be disabled by ROM code option to conserve power.
O S C 1
O S C 2
R C O s c illa to r
System oscillator
Watchdog timer - WDT
The clock source of WDT is implemented by a
dedicated RC oscillator (WDT oscillator) or instruction clock (system clock divided by 4), decided by ROM code option. This timer is
designed to prevent a software malfunction or
sequence from jumping to an unknown location
with unpredictable results. The watchdog
timer can be disabled by a ROM code option. If
the watchdog timer is disabled, all the executions related to the WDT result in no operation.
Both are designed for system clocks, namely
the RC oscillator and the Crystal oscillator,
which are determined by the ROM code option.
No matter what oscillator type is selected, the
signal provides the system clock. The HALT
mode stops the system oscillator and ignores an
external signal to conserve power.
If an RC oscillator is used, an external resistor
between OSC1 and VDD is required and the
resistance must range from 51kW to 1MW. The
system clock, divided by 4, is available on
OSC2, which can be used to synchronize external logic. The RC oscillator provides the most
cost effective solution. However, the frequency
of oscillation may vary with VDD, temperatures and the chip itself due to process variations. It is, therefore, not suitable for timing
sensitive operations where an accurate oscillator frequency is desired.
Once the internal WDT oscillator (RC oscillator
with a period of 65ms/5V normally) is selected, it
is first divided by 256 (8-stage) to get the nominal time-out period of approximately
16.6ms/5V. This time-out period may vary with
temperatures, VDD and process variations. By
invoking the WDT prescaler, longer time-out
periods can be realized. Writing data to WS2,
WS1, WS0 (bit 2,1,0 of the WDTS) can give different time-out periods. If WS2, WS1, and WS0 are
all equal to 1, the division ratio is up to 1:128, and
If the Crystal oscillator is used, a crystal across
S y s te m
HT48R06A-1
C lo c k /4
W D T
O S C
R O M
C o d e
O p tio n
S e le c t
W D T P r e s c a le r
8 - b it C o u n te r
7 - b it C o u n te r
8 -to -1 M U X
W S 0 ~ W S 2
W D T T im e - o u t
Watchdog timer
12
February 25, 2000
Preliminary
the maximum time-out period is 2.2s/5V seconds.
If the WDT oscillator is disabled, the WDT clock
may still come from the instruction clock and operate in the same manner except that in the
HALT state the WDT may stop counting and lose
its protecting purpose. In this situation the logic
can only be restarted by external logic. The high
nibble and bit 3 of the WDTS are reserved for
user's defined flags, which can be used to indicate
some specified status.
Power down operation - HALT
The HALT mode is initialized by the "HALT" instruction and results in the following...
· The system oscillator will be turned off but
·
·
If the device operates in a noisy environment, using the on-chip RC oscillator (WDT OSC) is
strongly recommended, since the HALT will stop
the system clock.
WS2
WS1
WS0
Division Ratio
0
0
0
1:1
0
0
1
1:2
0
1
0
1:4
0
1
1
1:8
1
0
0
1:16
1
0
1
1:32
1
1
0
1:64
1
1
1
1:128
HT48R06A-1
·
·
the WDT oscillator keeps running (if the
WDT oscillator is selected).
The contents of the on chip RAM and registers remain unchanged.
WDT and WDT prescaler will be cleared and
recounted again (if the WDT clock is from the
WDT oscillator).
AlloftheI/Oportsmaintaintheiroriginalstatus.
The PD flag is set and the TO flag is cleared.
The system can leave the HALT mode by means
of an external reset, an interrupt, an external
falling edge signal on port A or a WDT overflow.
An external reset causes a device initialization
and the WDT overflow performs a "warm reset". After the TO and PD flags are examined,
the reason for chip reset can be determined.
The PD flag is cleared by system power-up or
executing the "CLR WDT" instruction and is set
when executing the "HALT" instruction. The
TO flag is set if the WDT time-out occurs, and
causes a wake-up that only resets the PC and
SP; the others keep their original status.
WDTS register
The port A wake-up and interrupt methods can
be considered as a continuation of normal execution. Each bit in port A can be independently
selected to wake up the device by the ROM code
option. Awakening from an I/O port stimulus,
the program will resume execution of the next
instruction. If it is awakening from an interrupt, two sequences may happen. If the related
interrupt is disabled or the interrupt is enabled
but the stack is full, the program will resume
execution at the next instruction. If the interrupt is enabled and the stack is not full, the regular interrupt response takes place. If an
interrupt request flag is set to "1" before entering the HALT mode, the wake-up function of
the related interrupt will be disabled. Once a
wake-up event occurs, it takes 1024 tSYS (system clock period) to resume normal operation.
In other words, a dummy period will be inserted
after wake-up. If the wake-up results from an
interrupt acknowledgment, the actual interrupt subroutine execution will be delayed by
one or more cycles. If the wake-up results in the
The WDT overflow under normal operation will
initialize "chip reset" and set the status bit
"TO". But in the HALT mode, the overflow will
initialize a ²warm reset², and only the PC and
SP are reset to zero. To clear the contents of
WDT (including the WDT prescaler), three
methods are adopted; external reset (a low level
to RES), software instruction and a "HALT" instruction. The software instruction include
"CLR WDT" and the other set - "CLR WDT1"
and "CLR WDT2". Of these two types of instruction, only one can be active depending on the
ROM code option - "CLR WDT times selection
option". If the "CLR WDT" is selected (i.e.
CLRWDT times equal one), any execution of
the "CLR WDT" instruction will clear the WDT.
In the case that "CLR WDT1" and "CLR WDT2"
are chosen (i.e. CLRWDT times equal two),
these two instructions must be executed to
clear the WDT; otherwise, the WDT may reset
the chip as a result of time-out.
13
February 25, 2000
Preliminary
next instruction execution, this will be executed
immediately after the dummy period is finished.
HT48R06A-1
V D D
R E S
tS
S S T T im e - o u t
To minimize power consumption, all the I/O
pins should be carefully managed before entering the HALT status.
C h ip
R e s e t
Reset timing chart
Reset
V
There are three ways in which a reset can occur:
D D
· RES reset during normal operation
· RES reset during HALT
· WDT time-out reset during normal operation
R E S
The WDT time-out during HALT is different
from other chip reset conditions, since it can
perform a "warm reset" that resets only the PC
and SP, leaving the other circuits in their original state. Some registers remain unchanged
during other reset conditions. Most registers
are reset to the ²initial condition² when the reset conditions are met. By examining the PD
and TO flags, the program can distinguish between different "chip resets".
TO PD
Reset circuit
H A L T
W a rm
0
RES reset during power-up
u
u
RES reset during normal operation
0
1
RES wake-up HALT
1
u
WDT time-out during normal operation
1
1
WDT wake-up HALT
R e s e t
W D T
R E S
RESET Conditions
0
S T
C o ld
R e s e t
S S T
1 0 - b it R ip p le
C o u n te r
O S C 1
S y s te m
R e s e t
Reset configuration
The functional unit chip reset status are shown
below.
Note: "u" means "unchanged"
PC
000H
To guarantee that the system oscillator is
started and stabilized, the SST (System
Start-up Timer) provides an extra-delay of 1024
system clock pulses when the system reset
(power-up, WDT time-out or RES reset) or the
system awakes from the HALT state.
Interrupt
Disable
Prescaler
Clear
WDT
Clear. After master reset,
WDT begins counting
Timer/event
Off
Counter
When a system reset occurs, the SST delay is
added during the reset period. Any wake-up
from HALT will enable the SST delay.
Input/output
Input mode
Ports
SP
14
Points to the top of
the stack
February 25, 2000
Preliminary
HT48R06A-1
The states of the registers is summarized in the table.
Reset
(Power On)
WDT time-out
(Normal
Operation)
RES Reset
(Normal
Operation)
RES Reset
(HALT)
WDT
Time-out
(HALT)*
TMR
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TMRC
00-0 1000
00-0 1000
00-0 1000
00-0 1000
uu-u uuuu
000H
000H
000H
000H
000H
MP
-xxx xxxx
-uuu uuuu
-uuu uuuu
-uuu uuuu
-uuu uuuu
ACC
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TBLP
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TBLH
--xx xxxx
--uu uuuu
--uu uuuu
--uu uuuu
--uu uuuu
STATUS
--00 xxxx
--1u uuuu
--uu uuuu
--01 uuuu
--11 uuuu
INTC
--00 -000
--00 -000
--00 -000
--00 -000
--uu -uuu
WDTS
0000 0111
0000 0111
0000 0111
0000 0111
uuuu uuuu
PA
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PAC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PB
---- -111
---- -111
---- -111
---- -111
---- -uuu
PBC
---- -111
---- -111
---- -111
---- -111
---- -uuu
PC
------11
------11
------11
------11
------uu
PCC
------11
------11
------11
------11
------uu
Register
Program
Counter
Note:
"*" means "warm reset"
"u" means "unchanged"
"x" means "unknown"
15
February 25, 2000
Preliminary
Timer/event counter
measure time intervals or pulse widths, or to
generate an accurate time base.
A timer/event counter (TMR) is implemented in
the microcontroller. The timer/event counter
contains an 8-bit programmable count-up counter and the clock may come from an external
source or the system clock.
There are 2 registers related to the timer/event
counter; TMR ([0DH]), TMRC ([0EH]). Two physical registers are mapped to TMR location; writing TMR makes the starting value be placed in
the timer/event counter preload register and
reading TMR gets the contents of the timer/event
counter. The TMRC is a timer/event counter control register, which defines some options.
Using the internal system clock, there is only
one reference time-base. The internal clock
source comes from fSYS. The external clock input allows the user to count external events,
Label (TMRC)
PSC0~PSC2
Bits
0~2
HT48R06A-1
Function
To define the prescaler stages, PSC2, PSC1, PSC0=
000: fINT=fSYS/2
001: fINT=fSYS/4
010: fINT=fSYS/8
011: fINT=fSYS/16
100: fINT=fSYS/32
101: fINT=fSYS/64
110: fINT=fSYS/128
111: fINT=fSYS/256
TE
3
To define the TMR active edge of timer/event counter
(0=active on low to high; 1=active on high to low)
TON
4
To enable/disable timer counting
(0=disabled; 1=enabled)
5
Unused bits, read as"0"
6
7
To define the operating mode
01=Event count mode (external clock)
10=Timer mode (internal clock)
11=Pulse width measurement mode
00=Unused
¾
TM0
TM1
TMRC register
fS
Y S
8 - s ta g e p r e s c a le r
f IN
8 -1 M U X
P S C 2 ~ P S C 0
D a ta B u s
T
T M 1
T M 0
T M R
T im e r /E v e n t C o u n te r
P r e lo a d R e g is te r
R e lo a d
T E
T M 1
T M 0
T O N
T im e r /e v e n t
C o u n te r
P u ls e W id th
M e a s u re m e n t
M o d e C o n tro l
O v e r flo w
to In te rru p t
1 /2
B Z
B Z
Timer/event counter
16
February 25, 2000
Preliminary
HT48R06A-1
counter is turned on, data written to it will only
be kept in the timer/event counter preload register. The timer/event counter will still operate
until overflow occurs. When the timer/event
counter (reading TMR) is read, the clock will be
blocked to avoid errors. As clock blocking may results in a counting error, this must be taken into
consideration by the programmer.
The TM0, TM1 bits define the operating mode.
The event count mode is used to count external
events, which means the clock source comes from
an external (TMR) pin. The timer mode functions
as a normal timer with the clock source coming
from the fINT clock. The pulse width measurement
mode can be used to count the high or low level duration of the external signal (TMR). The counting
is based on the fINT clock.
The bit0~bit2 of the TMRC can be used to define the pre-scaling stages of the internal clock
sources of timer/event counter. The definitions
are as shown. The overflow signal of
timer/event counter can be used to generate
PFD signals for buzzer driving.
In the event count or timer mode, once the
timer/event counter starts counting, it will count
from the current contents in the timer/event
counter to FFH. Once overflow occurs, the counter is reloaded from the timer/event counter
preload register and generates the interrupt request flag (TF; bit 5 of INTC) at the same time.
Input/output ports
There are 13 bidirectional input/output lines in
the microcontroller, labeled from PA to PC, which
are mapped to the data memory of [12H], [14H]
and [16H] respectively. All of these I/O ports can
be used for input and output operations. For input operation, these ports are non-latching, that
is, the inputs must be ready at the T2 rising edge
of instruction "MOV A,[m]" (m=12H, 14H or
16H). For output operation, all the data is latched
and remains unchanged until the output latch is
rewritten.
In the pulse width measurement mode with
the TON and TE bits equal to one, once the
TMR has received a transient from low to high
(or high to low if the TE bits is "0") it will start
counting until the TMR returns to the original
level and resets the TON. The measured result
will remain in the timer/event counter even if
the activated transient occurs again. In other
words, only one cycle measurement can be
done. Until setting the TON, the cycle measurement will function again as long as it receives
further transient pulse. Note that, in this operating mode, the timer/event counter starts
counting not according to the logic level but according to the transient edges. In the case of
counter overflows, the counter is reloaded from
the timer/event counter preload register and issues the interrupt request just like the other
two modes. To enable the counting operation,
the timer ON bit (TON; bit 4 of TMRC) should
be set to 1. In the pulse width measurement
mode, the TON will be cleared automatically after the measurement cycle is completed. But in
the other two modes the TON can only be reset
by instructions. The overflow of the timer/event
counter is one of the wake-up sources. No matter what the operation mode is, writing a 0 to
ETI can disable the interrupt service.
Each I/O line has its own control register (PAC,
PBC, PCC) to control the input/output configuration. With this control register, CMOS output
or schmitt trigger input with or without
pull-high resistor structures can be reconfigured dynamically (i.e. on-the-fly) under software control. To function as an input, the
corresponding latch of the control register must
write "1". The input source also depends on the
control register. If the control register bit is "1",
the input will read the pad state. If the control
register bit is "0", the contents of the latches
will move to the internal bus. The latter is possible in the "read-modify-write" instruction.
For output function, CMOS is the only configuration. These control registers are mapped to
locations 13H, 15H and 17H.
In the case of timer/event counter OFF condition, writing data to the timer/event counter
preload register will also reload that data to
the timer/event counter. But if the timer/event
After a chip reset, these input/output lines remain at high levels or floating state (dependent
on pull-high options). Each bit of these in-
17
February 25, 2000
Preliminary
HT48R06A-1
The PB0 and PB1 are pin-shared with BZ and
BZ signal, respectively. If the BZ/BZ option is
selected, the output signal in output mode of
PB0/PB1 will be the PFD signal generated by
timer/event counter overflow signal. The input
mode always remaining its original functions.
Once the BZ/BZ option is selected, the buzzer
output signals are controlled by PB0 data register only. The I/O functions of PB0/PB1 are
shown below.
put/output latches can be set or cleared by "SET
[m].i" and "CLR [m].i" (m=12H, 14H or 16H) instructions.
Some instructions first input data and then follow the output operations. For example, "SET
[m].i", "CLR [m].i", "CPL [m]", "CPLA [m]" read
the entire port states into the CPU, execute the
defined operations (bit-operation), and then
write the results back to the latches or the accumulator.
Each line of port A has the capability of waking-up the device. The highest 6-bit of port C and
5 bits of port B are not physically implemented;
on reading them a "0" is returned whereas writing then results in a no-operation. See Application note.
PB0 I/O
I
PB1 I/O
I O O O I
There is a pull-high option available for all I/O
lines. Once the pull-high option is selected, all
I/O lines have pull-high resistors. Otherwise,
the pull-high resistors are absent. It should be
noted that a non-pull-high I/O line operating in
input mode will cause a floating state.
PB0 Pad Status I
C o n tr o l B it
I O O O O O O
I I O O O
PB0 Data
x x 0 1 D 0 1 D0 0 1
PB1 Data
x D x x x x x D1 x x
I
I
I D 0 B D0 0 B
PB1 Pad Status I D 0 B I
Note:
I I D1 0 B
I: input; O: output; D, D0, D1: data;
B: buzzer option, BZ or BZ; x: don't care
C: CMOS output
D D
P U
Q
D
C K
W r ite C o n tr o l R e g is te r
I
PB0/PB1 Mode x C B B C B B C B B
V
D a ta B u s
I
Q B
S
C h ip R e s e t
R e a d C o n tr o l R e g is te r
P A 0 ~ P A 7
P B 0 ~ P B 2
P C 0 ~ P C 1
D a ta B it
Q
D
C K
W r ite D a ta R e g is te r
Q B
S
( P B 0 , P B 1 O n ly )
M
P B 0
E X T
M
R e a d D a ta R e g is te r
U
U
X
E X T E N
( P B 0 , P B 1 O n ly )
X
S y s te m W a k e -u p
( P A o n ly )
O P 0 ~ O P 7
IN T fo r P C 0 O n ly
T M R fo r P C 1 O n ly
E X T = B Z fo r P B 0 o n ly , E X T = B Z fo r P B 1 o n ly , c o n tr o l= P B 0 d a ta r e g is te r
Input/output ports
18
February 25, 2000
Preliminary
HT48R06A-1
The PC0 and PC1 are pin-shared with INT,
TMR and pins respectively.
edge of PA4 (CLK) for OTP programming and
verification.
It is recommended that unused or not bonded
out I/O lines should be set as output pins by
software instruction to avoid consuming power
under input floating state.
The address data contains the code address (11
bits) and two option bits. A complete write cycle
will contain four CLK cycles. The first cycle,
bits 0~3 of the address are latched into the
device. The second and third cycles, bits 4~7
and bits 8~9 are latched respectively. The
fourth cycle, bit 2 is the TSEL option bit and bit
3 is the OSEL option bit. Bits 2~3 in the third
cycle and bits 0~1 in the fourth cycle are undefined. If the TSEL is "1" and the OSEL is "0",
the TEST memory will be read. If the TSEL is
"0" and the OSEL is "1", the option memory will
be accessed. If both the TSEL and OSEL are
"0", the program memory will be managed.
ROM code option
The following table shows all kinds of ROM
code option in the microcontroller. All of the
ROM code options must be defined to ensure
proper system functioning.
Items
Option
1
WDT clock source: WDTOSC/fTID
2
WDT enable/disable: enable/disable
3
LVD enable/disable: enable/disable
4
CLRWDT instruction(s)
: one/two clear WDT
instruction(s)
5
System oscillator: RC/Crystal
6
Pull-high resistors (PA~PC):
none/pull-high
7
BZ option: disable/enable
8
PA0~PA7 wake-up: disable/enable
9
Lock: unlock/lock
The code data is 14 bits wide. A complete
read/write cycle contains four CLK cycles. In
the first cycle, bits 0~3 of the code data are accessed. In the second and third, bits 4~7 and
bits 8~11 are accessed respectively. In the
fourth cycle, bits 12~13 are accessed. Bits
14~15 are undefined. During code verification,
reading will return the result "00".
Select the TSEL and OSEL to program and
verify the program memory and option
memory. Use the R/W (PA6) to select between
programming or verification.
The address is incremented by one automatically after a code verification cycle. If the discontinued address programming or
verification is accomplished, the automatic addressing increment is disabled. For the discontinued address programming and verification,
the CS pin must return to high level for a programming or verification cycle, that is, if a discontinued address is managed, the
programming or verification cycle must be interrupted and restarted as well.
PROM programming and verification
T h e p r og r a m m em or y us ed i n t h e
microcontroller is arranged into a 1024´14 bits
program memory and a 3´8 bits option memory.
The program code and option code are stored in
the program and option memories. The programming of memories can be summarized in
nine steps as described below:
· Power on (VDD=6.25V)
· Set VPP (RES) to 12.5V
· Set CS (PA5) to low
Let PA3~PA0 (AD3~AD0) be the address and
data bus and the PA4 (CLK) be the clock input.
The data on the AD3~AD0 pins will be clocked
into or out of the microcontroller on the falling
19
February 25, 2000
Preliminary
The related pins of OTP programming and verification are listed in the following table.
Pin
Function
Name
The timing charts of programming and verification are as shown. There is a LOCK signal for
code protection. If the LOCK is "1", reading the
code will return the result "1". However, if the
LOCK is "0", the code protection is disabled and
the code can be read always until the LOCK is
programmed as "1".
Description
PA0
AD0
Bit 0 of address/data bus
PA1
AD1
Bit 1 of address/data bus
PA2
AD2
Bit 2 of address/data bus
PA3
AD3
Bit 3 of address/data bus
PA4
CLK
Serial clock input for address and data
PA5
CS
PA6
R/W
Read/write control input
RES
VPP
Programming the power
supply
HT48R06A-1
Chip select, active low
V P P
C S
R /W
C L K
A D 0
A D 1
A D 2
A D 3
V e r ific a tio n
V e r ific a tio n
P C 0
P C 4
P C 8
0
D 0
D 4
D 8
D 1 2
D 0
D 4
D 8
D 1 2
D 0
P C 1
P C 5
P C 9
0
D 1
D 5
D 9
D 1 3
D 1
D 5
D 9
D 1 3
D 1
P C 2
P C 6
0
T S E L
D 2
D 6
D 1 0
0
D 2
D 6
D 1 0
0
D 2
P C 3
P C 7
0
O S E L
D 3
D 7
D 1 1
D 7
D 1 1
0
D 3
0
D 3
P C
in c r e s in g a u to m a tic a lly
Successive verification
20
February 25, 2000
Preliminary
HT48R06A-1
V P P
C S
V e r ific a tio n
R /W
V e r ific a tio n
V e r ific a tio n
C L K
A D 0
A D 1
A D 2
A D 3
P C 0 ~ P C 9
D 0 ~ D 1 3
P C 0 ~ P C 9
D 0 ~ D 1 3
P C 0 ~ P C 9
D 0 ~ D 1 3
Non-successive verification
V P P
tC
V S
C S
R /W
tC
tR
W S
tC
tC
C S
A D 1
A D 2
A D 3
V e r ific a tio n
tC
H P
C L K
A D 0
C S
P r o g r a m m in g
tC
tW
L P
tD
P
tW
R S
C S
C S
P C 0
P C 4
P C 8
0
D 0
D 4
D 8
D 1 2
D 0
D 4
D 8
D 1 2
P C 1
P C 5
P C 9
0
D 1
D 5
D 9
D 1 3
D 1
D 5
D 9
D 1 3
P C 2
P C 6
0
T S E L
D 2
D 6
D 1 0
0
D 2
D 6
D 1 0
0
P C 3
P C 7
0
O S E L
D 3
D 7
D 1 1
D 3
D 7
D 1 1
0
0 o r L o c k
Code programming and verification
21
February 25, 2000
Preliminary
HT48R06A-1
V P P
C S
R /W
P r o g r m m in g
P r o g r m m in g
V e r ific a tio n
V e r ific a tio n
C L K
A D 0
A D 1
A D 2
A D 3
P C 0 ~ P C 9
D 0 ~ D 1 3
D 0 ~ D 1 3
P C 0 ~ P C 9
D 0 ~ D 1 3
D 0 ~ D 1 3
Non-successive programming and verification
V P P
C S
R /W
C L K
A D 0
ID 0
ID 1
ID 2
ID 3
ID 4
ID 5
ID 6
ID 7
A D 1 , A D 2 , A D 3 : d o n 't c a r e
ID code verification
22
February 25, 2000
Preliminary
HT48R06A-1
V P P
C S
V e r ific a tio n
P r o g r m m in g
R /W
P r o g r m m in g
V e r ific a tio n
P r o g r m m in g
V e r ific a tio n
C L K
A D 0
A D 1
A D 2
A D 3
P C 0 ~ P C 9
D 0 ~ D 1 3
D 0 ~ D 1 3
P C
D 0 ~ D 1 3
D 0 ~ D 1 3
+ 1 a u to m a tic a lly
P C
D 0 ~ D 1 3
D 0 ~ D 1 3
+ 1 a u to m a tic a lly
Successive programming and verification
Application Circuits
R C o s c illa to r fo r m u ltip le I/O
V
0 .1 m F
C 1
O S C 1
4 7 0 p F
Y S
C r y s ta l o s c illa to r fo r m u ltip le I/O
a p p lic a tio n s
D D
5 1 k W ~
1 M W
fS
a p p lic a tio n s
P A 0 ~ P A 7
O S C 1
P A 0 ~ P A 7
C 2
O S C 2
/4
V
O S C 2
P B 0 /B Z
P B 1 /B Z
P B 2
V
H T 4 8 R 0 6 A -1
D D
H T 4 8 R 0 6 A -1
P C 0 /IN T
P C 1 /T M R
1 0 0 k W
0 .1 m F
P C 0 /IN T
P C 1 /T M R
1 0 0 k W
R E S
R E S
0 .1 m F
N o te : T h e r e s is ta n c e a n d c a p
fo r r e s e t c ir c u it s h o u ld b
to e n s u re th a t th e V D D
r e m a in s in a v a lid r a n g e
v o lta g e b e fo r e b r in g in g
P B 0 /B Z
P B 1 /B Z
P B 2
D D
0 .1 m F
a c ita n c e
e d e s ig n
is s ta b le
o f th e o
R E S to h
N o te : C
e d
a n d
p e r a tin g
ig h .
23
1 = C 2 = 3 0 0 p F if fS Y S < 1 M H z
O th e r w is e , C 1 = C 2 = 0 .
February 25, 2000
Preliminary
HT48R06A-1
Instruction Set Summary
Mnemonic
Description
Instruction
Cycle
Flag
Affected
1
1(1)
1
1
1(1)
1
1
1(1)
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
1
1(1)
Z,C,AC,OV
Z,C,AC,OV
1(1)
C
1
1
1
1(1)
1(1)
1(1)
1
1
1
1(1)
1
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
1
1(1)
1
1(1)
Z
Z
Z
Z
Arithmetic
ADD A,[m]
ADDM A,[m]
ADD A,x
ADC A,[m]
ADCM A,[m]
SUB A,x
SUB A,[m]
SUBM A,[m]
SBC A,[m]
SBCM A,[m]
DAA [m]
Add data memory to ACC
Add ACC to data memory
Add immediate data to ACC
Add data memory to ACC with carry
Add ACC to register with carry
Subtract immediate data from ACC
Subtract data memory from ACC
Subtract data memory from ACC with result in data
memory
Subtract data memory from ACC with carry
Subtract data memory from ACC with carry and result
in data memory
Decimal adjust ACC for addition with result in data
memory
Logic Operation
AND A,[m]
OR A,[m]
XOR A,[m]
ANDM A,[m]
ORM A,[m]
XORM A,[m]
AND A,x
OR A,x
XOR A,x
CPL [m]
CPLA [m]
AND data memory to ACC
OR data memory to ACC
Exclusive-OR data memory to ACC
AND ACC to data memory
OR ACC to data memory
Exclusive-OR ACC to data memory
AND immediate data to ACC
OR immediate data to ACC
Exclusive-OR immediate data to ACC
Complement data memory
Complement data memory with result in ACC
Increment & Decrement
INCA [m]
INC [m]
DECA [m]
DEC [m]
Increment data memory with result in ACC
Increment data memory
Decrement data memory with result in ACC
Decrement data memory
24
February 25, 2000
Preliminary
HT48R06A-1
Instruction
Cycle
Flag
Affected
1
1(1)
1
None
None
C
1(1)
1
1(1)
1
C
None
None
C
1(1)
C
1
1(1)
1
None
None
None
Clear bit of data memory
Set bit of data memory
1(1)
1(1)
None
None
Jump unconditionally
Skip if data memory is zero
Skip if data memory is zero with data movement
ACC
Skip if bit i of data memory is zero
Skip if bit i of data memory is not zero
Skip if increment data memory is zero
Skip if decrement data memory is zero
Skip if increment data memory is zero with result
ACC
Skip if decrement data memory is zero with result
ACC
Subroutine call
Return from subroutine
Return from subroutine and load immediate data
ACC
Return from interrupt
to
2
1(2)
1(2)
None
None
None
in
1(2)
1(2)
1(3)
1(3)
1(2)
None
None
None
None
None
in
1(2)
None
to
2
2
2
None
None
None
2
None
Mnemonic
Description
Rotate
RRA [m]
RR [m]
RRCA [m]
RRC [m]
RLA [m]
RL [m]
RLCA [m]
RLC [m]
Rotate data memory right with result in ACC
Rotate data memory right
Rotate data memory right through carry with result in
ACC
Rotate data memory right through carry
Rotate data memory left with result in ACC
Rotate data memory left
Rotate data memory left through carry with result in
ACC
Rotate data memory left through carry
Data Move
MOV A,[m]
MOV [m],A
MOV A,x
Move data memory to ACC
Move ACC to data memory
Move immediate data to ACC
Bit Operation
CLR [m].i
SET [m].i
Branch
JMP addr
SZ [m]
SZA [m]
SZ [m].i
SNZ [m].i
SIZ [m]
SDZ [m]
SIZA [m]
SDZA [m]
CALL addr
RET
RET A,x
RETI
25
February 25, 2000
Preliminary
Mnemonic
Description
HT48R06A-1
Instruction
Cycle
Flag
Affected
2(1)
None
2(1)
None
1
1(1)
1(1)
1
1
1
1(1)
1
1
None
None
None
TO,PD
TO(4),PD(4)
TO(4),PD(4)
None
None
TO,PD
Table Read
TABRDC [m] Read ROM code (current page) to data memory and
TBLH
TABRDL [m] Read ROM code (last page) to data memory and TBLH
Miscellaneous
NOP
CLR [m]
SET [m]
CLR WDT
CLR WDT1
CLR WDT2
SWAP [m]
SWAPA [m]
HALT
Note:
No operation
Clear data memory
Set data memory
Clear watchdog timer
Pre-clear watchdog timer
Pre-clear watchdog timer
Swap nibbles of data memory
Swap nibbles of data memory with result in ACC
Enter power down mode
x: 8 bits immediate data
m: Data memory address
A: Accumulator
i: 0~7 number of bits
addr: Program memory address
Ö: Flag is affected
-: Flag is not affected
(1)
: If a loading to the PCL register occurs, the execution cycle of instructions will be delayed
one more cycle (four system clocks).
(2)
: If a skipping to next instruction occurs, the execution cycle of instructions will be delayed
one more cycle (four system clocks). Otherwise the original instruction cycle is unchanged.
(3) (1)
:
(4)
and (2)
: The flags may be affected by the execution status. If the watchdog timer is cleared by
executing the CLR WDT1 or CLR WDT2 instruction, the TO is set and the PD is cleared.
Otherwise the TO and PD flags remain unchanged.
26
February 25, 2000
Preliminary
HT48R06A-1
Instruction Definition
ADC A,[m]
Add data memory and carry to the accumulator
Description
The contents of the specified data memory, accumulator and the carry flag
are added simultaneously, leaving the result in the accumulator.
Operation
ACC ¬ ACC+[m]+C
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
Ö
Ö
Ö
Ö
ADCM A,[m]
Add the accumulator and carry to data memory
Description
The contents of the specified data memory, accumulator and the carry flag
are added simultaneously, leaving the result in the specified data memory.
Operation
[m] ¬ ACC+[m]+C
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
Ö
Ö
Ö
Ö
ADD A,[m]
Add data memory to the accumulator
Description
The contents of the specified data memory and the accumulator are added.
The result is stored in the accumulator.
Operation
ACC ¬ ACC+[m]
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
Ö
Ö
Ö
Ö
ADD A,x
Add immediate data to the accumulator
Description
The contents of the accumulator and the specified data are added, leaving
the result in the accumulator.
Operation
ACC ¬ ACC+x
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
Ö
Ö
Ö
Ö
27
February 25, 2000
Preliminary
HT48R06A-1
ADDM A,[m]
Add the accumulator to the data memory
Description
The contents of the specified data memory and the accumulator are added.
The result is stored in the data memory.
Operation
[m] ¬ ACC+[m]
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
Ö
Ö
Ö
Ö
AND A,[m]
Logical AND accumulator with data memory
Description
Data in the accumulator and the specified data memory perform a bitwise
logical_AND operation. The result is stored in the accumulator.
Operation
ACC ¬ ACC "AND" [m]
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
¾
¾
AND A,x
Logical AND immediate data to the accumulator
Description
Data in the accumulator and the specified data perform a bitwise logical_AND operation. The result is stored in the accumulator.
Operation
ACC ¬ ACC "AND" x
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
¾
¾
ANDM A,[m]
Logical AND data memory with the accumulator
Description
Data in the specified data memory and the accumulator perform a bitwise
logical_AND operation. The result is stored in the data memory.
Operation
[m] ¬ ACC "AND" [m]
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
¾
¾
28
February 25, 2000
Preliminary
HT48R06A-1
CALL addr
Subroutine call
Description
The instruction unconditionally calls a subroutine located at the indicated
address. The program counter increments once to obtain the address of the
next instruction, and pushes this onto the stack. The indicated address is
then loaded. Program execution continues with the instruction at this address.
Operation
Stack ¬ PC+1
PC ¬ addr
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
CLR [m]
Clear data memory
Description
The contents of the specified data memory are cleared to zero.
Operation
[m] ¬ 00H
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
CLR [m].i
Clear bit of data memory
Description
The bit i of the specified data memory is cleared to zero.
Operation
[m].i ¬ 0
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
CLR WDT
Clear watchdog timer
Description
The WDT and the WDT Prescaler are cleared (re-counting from zero). The
power down bit (PD) and time-out bit (TO) are cleared.
Operation
WDT and WDT Prescaler ¬ 00H
PD and TO ¬ 0
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
0
0
¾
¾
¾
¾
29
February 25, 2000
Preliminary
HT48R06A-1
CLR WDT1
Preclear watchdog timer
Description
The TD, PD flags, WDT and the WDT Prescaler has cleared (re-counting
from zero), if the other preclear WDT instruction has been executed. Only execution of this instruction without the other preclear instruction just sets the
indicated flag which implies this instruction has been executed and the TO
and PD flags remain unchanged.
Operation
WDT and WDT Prescaler ¬ 00H*
PD and TO ¬ 0*
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
0*
0*
¾
¾
¾
¾
CLR WDT2
Preclear watchdog timer
Description
The TO, PD flags, WDT and the WDT Prescaler are cleared (re-counting
from zero), if the other preclear WDT instruction has been executed. Only execution of this instruction without the other preclear instruction, sets the indicated flag which implies this instruction has been executed and the TO and
PD flags remain unchanged.
Operation
WDT and WDT Prescaler ¬ 00H*
PD and TO ¬ 0*
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
0*
0*
¾
¾
¾
¾
CPL [m]
Complement data memory
Description
Each bit of the specified data memory is logically complemented (1's complement). Bits which previously contained a one are changed to zero and
vice-versa.
Operation
[m] ¬ [m]
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
¾
¾
30
February 25, 2000
Preliminary
HT48R06A-1
CPLA [m]
Complement data memory and place result in the accumulator
Description
Each bit of the specified data memory is logically complemented (1's complement). Bits which previously contained a one are changed to zero and
vice-versa. The complemented result is stored in the accumulator and the
contents of the data memory remain unchanged.
Operation
ACC ¬ [m]
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
¾
¾
DAA [m]
Decimal-Adjust accumulator for addition
Description
The accumulator value is adjusted to the BCD (Binary Code Decimal) code.
The accumulator is divided into two nibbles. Each nibble is adjusted to the
BCD code and an internal carry (AC1) will be done if the low nibble of the accumulator is greater than 9. The BCD adjustment is done by adding 6 to the
original value if the original value is greater than 9 or a carry (AC or C) is set;
otherwise the original value remains unchanged. The result is stored in the
data memory and only the carry flag (C) may be affected.
Operation
If ACC.3~ACC.0 >9 or AC=1
then [m].3~[m].0 ¬ (ACC.3~ACC.0)+6, AC1=AC
else [m].3~[m].0) ¬ (ACC.3~ACC.0), AC1=0
and
If ACC.7~ACC.4+AC1 >9 or C=1
then [m].7~[m].4 ¬ ACC.7~ACC.4+6+AC1,C=1
else [m].7~[m].4 ¬ ACC.7~ACC.4+AC1,C=C
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
Ö
DEC [m]
Decrement data memory
Description
Data in the specified data memory is decremented by one
Operation
[m] ¬ [m]-1
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
¾
¾
31
February 25, 2000
Preliminary
HT48R06A-1
DECA [m]
Decrement data memory and place result in the accumulator
Description
Data in the specified data memory is decremented by one, leaving the result
in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC ¬ [m]-1
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
¾
¾
HALT
Enter power down mode
Description
This instruction stops program execution and turns off the system clock. The
contents of the RAM and registers are retained. The WDT and prescaler are
cleared. The power down bit (PD) is set and the WDT time-out bit (TO) is
cleared.
Operation
PC ¬ PC+1
PD ¬ 1
TO ¬ 0
Affected flag(s)
INC [m]
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
0
1
¾
¾
¾
¾
Increment data memory
Description
Data in the specified data memory is incremented by one
Operation
[m] ¬ [m]+1
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
¾
¾
INCA [m]
Increment data memory and place result in the accumulator
Description
Data in the specified data memory is incremented by one, leaving the result
in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC ¬ [m]+1
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
¾
¾
32
February 25, 2000
Preliminary
HT48R06A-1
JMP addr
Directly jump
Description
Bits of the program counter are replaced with the directly-specified address
unconditionally, and control is passed to this destination.
Operation
PC ¬ addr
Affected flag(s)
MOV A,[m]
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
Move data memory to the accumulator
Description
The contents of the specified data memory are copied to the accumulator.
Operation
ACC ¬ [m]
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
MOV A,x
Move immediate data to the accumulator
Description
The 8-bit data specified by the code is loaded into the accumulator.
Operation
ACC ¬ x
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
MOV [m],A
Move the accumulator to data memory
Description
The contents of the accumulator are copied to the specified data memory (one
of the data memory).
Operation
[m] ¬ ACC
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
NOP
No operation
Description
No operation is performed. Execution continues with the next instruction.
Operation
PC ¬ PC+1
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
33
February 25, 2000
Preliminary
HT48R06A-1
OR A,[m]
Logical OR accumulator with data memory
Description
Data in the accumulator and the specified data memory (one of the data
memory) perform a bitwise logical_OR operation. The result is stored in the
accumulator.
Operation
ACC ¬ ACC "OR" [m]
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
¾
¾
OR A,x
Logical OR immediate data to the accumulator
Description
Data in the accumulator and the specified data perform a bitwise logical_OR
operation. The result is stored in the accumulator.
Operation
ACC ¬ ACC "OR" x
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
¾
¾
ORM A,[m]
Logical OR data memory with the accumulator
Description
Data in the data memory (one of the data memory) and the accumulator perform a bitwise logical_OR operation. The result is stored in the data memory.
Operation
[m] ¬ ACC "OR" [m]
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
¾
¾
RET
Return from subroutine
Description
The program counter is restored from the stack. This is a two cycle instruction.
Operation
PC ¬ Stack
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
34
February 25, 2000
Preliminary
HT48R06A-1
RET A,x
Return and place immediate data in the accumulator
Description
The program counter is restored from the stack and the accumulator loaded
with the specified 8-bit immediate data.
Operation
PC ¬ Stack
ACC ¬ x
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
RETI
Return from interrupt
Description
The program counter is restored from the stack, and interrupts are enabled
by setting the EMI bit. EMI is the enable master (global) interrupt bit (bit 0;
register INTC).
Operation
PC ¬ Stack
EMI ¬ 1
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
RL [m]
Rotate data memory left
Description
The contents of the specified data memory are rotated one bit left with bit 7
rotated into bit 0.
Operation
[m].(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
[m].0 ¬ [m].7
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
RLA [m]
Rotate data memory left and place result in the accumulator
Description
Data in the specified data memory is rotated one bit left with bit 7 rotated
into bit 0, leaving the rotated result in the accumulator. The contents of the
data memory remain unchanged.
Operation
ACC.(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
ACC.0 ¬ [m].7
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
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February 25, 2000
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HT48R06A-1
RLC [m]
Rotate data memory left through carry
Description
The contents of the specified data memory and the carry flag are rotated one
bit left. Bit 7 replaces the carry bit; the original carry flag is rotated into the
bit 0 position.
Operation
[m].(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
[m].0 ¬ C
C ¬ [m].7
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
Ö
RLCA [m]
Rotate left through carry and place result in the accumulator
Description
Data in the specified data memory and the carry flag are rotated one bit left.
Bit 7 replaces the carry bit and the original carry flag is rotated into bit 0 position. The rotated result is stored in the accumulator but the contents of the
data memory remain unchanged.
Operation
ACC.(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
ACC.0 ¬ C
C ¬ [m].7
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
Ö
RR [m]
Rotate data memory right
Description
The contents of the specified data memory are rotated one bit right with bit 0
rotated to bit 7.
Operation
[m].i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
[m].7 ¬ [m].0
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
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February 25, 2000
Preliminary
HT48R06A-1
RRA [m]
Rotate right and place result in the accumulator
Description
Data in the specified data memory is rotated one bit right with bit 0 rotated
into bit 7, leaving the rotated result in the accumulator. The contents of the
data memory remain unchanged.
Operation
ACC.(i) ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
ACC.7 ¬ [m].0
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
RRC [m]
Rotate data memory right through carry
Description
The contents of the specified data memory and the carry flag are together rotated one bit right. Bit 0 replaces the carry bit; the original carry flag is rotated into the bit 7 position.
Operation
[m].i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
[m].7 ¬ C
C ¬ [m].0
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
Ö
RRCA [m]
Rotate right through carry and place result in the accumulator
Description
Data of the specified data memory and the carry flag are rotated one bit
right. Bit 0 replaces the carry bit and the original carry flag is rotated into
the bit 7 position. The rotated result is stored in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC.i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
ACC.7 ¬ C
C ¬ [m].0
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
Ö
37
February 25, 2000
Preliminary
HT48R06A-1
SBC A,[m]
Subtract data memory and carry from the accumulator
Description
The contents of the specified data memory and the complement of the carry
flag are subtracted from the accumulator, leaving the result in the accumulator.
Operation
ACC ¬ ACC+[m]+C
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
Ö
Ö
Ö
Ö
SBCM A,[m]
Subtract data memory and carry from the accumulator
Description
The contents of the specified data memory and the complement of the carry
flag are subtracted from the accumulator, leaving the result in the data
memory.
Operation
[m] ¬ ACC+[m]+C
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
Ö
Ö
Ö
Ö
SDZ [m]
Skip if decrement data memory is zero
Description
The contents of the specified data memory are decremented by one. If the result is zero, the next instruction is skipped. If the result is zero, the following
instruction, fetched during the current instruction execution, is discarded
and a dummy cycle is replaced to get the proper instruction (two cycles). Otherwise proceed with the next instruction (one cycle).
Operation
Skip if ([m]-1)=0, [m] ¬ ([m]-1)
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
SDZA [m]
Decrement data memory and place result in ACC, skip if zero
Description
The contents of the specified data memory are decremented by one. If the result is zero, the next instruction is skipped. The result is stored in the accumulator but the data memory remains unchanged. If the result is zero, the
following instruction, fetched during the current instruction execution, is
discarded and a dummy cycle is replaced to get the proper instruction (two
cycles). Otherwise proceed with the next instruction (one cycle).
Operation
Skip if ([m]-1)=0, ACC ¬ ([m]-1)
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
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February 25, 2000
Preliminary
HT48R06A-1
SET [m]
Set data memory
Description
Each bit of the specified data memory is set to one.
Operation
[m] ¬ FFH
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
SET [m].i
Set bit of data memory
Description
Bit "i" of the specified data memory is set to one.
Operation
[m].i ¬ 1
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
SIZ [m]
Skip if increment data memory is zero
Description
The contents of the specified data memory are incremented by one. If the result is zero, the following instruction, fetched during the current instruction
execution, is discarded and a dummy cycle is replaced to get the proper instruction (two cycles). Otherwise proceed with the next instruction (one cycle).
Operation
Skip if ([m]+1)=0, [m] ¬ ([m]+1)
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
SIZA [m]
Increment data memory and place result in ACC, skip if zero
Description
The contents of the specified data memory are incremented by one. If the result is zero, the next instruction is skipped and the result is stored in the accumulator. The data memory remains unchanged. If the result is zero, the
following instruction, fetched during the current instruction execution, is
discarded and a dummy cycle is replaced to get the proper instruction (two
cycles). Otherwise proceed with the next instruction (one cycle).
Operation
Skip if ([m]+1)=0, ACC ¬ ([m]+1)
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
39
February 25, 2000
Preliminary
HT48R06A-1
SNZ [m].i
Skip if bit "i" of the data memory is not zero
Description
If bit "i" of the specified data memory is not zero, the next instruction is
skipped. If bit "i" of the data memory is not zero, the following instruction,
fetched during the current instruction execution, is discarded and a dummy
cycle is replaced to get the proper instruction (two cycles). Otherwise proceed
with the next instruction (one cycle).
Operation
Skip if [m].i¹0
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
SUB A,[m]
Subtract data memory from the accumulator
Description
The specified data memory is subtracted from the contents of the accumulator, leaving the result in the accumulator.
Operation
ACC ¬ ACC+[m]+1
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
Ö
Ö
Ö
Ö
SUBM A,[m]
Subtract data memory from the accumulator
Description
The specified data memory is subtracted from the contents of the accumulator, leaving the result in the data memory.
Operation
[m] ¬ ACC+[m]+1
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
Ö
Ö
Ö
Ö
SUB A,x
Subtract immediate data from the accumulator
Description
The immediate data specified by the code is subtracted from the contents of
the accumulator, leaving the result in the accumulator.
Operation
ACC ¬ ACC+x+1
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
Ö
Ö
Ö
Ö
40
February 25, 2000
Preliminary
HT48R06A-1
SWAP [m]
Swap nibbles within the data memory
Description
The low-order and high-order nibbles of the specified data memory (one of
the data memories) are interchanged.
Operation
[m].3~[m].0 « [m].7~[m].4
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
SWAPA [m]
Swap data memory and place result in the accumulator
Description
The low-order and high-order nibbles of the specified data memory are interchanged, writing the result to the accumulator. The contents of the data
memory remain unchanged.
Operation
ACC.3~ACC.0 ¬ [m].7~[m].4
ACC.7~ACC.4 ¬ [m].3~[m].0
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
SZ [m]
Skip if data memory is zero
Description
If the contents of the specified data memory are zero, the following instruction, fetched during the current instruction execution, is discarded and a
dummy cycle is replaced to get the proper instruction (two cycles). Otherwise
proceed with the next instruction (one cycle).
Operation
Skip if [m]=0
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
SZA [m]
Move data memory to ACC, skip if zero
Description
The contents of the specified data memory are copied to the accumulator. If
the contents is zero, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the
proper instruction (two cycles). Otherwise proceed with the next instruction
(one cycle).
Operation
Skip if [m]=0
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
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February 25, 2000
Preliminary
HT48R06A-1
SZ [m].i
Skip if bit "i" of the data memory is zero
Description
If bit "i" of the specified data memory is zero, the following instruction,
fetched during the current instruction execution, is discarded and a dummy
cycle is replaced to get the proper instruction (two cycles). Otherwise proceed
with the next instruction (one cycle).
Operation
Skip if [m].i=0
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
TABRDC [m]
Move the ROM code (current page) to TBLH and data memory
Description
The low byte of ROM code (current page) addressed by the table pointer
(TBLP) is moved to the specified data memory and the high byte transferred
to TBLH directly.
Operation
[m] ¬ ROM code (low byte)
TBLH ¬ ROM code (high byte)
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
TABRDL [m]
Move the ROM code (last page) to TBLH and data memory
Description
The low byte of ROM code (last page) addressed by the table pointer (TBLP)
is moved to the data memory and the high byte transferred to TBLH directly.
Operation
[m] ¬ ROM code (low byte)
TBLH ¬ ROM code (high byte)
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
XOR A,[m]
Logical XOR accumulator with data memory
Description
Data in the accumulator and the indicated data memory perform a bitwise
logical Exclusive_OR operation and the result is stored in the accumulator.
Operation
ACC ¬ ACC "XOR" [m]
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
¾
¾
42
February 25, 2000
Preliminary
HT48R06A-1
XORM A,[m]
Logical XOR data memory with the accumulator
Description
Data in the indicated data memory and the accumulator perform a bitwise
logical Exclusive_OR operation. The result is stored in the data memory. The
zero flag is affected.
Operation
[m] ¬ ACC "XOR" [m]
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
¾
¾
XOR A,x
Logical XOR immediate data to the accumulator
Description
Data in the the accumulator and the specified data perform a bitwise logical
Exclusive_OR operation. The result is stored in the accumulator. The zero
flag is affected.
Operation
ACC ¬ ACC "XOR" x
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
¾
¾
43
February 25, 2000
Preliminary
HT48R06A-1
Holtek Semiconductor Inc. (Headquarters)
No.3 Creation Rd. II, Science-based Industrial Park, Hsinchu, Taiwan, R.O.C.
Tel: 886-3-563-1999
Fax: 886-3-563-1189
Holtek Semiconductor Inc. (Taipei Office)
5F, No.576, Sec.7 Chung Hsiao E. Rd., Taipei, Taiwan, R.O.C.
Tel: 886-2-2782-9635
Fax: 886-2-2782-9636
Fax: 886-2-2782-7128 (International sales hotline)
Holtek Semiconductor (Hong Kong) Ltd.
RM.711, Tower 2, Cheung Sha Wan Plaza, 833 Cheung Sha Wan Rd., Kowloon, Hong Kong
Tel: 852-2-745-8288
Fax: 852-2-742-8657
Copyright Ó 2000 by HOLTEK SEMICONDUCTOR INC.
The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek
assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are
used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications
will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holtek reserves the right to alter its products without prior
notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw.
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February 25, 2000