HOLTEK HT48E30

HT48E30
I/O Type 8-Bit MTP MCU With EEPROM
Technical Document
· Tools Information
· FAQs
· Application Note
-
HA0086E
HA0087E
HA0088E
HA0089E
HT48E MCU Series - Using Assembly Language to Write to the 1K EEPROM Data Memory
HT48E MCU Series - Using C Language to Write to the 1K EEPROM Data Memory
HT48E MCU Series - Using Assembly Language to Write to the 2K EEPROM Data Memory
HT48E MCU Series - Using C Language to Write to the 2K EEPROM Data Memory
Features
· Operating voltage:
· Buzzer driving pair and PFD supported
fSYS=4MHz: 2.2V~5.5V
fSYS=8MHz: 3.3V~5.5V
· HALT function and wake-up feature reduce power
consumption
· Low voltage reset function
· 4-level subroutine nesting
· 23 bidirectional I/O lines (max.)
· Up to 0.5ms instruction cycle with 8MHz system clock
· 1 interrupt input shared with an I/O line
at VDD=5V
· 8-bit programmable timer/event counter with overflow
· Bit manipulation instruction
interrupt and 8-stage prescaler
· 14-bit table read instruction
· On-chip crystal and RC oscillator
· 63 powerful instructions
· Watchdog Timer
· 106 erase/write cycles EEPROM data memory
· 1,000 erase/write cycles MTP program memory
· EEPROM data retention > 10 years
· 2048´14 program memory ROM (MTP)
· All instructions in one or two machine cycles
· 128´8 data memory EEPROM
· In system programming (ISP)
· 96´8 data memory RAM
· 24/28-pin SKDIP/SOP package
General Description
wake-up functions, watchdog timer, buzzer driver, as
well as low cost, enhance the versatility of these devices
to suit a wide range of application possibilities such as
industrial control, consumer products, subsystem controllers, etc.
The HT48E30 is an 8-bit high performance, RISC architecture microcontroller device specifically designed for
multiple I/O control product applications.
The advantages of low power consumption, I/O flexibility, timer functions, oscillator options, HALT and
Rev. 1.20
1
March 3, 2006
HT48E30
Block Diagram
IN T /P G 0
In te rru p t
C ir c u it
P ro g ra m
M e m o ry
S T A C K
4 L e v e ls
P ro g ra m
C o u n te r
M
T M R 0
IN T C
X
T M R /P C 0
T M R 0 C
P G 0
In s tr u c tio n
R e g is te r
U
M
M P
D A T A
M e m o ry
X
fS
E N /D IS
W D T S
U
W D T P r e s c a le r
M
P r e s c a le r
M
W D T
U
Y S
U
fS
Y S
X
/4
X
W D T O S C
P A C
M U X
In s tr u c tio n
D e c o d e r
P B C
P G 1
P G 2
S h ifte r
P O R T B
O S
R E
V D
V S
C 1
S
D
S
P O R T C
P C
A C C
D a ta M e m o ry
E E P R O M
P B 0 ~ P B 7
P B
P C C
O S C 2
P A 0 ~ P A 7
B Z /B Z
S T A T U S
A L U
T im in g
G e n e ra to r
P O R T A
P A
P G C
E E C R
P O R T G
P G
P C 0 ~ P C 5
P G 0
Pin Assignment
1
2 8
P B 6
P B 4
2
2 7
P B 7
P B 5
1
2 4
P B 6
P A 3
3
2 6
P A 4
P B 4
2
2 3
P B 7
P A 2
4
2 5
P A 5
P A 3
3
2 2
P A 4
P A 1
5
2 4
P A 6
P A 2
4
2 1
P A 5
P A 0
6
2 3
P A 7
P A 1
5
2 0
P A 6
P B 3
7
2 2
O S C 2
P A 0
6
1 9
P A 7
P B 2
8
2 1
O S C 1
P B 3
7
1 8
O S C 2
P B 1 /B Z
9
2 0
V D D
P B 2
8
1 7
O S C 1
P B 0 /B Z
1 0
1 9
R E S
P B 1 /B Z
9
1 6
V D D
V S S
1 1
1 8
P C 5
P B 0 /B Z
1 0
1 5
R E S
P G 0 /IN T
1 2
1 7
P C 4
V S S
1 1
1 4
P C 2
P C 0 /T M R
1 3
1 6
P C 3
P G 0 /IN T
1 2
1 3
P C 0 /T M R
P C 1
1 4
1 5
P C 2
H T 4 8 E 3 0
2 4 S K D IP -A /S O P -A
Rev. 1.20
P B 5
H T 4 8 E 3 0
2 8 S K D IP -A /S O P -A
2
March 3, 2006
HT48E30
Pad Description
Pad Name
I/O
Options
Description
PA0~PA7
I/O
Pull-high*
Wake-up
CMOS/Schmitt trigger
Input
Bidirectional 8-bit input/output port. Each bit can be configured as a
wake-up input by options. Software instructions determine the CMOS
output or Schmitt trigger or CMOS input (depends on options) with
pull-high resistor (determined by 1-bit pull-high options).
Bidirectional 8-bit input/output port. Software instructions determine the
CMOS output or Schmitt trigger input with pull-high resistor (determined by pull-high options).
The PB0 and PB1 are pin-shared with the BZ and BZ, respectively.
Once the PB0 or PB1 is selected as buzzer driving outputs, the output
signals come from an internal PFD generator (shared with timer/event
counter).
PB0/BZ
PB1/BZ
PB2~PB7
I/O
Pull-high*
PB0 or BZ
PB1 or BZ
VSS
¾
¾
Negative power supply, ground
PG0/INT
I/O
Pull-high*
Bidirectional I/O lines. Software instructions determine the CMOS output or Schmitt trigger input with pull-high resistor (determined by 1-bit
pull-high options). This external interrupt input is pin-shared with PG0.
The external interrupt input is activated on a high to low transition.
PC0/TMR
PC1~PC5
I/O
Pull-high*
Bidirectional I/O lines. Software instructions determine the CMOS output or Schmitt trigger input with pull-high resistor (determined by 1-bit
pull-high options). The timer input are pin-shared with PC0.
RES
I
¾
Schmitt trigger reset input. Active low.
VDD
¾
¾
Positive power supply
OSC1
OSC2
I
O
Crystal or RC
Note:
OSC1and OSC2 are connected to an RC network or Crystal (determined by options) for the internal system clock. In the case of RC operation, OSC2 is the output terminal for 1/4 system clock.
²*² The pull-high resistors of each I/O port (PA, PB, PC, PG) are controlled by a 1-bit option.
CMOS or Schmitt trigger option of port A is controlled by a 1-bit option.
Absolute Maximum Ratings
Supply Voltage ...........................VSS-0.3V to VSS+6.0V
Storage Temperature ............................-50°C to 125°C
Input Voltage..............................VSS-0.3V to VDD+0.3V
Operating Temperature...........................-40°C to 85°C
Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may
cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed
in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
D.C. Characteristics
Symbol
VDD
IDD1
Parameter
Operating Voltage
Ta=25°C
Test Conditions
Conditions
VDD
Rev. 1.20
Unit
2.2
¾
5.5
V
¾
fSYS=8MHz
3.3
¾
5.5
V
¾
0.6
1.5
mA
¾
2
4
mA
¾
0.8
1.5
mA
¾
2.5
4
mA
¾
4
8
mA
3V
Operating Current (Crystal OSC)
3V
Operating Current (RC OSC)
Operating Current
(Crystal OSC, RC OSC)
Max.
fSYS=4MHz
No load, fSYS=4MHz
No load, fSYS=4MHz
5V
IDD3
Typ.
¾
5V
IDD2
Min.
5V
No load, fSYS=8MHz
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March 3, 2006
HT48E30
Symbol
ISTB1
Parameter
Test Conditions
Conditions
VDD
3V
Standby Current (WDT Enabled)
No load*, system HALT
5V
ISTB2
3V
Standby Current (WDT Disabled)
No load*, system HALT
5V
Min.
Typ.
Max.
Unit
¾
¾
10
mA
¾
¾
15
mA
¾
¾
3
mA
¾
¾
5
mA
VIL1
Input Low Voltage for I/O Ports
¾
¾
0
¾
0.3VDD
V
VIH1
Input High Voltage for I/O Ports
¾
¾
0.7VDD
¾
VDD
V
VIL2
Input Low Voltage (RES)
¾
¾
0
¾
0.4VDD
V
VIH2
Input High Voltage (RES)
¾
¾
0.9VDD
¾
VDD
V
VLVR
Low Voltage Reset Voltage
¾
LVR enabled
2.7
3.0
3.3
V
IOL
3V
VOL=0.1VDD
4
8
¾
mA
I/O Port Sink Current
5V
VOL=0.1VDD
10
20
¾
mA
3V
VOH=0.9VDD
-2
-4
¾
mA
5V
VOH=0.9VDD
-5
-10
¾
mA
IOH
RPH
I/O Port Source Current
3V
¾
20
60
100
kW
5V
¾
10
30
50
kW
Pull-high Resistance
Note: ²*² All tests are conducted with the I/O pins setup as outputs and set to a low value.
A.C. Characteristics
Symbol
fSYS1
fSYS2
fTIMER
tWDTOSC
Parameter
System Clock (Crystal OSC)
System Clock (RC OSC)
Timer I/P Frequency (TMR)
Ta=25°C
Test Conditions
VDD
Conditions
Min.
Typ.
Max.
Unit
¾
2.2V~5.5V
400
¾
4000
kHz
¾
3.3V~5.5V
400
¾
8000
kHz
¾
2.2V~5.5V
400
¾
4000
kHz
¾
3.3V~5.5V
400
¾
8000
kHz
¾
2.2V~5.5V
0
¾
4000
kHz
¾
3.3V~5.5V
0
¾
8000
kHz
3V
¾
45
90
180
ms
5V
¾
32
65
130
ms
11
23
46
ms
8
17
33
ms
Watchdog Oscillator Period
tWDT1
Watchdog Time-out Period
(WDT OSC)
3V
tWDT2
Watchdog Time-out Period
(System Clock)
¾
Without WDT prescaler
¾
1024
¾
tSYS
tRES
External Reset Low Pulse Width
¾
¾
1
¾
¾
ms
tSST
System Start-up Timer Period
¾
¾
1024
¾
tSYS
tINT
Interrupt Pulse Width
¾
1
¾
¾
ms
Rev. 1.20
Without WDT prescaler
5V
Wake-up from HALT
¾
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March 3, 2006
HT48E30
Functional Description
incremented by one. The program counter then points to
the memory word containing the next instruction code.
Execution Flow
The HT48E30 system clock is derived from either a
crystal or an RC oscillator and is internally divided into
four non-overlapping clocks. One instruction cycle consists of four system clock cycles.
When executing a jump instruction, conditional skip execution, loading into the PCL register, subroutine call or
return from subroutine, initial reset, internal interrupt,
external interrupt or return from interrupt, the PC manipulates the program transfer by loading the address corresponding to each instruction.
Instruction fetching and execution are pipelined in such
a way that a fetch takes an instruction cycle while decoding and execution takes the next instruction cycle.
This pipelining scheme ensures that instructions are effectively executed in one cycle. If an instruction changes
the contents of the program counter, two cycles are required to complete the instruction.
The conditional skip is activated by instructions. Once
the condition is met, the next instruction, fetched during
the current instruction execution, is discarded and a
dummy cycle replaces it to get the proper instruction.
Otherwise proceed with the next instruction.
Program Counter - PC
The lower byte of the program counter (PCL) is a readable and writeable register (06H). Moving data into the
PCL performs a short jump. The destination will be
within the current program ROM page.
The program counter (PC) controls the sequence in
which the instructions stored in the program ROM are
executed and its contents specify a full range of program memory.
When a control transfer takes place, an additional
dummy cycle is required.
After accessing a program memory word to fetch an instruction code, the contents of the program counter are
S y s te m
O S C 2 (R C
C lo c k
T 1
T 2
T 3
T 4
T 1
T 2
T 3
T 4
T 1
T 2
T 3
T 4
o n ly )
P C
P C
P C + 1
F e tc h IN S T (P C )
E x e c u te IN S T (P C -1 )
P C + 2
F e tc h IN S T (P C + 1 )
E x e c u te IN S T (P C )
F e tc h IN S T (P C + 2 )
E x e c u te IN S T (P C + 1 )
Execution Flow
Program Counter
Mode
*10
*9
*8
*7
*6
*5
*4
*3
*2
*1
*0
Initial Reset
0
0
0
0
0
0
0
0
0
0
0
External Interrupt
0
0
0
0
0
0
0
0
1
0
0
Timer/Event Counter Overflow
0
0
0
0
0
0
0
1
0
0
0
@3
@2
@1
@0
Skip
Program Counter+2
Loading PCL
*10
*9
*8
@7
@6
@5
@4
Jump, Call Branch
#10
#9
#8
#7
#6
#5
#4
#3
#2
#1
#0
Return from Subroutine
S10
S9
S8
S7
S6
S5
S4
S3
S2
S1
S0
Program Counter
Note: *10~*0: Program counter bits
S10~S0: Stack register bits
#10~#0: Instruction code bits
Rev. 1.20
@7~@0: PCL bits
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March 3, 2006
HT48E30
· Location 000H
In System Programming
This area is reserved for program initialization. After a
chip reset, the program always begins execution at location 000H.
In system programming allows programming and reprogramming of HT48EXX microcontroller on application
circuit board, this will save time and money, both during
development in the lab. Using a simple 3-wire interface,
the ISP communicates serially with the HT48EXX
microcontroller, reprogramming program memory and
EEPROM data memory on the chip.
Pin Name
Function
PA0
SDATA
Serial data input/output
PA4
SCLK
Serial clock input
RES
RESET
Device reset
VDD
VDD
Power supply
VSS
VSS
Ground
· Location 004H
This area is reserved for the external interrupt service
program. If the INT input pin is activated, the interrupt
is enabled and the stack is not full, the program begins
execution at location 004H.
Description
· Location 008H
This area is reserved for the timer/event counter interrupt service program. If a timer interrupt results from a
timer/event counter overflow, and if the interrupt is enabled and the stack is not full, the program begins execution at location 008H.
· Table location
ISP Pin Assignments
Any location in the program memory space can be
used as look-up tables. The instructions ²TABRDC
[m]² (the current page, one page=256 words) and
²TABRDL [m]² (the last page) transfer the contents of
the lower-order byte to the specified data memory,
and the higher-order byte to TBLH (08H). Only the
destination of the lower-order byte in the table is
well-defined, the other bits of the table word are transferred to the lower portion of TBLH, and the remaining
2-bits words are read as ²0². The Table Higher-order
byte register (TBLH) is read only. The table pointer
(TBLP) is a read/write register (07H), which indicates
the table location. Before accessing the table, the location must be placed in the TBLP. The TBLH is read
only and cannot be restored. If the main routine and
the ISR (Interrupt Service Routine) both employ the
table read instruction, the contents of the TBLH in the
main routine are likely to be changed by the table read
instruction used in the ISR. Errors can occur. In other
words, using the table read instruction in the main routine and the ISR simultaneously should be avoided.
However, if the table read instruction has to be applied
in both the main routine and the ISR, the interrupt is
supposed to be disabled prior to the table read instruction. It will not be enabled until the TBLH has
been backed up. All table related instructions require
two cycles to complete the operation. These areas
may function as normal program memory depending
upon the requirements.
Program Memory - ROM
The program memory is used to store the program instructions which are to be executed. It also contains
data, table, and interrupt entries, and is organized into
2048´14 bits, addressed by the program counter and table pointer.
Certain locations in the program memory are reserved
for special usage:
0 0 0 H
D e v ic e In itia liz a tio n P r o g r a m
0 0 4 H
E x te r n a l In te r r u p t S u b r o u tin e
0 0 8 H
T im e r /E v e n t C o u n te r
In te r r u p t S u b r o u tin e
P ro g ra m
M e m o ry
n 0 0 H
L o o k - u p T a b le ( 2 5 6 w o r d s )
n F F H
7 0 0 H
L o o k - u p T a b le ( 2 5 6 w o r d s )
7 F F H
1 4 b its
N o te : n ra n g e s fro m
0 to 7
Program Memory
Instruction
Table Location
*10
*9
*8
*7
*6
*5
*4
*3
*2
*1
*0
TABRDC [m]
P10
P9
P8
@7
@6
@5
@4
@3
@2
@1
@0
TABRDL [m]
1
1
1
@7
@6
@5
@4
@3
@2
@1
@0
Table Location
Note: *10~*0: Table location bits
P10~P8: Current program counter bits
@7~@0: Table pointer bits
Rev. 1.20
6
March 3, 2006
HT48E30
0 0 H
Stack Register - STACK
This is a special part of the memory which is used to
save the contents of the Program Counter only. The
stack is organized into 4 levels and is neither part of the
data nor part of the program space, and is neither readable nor writeable. The activated level is indexed by the
Stack Pointer (SP) and is neither readable nor writeable.
At a subroutine call or interrupt acknowledge signal, the
contents of the program counter are pushed onto the
stack. At the end of a subroutine or an interrupt routine,
signaled by a return instruction (RET or RETI), the program counter is restored to its previous value from the
stack. After a chip reset, the Stack Pointer will point to
the top of the stack.
M P 0
0 2 H
In d ir e c t A d d r e s s in g R e g is te r 1
0 3 H
M P 1
0 4 H
B P
0 5 H
A C C
0 6 H
P C L
0 7 H
T B L P
0 8 H
T B L H
0 9 H
W D T S
0 A H
S T A T U S
0 B H
IN T C
0 C H
0 D H
T M R
0 E H
T M R C
0 F H
S p e c ia l P u r p o s e
D a ta M e m o ry
1 0 H
1 1 H
If the stack is full and a non-masked interrupt takes
place, the interrupt request flag will be recorded but the
acknowledge signal will be inhibited. When the stack
pointer is decremented (by RET or RETI), the interrupt
will be serviced. This feature prevents stack overflow allowing the programmer to use the structure more easily.
In a similar case, if the stack is full and a ²CALL² is subsequently executed, stack overflow occurs and the first
entry will be lost (only the most recent 4 return addresses are stored).
1 2 H
P A
1 3 H
P A C
1 4 H
P B
1 5 H
P B C
1 6 H
P C
1 7 H
P C C
1 8 H
1 9 H
1 A H
1 B H
1 C H
: U n u s e d
1 D H
Data Memory - RAM
The data memory has a capacity of 115´8 bits and is divided into two functional groups: special function registers and general purpose data memory (96´8). Most
are read/write, but some are read only.
1 E H
P G
1 F H
2 0 H
P G C
7 F H
R e a d a s "0 0 "
4 0 H
G e n e ra l P u rp o s e
D a ta M e m o ry
(9 6 B y te s )
B a n k 0
The special function registers include the Indirect addressing registers (IAR0;00H), Timer/event counter
(TMR;0DH), Timer/event counter control register
(TMRC;0EH), Program counter lower-order byte register (PCL;06H), Memory pointer registers (MP;01H),
Accumulator (ACC;05H), Table pointer (TBLP;07H),
Table higher-order byte register (TBLH;08H), Status
register (STATUS;0AH), Interrupt control register
(INTC;0BH), Watchdog Timer option setting register
(WDTS;09H), I/O registers (PA;12H, PB;14H, PC;16H,
PG;1EH) and I/O control registers (PAC;13H,
PBC;15H, PCC;17H, PGC;1FH). The remaining space
before the 20H is reserved for future expanded usage
and reading these locations will return the result ²00H².
The general purpose data memory, addressed from
20H to 7FH, is used for data and control information under instruction commands.
E E C R
B a n k 1
RAM Mapping
Indirect Addressing Register
Location 00H and 02H are indirect addressing registers
that are not physically implemented. Any read/write operation on [00H] and [02H] access the RAM pointed to
by MP0 (01H) and MP1 (03H), respectively. Reading location 00H or 02H indirectly returns the result 00H.
While, writing it indirectly leads to no operation.
The function of data movement between two indirect addressing registers is not supported. The memory pointer
registers, MP0 and MP1, are both 7-bit registers used to
access the RAM by combining corresponding indirect
addressing registers. MP0 can only be applied to data
memory in Bank 0, while MP1 can be applied to data
memory in Bank 0 and Bank 1.
All of the data memory areas can handle arithmetic,
logic, increment, decrement and rotate operations directly. Except for some dedicated bits, each bit in the
data memory can be set and reset by ²SET [m].i² and
²CLR [m].i². They are also indirectly accessible through
memory pointer registers (MP). The control register of
the EEPROM data memory is located at [40H] in Bank 1.
Rev. 1.20
In d ir e c t A d d r e s s in g R e g is te r 0
0 1 H
7
March 3, 2006
HT48E30
In addition, on entering the interrupt sequence or executing the subroutine call, the status register will not be
pushed onto the stack automatically. If the contents of
the status are important and if the subroutine may corrupt the status register, precautions must be taken to
save it properly.
Accumulator
The accumulator is closely related to ALU operations. It
is also mapped to location 05H of the data memory and
can carry out immediate data operations. The data
movement between two data memory locations must
pass through the accumulator.
Arithmetic and logic unit - ALU
Interrupt
This circuit performs 8-bit arithmetic and logic operations. The ALU provides the following functions:
The device provides an external interrupt and internal
timer/event counter interrupts. The Interrupt Control
Register (INTC;0BH) contains the interrupt control bits
to set the enable or disable and the interrupt request
flags.
· Arithmetic operations (ADD, ADC, SUB, SBC, DAA)
· Logic operations (AND, OR, XOR, CPL)
· Rotation (RL, RR, RLC, RRC)
Once an interrupt subroutine is serviced, all the other interrupts will be blocked (by clearing the EMI bit). This
scheme may prevent any further interrupt nesting. Other
interrupt requests may occur during this interval but only
the interrupt request flag is recorded. If a certain interrupt requires servicing within the service routine, the
EMI bit and the corresponding bit of the INTC may be set
to allow interrupt nesting. If the stack is full, the interrupt
request will not be acknowledged, even if the related interrupt is enabled, until the SP is decremented. If immediate service is desired, the stack must be prevented from
becoming full.
· Increment and Decrement (INC, DEC)
· Branch decision (SZ, SNZ, SIZ, SDZ ....)
The ALU not only saves the results of a data operation
but also changes the status register.
Status Register - STATUS
This 8-bit register (0AH) contains the zero flag (Z), carry
flag (C), auxiliary carry flag (AC), overflow flag (OV),
power down flag (PDF), and watchdog time-out flag
(TO). It also records the status information and controls
the operation sequence.
With the exception of the TO and PDF flags, bits in
the status register can be altered by instructions like
most other registers. Any data written into the status
register will not change the TO or PDF flag. In addition operations related to the status register may give
different results from those intended. The TO flag
can be affected only by a system power-up, a WDT
time-out or executing the ²CLR WDT² or ²HALT² instruction. The PDF flag can be affected only by executing the ²HALT² or ²CLR WDT² instruction or
during a system power-up.
All these kinds of interrupts have a wake-up capability.
As an interrupt is serviced, a control transfer occurs by
pushing the program counter onto the stack, followed by
a branch to a subroutine at specified location in the program memory. Only the program counter is pushed onto
the stack. If the contents of the register or status register
(STATUS) are altered by the interrupt service program
which corrupts the desired control sequence, the contents should be saved in advance.
External interrupts are triggered by a high to low transition of the INT and the related interrupt request flag (EIF;
bit 4 of INTC) will be set. When the interrupt is enabled,
the stack is not full and the external interrupt is active, a
subroutine call to location 04H will occur. The interrupt
The Z, OV, AC and C flags generally reflect the status of
the latest operations.
Bit No.
Label
Function
0
C
C is set if an operation results in a carry during an addition operation or if a borrow does not
take place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate
through carry instruction.
1
AC
AC is set if an operation results in a carry out of the low nibbles in addition or no borrow from
the high nibble into the low nibble in subtraction; otherwise AC is cleared.
2
Z
3
OV
OV is set if an operation results in a carry into the highest-order bit but not a carry out of the
highest-order bit, or vice versa; otherwise OV is cleared.
4
PDF
PDF is cleared by a system power-up or executing the ²CLR WDT² instruction.
PDF is set by executing the ²HALT² instruction.
5
TO
TO is cleared by a system power-up or executing the ²CLR WDT² or ²HALT² instruction.
TO is set by a WDT time-out.
6~7
¾
Unused bit, read as ²0²
Z is set if the result of an arithmetic or logic operation is zero; otherwise Z is cleared.
Status (0AH) Register
Rev. 1.20
8
March 3, 2006
HT48E30
Bit No.
Label
Function
0
EMI
Controls the master (global) interrupt (1= enabled; 0= disabled)
1
EEI
Controls the external interrupt (1= enabled; 0= disabled)
2
ETI
Controls the Timer/Event Counter 0 interrupt (1= enabled; 0= disabled)
3, 6~7
¾
Unused bit, read as ²0²
4
EIF
External interrupt request flag (1= active; 0= inactive)
5
TF
Internal Timer/Event Counter 0 request flag (1= active; 0= inactive)
INTC (0BH) Register
Oscillator Configuration
request flag (EIF) and EMI bits will be cleared to disable
other interrupts.
There are 2 oscillator circuits in the microcontroller.
The internal timer/event counter interrupt is initialized by
setting the timer/event counter interrupt request flag
(TF; bit 5 of INTC), caused by a timer overflow. When
the interrupt is enabled, the stack is not full and the TF
bit is set, a subroutine call to location 08H will occur. The
related interrupt request flag (TF) will be reset and the
EMI bit cleared to disable further interrupts.
V
O S C 1
C r y s ta l O s c illa to r
Priority
1
04H
Timer/Event Counter Overflow
2
08H
R C O s c illa to r
If an RC oscillator is used, an external resistor between
OSC1 and VDD is required and the resistance must
range from 24kW to 1MW. The system clock, divided by
4, is available on OSC2, which can be used to synchronize external logic. The RC oscillator provides the most
cost effective solution. However, the frequency of oscillation may vary with VDD, temperatures and the chip itself due to process variations. It is, therefore, not
suitable for timing sensitive operations where an accurate oscillator frequency is desired.
The timer/event counter interrupt request flag (TF), external interrupt request flag (EIF), enable timer/event
counter interrupt bit (ETI), enable external interrupt bit
(EEI) and enable master interrupt bit (EMI) constitute an
interrupt control register (INTC) which is located at 0BH
in the data memory. EMI, EEI, ETI are used to control
the enabling/disabling of interrupts. These bits prevent
the requested interrupt from being serviced. Once the
interrupt request flags (TF, EIF) are set, they will remain
in the INTC register until the interrupts are serviced or
cleared by a software instruction.
If a Crystal oscillator is used, a crystal across OSC1 and
OSC2 is needed to provide the feedback and phase
shift required for the oscillator. No other external components are required. In stead of a crystal, a resonator can
also be connected between OSC1 and OSC2 to obtain
a frequency reference, but two external capacitors in
OSC1 and OSC2 are required.
The WDT oscillator is a free running on-chip RC oscillator, and no external components are required. Even if
the system enters the power down mode and the system clock is stopped, the oscillator still works within a
period of 65ms at 5V. The WDT oscillator can be disabled by options to conserve power.
It is recommended that a program does not use the
²CALL subroutine² within the interrupt subroutine. Interrupts often occur in an unpredictable manner or need to
be serviced immediately in some applications. If only one
stack is left and enabling the interrupt is not well controlled, the original control sequence will be damaged
once the ²CALL² operates in the interrupt subroutine.
Rev. 1.20
O S C 2
All of them are designed for system clocks, namely, external RC oscillator and external Crystal oscillator,
which are determined by options. No matter what oscillator type is selected, the signal provides the system
clock. The HALT mode stops the system oscillator and
ignores an external signal to conserve power.
Vector
External Interrupt
fS Y S /4
N M O S O p e n D r a in
O S C 1
System Oscillator
Interrupts, occurring in the interval between the rising
edges of two consecutive T2 pulses, will be serviced on
the latter of the two T2 pulses, if the corresponding interrupts are enabled. In the case of simultaneous requests
the following table shows the priority that is applied.
These can be masked by resetting the EMI bit.
Interrupt Source
4 7 0 p F
O S C 2
During the execution of an interrupt subroutine, other interrupt acknowledge signals are held until the ²RETI² instruction is executed or the EMI bit and the related
interrupt control bit are set to 1 (if the stack is not full). To
return from the interrupt subroutine, ²RET² or ²RETI²
may be invoked. RETI will set the EMI bit to enable an interrupt service, but RET will not.
D D
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March 3, 2006
HT48E30
Watchdog Timer - WDT
The WDT overflow under normal operation will initialize
a ²chip reset² and set the status bit ²TO². But in the
HALT mode, the overflow will initialize a ²warm reset²
and only the Program Counter and SP are reset to zero.
To clear the contents of WDT (including the WDT
prescaler), three methods are adopted; external reset (a
low level to RES), software instruction and a ²HALT² instruction. The software instruction includes ²CLR WDT²
and the other set - ²CLR WDT1² and ²CLR WDT2². Of
these two types of instruction, only one can be active depending on the option - ²CLR WDT times selection option². If the ²CLR WDT² is selected (i.e. CLRWDT times
equal one), any execution of the ²CLR WDT² instruction
will clear the WDT. In the case that ²CLR WDT1² and
²CLR WDT2² are chosen (i.e. CLRWDT times equal
two), these two instructions must be executed to clear
the WDT; otherwise, the WDT may reset the chip as a
result of time-out.
The WDT clock source is implemented by a dedicated
RC oscillator (WDT oscillator), instruction clock (system
clock divided by 4), determines the options. This timer is
designed to prevent a software malfunction or sequence
from jumping to an unknown location with unpredictable
results. The Watchdog Timer can be disabled by options. If the Watchdog Timer is disabled, all the executions related to the WDT result in no operation.
Once the internal WDT oscillator (RC oscillator with a
period of 65ms at 5V normally) is selected, it is first divided by 256 (8-stage) to get the nominal time-out period of 18.6ms at 5V. This time-out period may vary with
temperatures, VDD and process variations. By invoking
the WDT prescaler, longer time-out periods can be realized. Writing data to WS2, WS1, WS0 (bit 2,1,0 of the
WDTS) can give different time-out periods. If WS2, WS1,
and WS0 are all equal to 1, the division ratio is up to 1:128,
and the maximum time-out period is 2.4s at 5V seconds. If
the WDT oscillator is disabled, the WDT clock may still
come from the instruction clock and operates in the same
manner except that in the HALT state the WDT may stop
counting and lose its protecting purpose. In this situation
the logic can only be restarted by an external logic. The
high nibble and bit 3 of the WDTS are reserved for user¢s
defined flags, which can be used to indicate some specified status.
Power Down Operation - HALT
The HALT mode is initialized by the ²HALT² instruction
and results in the following...
· The system oscillator will be turned off but the WDT
oscillator remains running (if the WDT oscillator is selected).
· The contents of the on chip RAM and registers remain
unchanged.
If the device operates in a noisy environment, using the
on-chip RC oscillator (WDT OSC) is strongly recommended, since the HALT will stop the system clock.
WS2
WS1
WS0
Division Ratio
0
0
0
1:1
0
0
1
1:2
0
1
0
1:4
0
1
1
1:8
1
0
0
1:16
1
0
1
1:32
1
1
0
1:64
1
1
1
1:128
· WDT and WDT prescaler will be cleared and re-
counted again (if the WDT clock is from the WDT oscillator).
· All of the I/O ports maintain their original status.
· The PDF flag is set and the TO flag is cleared.
The system can leave the HALT mode by means of an
external reset, an interrupt, an external falling edge signal on port A or a WDT overflow. An external reset
causes a device initialization and the WDT overflow performs a ²warm reset². After the TO and PDF flags are
examined, the reason for chip reset can be determined.
The PDF flag is cleared by a system power-up or executing the ²CLR WDT² instruction and is set when executing the ²HALT² instruction. The TO flag is set if a
WDT time-out occurs, and causes a wake-up that only
resets the Program Counter and SP; the others remain
in their original status.
WDTS (09H) Register
S y s te m
C lo c k /4
W D T P r e s c a le r
O p tio n
S e le c t
8 - b it C o u n te r
W D T
O S C
7 - b it C o u n te r
8 -to -1 M U X
W S 0 ~ W S 2
W D T T im e - o u t
Watchdog Timer
Rev. 1.20
10
March 3, 2006
HT48E30
The port A wake-up and interrupt methods can be considered as a continuation of normal execution. Each bit
in port A can be independently selected to wake-up the
device by options. Awakening from an I/O port stimulus,
the program will resume execution of the next instruction. If it awakens from an interrupt, two sequence may
occur. If the related interrupt is disabled or the interrupt
is enabled but the stack is full, the program will resume
execution at the next instruction. If the interrupt is enabled and the stack is not full, a regular interrupt response takes place. If an interrupt request flag is set to
²1² before entering the HALT mode, the wake-up function of the related interrupt will be disabled. Once a
wake-up event occurs, it takes 1024 (system clock period) to resume to normal operation. In other words, a
dummy period will be inserted after a wake-up. If the
wake-up results from an interrupt acknowledge signal,
the actual interrupt subroutine execution will be delayed
by one or more cycles. If the wake-up results in the next
instruction execution, this will be executed immediately
after the dummy period is finished.
V D D
R E S
tS
S S T T im e - o u t
C h ip
R e s e t
Reset Timing Chart
V
D D
0 .0 1 m F *
1 0 0 k W
R E S
1 0 k W
0 .1 m F *
Reset Circuit
Note:
To minimize power consumption, all the I/O pins should
be carefully managed before entering the HALT status.
²*² Make the length of the wiring, which is connected to the RES pin as short as possible, to
avoid noise interference.
H A L T
Reset
W a rm
· RES reset during normal operation
R E S
C o ld
R e s e t
· RES reset during HALT
· WDT time-out reset during normal operation
O S C 1
The time-out during HALT is different from other chip reset conditions, since it can perform a ²warm reset² that
resets only the Program Counter and SP, leaving the
other circuits in their original state. Some registers remain unchanged during other reset conditions. Most
registers are reset to the ²initial condition² when the reset conditions are met. By examining the PDF and TO
flags, the program can distinguish between different
²chip resets².
PDF
0
0
RES reset during power-up
u
u
RES reset during normal operation
0
1
RES wake-up HALT
1
u
WDT time-out during normal operation
1
1
WDT wake-up HALT
S S T
1 0 - b it R ip p le
C o u n te r
S y s te m
R e s e t
Reset Configuration
When a system reset occurs, the SST delay is added
during the reset period. Any wake-up from HALT will enable an SST delay.
RESET Conditions
An extra option load time delay is added during system
reset (power-up, WDT time-out at normal mode or RES
reset).
The functional unit chip reset status are shown below.
Note: ²u² stands for unchanged”
To guarantee that the system oscillator is started and
stabilized, the SST (System Start-up Timer) provides an
extra delay of 1024 system clock pulses when the system reset (power-up, WDT time-out or RES reset) or the
system awakes from the HALT state.
Rev. 1.20
R e s e t
W D T
There are three ways in which a reset can occur:
TO
S T
11
Program Counter
000H
Interrupt
Disable
Prescaler
Clear
WDT
Clear. After master reset,
WDT begins counting
Timer/Event Counter
Off
Input/Output Ports
Input mode
Stack Pointer
Points to the top of the stack
March 3, 2006
HT48E30
The registers status is summarized in the following table.
Register
MP0
MP1
Reset
(Power-on)
WDT Time-out
(Normal Operation)
RES Reset
(Normal Operation)
RES Reset
(HALT)
WDT Time-out
(HALT)*
-xxx xxxx
-uuu uuuu
-uuu uuuu
-uuu uuuu
-uuu uuuu
-xxx xxxx
-uuu uuuu
-uuu uuuu
-uuu uuuu
-uuu uuuu
BP
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
ACC
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
000H
000H
000H
000H
000H
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
Program
Counter
TBLP
TBLH
--xx xxxx
--uu uuuu
--uu uuuu
--uu uuuu
--uu uuuu
WDTS
0000 0111
0000 0111
0000 0111
0000 0111
uuuu uuuu
STATUS
--00 xxxx
--1u uuuu
--uu uuuu
--01 uuuu
--11 uuuu
INTC
--00 0000
--00 0000
--00 0000
--00 0000
--uu uuuu
TMR
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
TMRC
00-0 1000
00-0 1000
00-0 1000
00-0 1000
uu-u uuuu
PA
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PAC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PB
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PBC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PC
--11 1111
--11 1111
--11 1111
--11 1111
--uu uuuu
PCC
--11 1111
--11 1111
--11 1111
--11 1111
--uu uuuu
PG
---- ---1
---- ---1
---- ---1
---- ---1
---- ---u
PGC
---- ---1
---- ---1
---- ---1
---- ---1
---- ---u
1000 ----
1000 ----
1000 ----
1000 ----
uuuu ----
EECR
Note:
²*² stands for ²warm reset²
²u² stands for ²unchanged²
²x² stands for ²unknown²
Timer/Event Counter
register and reading TMR retrieves the contents of the
timer/event counter. The TMRC is a timer/event counter
control register, which defines some options.
Timer/event counters (TMR) is implemented in the
microcontroller. The timer/event counter contains an 8-bit
programmable count-up counter and the clock may come
from an external source or from the system clock.
The TM0, TM1 bits define the operating mode. The
event count mode is used to count external events,
which means the clock source comes from an external
(TMR) pin. The timer mode functions as a normal timer
with the clock source coming from the fINT clock. The
pulse width measurement mode can be used to count the
high or low level duration of the external signal (TMR). The
counting is based on the fINT clock.
Using the internal clock sources, there are 2 reference
time-bases for the timer/event counter. The internal
clock source can be selected as coming from fSYS or by
options. Using an external clock input allows the user to
count external events, measure time internals or pulse
widths, or generate an accurate time base. While using
the internal clock allows the user to generate an accurate time base.
In the event count or timer mode, once the timer/event
counter starts counting, it will count from the current
contents in the timer/event counter to FFH. Once overflow occurs, the counter is reloaded from the timer/event
counter preload register and generates the interrupt request flag (TF; bit 5 of INTC) at the same time.
The timer/event counter can generate PFD signals by
using external or internal clock and the PFD frequency
is determine by the equation fINT/[2´(256-N)].
There are 2 registers related to the timer/event counter;
TMR ([0DH]), TMRC ([0EH]). Two physical registers are
mapped to TMR location; writing TMR makes the starting value be placed in the timer/event counter preload
Rev. 1.20
In the pulse width measurement mode with the TON and
TE bits equal to one, once the TMR has received a transient from low to high (or high to low if the TE bits is ²0²)
12
March 3, 2006
HT48E30
But in the other two modes the TON can only be reset by
instructions. The overflow of the timer/event counter is
one of the wake-up sources. No matter what the operation mode is, writing a ²0² to ETI can disable the corresponding interrupt services.
it will start counting until the TMR returns to the original
level and resets the TON. The measured result will remain in the timer/event counter even if the activated
transient occurs again. In other words, only one cycle
measurement can be done. Until setting the TON, the
cycle measurement will function again as long as it receives further transient pulse. Note that, in this operating mode, the timer/event counter starts counting not
according to the logic level but according to the transient
edges. In the case of counter overflows, the counter is
reloaded from the timer/event counter preload register
and issues the interrupt request just like the other two
modes. To enable the counting operation, the timer ON
bit (TON; bit 4 of TMRC) should be set to 1. In the pulse
width measurement mode, the TON will be cleared automatically after the measurement cycle is completed.
Bit No.
In the case of timer/event counter OFF condition, writing
data to the timer/event counter preload register will also
reload that data to the timer/event counter. But if the
timer/event counter is turned on, data written to it will
only be kept in the timer/event counter preload register.
The timer/event counter will still operate until overflow
occurs. When the timer/event counter (reading TMR) is
read, the clock will be blocked to avoid errors. As clock
blocking may results in a counting error, this must be
taken into consideration by the programmer.
Label
Function
Defines the prescaler stages, PSC2, PSC1, PSC0=
000: fINT=fSYS/2
001: fINT=fSYS/4
010: fINT=fSYS/8
PSC0~PSC2 011: fINT=fSYS/16
100: fINT=fSYS/32
101: fINT=fSYS/64
110: fINT=fSYS/128
111: fINT=fSYS/256
0~2
3
TE
Defines the TMR active edge of the timer/event counter:
In Event Counter Mode (TM1,TM0)=(0,1):
1:count on falling edge;
0:count on rising edge
In Pulse Width measurement mode (TM1,TM0)=(1,1):
1: start counting on the rising edge, stop on the falling edge;
0: start counting on the falling edge, stop on the rising edge
4
TON
Enable or disable timer 0 counting (0=disabled; 1=enabled)
5
¾
6
7
TM0
TM1
Unused bit, read as ²0²
Defines the operating mode
01=Event count mode (external clock)
10=Timer mode (internal clock)
11=Pulse width measurement mode
00=Unused
TMRC (0EH) Register
(1 /2 ~ 1 /2 5 6 )
fS
Y S
8 - s ta g e P r e s c a le r
f IN
8 -1 M U X
P S C 2 ~ P S C 0
D a ta B u s
T
T M 1
T M 0
T M R
T im e r /E v e n t C o u n te r
P r e lo a d R e g is te r
R e lo a d
T E
T M 1
T M 0
T O N
P u ls e W id th
M e a s u re m e n t
M o d e C o n tro l
T im e r /E v e n t
C o u n te r
1 /2
O v e r flo w
to In te rru p t
B Z
B Z
Timer/Event Counter
Rev. 1.20
13
March 3, 2006
HT48E30
For output function, CMOS is the only configuration.
These control registers are mapped to locations 13H,
15H, 17H and 1FH.
The bit0~bit2 of the TMRC can be used to define the
pre-scaling stages of the internal clock sources of
timer/event counter. The definitions are as shown. The
overflow signal of the timer/event counter can be used
to generate PFD signals for buzzer driving.
After a chip reset, these input/output lines remain at high
levels or floating state (depending on the pull-high options). Each bit of these input/output latches can be set
or cleared by ²SET [m].i² and ²CLR [m].i² (m=12H, 14H,
16H or 1EH) instructions.
Input/Output Ports
There are 23 bidirectional input/output lines in the
microcontroller, labeled from PA to PC and PG, which
are mapped to the data memory of [12H], [14H], [16H]
and [1EH], respectively. All of these I/O ports can be
used for input and output operations. For input operation, these ports are non-latching, that is, the inputs
must be ready at the T2 rising edge of instruction ²MOV
A,[m]² (m=12H, 14H, 16H or 1EH). For output operation,
all the data is latched and remains unchanged until the
output latch is rewritten.
Some instructions first input data and then follow the
output operations. For example, ²SET [m].i², ²CLR
[m].i², ²CPL [m]², ²CPLA [m]² read the entire port states
into the CPU, execute the defined operations
(bit-operation), and then write the results back to the
latches or the accumulator.
Each line of port A has the capability of waking-up the device. The highest 7-bit of port G are not physically implemented; on reading them a ²0² is returned whereas writing
then results in no operation. See Application note.
Each I/O line has its own control register (PAC, PBC,
PCC, PGC) to control the input/output configuration.
With this control register, CMOS output or Schmitt trigger input with or without pull-high resistor structures can
be reconfigured dynamically under software control. To
function as an input, the corresponding latch of the control register must write a ²1². The input source also depends on the control register. If the control register bit is
²1², the input will read the pad state. If the control register bit is ²0², the contents of the latches will move to the
in t e rn a l bus . Th e l a t t e r i s pos s i b l e i n t h e
²read-modify-write² instruction.
There is a pull-high option available for all I/O lines (bit
option). Once the pull-high option of an I/O line is selected, the I/O line has a pull-high resistor. Otherwise,
the pull-high resistor is absent. It should be noted that a
non-pull-high I/O line operating in input mode will cause
a floating state.
The PB0 and PB1 are pin-shared with BZ and BZ signals, respectively. If the BZ/BZ option is selected, the
output signal in output mode of PB0/PB1 will be the PFD
signal generated by timer/event counter 0 overflow signal. The input mode always remain in its original functions. Once the BZ/BZ option is selected, the buzzer
output signals are controlled by the PB0 data register
only.
The I/O functions of PB0/PB1 are shown below.
PB0 I/O
I
I
O
O
O
O
O
O
O
O
PB1 I/O
I
O
I
I
I
O
O
O
O
O
PB0 Mode
x
x
C
B
B
C
B
B
B
B
PB1 Mode
x
C
x
x
x
C
C
C
B
B
PB0 Data
x
x
D
0
1
D0
0
1
0
1
PB1 Data
x
D
x
x
x
D1
D
D
x
x
PB0 Pad Status
I
I
D
0
B
D0
0
B
0
B
PB1 Pad Status
I
D
I
I
I
D1
D
D
0
B
Note:
²I² input, ²O² output, ²D, D0, D1² data,
²B² buzzer option, BZ or BZ, ²x² don¢t care
²C² CMOS output
Rev. 1.20
14
March 3, 2006
HT48E30
D a ta B u s
C o n tr o l B it
Q
D
W r ite C o n tr o l R e g is te r
V
P u ll- h ig h
O p tio n
D D
Q
C K
S
P A
P B
P C
P G
C h ip R e s e t
R e a d C o n tr o l R e g is te r
W r ite D a ta R e g is te r
( P B 0 , P B 1 O n ly )
D a ta B it
Q
D
C K
S
Q
M
P B 0
B Z /B Z
M
R e a d D a ta R e g is te r
0 ~ P A 7
0 ~ P B 7
0 ~ P C 5
0
U
U
X
B Z E N
( P B 0 , P B 1 O n ly )
X
S y s te m W a k e -u p
( P A o n ly )
O P 0 ~ O P 7
IN T fo r P G 0 O n ly
Input/Output Ports
The PG0 is pin-shared with INT.
The relationship between VDD and VLVR is shown below.
It is recommended that unused or not bonded out I/O
lines should be set as output pins by software instruction
to avoid consuming power under input floating state.
V D D
5 .5 V
V
O P R
5 .5 V
Low Voltage Reset - LVR
The HT48E30 provides a low voltage reset circuit in order to monitor the supply voltage of the device. If the
supply voltage is within the range 0.9V~VLVR, such as
when changing a battery, the LVR will automatically reset the device internally.
V
L V R
3 .3 V
2 .4 V
The LVR includes the following specifications:
0 .9 V
· The low voltage (0.9V~VLVR) has to remain in its orig-
Note:
inal state for longer than 1ms. If the low voltage state
does not exceed 1ms, the LVR will ignore it and will
not perform a reset function.
VOPR is the voltage range for proper chip operation at 4MHz system clock.
· The LVR uses an ²OR² function with the external RES
signal to perform a chip reset.
Rev. 1.20
15
March 3, 2006
HT48E30
V
D D
5 .5 V
V
L V R
L V R
D e te c t V o lta g e
0 .9 V
0 V
R e s e t S ig n a l
N o r m a l O p e r a tio n
R e s e t
R e s e t
*1
*2
Low Voltage Reset
Note:
*1: To make sure that the system oscillator has stabilized, the SST provides an extra delay of 1024 system
clock pulses before starting the normal operation.
*2: Since low voltage state has to be maintained its original state for longer than 1ms, therefore after 1ms delay,
the device enters the reset mode.
EEPROM Data Memory
The 128´8 bits EEPROM data memory is readable and writable during normal operation. It is indirectly addressed
through the control register EECR ([40H] in Bank 1). The EECR can be read and written to only by indirect addressing
mode using MP1.
Bit No.
Label
Function
0~3
¾
Unused bit, read as ²0²
4
CS
EEPROM data memory select
5
SK
Serial clock input to EEPROM data memory
6
DI
Serial data input to EEPROM data memory
7
DO
Serial data output from EEPROM data memory
EECR (40H) Register
C S
S K
C S
E E C R
S K
C o n tro l
L o g ic
a n d
C lo c k
G e n e ra to r
D I
D O
V
D D
D I
D a ta
R e g is te r
A d d r e s s R e g is te r
A d d re s s D e c o d e r
M e m o r y C e ll A r r a y
1 K : (1 2 8 ´ 8 )
O u tp u t B u ffe r
D O
S a m e a s H T 9 3 L C 4 6
EEPROM Data Memory Block Diagram
Rev. 1.20
16
March 3, 2006
HT48E30
memory at the rising edge of SK. During the READ cycle, DO acts as the data output and during the WRITE or
ERASE cycle, DO indicates the BUSY/READY status.
When the DO is active for read data or as a BUSY/
READY indicator the CS pin must be high; otherwise
DO will be in a high state. For successful instructions,
CS must be low once after the instruction is sent. After
power-on, the device is by default in the EWDS state.
And, an EWEN instruction must be performed before
any ERASE or WRITE instruction can be executed.
The EEPROM data memory is accessed via a
three-wire serial communication interface by writing to
EECR. It is arranged into 128 words by 8 bits. The
EEPROM data memory contains seven instructions:
READ, ERASE, WRITE, EWEN, EWDS, ERAL and
WRAL. These instructions are all made up of 10 bits
data: 1 start bit, 2 op-code bits and 7 address bits.
By writing CS, SK and DI, these instructions can be
given to the EEPROM. These serial instruction data presented at the DI will be written into the EEPROM data
The following are the functional descriptions and timing diagrams of all seven instructions.
C S
tC
S S
tC
tS
S K
tD
IS
D I
tS
K H
K L
tC
t D IH
V a lid D a ta
tP
D O
D S
S H
V a lid D a ta
tP
D 0
D 1
1
EECR A.C. Characteristics
Symbol
Parameter
Ta=25°C
VCC=5V±10%
Min.
Max.
VCC=2.2V±10%
Min.
Max.
Unit
fSK
Clock Frequency
0
2
0
1
MHz
tSKH
SK High Time
250
¾
500
¾
ns
tSKL
SK Low Time
250
¾
500
¾
ns
tCSS
CS Setup Time
50
¾
100
¾
ns
tCSH
CS Hold Time
0
¾
0
¾
ns
tCDS
CS Deselect Time
250
¾
250
¾
ns
tDIS
DI Setup Time
100
¾
200
¾
ns
tDIH
DI Hold Time
100
¾
200
¾
ns
tPD1
DO Delay to ²1²
¾
250
¾
500
ns
tPD0
DO Delay to ²0²
¾
250
¾
500
ns
tSV
Status Valid Time
¾
250
¾
250
ns
tHZ
DO Disable Time
100
¾
200
¾
ns
tPR
Write Cycle Time Per Word
¾
2
¾
5
ms
Rev. 1.20
17
March 3, 2006
HT48E30
READ
WRITE
The READ instruction will stream out data at a specified
address on the DO. The data on DO changes during the
low-to-high edge of SK. The 8 bits data stream is preceded by a logical ²0² dummy bit. Irrespective of the
condition of the EWEN or EWDS instruction, the READ
command is always valid and independent of these two
instructions. After the data word has been read the internal address will be automatically incremented by 1 allowing the next consecutive data word to be read out
without entering further address data. The address will
wrap around with CS High until CS returns to Low.
The WRITE instruction writes data into the EEPROM
data memory at the specified addresses in the programming enable mode. After the WRITE op-code and the
specified address and data have been issued, the data
writing is activated by the falling edge of CS. Since the
internal auto-timing generator provides all timing signal
for the internal writing, so the SK clock is not required.
The auto-timing write cycle includes an automatic
erase-before-write capability. So, it is not necessary to
erase data before the WRITE instruction. During the internal writing, we can verify the busy/ready status if CS
is high. The DO will remain low but when the operation is
over, the DO will return to high and further instructions
can be executed.
EWEN/EWDS
The EWEN/EWDS instruction will enable or disable the
programming capabilities. At both the power-on and
power off state the device automatically entered the disable mode. Before a WRITE, ERASE, WRAL or ERAL instruction is given, the programming enable instruction
EWEN must be issued, otherwise the ERASE/WRITE instruction is invalid. After the EWEN instruction is issued,
the programming enable condition remains until power is
turned off or an EWDS instruction is given. No data can be
written into the EEPROM data memory in the programming disabled state. By so doing, the internal memory data
can be protected.
ERAL
The ERAL instruction erases the entire 128´8 memory
cells to a logical ²1² state in the programming enable
mode. After the erase-all instruction set has been issued, the data erase feature is activated by the falling
edge of CS. Since the internal auto-timing generator
provides all timing signal for the erase-all operation, so
the SK clock is not required. During the internal erase-all
operation, we can verify the busy/ready status if CS is
high. The DO will remain low but when the operation is
over, the DO will return to high and further instruction
can be executed.
ERASE
The ERASE instruction erases data at the specified addresses in the programming enable mode. After the
ERASE op-code and the specified address have been
issued, the data erase is activated by the falling edge of
CS. Since the internal auto-timing generator provides all
timing signals for the internal erase, so the SK clock is
not required. During the internal erase, we can verify the
busy/ready status if CS is high. The DO will remain low
but when the operation is over, the DO will return to high
and further instructions can be executed.
WRAL
The WRAL instruction writes data into the entire 128´8
memory cells in the programming enable mode. After
the write-all instruction set has been issued, the data
writing is activated by the falling edge of CS. Since the
internal auto-timing generator provides all timing signals
for the write-all operation, so the SK clock is not required. During the internal write-all operation, we can
verify the busy/ready status if CS is high. The DO will remain low but when the operation is over the DO will return to high and further instruction can be executed.
EECR Control Timing Diagrams
· READ
tC
D S
C S
S K
(1 ) 1
S ta r t b it
D I
1
D O
0
A N
A 0
0
D X
D 0
1
D X
*
* A d d r e s s p o in te r a u to m a tic a lly c y c le s to th e n e x t w o r d
Rev. 1.20
M o d e
18
(X 8 )
A N
A 6
D X
D 7
March 3, 2006
HT48E30
· EWEN/EWDS
C S
S ta n d b y
S K
D I
0
(1 )
S ta r t b it
0
1 1 = E W E N
0 0 = E W D S
· WRITE
tC
C S
D S
V e r ify
S ta n d b y
S K
D I
0
(1 )
S ta r t b it
A N
1
A N -1
A N -2
A 1
A 0
D X
D 0
tS
1
D O
V
B u s y
tP
R e a d y
R
· ERASE
tC
C S
D S
V e r ify
S ta n d b y
S K
D I
1
(1 )
S ta r t b it
D O
A N
1
A N -1
A N -2
A 1
A 0
tS
1
V
B u s y
tP
R e a d y
R
· ERAL
tC
C S
D S
V e r ify
S ta n d b y
S K
D I
D O
0
(1 )
S ta r t b it
0
1
0
tS
1
tP
Rev. 1.20
V
B u s y
19
R e a d y
R
March 3, 2006
HT48E30
· WRAL
tC
C S
D S
V e r ify
S ta n d b y
S K
0
(1 )
S ta r t b it
D I
D O
0
0
1
D X
D 0
tS
1
V
B u s y
tP
R e a d y
R
EEPROM Data Memory Instruction Set Summary
Instruction
Comments
Start bit
Op Code
Address
Data
READ
Read data
1
10
A6~A0
D7~D0
ERASE
Erase data
1
11
A6~A0
¾
WRITE
Write data
1
01
A6~A0
D7~D0
EWEN
Erase/Write Enable
1
00
11XXXXX
¾
EWDS
Erase/Write Disable
1
00
00XXXXX
¾
ERAL
Erase All
1
00
10XXXXX
¾
WRAL
Write All
1
00
01XXXXX
D7~D0
²X² stands for ²don¢t care²
Note:
Options
The following table shows all kinds of options in the microcontroller. All of the options must be defined to ensure proper
system functioning.
No.
Options
1
WDT clock source: WDT oscillator or fSYS/4 or disable
2
CLRWDT instructions: 1 or 2 instructions
3
Timer/event counter clock source: fSYS
4
PA bit wake-up enable or disable
5
PA CMOS or Schmitt input
6
PA, PB, PC, PG pull-high enable or disable (by port)
7
BZ/BZ enable or disable
8
LVR enable or disable
9
System oscillator: RC or crystal
Rev. 1.20
20
March 3, 2006
HT48E30
Application Circuits
V
D D
0 .0 1 m F *
V D D
P A 0 ~ P A 7
R E S
P C 1 ~ P C 5
1 0 0 k W
P B 2 ~ P B 7
0 .1 m F
1 0 k W
V
0 .1 m F *
V S S
R
P B 0 /B Z
P B 1 /B Z
O S C
C ir c u it
O S C
O S C 1
4 7 0 p F
R C S y s te m O s c illa to r
2 4 k W < R O S C < 1 M W
O S C 2
N M O S o p e n d r a in
O S C 1
P C 0 /T M R
O S C 2
D D
C 1
O S C 1
S e e R ig h t S id e
C 2
P G 0 /IN T
R 1
H T 4 8 E 3 0
O S C 2
O S C
C ry s ta l S y s te m
F o r th e v a lu e s ,
s e e ta b le b e lo w
O s c illa to r
C ir c u it
The following table shows the C1, C2 and R1 values corresponding to the different crystal values. (For reference only)
C1, C2
R1
4MHz Crystal
Crystal or Resonator
0pF
10kW
4MHz Resonator
10pF
12kW
3.58MHz Crystal
0pF
10kW
3.58MHz Resonator
25pF
10kW
2MHz Crystal & Resonator
25pF
10kW
1MHz Crystal
35pF
27kW
480kHz Resonator
300pF
9.1kW
455kHz Resonator
300pF
10kW
429kHz Resonator
300pF
10kW
The function of the resistor R1 is to ensure that the oscillator will switch off should low voltage conditions occur.
Such a low voltage, as mentioned here, is one which is less than the lowest value of the MCU operating voltage. Note however that if the LVR is enabled then R1 can be removed.
Note:
The resistance and capacitance for reset circuit should be designed in such a way as to ensure that the VDD is
stable and remains within a valid operating voltage range before bringing RES high.
²*² Make the length of the wiring, which is connected to the RES pin as short as possible, to avoid noise
interference.
Rev. 1.20
21
March 3, 2006
HT48E30
Instruction Set Summary
Description
Instruction
Cycle
Flag
Affected
Add data memory to ACC
Add ACC to data memory
Add immediate data to ACC
Add data memory to ACC with carry
Add ACC to data memory with carry
Subtract immediate data from ACC
Subtract data memory from ACC
Subtract data memory from ACC with result in data memory
Subtract data memory from ACC with carry
Subtract data memory from ACC with carry and result in data memory
Decimal adjust ACC for addition with result in data memory
1
1(1)
1
1
1(1)
1
1
1(1)
1
1(1)
1(1)
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
C
1
1
1
1(1)
1(1)
1(1)
1
1
1
1(1)
1
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Increment data memory with result in ACC
Increment data memory
Decrement data memory with result in ACC
Decrement data memory
1
1(1)
1
1(1)
Z
Z
Z
Z
Rotate data memory right with result in ACC
Rotate data memory right
Rotate data memory right through carry with result in ACC
Rotate data memory right through carry
Rotate data memory left with result in ACC
Rotate data memory left
Rotate data memory left through carry with result in ACC
Rotate data memory left through carry
1
1(1)
1
1(1)
1
1(1)
1
1(1)
None
None
C
C
None
None
C
C
Move data memory to ACC
Move ACC to data memory
Move immediate data to ACC
1
1(1)
1
None
None
None
Clear bit of data memory
Set bit of data memory
1(1)
1(1)
None
None
Mnemonic
Arithmetic
ADD A,[m]
ADDM A,[m]
ADD A,x
ADC A,[m]
ADCM A,[m]
SUB A,x
SUB A,[m]
SUBM A,[m]
SBC A,[m]
SBCM A,[m]
DAA [m]
Logic Operation
AND A,[m]
OR A,[m]
XOR A,[m]
ANDM A,[m]
ORM A,[m]
XORM A,[m]
AND A,x
OR A,x
XOR A,x
CPL [m]
CPLA [m]
AND data memory to ACC
OR data memory to ACC
Exclusive-OR data memory to ACC
AND ACC to data memory
OR ACC to data memory
Exclusive-OR ACC to data memory
AND immediate data to ACC
OR immediate data to ACC
Exclusive-OR immediate data to ACC
Complement data memory
Complement data memory with result in ACC
Increment & Decrement
INCA [m]
INC [m]
DECA [m]
DEC [m]
Rotate
RRA [m]
RR [m]
RRCA [m]
RRC [m]
RLA [m]
RL [m]
RLCA [m]
RLC [m]
Data Move
MOV A,[m]
MOV [m],A
MOV A,x
Bit Operation
CLR [m].i
SET [m].i
Rev. 1.20
22
March 3, 2006
HT48E30
Instruction
Cycle
Flag
Affected
Jump unconditionally
Skip if data memory is zero
Skip if data memory is zero with data movement to ACC
Skip if bit i of data memory is zero
Skip if bit i of data memory is not zero
Skip if increment data memory is zero
Skip if decrement data memory is zero
Skip if increment data memory is zero with result in ACC
Skip if decrement data memory is zero with result in ACC
Subroutine call
Return from subroutine
Return from subroutine and load immediate data to ACC
Return from interrupt
2
1(2)
1(2)
1(2)
1(2)
1(3)
1(3)
1(2)
1(2)
2
2
2
2
None
None
None
None
None
None
None
None
None
None
None
None
None
Read ROM code (current page) to data memory and TBLH
Read ROM code (last page) to data memory and TBLH
2(1)
2(1)
None
None
No operation
Clear data memory
Set data memory
Clear Watchdog Timer
Pre-clear Watchdog Timer
Pre-clear Watchdog Timer
Swap nibbles of data memory
Swap nibbles of data memory with result in ACC
Enter power down mode
1
1(1)
1(1)
1
1
1
1(1)
1
1
None
None
None
TO,PDF
TO(4),PDF(4)
TO(4),PDF(4)
None
None
TO,PDF
Mnemonic
Description
Branch
JMP addr
SZ [m]
SZA [m]
SZ [m].i
SNZ [m].i
SIZ [m]
SDZ [m]
SIZA [m]
SDZA [m]
CALL addr
RET
RET A,x
RETI
Table Read
TABRDC [m]
TABRDL [m]
Miscellaneous
NOP
CLR [m]
SET [m]
CLR WDT
CLR WDT1
CLR WDT2
SWAP [m]
SWAPA [m]
HALT
Note:
x: Immediate data
m: Data memory address
A: Accumulator
i: 0~7 number of bits
addr: Program memory address
Ö: Flag is affected
-: Flag is not affected
(1)
: If a loading to the PCL register occurs, the execution cycle of instructions will be delayed for one more cycle
(four system clocks).
(2)
: If a skipping to the next instruction occurs, the execution cycle of instructions will be delayed for one more
cycle (four system clocks). Otherwise the original instruction cycle is unchanged.
(3) (1)
:
(4)
Rev. 1.20
and (2)
: The flags may be affected by the execution status. If the Watchdog Timer is cleared by executing the
²CLR WDT1² or ²CLR WDT2² instruction, the TO and PDF are cleared.
Otherwise the TO and PDF flags remain unchanged.
23
March 3, 2006
HT48E30
Instruction Definition
ADC A,[m]
Add data memory and carry to the accumulator
Description
The contents of the specified data memory, accumulator and the carry flag are added simultaneously, leaving the result in the accumulator.
Operation
ACC ¬ ACC+[m]+C
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
ADCM A,[m]
Add the accumulator and carry to data memory
Description
The contents of the specified data memory, accumulator and the carry flag are added simultaneously, leaving the result in the specified data memory.
Operation
[m] ¬ ACC+[m]+C
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
ADD A,[m]
Add data memory to the accumulator
Description
The contents of the specified data memory and the accumulator are added. The result is
stored in the accumulator.
Operation
ACC ¬ ACC+[m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
ADD A,x
Add immediate data to the accumulator
Description
The contents of the accumulator and the specified data are added, leaving the result in the
accumulator.
Operation
ACC ¬ ACC+x
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
ADDM A,[m]
Add the accumulator to the data memory
Description
The contents of the specified data memory and the accumulator are added. The result is
stored in the data memory.
Operation
[m] ¬ ACC+[m]
Affected flag(s)
Rev. 1.20
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
24
March 3, 2006
HT48E30
AND A,[m]
Logical AND accumulator with data memory
Description
Data in the accumulator and the specified data memory perform a bitwise logical_AND operation. The result is stored in the accumulator.
Operation
ACC ¬ ACC ²AND² [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
AND A,x
Logical AND immediate data to the accumulator
Description
Data in the accumulator and the specified data perform a bitwise logical_AND operation.
The result is stored in the accumulator.
Operation
ACC ¬ ACC ²AND² x
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
ANDM A,[m]
Logical AND data memory with the accumulator
Description
Data in the specified data memory and the accumulator perform a bitwise logical_AND operation. The result is stored in the data memory.
Operation
[m] ¬ ACC ²AND² [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
CALL addr
Subroutine call
Description
The instruction unconditionally calls a subroutine located at the indicated address. The
program counter increments once to obtain the address of the next instruction, and pushes
this onto the stack. The indicated address is then loaded. Program execution continues
with the instruction at this address.
Operation
Stack ¬ Program Counter+1
Program Counter ¬ addr
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
CLR [m]
Clear data memory
Description
The contents of the specified data memory are cleared to 0.
Operation
[m] ¬ 00H
Affected flag(s)
Rev. 1.20
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
25
March 3, 2006
HT48E30
CLR [m].i
Clear bit of data memory
Description
The bit i of the specified data memory is cleared to 0.
Operation
[m].i ¬ 0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
CLR WDT
Clear Watchdog Timer
Description
The WDT is cleared (clears the WDT). The power down bit (PDF) and time-out bit (TO) are
cleared.
Operation
WDT ¬ 00H
PDF and TO ¬ 0
Affected flag(s)
TO
PDF
OV
Z
AC
C
0
0
¾
¾
¾
¾
CLR WDT1
Preclear Watchdog Timer
Description
Together with CLR WDT2, clears the WDT. PDF and TO are also cleared. Only execution
of this instruction without the other preclear instruction just sets the indicated flag which implies this instruction has been executed and the TO and PDF flags remain unchanged.
Operation
WDT ¬ 00H*
PDF and TO ¬ 0*
Affected flag(s)
TO
PDF
OV
Z
AC
C
0*
0*
¾
¾
¾
¾
CLR WDT2
Preclear Watchdog Timer
Description
Together with CLR WDT1, clears the WDT. PDF and TO are also cleared. Only execution
of this instruction without the other preclear instruction, sets the indicated flag which implies this instruction has been executed and the TO and PDF flags remain unchanged.
Operation
WDT ¬ 00H*
PDF and TO ¬ 0*
Affected flag(s)
TO
PDF
OV
Z
AC
C
0*
0*
¾
¾
¾
¾
CPL [m]
Complement data memory
Description
Each bit of the specified data memory is logically complemented (1¢s complement). Bits
which previously contained a 1 are changed to 0 and vice-versa.
Operation
[m] ¬ [m]
Affected flag(s)
Rev. 1.20
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
26
March 3, 2006
HT48E30
CPLA [m]
Complement data memory and place result in the accumulator
Description
Each bit of the specified data memory is logically complemented (1¢s complement). Bits
which previously contained a 1 are changed to 0 and vice-versa. The complemented result
is stored in the accumulator and the contents of the data memory remain unchanged.
Operation
ACC ¬ [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
DAA [m]
Decimal-Adjust accumulator for addition
Description
The accumulator value is adjusted to the BCD (Binary Coded Decimal) code. The accumulator is divided into two nibbles. Each nibble is adjusted to the BCD code and an internal
carry (AC1) will be done if the low nibble of the accumulator is greater than 9. The BCD adjustment is done by adding 6 to the original value if the original value is greater than 9 or a
carry (AC or C) is set; otherwise the original value remains unchanged. The result is stored
in the data memory and only the carry flag (C) may be affected.
Operation
If ACC.3~ACC.0 >9 or AC=1
then [m].3~[m].0 ¬ (ACC.3~ACC.0)+6, AC1=AC
else [m].3~[m].0 ¬ (ACC.3~ACC.0), AC1=0
and
If ACC.7~ACC.4+AC1 >9 or C=1
then [m].7~[m].4 ¬ ACC.7~ACC.4+6+AC1,C=1
else [m].7~[m].4 ¬ ACC.7~ACC.4+AC1,C=C
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
DEC [m]
Decrement data memory
Description
Data in the specified data memory is decremented by 1.
Operation
[m] ¬ [m]-1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
DECA [m]
Decrement data memory and place result in the accumulator
Description
Data in the specified data memory is decremented by 1, leaving the result in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC ¬ [m]-1
Affected flag(s)
Rev. 1.20
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
27
March 3, 2006
HT48E30
HALT
Enter power down mode
Description
This instruction stops program execution and turns off the system clock. The contents of
the RAM and registers are retained. The WDT and prescaler are cleared. The power down
bit (PDF) is set and the WDT time-out bit (TO) is cleared.
Operation
Program Counter ¬ Program Counter+1
PDF ¬ 1
TO ¬ 0
Affected flag(s)
TO
PDF
OV
Z
AC
C
0
1
¾
¾
¾
¾
INC [m]
Increment data memory
Description
Data in the specified data memory is incremented by 1
Operation
[m] ¬ [m]+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
INCA [m]
Increment data memory and place result in the accumulator
Description
Data in the specified data memory is incremented by 1, leaving the result in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC ¬ [m]+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
JMP addr
Directly jump
Description
The program counter are replaced with the directly-specified address unconditionally, and
control is passed to this destination.
Operation
Program Counter ¬addr
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
MOV A,[m]
Move data memory to the accumulator
Description
The contents of the specified data memory are copied to the accumulator.
Operation
ACC ¬ [m]
Affected flag(s)
Rev. 1.20
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
28
March 3, 2006
HT48E30
MOV A,x
Move immediate data to the accumulator
Description
The 8-bit data specified by the code is loaded into the accumulator.
Operation
ACC ¬ x
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
MOV [m],A
Move the accumulator to data memory
Description
The contents of the accumulator are copied to the specified data memory (one of the data
memories).
Operation
[m] ¬ACC
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
NOP
No operation
Description
No operation is performed. Execution continues with the next instruction.
Operation
Program Counter ¬ Program Counter+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
OR A,[m]
Logical OR accumulator with data memory
Description
Data in the accumulator and the specified data memory (one of the data memories) perform a bitwise logical_OR operation. The result is stored in the accumulator.
Operation
ACC ¬ ACC ²OR² [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
OR A,x
Logical OR immediate data to the accumulator
Description
Data in the accumulator and the specified data perform a bitwise logical_OR operation.
The result is stored in the accumulator.
Operation
ACC ¬ ACC ²OR² x
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
ORM A,[m]
Logical OR data memory with the accumulator
Description
Data in the data memory (one of the data memories) and the accumulator perform a
bitwise logical_OR operation. The result is stored in the data memory.
Operation
[m] ¬ACC ²OR² [m]
Affected flag(s)
Rev. 1.20
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
29
March 3, 2006
HT48E30
RET
Return from subroutine
Description
The program counter is restored from the stack. This is a 2-cycle instruction.
Operation
Program Counter ¬ Stack
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RET A,x
Return and place immediate data in the accumulator
Description
The program counter is restored from the stack and the accumulator loaded with the specified 8-bit immediate data.
Operation
Program Counter ¬ Stack
ACC ¬ x
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RETI
Return from interrupt
Description
The program counter is restored from the stack, and interrupts are enabled by setting the
EMI bit. EMI is the enable master (global) interrupt bit.
Operation
Program Counter ¬ Stack
EMI ¬ 1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RL [m]
Rotate data memory left
Description
The contents of the specified data memory are rotated 1 bit left with bit 7 rotated into bit 0.
Operation
[m].(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
[m].0 ¬ [m].7
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RLA [m]
Rotate data memory left and place result in the accumulator
Description
Data in the specified data memory is rotated 1 bit left with bit 7 rotated into bit 0, leaving the
rotated result in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC.(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
ACC.0 ¬ [m].7
Affected flag(s)
Rev. 1.20
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
30
March 3, 2006
HT48E30
RLC [m]
Rotate data memory left through carry
Description
The contents of the specified data memory and the carry flag are rotated 1 bit left. Bit 7 replaces the carry bit; the original carry flag is rotated into the bit 0 position.
Operation
[m].(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
[m].0 ¬ C
C ¬ [m].7
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
RLCA [m]
Rotate left through carry and place result in the accumulator
Description
Data in the specified data memory and the carry flag are rotated 1 bit left. Bit 7 replaces the
carry bit and the original carry flag is rotated into bit 0 position. The rotated result is stored
in the accumulator but the contents of the data memory remain unchanged.
Operation
ACC.(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
ACC.0 ¬ C
C ¬ [m].7
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
RR [m]
Rotate data memory right
Description
The contents of the specified data memory are rotated 1 bit right with bit 0 rotated to bit 7.
Operation
[m].i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
[m].7 ¬ [m].0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RRA [m]
Rotate right and place result in the accumulator
Description
Data in the specified data memory is rotated 1 bit right with bit 0 rotated into bit 7, leaving
the rotated result in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC.(i) ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
ACC.7 ¬ [m].0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RRC [m]
Rotate data memory right through carry
Description
The contents of the specified data memory and the carry flag are together rotated 1 bit
right. Bit 0 replaces the carry bit; the original carry flag is rotated into the bit 7 position.
Operation
[m].i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
[m].7 ¬ C
C ¬ [m].0
Affected flag(s)
Rev. 1.20
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
31
March 3, 2006
HT48E30
RRCA [m]
Rotate right through carry and place result in the accumulator
Description
Data of the specified data memory and the carry flag are rotated 1 bit right. Bit 0 replaces
the carry bit and the original carry flag is rotated into the bit 7 position. The rotated result is
stored in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC.i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
ACC.7 ¬ C
C ¬ [m].0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
SBC A,[m]
Subtract data memory and carry from the accumulator
Description
The contents of the specified data memory and the complement of the carry flag are subtracted from the accumulator, leaving the result in the accumulator.
Operation
ACC ¬ ACC+[m]+C
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
SBCM A,[m]
Subtract data memory and carry from the accumulator
Description
The contents of the specified data memory and the complement of the carry flag are subtracted from the accumulator, leaving the result in the data memory.
Operation
[m] ¬ ACC+[m]+C
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
SDZ [m]
Skip if decrement data memory is 0
Description
The contents of the specified data memory are decremented by 1. If the result is 0, the next
instruction is skipped. If the result is 0, the following instruction, fetched during the current
instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if ([m]-1)=0, [m] ¬ ([m]-1)
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SDZA [m]
Decrement data memory and place result in ACC, skip if 0
Description
The contents of the specified data memory are decremented by 1. If the result is 0, the next
instruction is skipped. The result is stored in the accumulator but the data memory remains
unchanged. If the result is 0, the following instruction, fetched during the current instruction
execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if ([m]-1)=0, ACC ¬ ([m]-1)
Affected flag(s)
Rev. 1.20
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
32
March 3, 2006
HT48E30
SET [m]
Set data memory
Description
Each bit of the specified data memory is set to 1.
Operation
[m] ¬ FFH
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SET [m]. i
Set bit of data memory
Description
Bit i of the specified data memory is set to 1.
Operation
[m].i ¬ 1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SIZ [m]
Skip if increment data memory is 0
Description
The contents of the specified data memory are incremented by 1. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a
dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with
the next instruction (1 cycle).
Operation
Skip if ([m]+1)=0, [m] ¬ ([m]+1)
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SIZA [m]
Increment data memory and place result in ACC, skip if 0
Description
The contents of the specified data memory are incremented by 1. If the result is 0, the next
instruction is skipped and the result is stored in the accumulator. The data memory remains unchanged. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper
instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if ([m]+1)=0, ACC ¬ ([m]+1)
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SNZ [m].i
Skip if bit i of the data memory is not 0
Description
If bit i of the specified data memory is not 0, the next instruction is skipped. If bit i of the data
memory is not 0, the following instruction, fetched during the current instruction execution,
is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if [m].i¹0
Affected flag(s)
Rev. 1.20
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
33
March 3, 2006
HT48E30
SUB A,[m]
Subtract data memory from the accumulator
Description
The specified data memory is subtracted from the contents of the accumulator, leaving the
result in the accumulator.
Operation
ACC ¬ ACC+[m]+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
SUBM A,[m]
Subtract data memory from the accumulator
Description
The specified data memory is subtracted from the contents of the accumulator, leaving the
result in the data memory.
Operation
[m] ¬ ACC+[m]+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
SUB A,x
Subtract immediate data from the accumulator
Description
The immediate data specified by the code is subtracted from the contents of the accumulator, leaving the result in the accumulator.
Operation
ACC ¬ ACC+x+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
SWAP [m]
Swap nibbles within the data memory
Description
The low-order and high-order nibbles of the specified data memory (1 of the data memories) are interchanged.
Operation
[m].3~[m].0 « [m].7~[m].4
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SWAPA [m]
Swap data memory and place result in the accumulator
Description
The low-order and high-order nibbles of the specified data memory are interchanged, writing the result to the accumulator. The contents of the data memory remain unchanged.
Operation
ACC.3~ACC.0 ¬ [m].7~[m].4
ACC.7~ACC.4 ¬ [m].3~[m].0
Affected flag(s)
Rev. 1.20
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
34
March 3, 2006
HT48E30
SZ [m]
Skip if data memory is 0
Description
If the contents of the specified data memory are 0, the following instruction, fetched during
the current instruction execution, is discarded and a dummy cycle is replaced to get the
proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if [m]=0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SZA [m]
Move data memory to ACC, skip if 0
Description
The contents of the specified data memory are copied to the accumulator. If the contents is
0, the following instruction, fetched during the current instruction execution, is discarded
and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed
with the next instruction (1 cycle).
Operation
Skip if [m]=0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SZ [m].i
Skip if bit i of the data memory is 0
Description
If bit i of the specified data memory is 0, the following instruction, fetched during the current
instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if [m].i=0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
TABRDC [m]
Move the ROM code (current page) to TBLH and data memory
Description
The low byte of ROM code (current page) addressed by the table pointer (TBLP) is moved
to the specified data memory and the high byte transferred to TBLH directly.
Operation
[m] ¬ ROM code (low byte)
TBLH ¬ ROM code (high byte)
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
TABRDL [m]
Move the ROM code (last page) to TBLH and data memory
Description
The low byte of ROM code (last page) addressed by the table pointer (TBLP) is moved to
the data memory and the high byte transferred to TBLH directly.
Operation
[m] ¬ ROM code (low byte)
TBLH ¬ ROM code (high byte)
Affected flag(s)
Rev. 1.20
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
35
March 3, 2006
HT48E30
XOR A,[m]
Logical XOR accumulator with data memory
Description
Data in the accumulator and the indicated data memory perform a bitwise logical Exclusive_OR operation and the result is stored in the accumulator.
Operation
ACC ¬ ACC ²XOR² [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
XORM A,[m]
Logical XOR data memory with the accumulator
Description
Data in the indicated data memory and the accumulator perform a bitwise logical Exclusive_OR operation. The result is stored in the data memory. The 0 flag is affected.
Operation
[m] ¬ ACC ²XOR² [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
XOR A,x
Logical XOR immediate data to the accumulator
Description
Data in the accumulator and the specified data perform a bitwise logical Exclusive_OR operation. The result is stored in the accumulator. The 0 flag is affected.
Operation
ACC ¬ ACC ²XOR² x
Affected flag(s)
Rev. 1.20
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
36
March 3, 2006
HT48E30
Package Information
24-pin SKDIP (300mil) Outline Dimensions
A
B
2 4
1 3
1
1 2
H
C
D
E
Symbol
Rev. 1.20
F
a
G
I
Dimensions in mil
Min.
Nom.
Max.
A
1235
¾
1265
B
255
¾
265
C
125
¾
135
D
125
¾
145
E
16
¾
20
F
50
¾
70
G
¾
100
¾
H
295
¾
315
I
345
¾
360
a
0°
¾
15°
37
March 3, 2006
HT48E30
28-pin SKDIP (300mil) Outline Dimensions
A
B
2 8
1 5
1
1 4
H
C
D
E
Symbol
Rev. 1.20
F
a
G
I
Dimensions in mil
Min.
Nom.
Max.
A
1375
¾
1395
B
278
¾
298
C
125
¾
135
D
125
¾
145
E
16
¾
20
F
50
¾
70
G
¾
100
¾
H
295
¾
315
I
330
¾
375
a
0°
¾
15°
38
March 3, 2006
HT48E30
24-pin SOP (300mil) Outline Dimensions
1 3
2 4
A
B
1 2
1
C
C '
G
H
D
E
Symbol
Rev. 1.20
a
F
Dimensions in mil
Min.
Nom.
Max.
A
394
¾
419
B
290
¾
300
C
14
¾
20
C¢
590
¾
614
D
92
¾
104
E
¾
50
¾
F
4
¾
¾
G
32
¾
38
H
4
¾
12
a
0°
¾
10°
39
March 3, 2006
HT48E30
28-pin SOP (300mil) Outline Dimensions
2 8
1 5
A
B
1
1 4
C
C '
G
H
D
E
Symbol
Rev. 1.20
a
F
Dimensions in mil
Min.
Nom.
Max.
A
394
¾
419
B
290
¾
300
C
14
¾
20
C¢
697
¾
713
D
92
¾
104
E
¾
50
¾
F
4
¾
¾
G
32
¾
38
H
4
¾
12
a
0°
¾
10°
40
March 3, 2006
HT48E30
Product Tape and Reel Specifications
Reel Dimensions
D
T 2
A
C
B
T 1
SOP 24W
Symbol
Description
A
Reel Outer Diameter
B
Reel Inner Diameter
Dimensions in mm
330±1.0
62±1.5
13.0+0.5
-0.2
C
Spindle Hole Diameter
D
Key Slit Width
2.0±0.5
T1
Space Between Flange
24.8+0.3
-0.2
T2
Reel Thickness
30.2±0.2
SOP 28W (300mil)
Symbol
Description
Dimensions in mm
A
Reel Outer Diameter
330±1.0
B
Reel Inner Diameter
62±1.5
C
Spindle Hole Diameter
13.0+0.5
-0.2
D
Key Slit Width
2.0±0.5
T1
Space Between Flange
24.8+0.3
-0.2
T2
Reel Thickness
30.2±0.2
Rev. 1.20
41
March 3, 2006
HT48E30
Carrier Tape Dimensions
P 0
D
P 1
t
E
F
W
C
D 1
B 0
P
K 0
A 0
SOP 24W
Symbol
W
Description
Dimensions in mm
Carrier Tape Width
24.0±0.3
P
Cavity Pitch
12.0±0.1
E
Perforation Position
1.75±0.1
F
Cavity to Perforation (Width Direction)
11.5±0.1
D
Perforation Diameter
1.55+0.1
D1
Cavity Hole Diameter
1.5+0.25
P0
Perforation Pitch
4.0±0.1
P1
Cavity to Perforation (Length Direction)
2.0±0.1
A0
Cavity Length
10.9±0.1
B0
Cavity Width
15.9±0.1
K0
Cavity Depth
3.1±0.1
t
Carrier Tape Thickness
C
Cover Tape Width
0.35±0.05
21.3
SOP 28W (300mil)
Symbol
Description
Dimensions in mm
W
Carrier Tape Width
24.0±0.3
P
Cavity Pitch
12.0±0.1
E
Perforation Position
1.75±0.1
F
Cavity to Perforation (Width Direction)
11.5±0.1
D
Perforation Diameter
1.5+0.1
D1
Cavity Hole Diameter
1.5+0.25
P0
Perforation Pitch
4.0±0.1
P1
Cavity to Perforation (Length Direction)
A0
Cavity Length
10.85±0.1
B0
Cavity Width
18.34±0.1
K0
Cavity Depth
2.97±0.1
t
Carrier Tape Thickness
0.35±0.01
C
Cover Tape Width
Rev. 1.20
2.0±0.1
21.3
42
March 3, 2006
HT48E30
Holtek Semiconductor Inc. (Headquarters)
No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan
Tel: 886-3-563-1999
Fax: 886-3-563-1189
http://www.holtek.com.tw
Holtek Semiconductor Inc. (Taipei Sales Office)
4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan
Tel: 886-2-2655-7070
Fax: 886-2-2655-7373
Fax: 886-2-2655-7383 (International sales hotline)
Holtek Semiconductor Inc. (Shanghai Sales Office)
7th Floor, Building 2, No.889, Yi Shan Rd., Shanghai, China 200233
Tel: 021-6485-5560
Fax: 021-6485-0313
http://www.holtek.com.cn
Holtek Semiconductor Inc. (Shenzhen Sales Office)
43F, SEG Plaza, Shen Nan Zhong Road, Shenzhen, China 518031
Tel:0755-83465589
Fax:0755-83465590
ISDN : 0755-8346559
Holtek Semiconductor Inc. (Beijing Sales Office)
Suite 1721, Jinyu Tower, A129 West Xuan Wu Men Street, Xicheng District, Beijing, China 100031
Tel:010-66410030, 66417751, 66417752
Fax:010-66410125
Holmate Semiconductor, Inc. (North America Sales Office)
46712 Fremont Blvd., Fremont, CA 94538
Tel: 510-252-9880
Fax: 510-252-9885
http://www.holmate.com
Copyright Ó 2006 by HOLTEK SEMICONDUCTOR INC.
The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used
solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable
without further modification, nor recommends the use of its products for application that may present a risk to human life
due to malfunction or otherwise. Holtek¢s products are not authorized for use as critical components in life support devices
or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information,
please visit our web site at http://www.holtek.com.tw.
Rev. 1.20
43
March 3, 2006