HOLTEK HTG2150

HTG2150
Preliminary
8-Bit 320 Pixel LCD Microcontroller
Features
·
·
·
·
·
·
·
·
·
Operating voltage: 2.2V~3.6V
16K ´ 16 bits program ROM
192 ´ 8 bits data RAM
8~12 bidirectional I/O lines
8 common ´ 33~40 segment LCD driver
One 16-bit programmable timer
with overflow interrupts
One 8-bit programmable timer with 8 stage
prescaler for PFD
One 8-bit programmable timer with 8 stage
prescaler for Time base
One 8-bit PWM audio output to directly
drive speaker and buzzer
·
·
·
·
·
·
·
Watchdog Timer
On-chip RC oscillator for system clock and
32768Hz crystal oscillator for timebase and
LCD driver
HALT function and wake-up feature reduce
power consumption
8-level subroutine nesting
Bit manipulation instructions
63 powerful instructions
One interrupt input
General Description
The HTG2150 is an 8-bit high performance
RISC-like microcontroller. The single cycle instruction and two-stage pipeline architecture
make it suitable for high speed application. The
device is ideally suited for multiple LCD low
power application among which are calculators, clock timer, game, scales, toys and hand
held LCD products, as well as for battery systems.
1
July 24, 2000
Preliminary
HTG2150
Block Diagram
S Y S C L K /4
T M R 0
S T A C K 0
S T A C K 1
IN T /S E G 3 7
T M R 0 C
S T A C K 2
S T A C K 3
P ro g ra m
C o u n te r
S T A C K 4
S T A C K 5
In te rru p t
C ir c u it
S T A C K 6
P ro g ra m
R O M
1 6 b it
8 -s ta g e
P r e s c a le r
T M R 2
IN T C
S T A C K 7
S Y S C L K
P W M D A C 1
T M R 2 C
M
P F D
M
P W M D A C 2
In s tr u c tio n
R e g is te r
M P 0
M P 1
M
U
X
W D T S
X
P W M 2
W D T R C
O S C
¸ 2 5 6
S T A T U S
A L U
T im in g
G e n e ra to r
S h ifte r
P A C
P O R T A
P A
S
U
M U X
In s tr u c tio n
D e c o d e r
S
P W M 1
X
D A T A
M e m o ry
W D T P r e s c a le r
O S
R E
V D
V S
U
P B C
A C C
C I
P O R T B
P B
D
L C D
M e m o ry
S Y S C L K
P A 0 ~ P A 7
P B 4 ~ P B 7 /S E G 3 3 ~ S E G 3 6
8 -s ta g e
P r e s c a le r
3 2 7 6 8 H z C ry s ta l
L C D
D r iv e r
T M R 3
C O M 0 ~ C O M 7
S E G 0
P B 4 ~
IN T /S
X O U T
X IN /S
~ S
P B
E G
/S
E G
8 -s ta g e
P r e s c a le r
M
U
X
T M R 3 C
E G 3 2
7 /S E G 3 3 ~ S E G 3 6
3 7
E G 3 8
3 9
S Y S C L K
P W M
D /A
P W M D A C 1
P W M D A C 2
2
July 24, 2000
Preliminary
HTG2150
Pad Assignment
S E G 1 7
S E G 1 6
S E G 1 5
5 7
5 6
5 5
5 4
5 3
S E G 9
S E G 1 8
5 8
S E G 1 0
S E G 1 9
5 9
S E G 1 1
S E G 2 0
6 0
S E G 1 2
S E G 2 1
6 1
S E G 1 4
S E G 2 2
6 2
S E G 1 3
S E G 2 3
1
S E G 2 4
S E G 2 5
5 2
5 1
5 0
4 9
4 8
4 7
S E G 2 6
2
4 6
S E G 8
S E G 2 7
3
4 5
S E G 7
S E G 2 8
4
4 4
S E G 6
S E G 2 9
5
4 3
S E G 5
S E G 3 0
6
4 2
S E G 4
S E G 3 1
7
4 1
S E G 3
S E G 3 2
8
4 0
S E G 2
P B 4 /S E G 3 3
9
P B 5 /S E G 3 4
1 0
P B 6 /S E G 3 5
1 1
P B 7 /S E G 3 6
1 2
IN T /S E G 3 7
1 3
X O U T /S E G 3 8
1 4
X IN /S E G 3 9
1 5
3 6
C O M 6
3 5
C O M 5
3 4
C O M 4
3 3
C O M 3
3 2
C O M 2
3 1
C O M 1
3 0
C O M 0
2 4
2 5
2 6
2 7
2 8
2 9
P A 6
P A 7
V S S
2 3
P A 5
O S C I
2 2
P A 4
V D D
2 1
C O M 7
P A 3
2 0
S E G 0
3 7
P A 2
1 9
S E G 1
P A 1
1 8
3 9
3 8
P A 0
1 7
P W M 2
1 6
P W M 1
R E S
(0 ,0 )
* The IC substrate should be connected to VSS in the PCB layout artwork.
3
July 24, 2000
Preliminary
Pad Coordinates
Pad No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
X
-880.45
-887.11
-887.11
-887.11
-887.11
-887.11
-887.11
-887.11
-822.70
-822.70
-822.70
-822.70
-824.04
-824.04
-823.97
-871.13
-720.90
-539.25
-404.50
-273.79
-99.06
58.61
175.41
289.41
406.21
520.21
637.01
751.01
867.81
882.36
882.36
HTG2150
Unit: mm
Y
1114.46
872.13
765.63
659.03
552.53
445.93
339.43
232.83
103.48
-13.52
-127.52
-244.52
-354.49
-462.62
-580.52
-1052.80
-1052.80
-1052.80
-1051.65
-1032.67
-1097.34
-1057.70
-1057.70
-1057.70
-1057.70
-1057.70
-1057.70
-1057.70
-1057.70
-852.57
-745.97
Pad No.
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
X
882.36
882.36
882.36
882.36
882.36
882.36
882.36
882.36
882.36
882.36
882.36
882.36
882.36
882.36
882.36
824.35
717.85
611.25
504.75
398.15
291.65
185.05
78.55
-28.05
-134.55
-241.15
-347.65
-454.25
-560.75
-667.35
-773.85
Y
-639.47
-532.87
-426.37
-319.77
-213.27
-106.67
-0.17
106.43
212.93
319.53
426.03
532.63
639.13
745.73
852.23
1114.46
1114.46
1114.46
1114.46
1114.46
1114.46
1114.46
1114.46
1114.46
1114.46
1114.46
1114.46
1114.46
1114.46
1114.46
1114.46
Pad Description
Pad No.
38~62
1~8
9~12
Pad Name
I/O
Mask
Option
SEG0~SEG24
SEG25~SEG32
O
¾
PB4~PB7/
SEG33~SEG36
I/O
or
O
Description
LCD segment signal output.
Selectable as bidirectional input/output or LCD
segment signal output by mask option. On
Input/Output
bidirectional input/output port. Software instrucor Segment
tions determine the CMOS output or schmitt trigOutput
ger input with pull-high resistor. PB4~PB7 share
pad with SEG33~SEG36.
4
July 24, 2000
Preliminary
Pad No.
13
Pad Name
INT/SEG37
HTG2150
I/O
Mask
Option
Description
I
or
O
Interrupt
input or
Segment 37
output
Selectable as external interrupt schmitt trigger
input or LCD segment 37 signal output by mask
option. External interrupt schmitt trigger input
with pull-high resistor. Edge triggered activated
on a high to low transition. INT shares pad with
SEG37.
I or O
O
Crystal or
Segment
Output
Selectable as 32768Hz crystal oscillator or LCD
segment signal output by mask option. Crystal
oscillator (32.768kHz) for Timer 3 and LCD
clock. XIN shares pad with SEG39; XOUT
shares pad with SEG38.
Schmitt trigger reset input. Active low without
pull-high resistor.
15
14
XIN/SEG39
XOUT/SEG38
16
RES
I
¾
17
PWM1
O
CMOS
Positive PWM CMOS output
18
PWM2
O
CMOS
Negative PWM CMOS output
19
VDD
¾
¾
Positive power supply
20
OSCI
I
¾
OSCI is connected to the RC network of the internal system clock.
21
VSS
¾
¾
Negative power supply, ground
I/O
Wake-up
or None
Wake-up
O
¾
22~29
PA0~PA7
37~31
COM7~COM0
Bidirectional 8-bit input/output port. Each bit
can be configured as a wake-up input by mask
option. Software instructions determine the
CMOS output or schmitt trigger input with
pull-high resistor.
LCD common signal output
Absolute Maximum Ratings
Supply Voltage..............................-0.3V to 3.6V
Storage Temperature.................-50°C to 125°C
Input Voltage .................VSS-0.3V to VDD+0.3V
Operating Temperature ..................0°C to 70°C
Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may cause substantial damage to the device. Functional operation of this device
at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
5
July 24, 2000
Preliminary
HTG2150
D.C. Characteristics
Symbol
Ta=25°C
Test Conditions
Parameter
VDD Conditions
VDD
Operating Voltage
¾
IDD
Operating Current (RC OSC)
3V
ISTB1
Standby Current With 7mA LCD Bias
Option (RTC ON, LCD ON)
ISTB2
Min. Typ. Max. Unit
2.2
¾
3.6
V
No load,
fSYS=4MHz
¾
1
2
mA
3V
No load,
HALT mode
¾
¾
20
mA
Standby Current LCD Bias Off Option
(RTC ON, LCD OFF)
3V
No load,
HALT mode
¾
¾
5
mA
VIL1
Input Low Voltage for PA/PB
3V
¾
0
¾
0.9
V
VIH1
Input High Voltage for PA/PB
3V
¾
2.1
¾
3
V
VIL2
Input Low Voltage (INT)
3V
¾
0
¾
0.7
V
¾
2.3
¾
3
V
¾
VIH2
Input High Voltage (INT)
3V
VIL3
Input Low Voltage (RES)
3V
¾
¾
1.5
¾
V
VIH3
Input High Voltage (RES)
3V
¾
¾
2.4
¾
V
IOH1
Port A, Port B Source Current
3V
VOH=2.7V
-1
-2
¾
mA
IOH2
Segment, Common Output Source
Current
3V
VOH=2.7V
-50
-90
¾
mA
IOH3
PWM1/PWM2 Source Current
3V
VOH=2.7V
-8
-10
¾
mA
IOL1
Port A, Port B Sink Current
3V
VOL=0.3V
1.5
4
¾
mA
IOL2
Segment, Common Output
Sink Current
3V
VOL=0.3V
80
130
¾
mA
IOL3
PWM1/PWM2 Sink Current
3V
VOH=0.3V
12
16
¾
mA
RPH
Pull-high Resistance of PA/PB and INT
3V
40
60
80
kW
¾
A.C. Characteristics
Symbol
Parameter
Ta=25°C
Test Conditions
Min. Typ. Max. Unit
VDD
Conditions
3V
¾
400
¾
4000
2.4V
¾
400
¾
2000 kHz
fSYS
System Clock (RC OSC)
2.2V
¾
400
¾
1000
tRES
External Reset Low Pulse Width
¾
¾
1
¾
¾
ms
tSST
System Start-up Timer Period
¾
Power-up or
Wake-up from HALT
¾
1024
¾
tSYS
tINT
Interrupt Pulse Width
¾
¾
1
¾
¾
ms
Note: tSYS=1/fSYS
6
July 24, 2000
Preliminary
HTG2150
Functional Description
The conditional skip is activated by instruction.
Once the condition is met, the next instruction,
fetched during the current instruction execution, is discarded and a dummy cycle replaces it
to get the proper instruction. Otherwise proceed with the next instruction.
The lower byte of the program counter (PCL) is
a readable and writeable register (06H).
Moving data into the PCL performs a short
jump. The destination will be within 256 locations.
When a control transfer takes place, an additional dummy cycle is required.
Execution flow
The system clock for the HTG2150 is derived
from an RC oscillator. The system clock is internally divided into four non-overlapping clocks.
One instruction cycle consists of four system
clock cycles.
Instruction fetching and execution are pipelined in
such a way that a fetch takes one instruction cycle
while decoding and execution takes the next instruction cycle. However, the pipelining scheme
causes each instruction to effectively execute in one
cycle. If an instruction changes the program counter, two cycles are required to complete the instruction.
Program memory - ROM
The program memory, which contains executable program instructions, data and table information, is composed of a 16384 x 16 bit format.
However as the PC (program counter) is comprised of only 13 bits, the remaining 1 ROM address bit is managed by dividing the program
memory into 2 banks, each bank having a range
between 0000H and 1FFFH. To move from the
present ROM bank to a different ROM bank,
the higher 1 bit of the ROM address are set by
the BP (Bank Pointer), while the remaining 13
bits of the PC are set in the usual way by executing the appropriate jump or call instruction.
As the full 14 address bits are latched during
the execution of a call or jump instruction, the
correct value of the BP must first be setup before a jump or call is executed. When either a
software or hardware interrupt is received,
note that no matter which ROM bank the pro-
Program counter - PC
The 13-bit program counter (PC) controls the
sequence in which the instructions stored in the
program ROM are executed and its contents
specify a maximum of 8192 addresses.
After accessing a program memory word to
fetch an instruction code, the contents of the
program counter are incremented by one. The
program counter then points to the memory
word containing the next instruction code.
When executing a jump instruction, conditional
skip execution, loading PCL register, subroutine call, initial reset, internal interrupt, external interrupt or return from subroutine, the PC
manipulates the program transfer by loading
the address corresponding to each instruction.
S y s te m
C lo c k
P C
T 1
T 2
T 3
P C
T 4
T 1
T 2
T 3
T 4
T 1
T 2
P C + 1
T 3
T 4
1 3 b its
P ro g ra m
C o u n te r
P C + 2
S ta c k
F e tc h IN S T (P C )
E x e c u te IN S T (P C -1 )
F e tc h IN S T (P C + 1 )
E x e c u te IN S T (P C )
F e tc h IN S T (P C + 2 )
E x e c u te IN S T (P C + 1 )
B a n k P o in te r
R e g is te r B it5
B a n k 0
B a n k 1
0 0 0 0 H
8 1 9 2 ´ 1 6
B its
1 F F F H
2 0 0 0 H
3 F F F H
R O M A d d re s s
A 1 3 b it L a tc h
L a tc h d a ta o n E x e c u tio n o f J u m p o r C a ll In s tr u c tio n
1 6 K P r o g r a m R O M A d d r e s s in g A r c h ite c tu r e
Execution flow
7
July 24, 2000
Preliminary
HTG2150
· Location 008H
gram is in the program will always jump to the
appropriate interrupt service address in Bank
0. The original full 14 bit address will be stored
on the stack and restored when the relevant
RET/RETI instruction is executed, automatically returning the program to the original
ROM bank. This eliminates the need for programmers to manage the BP when interrupts
occur.
Certain locations in Bank 0 of program memory
are reserved for special usage:
This area is reserved for the timer counter 0 interrupt service program. If a timer interrupt results from a timer counter 0 overflow, and if the
interrupt is enabled and the stack is not full,
the program begins execution at location 008H.
0 0 0 0 H
D e v ic e in itia liz a tio n p r o g r a m
0 0 0 4 H
E x te r n a l in te r r u p t s u b r o u tin e
0 0 0 8 H
T im e r c o u n te r 0 in te r r u p t s u b r o u tin e
0 0 0 C H
· ROM Bank 0 (BP5~BP7=000B)
The ROM bank 0 ranges from 0000H to
1FFFH.
U n u s e d
0 1 0 H
T im e r 2 in te r r u p t s u b r o u tin e
0 1 4 H
· Location 000H
T im e r 3 in te r r u p t s u b r o u tin e
0 1 8 H
This area is reserved for the initialization
program. After chip reset, the program always begins execution at location 000H.
P ro g ra m
R O M
D /A b u ffe r e m p ty in te r r u p t
· Location 004H
This area is reserved for the external interrupt service program. If the INT input pin is
activated, and the interrupt is enabled and
the stack is not full, the program begins execution at location 004H.
Mode
3 F F F H
1 6 b its
Program memory
Program Rom Address
*13 *12 *11 *10 *9 *8
*7
*6
*5
*4
*3
*2
*1
*0
Initial reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
External interrupt
0
0
0
0
0
0
0
0
0
0
0
1
0
0
Timer counter 0 overflow
0
0
0
0
0
0
0
0
0
0
1
0
0
0
Timer 2 overflow
0
0
0
0
0
0
0
0
0
1
0
0
0
0
Timer 3 overflow
0
0
0
0
0
0
0
0
0
1
0
1
0
0
D/A buffer empty interrupt
0
0
0
0
0
0
0
0
0
1
1
0
0
0
Skip
PC+2
Loading PCL
*13 *12 *11 *10 *9 *8 @7 @6 @5 @4 @3 @2 @1 @0
Jump, call branch
BP.5 #12 #11 #10 #9 #8
#7 #6
#5
#4
#3
#2
#1
#0
Return from subroutine
S13 S12 S11 S10 S9 S8 S7 S6 S5
S4
S3
S2 S1
S0
Program rom address
S13~S0: Stack register bits
BP.5: Bit 5 of bank pointer (04H)
Note: *13~*0: Program ROM address
@[email protected]: PCL bits
#12~#0: Instruction code bits
8
July 24, 2000
Preliminary
· Location 010H/014H
the main routine are likely to be changed by
the table read instruction used in the ISR. Errors can occur. In other words, using the table
read instruction in the main routine and the
ISR simultaneously should be avoided. However, if the table read instruction has to be applied in both the main routine and the ISR,
the interrupt is supposed to be disabled prior
to the table read instruction. It will not be enabled until the TBLH has been backed up. All
table related instructions need two cycles to
complete the operation. These areas may
function as normal program memory depending upon the requirements.
This area is reserved for the timer 2/3 interrupt
service program. If a timer interrupt results
from a timer 2/3 overflow, and if the interrupt is
enabled and the stack is not full, the program
begins execution at location 010H/014H.
· Location 018H
This area is reserved for the D/A buffer empty
interrupt service program. After the system
latch a D/A code at RAM address 28H, the interrupt is enable, and the stack is not full, the
program begins execution at location 020H.
· Location 020H
For best condition, this is the starting location for writing the program..
Stack register - STACK
This is a special part of the memory which is
used to save the contents of the program counter (PC) only. The stack is organized into eight
levels and is neither part of the data nor part of
the program space, and is neither readable nor
writeable. The activated level is indexed by the
stack pointer (SP) and is neither readable nor
writeable. At a subroutine call or interrupt acknowledgment, the contents of the program
counter and ROM address A13 bit latch Data
are pushed onto the stack. At the end of a subroutine or an interrupt routine, signaled by a
return instruction (RET or RETI), the program
counter and ROM address A13 bit latch Data
are restored to its previous value from the
stack. After a chip reset, the SP will point to the
top of the stack.
· ROM Bank 1 (BP5~BP7=001B)
The range of the ROM starts from 2000H to
3FFFH.
· Table location
Any location in the ROM space can be used as
look up tables. The instructions TABRDC [m]
(use for any bank) and TABRDL [m] (only
used for last page of program ROM) transfers
the contents of the lower-order byte to the
specified data memory, and the higher-order
byte to TBLH (08H). Only the destination of
t h e l ow er - or d er b y te i n t he t a b l e i s
well-defined. The higher-order byte of the table word are transferred to the TBLH. The table higher-order byte register (TBLH) is read
only. The table pointer (TBHP, TBLP) is a
read/write register (1FH, 07H), which indicates the table location. Before accessing the
table, the location must be placed in TBLP.
The TBLH is read only and cannot be restored. If the main routine and the ISR (Interrupt Service Routine) both employ the table
read instruction, the contents of the TBLH in
Instruction(s)
HTG2150
If the stack is full and a non-masked interrupt
takes place, the interrupt request flag will be recorded but the acknowledgment will be inhibited.
When the stack pointer is decremented (by RET
or RETI), the interrupt will be serviced. This feature prevents stack overflow allowing the proTable Location
*13 *12 *11 *10
*9
*8
*7
*6
*5
*4
*3
*2
*1
*0
TABRDC [m]
#5
#4
#3
#2
#1
#0
@7
@6
@5
@4
@3
@2
@1
@0
TABRDL [m]
1
1
1
1
1
1
@7
@6
@5
@4
@3
@2
@1
@0
Table location
Note: @[email protected]: TBLP register bit 7~bit 0
#5~#0: TBHP register bit 13~bit 8
*13~*0: Current Program ROM table
address bit 13~bit 0
9
July 24, 2000
Preliminary
grammer to use the structure more easily. In a
similar case, if the stack is full and a CALL is
subsequently executed, stack overflow occurs and
the first entry will be lost (only the most recent
eight return address are stored).
0 0 H
IA R 0
0 1 H
M P 0
M e m o r y P o in te r 0
0 2 H
IA R 1
In d ir e c t A d d r e s s in g R e g is te r 1
0 3 H
Data memory - RAM
· Bank 0 (BP4~BP0=00000)
The Bank 0 data memory includes special
purpose and general purpose memory. The
special purpose memory is addressed from
00H to 2FH, while general purpose memory is
addressed from 40H to FFH. All data memory
areas can handle arithmetic, logic, increment,
decrement and rotate operations directly. Except for some dedicated bits, each bit in the
data memory can be set and reset by the SET
[m].i and CLR [m].i instructions, respectively.
They are also indirectly accessible through the
memory pointer registers (MP0;01H, MP1;03H).
In d ir e c t A d d r e s s in g R e g is te r 0
M P 1
M e m o r y P o in te r 1
0 4 H
B P
B a n k P o in te r
0 5 H
A C C
0 6 H
P C L
A c c u m u la to r
P ro g ra m
C o u n te r L o w e r - b y te R e g is te r
0 7 H
T B L P
0 8 H
T B L H
T a b le H ig h e r - o r d e r B y te R e g is te r
W a tc h d o g T im e r O p tio n S e ttin g R e g is te r
T a b le P o in te r L o w e r - o r d e r B y te R e g is te r
0 9 H
W D T S
0 A H
S T A T U S
S ta tu s R e g is te r
0 B H
IN T C
In te r r u p t C o n tr o l R e g is te r
0 C H
T M R 0 H
T im e r C o u n te r 0 H ig h e r - o r d e r B y te R e g is te r
0 D H
T M R 0 L
T im e r C o u n te r 0 L o w e r - o r d e r B y te R e g is te r
0 E H
T M R 0 C
T im e r C o u n te r 0 C o n tr o l R e g is te r
· Bank 15 (BP4~BP0=01111B)
0 F H
The range of RAM starts from 80H to A7H.
On the LCD, every bit stands for one dot. If
the bit is ²1², the light of the dot on the LCD
will be turned on. If the bit is ²0², then it will
be turned off. Only MP1 can deal with the
memory of this range.
The contrast form of RAM location, COMMON, and SEGMENT is as follows.
1 0 H
1 1 H
1 2 H
P A
1 3 H
P A C
1 4 H
P B
1 5 H
P B C
P A I/O
P A I/O
D a ta R e g is te r
C o n tr o l R e g is te r
P B I/O
P B I/O
D a ta R e g is te r
C o n tr o l R e g is te r
1 6 H
S p e c ia l P u r p o s e
D a ta M e m o ry
1 7 H
1 8 H
1 9 H
1 A H
1 B H
1 C H
1 D H
1 E H
IN T C H
1 F H
T B H P
Indirect addressing register
In te r r u p t C o n tr o l H ig h e r - o r d e r B y te R e g is te r
T a b le P o in te r H ig h e r - o r d e r B y te R e g is te r
Location 00H and 02H are indirect addressing
registers that are not physically implemented.
Any read/write operation of [00H] and [02H] access data memory are pointed to by MP0 (01H)
and MP1 (03H) respectively. Reading location
00H or 02H indirectly will return the result 00H.
Writing indirectly results in no operation.
The function of data movement between two indirect addressing registers, is not supported. The
memory pointer registers, MP0 and MP1, are
8-bit registers which can be used to access the
data memory by combining corresponding indirect addressing registers but Bank 15 can use
MP1 only.
2 0 H
2 1 H
T M R 2
T im e r 2 R e g is te r
2 2 H
T M R 2 C
T im e r 2 C o n tr o l R e g is te r
2 3 H
2 4 H
T M R 3
2 5 H
T M R 3 C
T im e r 3 C o n tr o l R e g is te r
2 6 H
X 'T A L C
X 't a l F a s t O s c illa t o r u p C o n t r o l
2 7 H
P W M C
2 8 H
P W M
T im e r 3 R e g is te r
P W M
P W M
C o n tro l
D a ta
2 9 H
2 A H
2 B H
2 C H
2 D H
2 E H
L C D C
2 F H
C O M R
L C D
C o n tr o l R e g is te r
C o m m o n P a d A d d re s s R o ta to r
3 0 H
3 F H
4 0 H
: U n u s e d
G e n e ra l P u rp o s e
B a n k 0 D a ta M e m o ry
(1 9 2 B y te )
HTG2150
R e a d a s "0 0 "
P B b it 3 /2 /1 /0 R e a d = 0
Accumulator
The accumulator is closely related to ALU operations. It is also mapped to location 05H of the
data memory and it can carry out immediate
data operations. The data movement between
two data memories has to pass through the accumulator.
F F H
8 0 H
B a n k 1 5 D a ta M e m o ry
(4 0 B y te )
A 7 H
RAM mapping
10
July 24, 2000
Preliminary
HTG2150
LCD driver output can be enabled or disabled by
setting the LCD (bit 6 of LCDC; 2EH) without the
influence of the related memory condition. There
is a special function for LCD display, which is Rotate function. There are 8 kinds of Rotate function, (user can change the data of the SS0 to SS3.)
LCD driver output
The maximum output number of the HTG2150
LCD driver is 8´40. The LCD driver bias type is
²R² type, no external capacitor is required and the
bias voltage is 1/4 bias. Some of the Segment outputs share pins with another pins, PB4~PB7
(SEG33~SEG36), INT (SEG37), XOUT (SEG38),
XIN (SEG39). Whether segment output or I/O pin
canindividuallybedecidedbymaskoption.
An example of an lcd driving waveform (1/8
duty, 1/4 bias) is shown below.
3 2 H z
2
1
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1
2
3
4
5
5 1 2 H z
C O M 0
V D D
3 /4 V D D
2 /4 V D D
1 /4 V D D
G N D
C O M 1
V D D
3 /4 V D D
2 /4 V D D
1 /4 V D D
G N D
S E G 0
V D D
3 /4 V D D
2 /4 V D D
1 /4 V D D
G N D
L C D d is p la y m e m o r y : (B a n k 1 5 )
A d d re s s
8 0 H
C O M 0
B it0
C O M 1
B it1
C O M 2
B it2
C O M 3
B it3
C O M 4
B it4
C O M 5
B it5
C O M 6
B it6
C O M 7
8 1 H
8 2 H
8 3 H
S E G 1
S E G 2
S E G 3
8 4 H
8 5 H
9 1 H
9 2 H
A 7 H
S E G 1 8
S E G 3 9
B it7
S E G 0
S E G 4
S E G 5
S E G 1 7
11
July 24, 2000
Preliminary
Register
Bit No.
Label
0~5
¾
6
LCD
7
RC
LCDC
HTG2150
Function
Can R/W (Default 000000B)
Control the LCD output (0=disable; 1=enabled) (Default=1)
LCD clock source select (Default=0)
1= 32768Hz crystal
0= system clock
LCDC register
Rotate
Description
SSL3 SSL2 SSL1 SSL0
x
0
0
0
The Pad of common 0 is connected to common 0 and the Pad of common
1 is connected to common 1 and so on.
x
0
0
1
The Pad of common 0 is connected to common 1 and the Pad of common
1 is connected to common 2 and so on.
x
0
1
0
The Pad of common 0 is connected to common 2 and the Pad of common
1 is connected to common 3 and so on.
x
0
1
1
The Pad of common 0 is connected to common 3 and the Pad of common
1 is connected to common 4 and so on.
x
1
0
0
The Pad of common 0 is connected to common 4 and the Pad of common
1 is connected to common 5 and so on.
x
1
0
1
The Pad of common 0 is connected to common 5 and the Pad of common
1 is connected to common 6 and so on.
x
1
1
0
The Pad of common 0 is connected to common 6 and the Pad of common
1 is connected to common 7 and so on.
x
1
1
1
The Pad of common 0 is connected to common 7 and the Pad of common
1 is connected to common 0 and so on.
2FH register
12
July 24, 2000
Preliminary
give different results from those intended. The
TO and PD flags can only be changed by system
power up, Watchdog Timer overflow, executing
the HALT instruction and clearing the Watchdog Timer.
Arithmetic and logic unit - ALU
This circuit performs 8-bit arithmetic and logic
operation. The ALU provides the following
functions:
· Arithmetic operations (ADD, ADC, SUB,
·
·
·
·
The Z, OV, AC and C flags generally reflect the
status of the latest operations.
SBC, DAA)
Logic operations (AND, OR, XOR, CPL)
Rotation (RL, RR, RLC, RRC)
Increment and Decrement (INC, DEC)
Branch decision (SZ, SNZ, SIZ, SDZ ....)
In addition, on entering the interrupt sequence
or executing the subroutine call, the status register will not be automatically pushed onto the
stack. If the contents of status are important
and if the subroutine can corrupt the status
register, precautions must be taken to save it
properly.
The ALU not only saves the results of a data operation but also changes the status register.
Status register - STATUS
Interrupt
This 8-bit register (0AH) contains the zero flag
(Z), carry flag (C), auxiliary carry flag (AC),
overflow flag (OV), power down flag (PD) and
watchdog time-out flag (TO). It also records the
status information and controls the operation sequence.
The HTG2150 provides an external interrupt and
a PWM D/A interrupt and internal timer interrupts. The Interrupt Control register (INTC;0BH,
INTCH;1EH) contains the interrupt control bits to
set the enable/disable and the interrupt request
flags.
With the exception of the TO and PD flags, bits
in the status register can be altered by instructions like any other register. Any data written
into the status register will not change the TO
or PD flags. In addition it should be noted that
operations related to the status register may
Labels
HTG2150
Once an interrupt subroutine is serviced, all
other interrupts will be blocked (by clearing the
EMI bit). This scheme may prevent any further
interrupt nesting. Other interrupt requests may
happen during this interval but only the inter-
Bits
Function
C
0
C is set if the operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation; otherwise C is cleared. C
is also affected by a rotate through carry instruction.
AC
1
AC is set if the operation results in a carry out of the low nibbles in addition or no
borrow from the high nibble into the low nibble in subtraction; otherwise AC is
cleared.
Z
2
Z is set if the result of an arithmetic or logic operation is zero; otherwise Z is
cleared.
OV
3
OV is set if the operation results in a carry into the highest-order bit but not a
carry out of the highest-order bit, or vice versa; otherwise OV is cleared.
PD
4
PD is cleared when either a system powers up or a CLR WDT instruction is executed. PD is set by executing the HALT instruction.
TO
5
TO is cleared by a system power-up or executing the CLR WDT or HALT instruction. TO is set by a WDT time-out.
¾
6, 7
Undefined bits, read as ²0².
Status register
13
July 24, 2000
Preliminary
request flag (T0F; bit 5 of INTC), resulting from
a timer 0 overflow. When the interrupt is enabled, and the stack is not full and the T0F bit
is set, a subroutine call to location 08H will occur. The related interrupt request flag (T0F)
will be reset and the EMI bit cleared to disable
further interrupts.
rupt request flag is recorded. If a certain interrupt needs servicing within the service routine,
the programmer may set the EMI bit and the
corresponding bit of the INTC to allow interrupt
nesting. If the stack is full, the interrupt request
will not be acknowledged, even if the related interrupt is enabled, until the SP is decremented. If
immediate service is desired, the stack must be
prevented from becoming full.
The Timer 2/3 interrupts are operated in the
same manner as timer 0. While ET2I/ET3I and
T2F/T3F are the related control bits and the related request flags of TMR2/TMR3, which locate at bit0/bit1 and bit4/bi5 of the INTCH
respectively.
All these kinds of interrupt have a wake-up capability. As an interrupt is serviced, a control
transfer occurs by pushing the program counter
and A13 bit onto the stack followed by a branch
to subroutines at specified locations in the program memory. Only the program counter and
A13 bit are pushed onto the stack. If the contents of the register and Status register
(STATUS) are altered by the interrupt service
program which corrupt the desired control sequence, the contents should be saved first.
During the execution of an interrupt subroutine,
other interrupt acknowledgments are held until
the RETI instruction is executed or the EMI bit
and the related interrupt control bit are set to 1 ( if
the stack is not full). To return from the interrupt
subroutine, the RET or RETI instruction may be
invoked. RETI will set the EMI bit to enable an interrupt service, but RET will not.
External interrupt is triggered by a high to low
transition of INT and the related interrupt request flag (EIF; bit 4 of INTC) will be set. When
the interrupt is enabled, and the stack is not
full and the external interrupt is active, a subroutine call to location 04H will occur. The interrupt request flag (EIF) and EMI bits will be
cleared to disable other interrupts.
Interrupts occurring in the interval between
the rising edges of two consecutive T2 pulses,
will be serviced on the latter of the two T2
pulses, if the corresponding interrupts are enabled. In the case of simultaneous requests the
priorities applied are shown in the following table. These can be masked by resetting the EMI
bit.
The internal timer counter 0 interrupt is initialized by setting the timer counter 0 interrupt
Register
INTC
HTG2150
Bit No.
Label
Function
0
EMI
Controls the (global) interrupt
(1=enable; 0=disable)
1
EEI
Controls the external interrupt
(1=enable; 0=disable)
2
ET0I
Controls the timer counter 0 interrupt
(1=enable; 0=disable)
3
¾
4
EIF
External interrupt request flag
(1=active; 0=inactive)
5
T0F
Internal timer counter 0 request flag
(1=active; 0=inactive)
6, 7
¾
Unused bit
Unused bit
INTC register
14
July 24, 2000
Preliminary
Register
INTCH
Bit No.
Label
0
ET2I
Controls the Timer 2 interrupt
(1=enable; 0=disable)
1
ET3I
Controls the Timer 3 interrupt
(1=enable; 0=disable)
2
PWMI
3
¾
4
T2F
Internal Timer 2 request flag
(1=active; 0=inactive)
5
T3F
Internal Timer 3 request flag
(1=active; 0=inactive)
6
PWMF
7
¾
HTG2150
Function
PWM D/A interrupt (1=enable; 0=disable)
Should be set as ²0² always
PWM D/A flag (1=active; 0=inactive)
Should be set as ²0² always
INTCH register
a
External interrupt
1
04H
b
Timer counter 0
overflow
2
08H
and enabling the interrupt is not well controlled,
the ²CALL subroutine² should not operate in the interrupt subroutine as it will damage the original
control sequence.
d
Timer 2 overflow
4
10H
Oscillator configuration
e
Timer 3 overflow
5
14H
There are two oscillator circuits in the HTG2150.
f
PWM D/A interrupt
6
18H
No. Interrupt Source Priority Vector
X IN
O S C I
The timer counter 0 and Timer 2/3 interrupt request flag (T0F/T2F/T3F), External interrupt request flag (EIF), PWM D/A interrupt request flag
(PWMF),Enable Timer 0/2/3 bit (ET0I/ET2I/ET3I)
, Enable PWM D/A interrupt (PWMI), Enable external interrupt bit (EEI) and Enable master interrupt bit (EMI) constitute an interrupt control
register (INTC/INTCH) which is located at
0BH/1EH in the data memory. EMI, EEI, ET0I,
ET2I, ET3I, PWMI are used to control the enabling/disabling of interrupts. These bits prevent
the requested interrupt from being serviced. Once
the interrupt request flags (T0F, T2F, T3F, EIF,
PWMF) are set, they will remain in the
INTC/INTCH register until the interrupts are serviced or cleared by a software instruction.
3 2 7 6 8 H z
R C
O s c illa to r
X O U T
R T C
O s c illa to r
System and RTC oscillator
The RC oscillator signal provides the internal
system clock. The HALT mode stops the system
oscillator and ignores any external signal to
conserve power. Only the RC oscillator is designed to drive the internal system clock. The
RTC oscillator provides the Timer 3 and LCD
driver clock source.
The RC oscillator needs an external resistor
connected between OSCI and VSS. The resistance value must range from 50kW to 400kW.
However, the frequency of the oscillation may
vary with VDD, temperature and the chip itself
due to process variations. It is, therefore, not suitable for timing sensitive operations where accurate oscillator frequency is desired.
It is recommended that a program does not use
the ²CALL subroutine² within the interrupt
subroutine. Interrupts often occur in an unpredictable manner or need to be serviced immediately in some applications. If only one stack is left
15
July 24, 2000
Preliminary
There is another oscillator circuit designed for
the real time clock. In this case, only the
32768Hz crystal can be applied. The crystal
should be connected between XIN and XOUT,
and two external capacitors are required for the
oscillator circuit in order to get a stable frequency.
mum time-out period is 2.6 seconds.
WS2
WS1
WS0
Division Ratio
0
0
0
1:1
0
0
1
1:2
0
1
0
1:4
0
1
1
1:8
1
0
0
1:16
1
0
1
1:32
1
1
0
1:64
1
1
1
1:128
The RTC oscillator is used to provide clock
source for the LCD driver and Timer 3. It can be
enabled or disabled by mask option.
The WDT oscillator is a free running on-chip
RC oscillator, requiring no external components. Even if the system enters the power
down mode, and the system clock is stopped,
the WDT oscillator still runs with a period of
approximately 78ms. The WDT oscillator can be
disabled by mask option to conserve power.
WDTS register
The WDT overflow under normal operation will
initialize ²chip reset² and set the status bit TO.
Whereas in the HALT mode, the overflow will
initialize a ²warm reset² only the PC and SP are
reset to zero. To clear the WDT contents (including the WDT prescaler), three methods are
adopted; external reset (a low level to RES),
software instructions, or a HALT instruction.
The software instruction is ²CLR WDT², execution of the CLR WDT instruction will clear the
WDT.
Watchdog Timer - WDT
The WDT clock source is implemented by a dedicated RC oscillator (WDT oscillator). This timer
is designed to prevent a software malfunction or
sequence jumping to an unknown location with
unpredictable results. The Watchdog Timer can
be disabled by mask option. If the Watchdog
Timer is disabled, all the executions related to
WDT result in no operation.
Power down operation - HALT
When the internal WDT oscillator (RC oscillator with 83ms period normally) is enable, it is
first divided by 256 (8 stages) to get the nominal
time-out period of approximately 21ms. This
time-out period may vary with temperature,
VDD and process variations. By invoking the
WDT prescaler, longer time-out periods can be
realized. Writing data to WS2, WS1, WS0 (bits
2,1,0 of the WDTS) can give different time-out
periods. If WS2, WS1, WS0 are all equal to 1,
the division ratio is up to 1:128, and the maxi-
W D T
O S C
HTG2150
The HALT mode is initialized by the HALT instruction and results in the following...
· The system oscillator will turn off but the
WDT oscillator keeps running (if the WDT oscillator is selected).
· The contents of the on-chip RAM and registers remain unchanged.
· WDT and WDT prescaler will be cleared and do
recounting again.
W D T P r e s c a le r
8 - b it C o u n te r
7 - b it C o u n te r
8 -to -1 M U X
W S 0 ~ W S 2
W D T T im e - o u t
Watchdog Timer
16
July 24, 2000
Preliminary
HTG2150
· All I/O ports maintain their original status.
· The PD flag is set and the TO flag is cleared.
Reset
The system can leave the HALT mode by means
of an external reset, an interrupt, an external
falling edge signal on port A or a WDT overflow.
An external reset causes a device initialization
and the WDT overflow performs a ²warm reset².
By examining the TO and PD flags, the reason for
chip reset can be determined. The PD flag is
cleared when the system powers up or upon executing the CLR WDT instruction and is set when
the HALT instruction is executed. The TO flag is
set if the WDT time-out occurs, and causes a
wake-up that only resets the PC and SP, the others maintain their original status.
· RES reset during normal operation
· RES reset during HALT
· WDT time-out reset during normal operation
There are three ways in which a reset can occur:
The WDT time-out during HALT is different
from other chip reset conditions, since it can
perform a ²warm reset² that just resets the PC
and SP, leaving the other circuits in their original state. Some registers remain unchanged
during other reset conditions. Most registers
are reset to the ²initial condition² when the reset conditions are met. By examining the PD
and TO flags, the program can distinguish between different ²chip resets².
The port A wake-up and interrupt methods can
be considered as a continuation of normal execution. Each bit in port A can be independently
selected to wake up the device by mask option.
Awakening from an I/O port stimulus, the program will resume execution of the next instruction. If awakening from an interrupt, two
sequences may happen. If the related interrupt
is disabled or the interrupt is enabled but the
stack is full, the program will resume execution
at the next instruction. If the interrupt is enabled and the stack is not full, the regular interrupt response takes place.
TO
PD
RESET Conditions
0
0
RES reset during power-up
u
u
RES reset during normal
operation
0
1
RES wake-up HALT
1
u
WDT time-out during normal
operation
1
1
WDT wake-up HALT
Note: ²u² means ²unchanged²
Once a wake-up event occurs, it takes 1024 tSYS
(system clock period) to resume normal operation. In other words, a dummy cycle period will
be inserted after the wake-up. If the wake-up
results from an interrupt acknowledge, the actual interrupt subroutine will be delayed by one
more cycle. If the wake-up results in the next
instruction execution, this will be executed immediately after a dummy period has finished. If
an interrupt request flag is set to ²1² before entering the HALT mode, the wake-up function of
the related interrupt will be disabled.
To guarantee that the system oscillator has
started and stabilized, the SST (System
Start-up Timer) provides an extra-delay of 1024
system clock pulses when the system powers up
or awakes from the HALT state.
When a system power-up occurs, the SST delay
is added during the reset period. But when the
reset comes from the RES pin, the SST delay is
disabled. Any wake-up from HALT will enable
the SST delay.
To minimize power consumption, all I/O pins
should be carefully managed before entering
the HALT status.
17
July 24, 2000
Preliminary
The functional unit chip reset status are shown
below.
PC
000H
Interrupt
Disable
Prescaler
Clear
WDT
Clear. After master
reset, WDT begins
counting
Timer (0/2/3)
Off
LCD Display
Enable
Pull-high of RESB
with
Input/output Ports
Input mode
SP
Points to the top of
the stack
Timer 0
The timer 0 contains 16-bit programmable
count-up counters and the clock source come
from the system clock divided by 4.
There are three registers related to timer counter 0; TMR0H (0CH), TMR0L (0DH), TMR0C
(0EH). Writing TMR0L only writes the data
into a low byte buffer, and writing TMR0H will
write the data and the contents of the low byte
buffer into the timer 0 preload register (16-bit)
simultaneously. The timer 0 preload register is
changed by writing TMR0H operations and
writing TMR0L will keep the timer 0 preload
register unchanged.
Reading TMR0H will also latch the TMR0L
into the low byte buffer to avoid the false timing
problem. Reading TMR0L returns the contents
of the low byte buffer. In other words, the low
byte of timer counter 0 cannot be read directly.
It must read the TMR0H first to make the low
byte contents of timer 0 be latched into the
buffer.
V D D
R E S
tS
S T
S S T T im e - o u t
C h ip
The TMR0C is the timer 0 control register,
which defines the timer 0 options.
R e s e t
Reset timing chart
V
The timer counter control registers define the
operating mode, counting enable or disable and
active edge.
D D
If the timer counter starts counting, it will
count from the current contents in the timer
counter to FFFFH. Once an overflow occurs,
the counter is reloaded from the timer counter
preload register and generates the corresponding interrupt request flag (T0F; bit of INTC) at
the same time.
To enable the counting operation, the Timer ON
bit (TON; bit 4 of TMR0C) should be set to 1. The
overflow of the timer counter is one of the
wake-up sources. No matter what the operation
mode is, writing a 0 to ET0I can disable the corresponding interrupt service.
In the case of timer counter OFF condition, writing data to the timer counter preload register
will also reload that data to the timer counter.
But if the timer counter is turned on, data
written to the timer counter will only be kept
in the timer counter preload register. The
timer counter will still operate until overflow
occurs.
R E S
Reset circuit
H A L T
W D T
W D T
W a rm
R e s e t
T im e - o u t
R e s e t
R E S
O S C 1
HTG2150
S S T
1 0 -s ta g e
R ip p le C o u n te r
C o ld
R e s e t
P o w e r - o n D e te c tio n
Reset configuration
18
July 24, 2000
Preliminary
HTG2150
The state of the registers is summarized in the following table:
Reset
(Power On)
WDT
Time-out
(Normal
Operation)
RES Reset
(Normal
Operation)
RES Reset
(HALT)
WDT
Time-out
(HALT)
TMR0H
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TMR0L
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TMR0C
00-0 1---
00-0 1---
00-0 1---
00-0 1---
uu-u u---
TMR2
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TMR2C
00-0 1000
00-0 1000
00-0 1000
00-0 1000
uu-u uuuu
TMR3
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TMR3C
00-0 1000
00-0 1000
00-0 1000
00-0 1000
uu-u uuuu
INTCH
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
TBHP
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
0000H
0000H
0000H
0000H
0000H*
MP0
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
MP1
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
ACC
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TBLP
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TBLH
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
STATUS
--00 xxxx
--1u uuuu
--uu uuuu
--01 uuuu
--11 uuuu
BP
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
LCDC
0100 0000
0100 0000
0100 0000
0100 0000
uuuu uuuu
INTC
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
WDTS
0000 0111
0000 0111
0000 0111
0000 0111
uuuu uuuu
PA
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PAC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PB
1111 0000
1111 0000
1111 0000
1111 0000
uuuu uuuu
PBC
1111 0000
1111 0000
1111 0000
1111 0000
uuuu 0000
COMR
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
PWMC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PWM
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
X¢TALC
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
Register
Program Counter
Note: ²*² means ²warm reset²
²u² means ²unchanged²
²x² means ²unknown²
19
July 24, 2000
Preliminary
Label
Bits
¾
0~2
Function
Unused bits, read as ²0².
TE
3
To define the TMR0 active edge of the timer counter
(0=active on low to high; 1=active on high to low)
TON
4
To enable/disable timer counting (0=disabled; 1=enabled)
5
Unused bits, read as ²x².
¾
TM0, TM1
6, 7
HTG2150
0, 1=Internal clock
TMR0C register
FFH. Once an overflow occurs, the counter is
reloaded from a preload register, and generates
an interrupt request flag (T2F; bit 4 of INTCH).
To enable the counting operation, the timer On
bit (TON; bit 4 of TMR2C) should be set to ²1².
For proper operation, bit 6 of TMR2C should be
set to ²1² and bit 3, bit7 should be set to ²0².
When the timer counter (reading TMR0H) is
read, the clock will be blocked to avoid errors. As this may results in a counting error,
this must be taken into consideration by the
programmer.
D a ta B u s
T im e r C o u n te r 0
P r e lo a d R e g is te r
S y s te m
C lo c k /4
T im e r
C o u n te r 0
The Timer 2 can also be used as PFD output by
setting PWM1 and PWM2 to be PFD and PFDB
output respectively by 2FH.7 and 2FH.6. When
the PFD/PFDB function is selected, setting
2FH.4/2FH.5 to ²1² will enable the PFD/PFDB
output and setting 2FH.4/2FH.5 to ²0² will disable the PFD/PFDB output. PFD Frequency:
T2f/[256-TMR2)´2]
R e lo a d
O v e r flo w
T o In te rru p t
L o w B y te
B u ffe r
Timer 3 has the same structure and operating
manner with Timer 2, except for clock source
and PFD function. The Timer 3 can be used as a
time base to generate a regular internal interrupt. The clock source of Timer 3 can come from
RTC OSC (X¢TAL 32kHz) or system clock divided by an 8-stage prescaler. If the RTC mask
option is enabled, a 32kHz crystal is needed
across XIN and XOUT pins. The 32kHz signal
is processed by an 8-stage prescaler to yield
various counting clock for Timer 3. There are 2
registers related to Timer 3; TMR3 (24H) and
TMR3C (25H). Writing data to B2, B1, B0 (bit 2,
1, 0 of TMR3C) can yield various counting clock.
Timer counter 0
Timer 2/3
Timer 2 is an 8-bit counter, and its clock source
comes from the system clock divided by an
8-stage prescaler. There are two registers related to Timer 2 ; TMR2 (21H) and TMR2C
(22H). Two physical registers are mapped to
TMR2 location; writing TMR2 makes the starting value be placed in the Timer 2 preload register and reading the TMR2 gets the contents of
the Timer 2 counter. The TMR2C is a control
register, which defines the division ratio of the
prescaler and counting enable or disable.
Writing data to B2, B1 and B0 (bits 2, 1, 0 of
TMR2C) can yield various clock sources.
Once the Timer 2 starts counting, it will count
from the current contents in the counter to
20
July 24, 2000
Preliminary
HTG2150
D a ta B u s
S Y S C L K
T im e r 2
P r e lo a d R e g is te r
8 -s ta g e
P r e s c a le r
R e lo a d
T o in te r r u p t
T 2 f
¸ 2
T im e r 2
T O N
O v e r flo w
2 F H .5
P W M 2
d a c
P W M 2
2 F H .7
2 F H .4
P W M 1
P W M 1 d a c
2 F H .6
Timer 2
Label
Bits
SSL 3~0
3~0
Function
LCD common used
PFD
4
To enable/disable PFD output (0=disable; 1=enable)
PFDB
5
To enable/disable PFDB output (0=disable; 1=enable)
PWM1
6
To select PFDB/PWM1 output (0=PWM1; 1=PFDB)
PWM2
7
To select PFD/PWM2 output (0=PWM2; 1=PFD)
2FH register
S y s te m
C lo c k
8 S ta g e P r e s c a le r
F 0
n e a r 3 2 7 6 8 H z
P r e lo a d
m a s k o p tio n
T 3 f
F 1
8 S ta g e P r e s c a le r
3 2 K X 'A T L
T im e r 3
T O N
¸ 6 4
2 E H .7
IN T
L C D D r iv e r
(5 1 2 H z )
Timer 3
21
July 24, 2000
Preliminary
TMR2C
TMR3C
T2f
Bit 2 Bit 1 Bit 0
HTG2150
T3f
Bit 2 Bit 1 Bit 0
0
0
0
SYS CLK/2
0
0
0
F1/2
0
0
1
SYS CLK/4
0
0
1
F1/4
0
1
0
SYS CLK/8
0
1
0
F1/8
0
1
1
SYS CLK/16
0
1
1
F1/16
1
0
0
SYS CLK/32
1
0
0
F1/32
1
0
1
SYS CLK/64
1
0
1
F1/64
1
1
0
SYS CLK/128
1
1
0
F1/128
1
1
1
SYS CLK/256
1
1
1
F1/256
TMR2C bit 4 to enable/disable timer counting
(0=disable;1=enable)
TMR2C bit 3 always write ²0²
TMR2C bit 5 always write ²0²
TMR2C bit 6 always write ²1²
TMR2C bit 7 always write ²0²
Time base frequency= T3f / (256 - TMR3)
TMR3C bit 4 to enable/disable timer counting
(0=disable; 1=enable)
TMR3C bit 3 always write ²0²
TMR3C bit 5 always write ²0²
TMR3C bit 6 always write ²1²
TMR3C bit 7 always write ²0²
F1 can select 4 frequency by mask option
Auto Mask Option
F0
SYS CLK near 512kHz
SYS CLK/16
SYS CLK near 1024kHz
SYS CLK/32
SYS CLK near 2048kHz
SYS CLK/64
SYS CLK near 4096kHz
SYS CLK/128
22
July 24, 2000
Preliminary
After a chip reset, these input/output lines stay
at high levels or floating (mask option). Each
bit of these input/output latches can be set or
cleared by the SET [m].i or CLR [m].i (m=12H,
14H) instruction.
Input/output ports
There are 12 bidirectional input/output lines in
the HTG2150, labeled PA and PB, which are
mapped to the data memory of [12H], [14H], respectively. All these I/O ports can be used for input and output operations. For input operation,
these ports are non-latching, that is, the inputs
must be ready at the T2 rising edge of instruction MOV A,[m] (m=12H, 14H). For output operation, all data is latched and remains
unchanged until the output latch is rewritten.
Some instructions first input data and then follow the output operations. For example, the
SET [m].i, CLR [m].i, CPL [m] and CPLA [m]
instructions read the entire port states into the
CPU, execute the defined operations
(bit-operation), and then write the results back
to the latches or the accumulator.
Each I/O line has its own control register (PAC,
PBC) to control the input/output configuration.
With this control register, CMOS output or
schmitt trigger input with or without pull-high
resistor (mask option) structures can be reconfigured dynamically under software control. To
function as an input, the corresponding latch of
the control register must write ²1². The
pull-high resistance will exhibit automatically
if the pull-high option is selected. The input
source also depends on the control register. If
the control register bit is ²1², the input will read
the pad state. If the control register bit is ²0²,
the contents of the latches will move to the int e r n a l b us . T he l a t ter i s p os s i b l e i n
²read-modify-write² instruction. For output
function, CMOS is the only configuration.
These control registers are mapped to locations
13H, 15H.
D A T A B u s
W r ite C o n tr o l R e g is te r
Each line of port A has the capability to wake-up
the device. Port B are share pad, each pin function are defined by mask option, the PB7 shares
with SEG36. The PB6, PB5 and PB4 share with
SEG35, SEG34 and SEG33. If the segment output is selected, the related I/O register (PB) cannot be used as general purpose register. Reading
the register will result to an unknown state.
PWM interface
The HTG2150 provides an 8 bit (bit 7 is a sign
bit) PWM D/A interface, which is good for
speech synthesis. The user can record or synthesize the sound and digitize it into the program ROM. These sound could be played back
in sequence of the functions as designed by the
internal program ROM. There are several algorithms that can be used in the HTG2150, they
are ... PCM, mLAW, DPCM, ADPCM..... .
V
Q
D
C K
Q
S
V
C h ip R e s e t
D
P A 0 ~ P A 7
P B 4 ~ P B 7
Q
C K
S
Q
M
R e a d I/O
S y s te m
D D
D D
W E A K
P u ll- u p
M a s k O p tio n
R e a d C o n tr o l R e g is te r
W r ite I/O
HTG2150
U
X
W a k e - u p ( P A o n ly )
M a s k O p tio n
Input/output ports
23
July 24, 2000
Preliminary
On the above table, we can easily see that the
sampling rate is dependent on the system clock.
If start bit is set to ²0², the PWM2 and PWM1
will output a GND level voltage.
The PWM circuit provides two pad outputs:
PWM2, PWM1 which can directly drive a piezo
or a 32W speaker without adding any external
element. Refer to the Application Circuits.
The PWM clock source comes from the system
clock divided by a 3-bit prescaler. Setting data
to P0, P1 and P2 (bit 3, 4, 5 of 27H) can yield
various clock sources. The clock source are use
for PWM modulating clock and sampling clock.
After setting the start bit (bit 0 27H) and the
next falling edge coming from the prescaler, the
²DIV² will generate a serial clock to PWM counter for modulating and PWMI for interrupt.
The PWM counter latch data at the first ²F1²
clock falling edge and the start counter at ²F1²
rising edge. The ²F2² clock is synchronous with
the first ²F1² clock and it is also connected to
the PWM output latch. In setting the ²start bit²
initial status, the ²PWM1 DAC² outputs a
²high² level and change the output status to
²LOW² while the ²7 bits counter² overflows.
F2
F1 (Sampling
Rate
BZ/SP
6/7
Bit
0
0
F0
F0/64
32W speaker
0
1
F0
F0/128
32W speaker
1
0
F0
F0/64
Buzzer/8W
speaker
1
1
F0
F0/128
Buzzer/8W
speaker
HTG2150
Label
Bits
Function
D/A
0
D/A control. 0:start ; 1:stop
BZ/SP
1
Output driver select
1:Buzzer ; 0:speaker
Bit
2
PWM counter bit select
1:7 bits ; 0:6 bits
P0~P2
3 bits preload counter,
3~5 bit 5/4/3:000B~111B (0~7)
bit 3:LSB
D0, D1
6, 7 PWMI
D0
Device
D1 Samping Time/PWM Interrupt
0
0
1
0
1
2
1
0
4
1
1
8
PWM control register
bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7
Note: F1: for PWM modulation clock and F2
for sampling clock.
F0: system /[n+1] n=0~7
(n:3 bits preload counter)
7 bit D0
D1
D2
D3 D4 D5
D6
D7
6 bit X
D1
D2
D3 D4 D5
D6
D7
Note: X means don¢t care.
bit7: Sign bit
PWM data buffer
F 0
S ta r t b it
L a tc h
1 2 8 c lo c k
F 1
F 2
O n e s a m p lin g tim e
7 bits PWM counter bit
24
July 24, 2000
Preliminary
HTG2150
D a ta B u s
S y s te m
c lo c k
F 0
S ta r t b it
2 7 H .0
P W M I
P W M D a ta
B u ffe r (2 8 H )
P r e s c a le r
D iv .
F 1
C K
D D
D Q
7 B its C o u n te r
O v e r flo w
P E
F 2
V
Q B
C K
R
P W M 1 d a c
fo r 3 2 W S P K
P W M 2 d a c
fo r 3 2 W S P K
27H.1=0 speaker
D a ta B u s
S y s te m
c lo c k
F 0
S ta r t b it
2 7 H .0
P W M I
P W M D a ta
B u ffe r (2 8 H )
P r e s c a le r
D iv .
F 2
F 1
C K
7 B its C o u n te r
O v e r flo w
P E
V
D D
D Q
Q B
C K
R
S ig n b it
P W M 1 d a c fo r B Z
P W M 2 d a c fo r B Z
27H.1=1 buzzer
25
July 24, 2000
Preliminary
HTG2150
Mask option
The following shows many kinds of mask options in the HTG2150. All the mask options must be defined on order to ensure proper system functioning.
No.
Mask Option
1
WDT enable/disable selection.
WDT can be enabled or disabled by mask option.
2
Wake-up selection. This option defines the wake-up activity. External I/O pins (PA only)
all have the capability to wake-up the chip from a HALT mode by a following edge.
3
External interrupt input pin share with other function selection.
INT/SEG37: INT can be set as an external interrupt input pin or LCD segment output
pin.
4
I/O pins share with other function selection.
PB4/SEG33, PB5/SEG34, PB6/SEG35, PB7/SEG36: PB4, PB5, PB6, PB7 can be set as
I/O pins or LCD segment output pins.
5
Segment output pins share with other function selection.
XIN/SEG39, XOUT/SEG38: SEG38, SEG39 ban be set as LCD segment output pins or
XIN, XOUT pins be connected to a 32768Hz crystal.
6
LCD bias register selection. This option describes the LCD bias current. There are three
types of selection. *
· Selectable as small, middle or large current.
Note: *
S m a ll c u r r e n t
V
M id d le c u r r e n t
V
D D
1 1 0 k W
L a rg e c u rre n t
V
D D
6 0 k W
3 /4 V
3 /4 V
D D
D D
6 0 k W
1 1 0 k W
2 /4 V
D D
6 0 k W
1 /4 V
1 1 0 k W
2 /4 V
D D
D D
1 /4 V
D D
1 0 k W
6 0 k W
G N D
D D
1 0 k W
1 /4 V
D D
3 /4 V
1 0 k W
2 /4 V
D D
1 1 0 k W
D D
1 0 k W
G N D
G N D
26
July 24, 2000
Preliminary
HTG2150
Application Circuits
3 2 W
s p e a k e r /B u z z e r a p p lic a tio n
8 W
O S C I
C O M 0 ~ C O M 7
S E G 0 ~ S E G 3 9
(M a x .)
s p e a k e r a p p lic a tio n
O S C I
1 /4 B ia s
L C D
P A N E L
C O M 0 ~ C O M 7
S E G 0 ~ S E G 3 9
(M a x .)
1 /4 B ia s
L C D
P A N E L
V
V
V
P W M 1
D D
D D
D D
8 W
S P K
3 2 W S P K
o r B u z z e r
P W M 2
P W M 2
R E S
8 0 5 0
R E S
*
3 2 7 6 8 H z
*
X IN /S E G 3 9
X O U T /S E G 3 8
IN T /S E G 3 7
3 2 7 6 8 H z
P A 0 ~ P A 7
X IN /S E G 3 9
X O U T /S E G 3 8
IN T /S E G 3 7
P A 0 ~ P A 7
H T G 2 1 5 0
H T G 2 1 5 0
Note: * Optional capacitors can be added to get a more accurate frequency.
Since each crystal has its own chararacteristics, the user should consult the crystal manufacturer for appropriate value of the external capacitors.
27
July 24, 2000
Preliminary
HTG2150
Instruction Set Summary
Mnemonic
Description
Instruction
Cycle
Flag
Affected
1
1(1)
1
1
1(1)
1
1
1(1)
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
1
1(1)
Z,C,AC,OV
Z,C,AC,OV
1(1)
C
1
1
1
1(1)
1(1)
1(1)
1
1
1
1(1)
1
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
1
1(1)
1
1(1)
Z
Z
Z
Z
Arithmetic
ADD A,[m]
ADDM A,[m]
ADD A,x
ADC A,[m]
ADCM A,[m]
SUB A,x
SUB A,[m]
SUBM A,[m]
SBC A,[m]
SBCM A,[m]
DAA [m]
Add data memory to ACC
Add ACC to data memory
Add immediate data to ACC
Add data memory to ACC with carry
Add ACC to register with carry
Subtract immediate data from ACC
Subtract data memory from ACC
Subtract data memory from ACC with result in
data memory
Subtract data memory from ACC with carry
Subtract data memory from ACC with carry with
result in data memory
Decimal adjust ACC for addition with result in
data memory
Logic Operation
AND A,[m]
OR A,[m]
XOR A,[m]
ANDM A,[m]
ORM A,[m]
XORM A,[m]
AND A,x
OR A,x
XOR A,x
CPL [m]
CPLA [m]
AND data memory to ACC
OR data memory to ACC
Exclusive-OR data memory to ACC
AND ACC to data memory
OR ACC to data memory
Exclusive-OR ACC to data memory
AND immediate data to ACC
OR immediate data to ACC
Exclusive-OR immediate data to ACC
Complement data memory
Complement data memory with result in ACC
Increment and Decrement
INCA [m]
INC [m]
DECA [m]
DEC [m]
Increment data memory with result in ACC
Increment data memory
Decrement data memory with result in ACC
Decrement data memory
28
July 24, 2000
Preliminary
Mnemonic
HTG2150
Instruction
Cycle
Flag
Affected
1
1(1)
1
None
None
C
1(1)
1
1(1)
1
C
None
None
C
1(1)
C
Move data memory to ACC
Move ACC to data memory
Move immediate data to ACC
1
1(1)
1
None
None
None
Clear bit of data memory
Set bit of data memory
1(1)
1(1)
None
None
Jump unconditional
Skip if data memory is zero
Skip if data memory is zero with data movement
to ACC
Skip if bit i of data memory is zero
Skip if bit i of data memory is not zero
Skip if increment data memory is zero
Skip if decrement data memory is zero
Skip if increment data memory is zero with
result in ACC
Skip if decrement data memory is zero with
result in ACC
Subroutine call
Return from subroutine
Return from subroutine and load immediate data
to ACC
Return from interrupt
2
1(2)
1(2)
None
None
None
1(2)
1(2)
1(3)
1(3)
1(2)
None
None
None
None
None
1(2)
None
2
2
2
None
None
None
2
None
Read ROM code (current page) to data memory and
TBLH
Read ROM code (last page) to data memory and
TBLH
2(1)
None
2(1)
None
Description
Rotate
RRA [m]
RR [m]
RRCA [m]
RRC [m]
RLA [m]
RL [m]
RLCA [m]
RLC [m]
Rotate data memory right with result in ACC
Rotate data memory right
Rotate data memory right through carry with
result in ACC
Rotate data memory right through carry
Rotate data memory left with result in ACC
Rotate data memory left
Rotate data memory left through carry with
result in ACC
Rotate data memory left through carry
Data Move
MOV A,[m]
MOV [m],A
MOV A,x
Bit Operation
CLR [m].i
SET [m].i
Branch
JMP addr
SZ [m]
SZA [m]
SZ [m].i
SNZ [m].i
SIZ [m]
SDZ [m]
SIZA [m]
SDZA [m]
CALL addr
RET
RET A,x
RETI
Table Read
TABRDC [m]
TABRDL [m]
29
July 24, 2000
Preliminary
HTG2150
Description
Instruction
Cycle
Flag
Affected
No operation
Clear data memory
Set data memory
Clear Watchdog Timer
Pre-clear Watchdog Timer
Pre-clear Watchdog Timer
Swap nibbles of data memory
Swap nibbles of data memory with result in ACC
Enter power down mode
1
1(1)
1(1)
1
1
1
1(1)
1
1
None
None
None
TO,PD
TO*,PD*
TO*,PD*
None
None
TO,PD
Mnemonic
Miscellaneous
NOP
CLR [m]
SET [m]
CLR WDT
CLR WDT1
CLR WDT2
SWAP [m]
SWAPA [m]
HALT
Note: x: 8 bits immediate data
m: 8 bits data memory address
A: accumulator
i: 0~7 number of bits
addr: 13 bits program memory address
Ö : Flag is affected
- : Flag is not affected
* : Flag may be affected by the execution status
(1)
(2)
: If a loading to the PCL register occurs, the execution cycle of instructions will be delayed
one for one more cycles (4 system clocks)
: If a skip to the next instruction occurs, the execution cycle of instructions will be delayed
one more cycle (4 system clocks). Otherwise the original instruction cycle(s) is unchanged.
(3) (1)
:
or
(2)
30
July 24, 2000
Preliminary
HTG2150
Instruction Definition
ADC A,[m]
Add data memory and carry to accumulator
Description
The contents of the specified data memory, accumulator and the carry flag
are added simultaneously, leaving the result in the accumulator.
Operation
ACC ¬ ACC+[m]+C
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
Ö
Ö
Ö
Ö
ADCM A,[m]
Add accumulator and carry to data memory
Description
The contents of the specified data memory, accumulator and the carry flag
are added simultaneously, leaving the result in the specified data memory.
Operation
[m] ¬ ACC+[m]+C
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
Ö
Ö
Ö
Ö
ADD A,[m]
Add data memory to accumulator
Description
The contents of the specified data memory and the accumulator are added.
The result is stored in the accumulator.
Operation
ACC ¬ ACC+[m]
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
Ö
Ö
Ö
Ö
ADD A,x
Add immediate data to accumulator
Description
The contents of the accumulator and the specified data are added, leaving
the result in the accumulator.
Operation
ACC ¬ ACC+x
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
Ö
Ö
Ö
Ö
31
July 24, 2000
Preliminary
HTG2150
ADDM A,[m]
Add accumulator to data memory
Description
The contents of the specified data memory and the accumulator are added.
The result is stored in the data memory.
Operation
[m] ¬ ACC+[m]
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
Ö
Ö
Ö
Ö
AND A,[m]
Logical AND accumulator with data memory
Description
Data in the accumulator and the specified data memory performs a bitwise
logical_AND operation. The result is stored in the accumulator.
Operation
ACC ¬ ACC ²AND² [m]
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
¾
¾
AND A,x
Logical AND immediate data to accumulator
Description
Data in the accumulator and the specified data performs a bitwise logical_AND operation. The result is stored in the accumulator.
Operation
ACC ¬ ACC ²AND² x
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
¾
¾
ANDM A,[m]
Logical AND data memory with accumulator
Description
Data in the specified data memory and the accumulator performs a bitwise
logical_AND operation. The result is stored in the data memory.
Operation
[m] ¬ ACC ²AND² [m]
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
¾
¾
32
July 24, 2000
Preliminary
HTG2150
CALL addr
Subroutine call
Description
The instruction unconditionally calls a subroutine located at the indicated
address. The program counter increments once to obtain the address of the
next instruction, and pushes this onto the stack. The indicated address is
then loaded. Program execution continues with the instruction at this address.
Operation
Stack ¬ PC+1
PC ¬ addr
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
CLR [m]
Clear data memory
Description
The contents of the specified data memory are cleared to zero.
Operation
[m] ¬ 00H
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
CLR [m].i
Clear bit of data memory
Description
The bit i of the specified data memory is cleared to zero.
Operation
[m].i ¬ 0
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
CLR WDT
Clear Watchdog Timer
Description
The WDT and the WDT Prescaler are cleared (re-counting from zero). The
power down bit (PD) and time-out bit (TO) are cleared.
Operation
WDT and WDT Prescaler ¬ 00H
PD and TO ¬ 0
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
0
0
¾
¾
¾
¾
33
July 24, 2000
Preliminary
HTG2150
CLR WDT1
Preclear Watchdog Timer
Description
The PD, TO flags, WDT and the WDT Prescaler are cleared (re-counting
from zero), if the other preclear WDT instruction had been executed. Execution of this instruction without the other preclear instruction only sets the
indicating flag which implies that this instruction was executed and the PD
and TO flags remain unchanged.
Operation
WDT and WDT Prescaler ¬ 00H*
PD and TO ¬ 0*
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
0*
0*
¾
¾
¾
¾
CLR WDT2
Preclear Watchdog Timer
Description
The PD, TO flags, WDT and the WDT Prescaler are cleared (re-counting
from zero), if the other preclear WDT instruction had been executed. Execution of this instruction without the other preclear instruction, only sets the
indicating flag which implies that this instruction was executed and the PD
and TO flags remain unchanged.
Operation
WDT and WDT Prescaler ¬ 00H*
PD and TO ¬ 0*
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
0*
0*
¾
¾
¾
¾
CPL [m]
Complement data memory
Description
Each bit of the specified data memory is logically complemented (1¢s complement). Bits which previously contain a one are changed to zero and
vice-versa.
Operation
[m] ¬ [m]
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
¾
¾
34
July 24, 2000
Preliminary
HTG2150
CPLA [m]
Complement data memory and place result in accumulator
Description
Each bit of the specified data memory is logically complemented (1¢s complement). Bits which previously contained a one are changed to zero and
vice-versa. The complemented result is stored in the accumulator and the
contents of the data memory remains unchanged.
Operation
ACC ¬ [m]
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
¾
¾
DAA [m]
Decimal-Adjust accumulator for addition
Description
The accumulator value is adjusted to the BCD (Binary Code Decimal) code.
The accumulator is divided into two nibbles. Each nibble is adjusted to the
BCD code and an internal carry (AC1) will be done if the low nibble of the accumulator is greater than 9. The BCD adjustment is done by adding 6 to the
original value if the original value is greater than 9 or a carry (AC or C) is set;
otherwise the original value remains unchanged. The result is stored in the
data memory and only the carry flag (C) may be affected.
Operation
If (ACC.3~ACC.0) >9 or AC=1
then ([m].3~[m].0) ¬ (ACC.3~ACC.0)+6, AC1=AC
else ([m].3~[m].0) ¬ (ACC.3~ACC.0), AC1=0
and
If (ACC.7~ACC.4)+AC1 >9 or C=1
then ([m].7~[m].4) ¬ (ACC.7~ACC.4)+6+AC1, C=1
else ([m].7~[m].4) ¬ (ACC.7~ACC.4)+AC1, C=C
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
Ö
DEC [m]
Decrement data memory
Description
Data in the specified data memory is decremented by one.
Operation
[m] ¬ [m] -1
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
¾
¾
35
July 24, 2000
Preliminary
HTG2150
DECA [m]
Decrement data memory and place result in accumulator
Description
Data in the specified data memory is decremented by one, leaving the result
in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC ¬ [m]-1
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
¾
¾
HALT
Enter power down mode
Description
This instruction stops the program execution and turns off the system clock.
The contents of the RAM and registers are retained. The WDT and prescaler
are cleared. The power down bit (PD) is set and the WDT time-out bit (TO) is
cleared.
Operation
PC ¬ PC+1
PD ¬ 1
TO ¬ 0
Affected flag(s)
INC [m]
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
0
1
¾
¾
¾
¾
Increment data memory
Description
Data in the specified data memory is incremented by one.
Operation
[m] ¬ [m]+1
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
¾
¾
INCA [m]
Increment data memory and place result in accumulator
Description
Data in the specified data memory is incremented by one, leaving the result
in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC ¬ [m]+1
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
¾
¾
36
July 24, 2000
Preliminary
HTG2150
JMP addr
Direct Jump
Description
Bits 0~12 of the program counter are replaced with the directly-specified address unconditionally, and control is passed to this destination.
Operation
PC ¬ addr
Affected flag(s)
MOV A,[m]
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
Move data memory to accumulator
Description
The contents of the specified data memory is copied to the accumulator.
Operation
ACC ¬ [m]
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
MOV A,x
Move immediate data to accumulator
Description
The 8-bit data specified by the code is loaded into the accumulator.
Operation
ACC ¬ x
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
MOV [m],A
Move accumulator to data memory
Description
The contents of the accumulator is copied to the specified data memory (one
of the data memory).
Operation
[m] ¬ ACC
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
37
July 24, 2000
Preliminary
HTG2150
NOP
No operation
Description
No operation is performed. Execution continues with the next instruction.
Operation
PC ¬ PC+1
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
OR A,[m]
Logical OR accumulator with data memory
Description
Data in the accumulator and the specified data memory (one of the data
memories) performs a bitwise logical_OR operation. The result is stored in
the accumulator.
Operation
ACC ¬ ACC ²OR² [m]
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
¾
¾
OR A,x
Logical OR immediate data to accumulator
Description
Data in the accumulator and the specified data performs a bitwise logical_OR operation. The result is stored in the accumulator.
Operation
ACC ¬ ACC ²OR² x
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
¾
¾
ORM A,[m]
Logical OR data memory with accumulator
Description
Data in the data memory (one of the data memories) and the accumulator
performs a bitwise logical_OR operation. The result is stored in the data
memory.
Operation
[m] ¬ ACC ²OR² [m]
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
¾
¾
38
July 24, 2000
Preliminary
HTG2150
RET
Return from subroutine
Description
Theprogramcounterisrestoredfromthestack.Thisisatwo-cycleinstruction.
Operation
PC ¬ Stack
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
RET A,x
Return and place immediate data in accumulator
Description
The program counter is restored from the stack and the accumulator loaded
with the specified 8-bit immediate data.
Operation
PC ¬ Stack
ACC ¬ x
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
RETI
Return from interrupt
Description
The program counter is restored from the stack, and interrupts are enabled
by setting the EMI bit. EMI is the enable master (global) interrupt bit (bit 0;
register INTC).
Operation
PC ¬ Stack
EMI ¬ 1
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
RL [m]
Rotate data memory left
Description
The contents of the specified data memory is rotated one bit left, with bit 7
rotated into bit 0.
Operation
[m].(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0-6)
[m].0 ¬ [m].7
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
39
July 24, 2000
Preliminary
HTG2150
RLA [m]
Rotate data memory left and place result in accumulator
Description
Data in the specified data memory is rotated one bit left, with bit 7 rotated
into bit 0, leaving the rotated result in the accumulator. The contents of the
data memory remain unchanged.
Operation
ACC.(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0-6)
ACC.0 ¬ [m].7
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
RLC [m]
Rotate data memory left through carry
Description
The contents of the specified data memory and the carry flag are together rotated one bit left. Bit 7 replaces the carry bit; the original carry flag is rotated into the bit 0 position.
Operation
[m].(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0-6)
[m].0 ¬ C
C ¬ [m].7
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
Ö
RLCA [m]
Rotate left through carry and place result in accumulator
Description
Data in the specified data memory and the carry flag are together rotated
one bit left. Bit 7 replaces the carry bit and the original carry flag is rotated
into bit 0 position. The rotated result is stored in the accumulator but the
contents of the data memory remain unchanged.
Operation
ACC.(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0-6)
ACC.0 ¬ C
C ¬ [m].7
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
Ö
40
July 24, 2000
Preliminary
HTG2150
RR [m]
Rotate data memory right
Description
The contents of the specified data memory are rotated one bit right with bit 0
rotated to bit 7.
Operation
[m].i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0-6)
[m].7 ¬ [m].0
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
RRA [m]
Rotate right and place result in accumulator
Description
Data in the specified data memory is rotated one bit right with bit 0 rotated
into bit 7, leaving the rotated result in the accumulator. The contents of the
data memory remain unchanged.
Operation
ACC.(i) ¬ [m].(i+1); [m].i:bit i of the data memory (i=0-6)
ACC.7 ¬ [m].0
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
RRC [m]
Rotate data memory right through carry
Description
The contents of the specified data memory and the carry flag are together rotated one bit right. Bit 0 replaces the carry bit; the original carry flag is rotated into the bit 7 position.
Operation
[m].i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0-6)
[m].7 ¬ C
C ¬ [m].0
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
Ö
41
July 24, 2000
Preliminary
HTG2150
RRCA [m]
Rotate right through carry and place result in accumulator
Description
Data of the specified data memory and the carry flag are together rotated
one bit right. Bit 0 replaces the carry bit and the original carry flag is rotated
into the bit 7 position. The rotated result is stored in the accumulator. The
contents of the data memory remain unchanged.
Operation
ACC.i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0-6)
ACC.7 ¬ C
C ¬ [m].0
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
Ö
SBC A,[m]
Subtract data memory and carry from accumulator
Description
The contents of the specified data memory and the complement of the carry
flag are together subtracted from the accumulator, leaving the result in the
accumulator.
Operation
ACC ¬ ACC+[m]+C
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
Ö
Ö
Ö
Ö
SBCM A,[m]
Subtract data memory and carry from accumulator
Description
The contents of the specified data memory and the complement of the carry
flag are together subtracted from the accumulator, leaving the result in the
data memory.
Operation
[m] ¬ ACC+[m]+C
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
Ö
Ö
Ö
Ö
42
July 24, 2000
Preliminary
HTG2150
SDZ [m]
Skip if decrement data memory is zero
Description
The contents of the specified data memory are decremented by one. If the result is zero, the next instruction is skipped. If the result is zero, the following
instruction, fetched during the current instruction execution, is discarded
and a dummy cycle is replaced to get the proper instruction. This makes a
two-cycle instruction. Otherwise proceed with the next instruction.
Operation
Skip if ([m]-1)=0, [m] ¬ ([m]-1)
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
SDZA [m]
Decrement data memory and place result in ACC, skip if zero
Description
The contents of the specified data memory are decremented by one. If the result is zero, the next instruction is skipped. The result is stored in the accumulator but the data memory remains unchanged. If the result is zero, the
following instruction, fetched during the current instruction execution, is
discarded and a dummy cycle is replaced to get the proper instruction, that
makes a two-cycle instruction. Otherwise proceed with the next instruction.
Operation
Skip if ([m]-1)=0, ACC ¬ ([m]-1)
Affected flag(s)
SET [m]
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
Set data memory
Description
Each bit of the specified data memory is set to one.
Operation
[m] ¬ FFH
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
43
July 24, 2000
Preliminary
HTG2150
SET [m].i
Set bit of data memory
Description
Bit i of the specified data memory is set to one.
Operation
[m].i ¬ 1
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
SIZ [m]
Skip if increment data memory is zero
Description
The contents of the specified data memory is incremented by one. If the result is zero, the following instruction, fetched during the current instruction
execution, is discarded and a dummy cycle is replaced to get the proper instruction. This is a two-cycle instruction. Otherwise proceed with the next
instruction.
Operation
Skip if ([m]+1)=0, [m] ¬ ([m]+1)
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
SIZA [m]
Increment data memory and place result in ACC, skip if zero
Description
The contents of the specified data memory is incremented by one. If the result is zero, the next instruction is skipped and the result is stored in the accumulator. The data memory remains unchanged. If the result is zero, the
following instruction, fetched during the current instruction execution, is
discarded and a dummy cycle is replaced to get the proper instruction. This
is a two-cycle instruction. Otherwise proceed with the next instruction.
Operation
Skip if ([m]+1)=0, ACC ¬ ([m]+1)
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
44
July 24, 2000
Preliminary
HTG2150
SNZ [m].i
Skip if bit i of the data memory is not zero
Description
If bit i of the specified data memory is not zero, the next instruction is
skipped. If bit i of the data memory is not zero, the following instruction,
fetched during the current instruction execution, is discarded and a dummy
cycle is replaced to get the proper instruction. This is a two-cycle instruction.
Otherwise proceed with the next instruction.
Operation
Skip if [m].i¹0
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
SUB A,[m]
Subtract data memory from accumulator
Description
The specified data memory is subtracted from the contents of the accumulator, leaving the result in the accumulator.
Operation
ACC ¬ ACC+[m]+1
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
Ö
Ö
Ö
Ö
SUBM A,[m]
Subtract data memory from accumulator
Description
The specified data memory is subtracted from the contents of the accumulator, leaving the result in the data memory.
Operation
[m] ¬ ACC [m]+1
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
Ö
Ö
Ö
Ö
SUB A,x
Subtract immediate data from accumulator
Description
The immediate data specified by the code is subtracted from the contents of
the accumulator, leaving the result in the accumulator.
Operation
ACC ¬ ACC+x+1
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
Ö
Ö
Ö
Ö
45
July 24, 2000
Preliminary
HTG2150
SWAP [m]
Swap nibbles within the data memory
Description
The low-order and high-order nibbles of the specified data memory (one of
the data memories) are interchanged.
Operation
[m].3~[m].0 « [m].7~[m].4
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
SWAPA [m]
Swap data memory and place result in accumulator
Description
The low-order and high-order nibbles of the specified data memory are interchanged, writing the result to the accumulator. The contents of the data
memory remain unchanged.
Operation
ACC.3~ACC.0 ¬ [m].7~[m].4
ACC.7~ACC.4 ¬ [m].3~[m].0
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
SZ [m]
Skip if data memory is zero
Description
If the contents of the specified data memory is zero, the following instruction, fetched during the current instruction execution, is discarded and a
dummy cycle is replaced to get the proper instruction. This is a two-cycle instruction. Otherwise proceed with the next instruction.
Operation
Skip if [m]=0
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
46
July 24, 2000
Preliminary
HTG2150
SZA [m]
Move data memory to ACC, skip if zero
Description
The contents of the specified data memory is copied to the accumulator. If the
contents is zero, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the
proper instruction. This is a two-cycle instruction. Otherwise proceed with
the next instruction.
Operation
Skip if [m]=0
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
SZ [m].i
Skip if bit i of the data memory is zero
Description
If bit i of the specified data memory is zero, the following instruction, fetched
during the current instruction execution, is discarded and a dummy cycle is
replaced to get the proper instruction. This is a two-cycle instruction. Otherwise proceed with the next instruction.
Operation
Skip if [m].i=0
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
TABRDC [m]
Move ROM code (current page) to TBLH and data memory
Description
The ROM code low byte (current page) addressed by the table pointer
(TBLP), (TBHP) is moved to the specified data memory and the high byte
transferred to TBLH directly.
Operation
[m] ¬ ROM code (low byte)
TBLH ¬ ROM code (high byte)
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
47
July 24, 2000
Preliminary
HTG2150
TABRDL [m]
Move the ROM code (last page) to TBLH and data memory
Description
The ROM code low byte (last page) addressed by the table pointer (TBLP) is
moved to the data memory and the high byte transferred to TBLH directly.
Operation
[m] ¬ ROM code (low byte)
TBLH ¬ ROM code (high byte)
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
XOR A,[m]
Logical XOR accumulator with data memory
Description
Data in the accumulator and the indicated data memory performs a bitwise
logical Exclusive_OR operation and the result is stored in the accumulator.
Operation
ACC ¬ ACC ²XOR² [m]
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
¾
¾
XORM A,[m]
Logical XOR data memory with accumulator
Description
Data in the indicated data memory and the accumulator perform a bitwise
logical Exclusive_OR operation. The result is stored in the data memory. The
zero flag is affected.
Operation
[m] ¬ ACC ²XOR² [m]
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
¾
¾
XOR A,x
Logical XOR immediate data to accumulator
Description
Data in the the accumulator and the specified data perform a bitwise logical
Exclusive_OR operation. The result is stored in the accumulator. The zero
flag is affected.
Operation
ACC ¬ ACC ²XOR² x
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
¾
¾
48
July 24, 2000
Preliminary
HTG2150
Holtek Semiconductor Inc. (Headquarters)
No.3 Creation Rd. II, Science-based Industrial Park, Hsinchu, Taiwan, R.O.C.
Tel: 886-3-563-1999
Fax: 886-3-563-1189
Holtek Semiconductor Inc. (Taipei Office)
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Tel: 886-2-2782-9635
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RM.711, Tower 2, Cheung Sha Wan Plaza, 833 Cheung Sha Wan Rd., Kowloon, Hong Kong
Tel: 852-2-745-8288
Fax: 852-2-742-8657
Copyright Ó 2000 by HOLTEK SEMICONDUCTOR INC.
The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek
assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are
used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications
will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holtek reserves the right to alter its products without prior
notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw.
49
July 24, 2000