SANYO LV8415CB

Ordering number : ENA1787A
Bi-CMOS integrated circuit
LV8415CB
Blurring correction driver IC for DSC
H bridge × 2ch driver
Overview
LV8415CB is blurring correction driver IC for DSC.
Functions
• Actuator driver (saturation drive H bridge) × 2ch
• Constant current hall bias circuit × 2ch
• With built-in for PWM signal generation logic circuit × 2ch
• 8bitDAC for hall amplifier offset adjustment × 2ch
• Two systems in power supply (VM: for actuator, VCC)
• With built-in low voltage malfunction prevention circuit
• Hall Amplifier × 2ch
• General-purpose amplifier × 2ch
• 8bitDAC for hall bias × 2ch
• Three line serial input
• With built-in thermal protection circuit
Specifications
Maximum Ratings at Ta = 25°C
Parameter
Symbol
Conditions
Ratings
Unit
Supply voltage 1
VM max
6
V
Supply voltage 2
VCC max
6
V
Output peak current
IO peak
OUT1 to 2 (t ≤ 10msec, duty ≤ 20%)
600
mA
Output current
IO max
OUT1 to 2
350
mA
Hall bias current
IHB max
5
mA
Allowable power dissipation
Pd max
Operating temperature
Storage temperature
On a specified board *
1
W
Topr
-20 to +85
°C
Tstg
-55 to +150
°C
* Specified board: 40.0mm×50.0mm×0.8mm, Four layers fiberglass epoxy circuit board.
Allowable Operating Ratings at Ta = 25°C
Parameter
Symbol
Conditions
Ratings
Unit
Supply voltage range 1
VM
2.7 to 5.5
Supply voltage range 2
VCC
2.7 to 5.5
V
V
Logic input voltage
VIN
0 to VCC+0.3
V
Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to
"standard application", intended for the use as general electronics equipment (home appliances, AV equipment,
communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be
intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace
instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety
equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case
of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee
thereof. If you should intend to use our products for applications outside the standard applications of our
customer who is considering such use and/or outside the scope of our intended standard applications, please
consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our
customer shall be solely responsible for the use.
Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate
the performance, characteristics, and functions of the described products in the independent state, and are not
guarantees of the performance, characteristics, and functions of the described products as mounted in the
customer' s products or equipment. To verify symptoms and states that cannot be evaluated in an independent
device, the customer should always evaluate and test devices mounted in the customer' s products or
equipment.
D2210 SY/82510 SY 20100818-S00003 No.A1787-1/12
LV8415CB
Electrical Characteristics at Ta = 25°C, VCC = 3.3V, VM = 5.0V
Parameter
Symbol
Ratings
Conditions
min
Current consumption when
ICCO
ST = ”L”
VM current consumption
IM
VM = 5.0V, ST = ”H”, no load
VCC current consumption
ICC
ST = ”H”, no load
VCC low voltage cutting voltage
VTHVCC
Low voltage hysteresis voltage
VTHHYS
Thermal shutdown temperature
TSD
Design guarantee
Thermal hysteresis width
ΔTSD
Design guarantee
Ronu
Rond
typ
Unit
max
1.0
μA
standing by
10
μA
2
3.2
mA
2.1
2.4
2.6
V
100
150
200
mV
155
175
195
°C
15
35
55
°C
IO = 100mA, Upper-side on resistance
0.7
0.98
Ω
IO = 100mA, Under-side on resistance
0.5
0.7
Ω
1
μA
ID = -100mA
0.7
H bridge output (OUT1-2)
Output on resistance
Output leakage current
IO leak
Diode forward voltage
VD
V
Operational amplifier (OP-AMP1-4)
Input offset voltage
OP_VIO
±1
±5
mV
Input offset current
OP_IIO
±5
±50
nA
Input bias current
OP_IB
30
250
nA
Equal phase input voltage range
VICM
0
Equal phase signal removal
CMR
60
80
dB
1
10
V/mV
VCC
V
ratio
Large amplitude voltage range
VG
RL = 20kΩ, VIN = 1mV(open loop gain)
Output voltage range
VOH
RL = 20kΩ
VOL
RL = 20kΩ
Power supply change removal
SVR
VCC-0.2
V
0.2
V
65
85
dB
1
2
mA
0.95
1.00
ratio
Output current (sink/source)
OP_IO
Hall bias (HB1-2)
Output current
IHB
RHG = 1kΩ, VHBIN = 1.0V
Output saturation voltage
VSATHB
IHB = 1mA
1.05
VCC-0.2
mA
V
Standard voltage
Standard voltage
VREF
Standard voltage load
VRref
IREF = 100μA
1.60
1.65
1.70
V
1.60
1.65
1.70
V
13.5
15
17.25
MHz
50
100
200
kΩ
1.0
μA
50
μA
1.0
V
characteristic
Internal CLK frequency for PWM drive
CLK frequency
Fclk
Control pin (ST, SCLK, DATA, STB)
Built-in pull-down resistance
Rin
Input current
IINL
VIN = 0V
IINH
VIN = 3.3V
Input “L” level voltage
VINL
Input “H” level voltage
VINH
20
2.5
33
V
No.A1787-2/12
LV8415CB
Package Dimensions
unit : mm (typ)
3397
0.235
0.4
F
E
D
2.47
0.4
C
B
A
2.47
6
4
3
2
1
0.245
0.69 MAX
SIDE VIEW
5
Pd max - Ta
1.2
BOTTOM VIEW
Allowable power dissipation, Pd max -- W
SIDE VIEW
0.235
TOP VIEW
Specified circuit board:
40.0 × 50.0 × 0.8mm3
Four layer glass epoxy board
1.0
0.8
0.6
0.52
0.4
0.2
0
-30
0
30
60
90
0.175
Ambient temperature, Ta -- C
SANYO : WLP32(2.47X2.47)
Pin Assignment
OUT
2A
OUT
2B
(NC_
TEST)
DATA
STB
VREF
VIN
+3
VIN
+4
SGND
VIN
-3
VIN
-4
HB2
F
OUT
1A
OUT
1B
PGND
E
VM
ST
SCLK
D
VCC
C
HB1
(NC_TEST) is pin only for the test.
Please NC_TESTpin connect GND
line.
Power supply pin
GND pin
B
HGND1
VOUT
3
VOUT
1
VOUT
2
VOUT
4
HGND2
Output pin
Logic control pin
A
VIN
+1
VIN
-1A
VIN
-1B
VIN
-2B
VIN
-2A
VIN
+2
1
2
3
4
5
6
Analog control pin
Ball side view
No.A1787-3/12
120
LV8415CB
Pin function
Pin No.
E2
E3
E4
E5
Pin name
ST
SCLK
DATA
STB
Pin function
Input pin.
High level 2V to (VCC = 3.3V)
Low level 0 to 0.5V (VCC = 3.3V)
Equivalent Circuit
VCC
IN
GND
F1
F2
F4
F5
E1
F3
OUT1A
OUT1B
OUT2A
OUT2B
VM
PGND
Output pin. (PWM output)
VM : POWER – Power supply pin.
PGND : POWER – GND pin.
VM
OT
OT
PG
D1
D6
C1
B1
C6
B6
VCC
SGND
HB1
HGND1
HB2
HGND2
Signal system power supply pin
Signal system GND pin
HB1, 2 pin
Hall bias source pin
HGND1, 2 pin
Hall bias current setting pin
VCC
IN
HB
HGND
GND
A1
A2
A3
A6
A5
A4
VIN+1
VIN-1A
VIN-1B
VIN+2
VIN-2A
VIN-2B
Hall amplifier input pin
VIN+ Hall amplifier+ input pin
VIN-A Hall amplifier- input pin
VIN-B LPF formation pin
(The filter is formed for the noise removal.)
VCC
INB
INA
IN+
GND
B3
B4
VOUT1
VOUT2
Hall amplifier output pin.
VOUT1 : Hall amplifier 1ch output pin.
VOUT2 : Hall amplifier 2ch output pin.
V
CC
OT
GND
Continued on next page.
No.A1787-4/12
LV8415CB
Continued from preceding page.
Pin No.
D2
C2
D5
C5
Pin name
VIN+3
VIN-3
VIN+4
VIN+4
Pin function
General purpose amplifier input pin.
VIN+3 : 3ch general purpose amplifier+ input pin
VIN-3 : 3ch general purpose amplifier- input pin
VIN+4 : 4ch general purpose amplifier+ input pin
VIN-4 : 4ch general purpose amplifier- input pin
Equivalent Circuit
VCC
IN-
IN+
GND
B2
B5
VOUT3
VOUT4
General purpose amplifier output pin.
VOUT3 : 3ch general purpose amplifier output pin
VOUT4 : 4ch general purpose amplifier output pin
V
CC
OT
GND
E6
VREF
Internal standard voltage pin
VCC/2 output
VCC
VREF
GND
F6
NC-TEST
N.C. pin
TEST pin
Please NC_TEST pin connect GND line.
VCC
NC
GND
No.A1787-5/12
LV8415CB
Block Diagram
VM
VCC
VCC low voltage
cutting circuit
Overheating
protection circuit
OUT1A
bitPWM
10
generation logic
Logic circuit
H bridge circuit
OUT1B
Oscillation
circuit
OUT2A
10 to 12bitPWM
generation logic
SCLK
DATA
Sirial
/pararel
Logic circuit
H bridge circuit
OUT2B
STB
PGND
Standard voltage
8bit DAC
8bit DAC
8bit DAC
+
+
+
+
+
+
+
-
-
-
-
-
-
-
ST
VOUT4
VIN-4
VIN+4
VOUT3
VIN-3
VIN+3
VOUT2
VIN+2
VIN-2B
VIN-2A
HB2
VOUT1
HGND2
VIN-1B
VIN-1A
HB1
VIN+1
VREF
HGND1
PGND
H
H
Setpoint signal
(3 line sirial)
8bit DAC
Hall Out
(Yaw)
Logic-Chip
Hall Out
(Pitch)
No.A1787-6/12
LV8415CB
3 line serial communication electrical Characteristics at Ta = 25°C, VCC = 3.3V, VM = 5.0V
Parameter
Symbol
Ratings
Conditions
min
Unit
typ
max
Serial data forwarding pin
Logic pin input current
IINL
VIN=0V(SCLK, DATA, STB)
IINH
VIN=3.3V(SCLK, DATA, STB)
33
1.0
μA
50
V
1.0
μs
Input “H” level voltage
VINH
SCLK, DATA, STB
Input “L” level voltage
VINL
SCLK, DATA, STB
2.5
V
Minimum SCLK “H” pulse width
TSCH
0.1
Minimum SCLK “L” pulse width
TSCL
0.1
μs
STB regulation time
Tlat
0.1
μs
Minimum STB pulse width
Tlatw
0.1
μs
Data set-up time
Tds
0.1
μs
Data hold time
Tdh
0.1
μs
maximum CLK frequency
Fclk
μs
4
Fclk
TSCH
MHz
TSCL
SCLK
Tds
DATA
A0
Tdh
A1
D10
A2
D11
Tlat
STB
Tlatw
Serial data timing condition
Serial data input timing chart
ST
DATA
A0
A1
A2
A3
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
SCLK
STB
The latch does the
state setting data
It inputs it from A0 in order of D11. The data transfer is done by the rising edge, and after all data transfers, the latch
does all data to SCLK by the STB signal standing up. The STB signal accepts and the internal logic of IC doesn't accept
the SCLK signal during "H".
No.A1787-7/12
LV8415CB
Serial logic map
PWMh - bridge relation serial map
A0
0
1
0
1
0
1
A1
0
0
1
1
0
0
A2
0
0
0
0
1
1
A3
0
0
0
0
0
0
D0
*
*
*
D1
*
*
*
D2
0
1
0
D3
0
0
1
*
*
*
*
0
1
1
1
*
*
0
*
*
*
*
*
*
*
*
*
*
Input
D4
0
0
0
D5
0
0
0
D6
0
0
0
D7
0
0
0
D8
0
0
0
D9
0
0
0
D10
0
0
0
D11
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
*
*
*
*
*
*
1
0
1
0
1
0
0
1
1
0
0
1
1
1
1
0
0
0
1
1
1
0
0
0
1
1
1
0
0
0
1
1
1
0
0
0
1
1
1
0
0
0
1
1
1
0
0
0
1
1
1
0
0
0
1
1
1
0
0
0
*
*
*
*
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
*
*
0
0
0
0
0
0
0
0
0
1
*
*
*
*
1
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
*
*
*
0
1
0
*
*
*
0
0
1
1
0
1
0
0
0
0
1
1
0
0
0
1
1
1
0
0
0
1
1
1
0
0
0
1
1
1
0
0
0
1
1
1
0
0
0
1
0
1
0
1
0
0
1
1
0
0
1
1
1
1
0
0
0
1
1
1
0
0
0
1
1
1
0
0
0
1
1
1
0
0
0
1
1
1
0
0
0
1
1
1
0
0
0
1
0
1
0
1
0
0
1
1
0
0
1
1
1
1
0
0
0
1
1
1
0
0
0
1
1
1
0
0
0
1
1
1
0
0
0
1
1
1
0
0
0
1
1
1
0
0
0
1
0
1
0
1
0
0
1
1
0
0
1
1
1
1
0
0
0
1
1
1
0
0
0
1
1
1
0
0
0
1
1
1
0
0
0
1
1
1
0
0
0
1
1
1
0
0
0
1
0
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
1
1
1
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
1
1
1
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
1
1
1
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
Setting mode
1ch PWM Duty set
Set content
Remarks
100%
511/512 × 100%
510/512 × 100%
…
2/512 × 100%
1/512 × 100%
Reverse
0%
Middle
point
1/512 × 100%
2/512 × 100%
…
509/512 × 100%
510/512 × 100%
511/512 × 100%
100%
511/512 × 100%
510/512 × 100%
…
2/512 × 100%
1/512 × 100%
2ch PWM Duty set
1ch hall bias set
(8bit DAC)
2ch hall bias set
(8bit DAC)
1ch hall amplifier
offset adjustment
(8bit DAC)
2ch hall amplifier
offset adjustment
(8bit DAC)
Normal
rotation
Reverse
Middle
point
0%
1/512 × 100%
2/512 × 100%
…
509/512 × 100%
510/512 × 100%
511/512 × 100%
0V
1/255 × VREF
2/255 × VREF
…
253/255 × VREF
254/255 × VREF
VREF
0V
1/255 × VREF
2/255 × VREF
…
253/255 × VREF
254/255 × VREF
VREF
0V
1/255 × VCC
2/255 × VCC
…
253/255 × VCC
254/255 × VCC
VCC
0V
1/255 × VCC
2/255 × VCC
…
253/255 × VCC
254/255 × VCC
VCC
Normal
rotation
The PWMh-bridge driver's ON/OFF operation is done with the ST pin.
No.A1787-8/12
LV8415CB
Hall amplifier gain setting range
Hall amplifier relation serial map
Input
A0
0
A1
0
A2
0
A3
1
1
0
0
1
0
1
0
1
1
1
0
1
D0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
D1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
D2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
D3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Setting mode
1ch hall amplifier gain setting
( “3” Resistance ÷ “2”
Resistance)
2ch hall amplifier gain setting
( “3” Resistance ÷ “2”
Resistance)
1ch hall amplifier offset
resistance / input resistance
( “1” Resistance ÷ “2”
Resistance)
2ch hall amplifier offset
resistance / input resistance
( “1” Resistance ÷ “2”
Resistance)
Hall amplifier magnification
()Inside: Resistance
10 (36k//3.6k)
20 (72k//3.6k)
40 (144k//3.6k)
50 (180k//3.6k)
60 (216k//3.6k)
70 (252k//3.6k)
90 (324k//3.6k)
100 (360k//3.6k)
110 (396k//3.6k)
120 (432k//3.6K)
140 (504k//3.6k)
150 (540k//3.6k)
160 (570k//3.6k)
170 (612k//3.6k)
190 (684k//3.6k)
200 (720k//3.6k)
10 (36k//3.6k)
20 (72k//3.6k)
40 (144k//3.6k)
50 (180k//3.6k)
60 (216k//3.6k)
70 (252k//3.6k)
90 (324k//3.6k)
100 (360k//3.6k)
110 (396k//3.6k)
120 (432k//3.6K)
140 (504k//3.6k)
150 (540k//3.6k)
160 (570k//3.6k)
170 (612k//3.6k)
190 (684k//3.6k)
200 (720k//3.6k)
10 (36k//3.6k)
20 (72k//3.6k)
40 (144k//3.6k)
50 (180k//3.6k)
60 (216k//3.6k)
70 (252k//3.6k)
90 (324k//3.6k)
100 (360k//3.6k)
110 (396k//3.6k)
120 (432k//3.6K)
140 (504k//3.6k)
150 (540k//3.6k)
160 (570k//3.6k)
170 (612k//3.6k)
190 (684k//3.6k)
200 (720k//3.6k)
10 (36k//3.6k)
20 (72k//3.6k)
40 (144k//3.6k)
50 (180k//3.6k)
60 (216k//3.6k)
70 (252k//3.6k)
90 (324k//3.6k)
100 (360k//3.6k)
110 (396k//3.6k)
120 (432k//3.6K)
140 (504k//3.6k)
150 (540k//3.6k)
160 (570k//3.6k)
170 (612k//3.6k)
190 (684k//3.6k)
200 (720k//3.6k)
No.A1787-9/12
LV8415CB
General-purpose amplifier ON/OFF setting
Input
A0
0
A1
0
A2
1
A3
1
D0
0
1
*
*
D1
*
*
0
1
D0
0
0
1
*
D1
0
1
0
*
Setting mode
Set content
Remarks
General-purpose
amplifier 1
General-purpose
amplifier 2
Stand-by
Operate
Stand-by
Operate
Setting mode
Set content
Remarks
10bit resolution
11bit resolution
12bit resolution
-
Initial value
PWM accuracy setting
PWM circuit accuracy setting
Input
A0
1
A1
0
A2
1
A3
1
PWM pulse width of moving
1ch (X axis side)
A0
0
A1
1
A2
1
Input [3:0]
A3
D0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
D1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
D2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
D3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Input [7:4]
A3
D4
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
D5
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
D6
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
D7
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Setting mode
1ch (X axis) side width of
moving
Moving pulse
number
0 (Initialization)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Note : 1 pulse = 1CLK
2ch (Y axis side)
A0
0
A1
1
A2
1
Setting mode
2ch (Y axis) side width of
moving
Moving pulse
number
0 (Initialization)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Note : 1 pulse = 1CLK
The ON/OFF operation of the hall amplifier and the hall bias is done with the ST pin.
Note : An initial value of A0 to A3 = 1111 is a static test mode. Use it specifying data D0 for one.
TEST mode setting
Input
A2
1
Setting mode
Content
Remarks
D0
0
External CLK
It uses it by the shipment inspection.
NC pin _ TEST mode
1
Internal CLK
Internal CLK operation
Note : External CLK mode is for the shipment inspection. Use it with internal CLK. Use it after it internal CLK switches because default is external CLK mode.
A0
1
A1
1
A3
1
No.A1787-10/12
LV8415CB
Hall bias, Offset adjustment circuit configuration
Bias adjustment
Offset adjustment
8bit DAC
8bit DAC
1
+ -
2
+ -
2
3
H
Hall amplifier, Hall bias equivalent circuit
About the gain adjustment
The resistance ratio of “2” and “3” is adjusted in figure and the gain is set. Refer to the setting to the cereal map. The
magnification can be set from ten by 200.
About the Offset adjustment
The resistance ratio of “1” and “2” is adjusted in figure and the Offset is set. Refer to the setting to the cereal map.
The magnification can be set from ten by 200.
No.A1787-11/12
LV8415CB
Note in design
• Stand-by function
IC becomes a stand-by state at ST = “L”, and IC enters the state of operation at ST =”H”. Moreover, the register in IC
is reset as for ST = “L” at times.
• Hall bias
The constant current output is built into for the hall element drive. The constant current value is set from detection
resistance (RHG) connected from the HBIN pin impression voltage and the HGND pin between GND.
Constant current value (IO) = HBIN voltage ÷ Detection resistance
VCC
HBIN
+ -
HB
IO
H
HGND
Constant current value (IO) becomes about 1mA when assuming HBIN pin impressed voltage =1.0V and detection
resistance = 1 kΩ from the above-mentioned calculation type. Moreover, the HGND pin must connect with the HB
pin, and connect the detection resistance of a large value as much as possible when you do not use the hall bias
circuit.
• Operation amplifier
Impress the bias to the VIN+ pin, and compose the buffer by the connection to the VOUT pin in the VIN- pin in the
operational amplifier not used.
VCC
+ -
VIN+
VOUT
VIN-
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products described or contained herein.
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to smoke or fire, or accidents that could cause damage to other property. When designing equipment, adopt
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limited to protective circuits and error prevention circuits for safe design, redundant design, and structural
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Any and all information described or contained herein are subject to change without notice due to
product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the
SANYO Semiconductor Co.,Ltd. product that you intend to use.
Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed
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This catalog provides information as of December, 2010. Specifications and information herein are subject
to change without notice.
PS No.A1787-12/12