VISHAY TFDS6500E

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Semiconductors
TFDU6100E/TFDS6500E/TFDT6500E
2.7–5.5V Fast Infrared Transceiver Module Family
(FIR, 4 Mbit/s)
Features
Compliant to IrDA 1.2 (Up to
4 Mbit/s), HP–SIR, Sharp ASK
and TV Remote
Wide Operating Voltage Range
(2.7 to 5.5 V )
Low-Power Consumption (3 mA
Supply Current)
Power Shutdown Mode (1 A
Shutdown Current)
Long Range (Up to 2.0 m at
4 Mbit/s in Nominal Design)
High Efficiency Emitter
(120 mW/sr min 15)
Three Surface Mount Package
Options
– Universal (9.7 x 4.7 x 4.0 mm)
– Side View (13.0 x 5.95 x 5.3 mm)
– Top View (13.0 x 7.6 x 5.95 mm)
Applications
BabyFace (Universal) Package
Capable of Surface Mount
Solderability to Side and Top
View Orientation
Directly Interfaces With Various
Super I/O and Controller Devices
Built–In EMI Protection – No
External Shielding Necessary
Few External Components
Required
Backward Compatible to All
TEMIC SIR and FIR Infrared
Transceivers
Notebook Computers, Desktop
PCs, Palmtop Computers (Win
CE, Palm PC), PDAs
Digital Still and Video Cameras
Printers, Fax Machines,
Photocopiers, Screen Projectors
Telecommunication Products
(Cellular Phones, Pagers)
Internet TV Boxes, Video
Conferencing Systems
External Infrared Adapters
(Dongles)
Medical and Industrial Data
Collection Devices
Description
The TFDU6100E, TFDS6500E, and TFDT6500E are a
family of low-power infrared transceiver modules
compliant to the IrDA 1.2 standard for fast infrared (FIR)
data communication, supporting IrDA speeds up to 4.0
Mbit/s, HP–SIR, Sharp ASK and carrier based remote
control modes up to 2 MHz. Integrated within the
transceiver modules are a photo PIN diode, infrared
emitter (IRED), and a low-power CMOS control IC to
provide a total front–end solution in a single package.
TEMIC’s FIR transceivers are available in three package
options, including our BabyFace package (TFDU6100E),
the smallest FIR transceiver available on the market. This
wide selection provides flexibility for a variety of
applications and space constraints.
The transceivers are capable of directly interfacing with
a wide variety of I/O chips which perform the pulse-width
modulation/demodulation function, including National
Semiconductor’s PC87338, PC87108 and PC87109,
SMSC’s FDC37C669, FDC37N769 and CAM35C44,
and Hitachi’s SH3. At a minimum, a current-limiting
resistor in series with the infrared emitter and a VCC
bypass capacitor are the only external components
required to implement a complete solution.
Package Options
TFDU6100E
Baby Face (Universal)
TFDS6500E
Side View
TFDT6500E
Top View
This product is currently in devleopment. Inquiries regarding the status of this product should be directed to TEMIC Marketing.
Pending—Rev. A, 03-Apr-98
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TFDU6100E/TFDS6500E/TFDT6500E
Semiconductors
Functional Block Diagram
VCC
Driver
Amplifier
Rxd
Comparator
IRED Anode
AGC
Logic
SD/Mode
IRED Cathode
Txd
Open Collector Driver
GND
Pin Assignment and Description
Pin Number
“ U ”, “ T ”
Option
“S”
Option
Function
1
8
IRED Anode
2
1
IRED Cathode
3
7
Txd
4
2
Rxd
5
6
6
Description
I/O
Active
Transmit Data Input
I
HIGH
Received Data Output, push–pull CMOS driver output capable of driving a
standard CMOS or TTL load. No external pull–up or pull–down resistor is
required (pin is floating when device is in shutdown mode).
O
LOW
SD/Mode
Shutdown/Mode
I
HIGH
3
VCC
Supply Voltage
7
5
NC
Do not connect.
8
4
GND
IRED anode, should be externally connected to VCC through a current
control resistor
IRED cathode, internally connected to driver transistor
Ground
8
IRED
7
6
5
Detector
IRED
Detector
1 2 3 4 5 6 7 8
1
IRED
”U” Option
BabyFace (Universal)
2
3
4
Detector
”S” Option
Side View
2
1
2
3
4
5
6 7
8
”T” Option
Top View
Pending—Rev. A, 03-Apr-98
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Semiconductors
TFDU6100E/TFDS6500E/TFDT6500E
Ordering Information
Part Number
Qty/ Reel
Description
TFDU6100E–TR3
1000 pcs
Oriented in carrier tape for side view surface mounting
TFDU6100E–TT3
1000 pcs
Oriented in carrier tape for top view surface mounting
TFDS6500E–TR3
750 pcs
TFDT6500E–TR3
750 pcs
Absolute Maximum Ratings
Parameter
Supply Voltage Range
Supply Voltage Range (Anode)
Symbol
Test Conditionsa
Minb
Typc
Maxb
VCC
– 0.5
6
Vanode
0
VCC+1.5
Unit
V
Input Currentsd
10
Output Sinking Current
25
mA
Power Dissipatione
PD
350
Junction Temperature
TJ
125
Ambient Temperature Range (Operating)
Tamb
–25
85
Storage Temperature Range
Tstg
–25
85
Soldering Temperature
See Recommended Solder Profile
Average Output Current
IIRED (DC)
Repetitive Pulsed Output Current
IIRED (RP)
IRED Anode Voltage at Current Output
130
mA
<90 µs, ton <20%
600
– 0.5
6
Transmitter Data Input Voltage
VTxd
– 0.5
VCC+0.5
Receiver Data Output Voltage
VRxd
– 0.5
VCC+0.5
d
2.5
Virtual Source
Maximum Intensity for Class 1 Operation
of IEC 825 or EN60825g
°C
240
VIREDA
Sizef
mW
EN60825, 1997
2.8
V
mm
320
mW/sr
Notes
a. Reference point GND pin unless otherwise noted.
b. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum.
c. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
d. Maximum input current for all pins (except IRED Anode pin).
e. See Derating Curve.
f. Method: (1-1/e) encircled energy.
g. Worst case IrDA SIR pulse pattern.
Pending—Rev. A, 03-Apr-98
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Electrical Characteristics
Parameter
Symbol
Test Conditionsa
Minb
Typc
Maxb
Unit
5.5
V
Transceiver
Supply Voltage
VCC
Dynamic Supply Currentd
ICC
SD = Low, Ee = 0 mW/m2
2.7
3
4
Dynamic Supply Current
ICC
SD = Low, Ee = 1 klxd
3
4
Standby Supply Currente
ISD
SD = High, Mode = floating,
25°C, Ee = 0 klx
1
Standby Supply Current
ISD
SD = High, Mode = floating,
T =25°C, Ee = 1 klxd
1.5
Standby Supply Currente
ISD
SD = High, Mode = floating,
T = 85°C
5
Operating Temperature Range
TA
–25
85
Output Voltage Low
VOL
Rload = 2.2 kΩ, Cload = 15 pF
Output Voltage High
VOH
Rload = 2.2 kΩ, Cload = 15 pF
Input Voltage Low
VIL
0
Input Voltage
Highf
VIH
0.9 * VCC
Input Voltage
Highg
VIH
Input Leakage Current
IL
Input Capacitance
CI
0.5
mA
µA
°C
0.8
VCC–0.5
VCC ≥ 4.5V
0.8
V
+10
µA
5
pF
2.4
–10
Notes
a. Tamb = 25, VCC = 2.7 – 5.5 V unless otherwise noted.
b. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum.
c. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
d. Receive mode only. In transmit mode, add additional 100 mA (typ) to IRED current.
e. Not ambient light sensitive.
f. CMOS levels.
g. TTL levels.
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Semiconductors
TFDU6100E/TFDS6500E/TFDT6500E
Optoelectronic Characteristics
Parameter
Symbol
Test Conditionsa
Minb
Typc
Maxb
Unit
Receiver
Minimum Detection Threshold Irradiance
Ee
9.6 kbit/s to 115.2 kbit/s
20
35
Minimum Detection Threshold Irradiance
Ee
1.152 Mbit/s to 4 Mbit/s
50
80
Maximum Detection Threshold Irradiance
Ee
5
Logic LOW Receiver Input Irradiance
Ee
4
Rise Time of Output Signal
tRR
10% to 90%, @2.2 kΩ, 15pF
10
40
Fall Time of Output Signal
tFR
90% to 10%, @2.2 kΩ, 15pF
10
40
Rx Pulse Width of Output Signal, 50%
Pw
Input pulse length 20 µs, 9.6 kbit/s
1.2
Rx Pulse Width of Output Signal, 50%
Pw
Input pulse length 1.41µs, 115.2 kbit/s
mode
1.2
2.2
Rx Pulse Width of Output Signal, 50%
Pw
Input pulse length 217 ns, 4.0 Mbit/s
mode
190
260
Rx Pulse Width of Output Signal, 50%
Pw
Input pulse length 125 ns, 4.0 Mbit/s
mode
90
165
Rx Pulse Width of Output Signal, 50%
Pw
Input pulse length 250 ns, 4.0 Mbit/s
mode (double pulse)
210
290
mW/m2
kW/m2
10
mW/m2
10
ns
20
µs
ns
Input Irradiance = 90 mW/m2,
4.0 Mbit/s mode
Jitter, Leading Edge
Latency
10
120
µs
0.48
0.55
A
140
280
mW/sr
.04
mW/sr
900
nm
800
mV
40
ns
25
%
tL
Transmitter
IRED Operating Current
ID
VCC = 5 V, R1= 5.6 Ω
Output Radiant Intensityd
Ie
Txd = High, SD = Low,
R1= 5.6 Ω
Output Radiant Intensity Half Angle
α
Output Radiant Intensityd
Ie
Peak Wavelength
λP
±24
Txd = Low or SD = Highe, RL=5.6 Ω
880
IF = 600 mA, pulse length 2 µs, duty
cycle 25%
Voltage drop at output driver
Rise Time, Fall Time
120
tR, tF
400
10
Optical Overshoot
Notes
a. Tamb = 25C, VCC = 2.7 – 5.5 V unless otherwise noted.
b. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum.
c. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
d. VCC = 5 V, a = 0, 15
e. Receiver is inactive as long as SD = High
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Semiconductors
Recommended Circuit Diagram
TEMIC FIR transceivers integrate a sensitive receiver
and a built–in power driver. The combination of both
needs a careful circuit board layout. The use of thin, long
resistive and inductive wiring should be avoided. The
inputs (Txd, SD/Mode) and the output Rxd should be
directly (DC) coupled to the I/O circuit.
300
250
Intensity (mW/sr)
The only required components for designing an IrDA 1.2
compatible design using TEMIC FIR transceivers are a
current limiting resistor, R1, to the IRED. However,
depending on the entire system design and board layout,
additional components may be required (see Figure 1).
200
5.25 V, Min. Efficiency,
Min. VF, Min. RDSon
150
4.75 V, Min. Efficiency,
Min. VF, Max. RDSon
100
50
IrDA Field of View: Cone of 15
0
4.0
6.0
8.0
10.0
12.0
14.0
16.0
VCC2
Current Control Resistor (W)
TFDx6x00
R1
Figure 2. Ie vs. Rl
IRED
Cathode
R2
Rxd
Txd
Rxd
C1
C2
VCC
GND
IRED
Anode
Txd
SD/Mode
NC
GND
The placement of these parts is critical. It is strongly
recommended to position C2 as near as possible to the
transceiver power supply pins. A tantalum capacitor
should be used for C1 while a ceramic capacitor is used
for C2. Also, when connecting the described circuit to the
power supply, low impedance wiring should be used.
Table 1. Recommended Application Circuit Components
SC
Note: Outlined components are optional depending on quality of
power supply.
Figure 1. Recommended Application Circuit
R1 is used for controlling the current through the IR
emitter. For increasing the output power of the IRED, the
value of the resistor should be reduced. Similarly, to
reduce the output power of the IRED, the value of the
resistor should be increased. For typical values of R1 see
Figure 2 . For IrDA compliant operation, a current control
resistor of 5.6 Ω is recommended. The upper drive current
limitation is dependent on the duty cycle and is given by
the absolute maximum ratings on the data sheet.
R2, C1 and C2 are optional and dependent on the quality
of the supply voltage VCC and injected noise. An unstable
power supply with dropping voltage during transmission
may reduce sensitivity (and transmission range) of the
transceiver.
Component
Recommended Value
C1
4.7 mF, Tantalum
C2
0.1 µF, Ceramic
R1
5.6 Ω , 0.25 W (recommend using two 0.125 W
resistors in parallel)
R2
47 Ω , 0.125 W
Mode Switching
The TFDU6100E, TFDS6500E and TFDT6500E powers
on in a no default mode, therefore the data transfer rate
has to be set by a programming sequence as described
below or selected by setting the mode pin. When using the
Mode pin, the standby current might be increased to about
50 to 60 µA. In standby mode, the mode input should float
to minimize standby current.
The low frequency mode covers speeds up to 115.2 kbit/s.
Signals with higher data rates should be detected in the
high frequency mode. Lower data frequency data can also
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received in high frequency mode with reduced sensitivity.
To switch the transceivers from low frequency mode to
the 4.0 Mbit/s mode and vice versa, the programming
sequences described below are required.
2. Set Txd input to logic ”HIGH”. Wait ts w200 ns.
3. Set SD/MODE to logic ”LOW” (this negative edge
latches state of Txd, which determines speed setting).
4. After waiting th w200 ns Txd can be set to logic
”LOW”. The hold time of Txd is limited by the
maximum allowed pulse length.
SD/Mode
ts
Txd is now enabled as normal Txd input for the high
bandwidth mode.
th
High
Setting to the Lower Bandwidth Mode (2.4 to
115.2 kbit/s)
Txd
Low
High: FIR
Low: SIR
Mode Pin
Figure 3. Timing Diagram
Setting to the High Bandwidth Mode (0.576 to
4.0 Mbit/s)
1. Set SD/MODE input to logic ”HIGH”.
1. Set SD/MODE input to logic ”HIGH”.
2. Set Txd input to logic ”LOW”. Wait ts w200 ns.
3. Set SD/MODE to logic ”LOW” (this negative edge
latches state of Txd, which determines speed setting).
4. Txd must be held for th w200 ns.
Txd is now enabled as normal Txd input for the lower
bandwidth mode.
Pending—Rev. A, 03-Apr-98
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TFDU6100E/TFDS6500E/TFDT6500E
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Semiconductors
TFDU6100E – BabyFace (Universal) Package
Mechanical Dimensions
8
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TFDU6100E/TFDS6500E/TFDT6500E
Semiconductors
TFDS6500E – Side View Package
Mechanical Dimensions
TK84 731
TFDS6500
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TFDU6100E/TFDS6500E/TFDT6500E
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TFDT6500E – Top View Package
Mechanical Dimensions
10
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TFDU6100E/TFDS6500E/TFDT6500E
Recommended SMD Pad Layouta
TFDU6100E - BabyFace (Universal) Package
0.8
TFDT6500E - Top View Package
TFDS6500E - Side View Package
a.
(note: leads of the device should be at least 0.3 mm
within the ends of the pads. Pad 1 is longer to designate
Pin 1 connection to transceiver.)
The leads of the device should be sodered in the center position pads.
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Recommended Solder Profile
260
10 s Max. @ 230 C
240
220
2 – 4 C/Seconds
C)
200
Temperature (
180
160
140
120 – 180 Seconds
90 s Max.
120
100
80
2 – 4 C/Seconds
60
40
20
0
0
50
100
150
200
250
300
350
Time (Seconds)
Current Derating Curve
600
Peak Operating Current (mA)
500
400
300
Current derating as a function of the
maximum forward current of IRED.
Maximum duty cycle: 25%
200
100
0
–40
–20
0
20
40
60
80
100
120
140
Temperature (C)
12
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