www.fairchildsemi.com FAN8036 5-CH Motor Driver + 2-Regulator Features Description • • • • • • • • • The FAN8036 is a monolithic integrated circuit suitable for a 5-CH motor driver which drives the tracking actuator, focus actuator, sled motor, spindle motor, and tray motor of the CDP/CAR-CD/DVDP systems. 4-CH Balanced Transformerless (BTL) Driver 1-CH (Forward Reverse) Control DC Motor Driver Operating Supply Voltage (4.5V ~ 13.2V) Built in Thermal Shut Down Circuit (TSD) Built in Channel Mute Circuit Built in Power Save Mode Circuit Built in TSD Monitor Circuit Built in 2 Regulators Built in 2-OP AMPs Typical Application • • • • Compact Disk Player Video Compact Disk Player Car Compact Disk Player Digital Video Disk Player 48-QFPH-1414 Ordering Information Device Package Operating Temperature FAN8036L 48-QFPH-1414 -35°C ~ +85°C FAN8036_NL 48-QFPH-1414 -35°C ~ +85°C Rev. 1.0.1 ©2003 Fairchild Semiconductor Corporation FAN8036 Pin Assignments IN1+ OPIN1+ OPIN1- OPOUT1 SVCC VREF 48 47 46 45 44 FIN (GND) REGVCC OPIN2+ OPIN2- OPOUT2 PVCC1 DO1+ 43 42 41 40 39 38 37 IN1- 1 36 DO1- OUT1 2 35 DO2+ IN2+ 3 34 DO2- IN2- 4 33 PGND1 OUT2 5 32 REGO1 RES1 6 31 REGO2 FIN (GND) FIN (GND) FAN8036 RES2 7 30 DO3+ REGCTL 8 29 DO3- IN3+ 9 28 DO4+ IN3- 10 27 DO4- OUT3 11 26 PGND2 IN4+ 12 25 DO5+ 2 18 13 14 15 16 17 IN4- OUT4 CTL FWD REV SGND 19 20 FIN MUTE123 MUTE4 (GND) 21 PS 22 23 TSD_M PVCC2 24 DO5- FAN8036 Pin Definitions Pin Number Pin Name I/O Pin Function Descrition 1 IN1− I CH1 OP-AMP Input (−) 2 OUT1 O CH1 OP-AMP Output 3 IN2+ I CH2 OP-AMP Input (+) 4 IN2− I CH2 OP-AMP Input (−) 5 OUT2 O CH2 OP-AMP Output 6 RES1 I Regulator1 Reset 7 RES2 I Regulator2 Reset 8 REGCTL I Regulator2 Control Voltage 9 IN3+ I CH3 OP-AMP Input (+) 10 IN3− I CH3 OP-AMP Input (−) 11 OUT3 O CH3 OP-AMP Output 12 IN4+ I CH4 OP-AMP Input (+) 13 IN4− I CH4 OP-AMP Input (−) 14 OUT4 O CH4 OP-AMP Output 15 CTL I CH5 Motor Speed Control 16 FWD I CH5 Forward Input 17 REV I CH5 Reverse Input 18 SGND - Signal Ground 19 MUTE123 I Mute for CH1,2,3 20 MUTE4 I Mute for CH4 21 PS I Power Save 22 TSD-M O TSD Monitor 23 PVCC2 - Power Supply Voltage 2 (for CH3,CH4,CH5) 24 DO5− O CH5 Drive Ouptut (−) 25 DO5+ O CH5 Drive Output (+) 26 PGND2 - Power Ground 2 (for CH3,CH4,CH5) 27 DO4− O CH4 Drive Ouptut (−) 28 DO4+ O CH4 Drive Output (+) 29 DO3− O CH3 Drive Ouptut (−) 30 DO3+ O CH3 Drive Output (+) 31 REGO2 O Regulator2 Ouptut 32 REGO1 O Regulator1 Ouptut 3 FAN8036 Pin Definitions (Continued) 4 Pin Number Pin Name I/O Pin Function Descrition 33 PGND1 - Power Ground 1 (for CH1, CH2) 34 DO2− O CH2 Drive Ouptut (−) 35 DO2+ O CH2 Drive Output (+) 36 DO1− O CH1 Drive Ouptut (−) 37 DO1+ O CH1 Drive Output (+) 38 PVCC1 - Power Supply Voltage 1 (for CH1, CH2) 39 REGVCC - Regulator Supply Voltage( Regulator1,2) 40 OPOUT2 O Normal OP-AMP2 Output 41 OPIN2− I Normal OP-AMP2 Input (−) 42 OPIN2+ I Normal OP-AMP2 Input (+) 43 VREF I Bias Voltage Input 44 SVCC - Signal & OPAMPs Supply Voltage 45 OPOUT1 O Normal OP-AMP1 Output 46 OPIN1− I Normal OP-AMP1 Input (−) 47 OPIN1+ I Normal OP-AMP1 Input (+) 48 IN1+ I CH1 OP-AMP Intput (+) FAN8036 Internal Block Diagram IN1+ OPIN1+ OPIN1- OPOUT1 SVCC VREF 48 47 46 45 44 FIN (GND) 43 REGVCC OPIN2+ OPIN2- OPOUT2 PVCC1 DO1+ 42 41 40 39 38 37 REGVCC IN1- 1 36 DO1- OUT1 2 35 DO2+ IN2+ 3 34 DO2- IN2- 4 33 PGND1 32 REGO1 31 REGO2 REGVCC REGVCC OUT2 5 RES1 6 TSD REGVCC REGVCC FIN (GND) FIN (GND) RES2 7 30 DO3+ REGCTL 8 29 DO3- IN3+ 9 28 DO4+ IN3- 10 27 DO4- OUT3 11 26 PGND2 25 DO5+ IN4+ S W 12 M S C + D - D MUTE123 MUTE4 13 IN4- 18 14 15 16 17 OUT4 CTL FWD REV SGND 19 20 FIN MUTE123 MUTE4 (GND) PS TSD_M 21 22 PS 23 TSD_M PVCC2 24 DO5- 5 FAN8036 Equivalent Circuits Description Pin No Internal Circuit VCC BTL INPUT & OP AMP1 INPUT 48,3,9,12,47 1,4,10,13,46 VCC 2K 2K 48 3 1 4 9 12 10 13 47 46 VCC VCC 5K OP AMP2 INPUT 5K 41,42 42 41 VCC VCC 1K VREF 43 43 1K VCC BTL OP AMP OUT OP AMP1 OUT 2,5,11,14,45 2 5 11 14 45 6 5K VCC FAN8036 Equivalent Circuits (Continued) Description Pin No Internal Circuit VCC OP AMP2 OUT VCC 40 0.05K 40 0.05K VCC 20K MUTE123,4 19,20 50K 19 20 50K VCC CTL 15 1K 15 39K TSD-M 22 22 20k 7 FAN8036 Equivalent Circuits (Continued) Description Pin No Internal Circuit VCC 100k PS 21 50K 21 50K VCC 30K FWD,REV 16,17 30K 16 30K 17 30K freewheeling diode VCC vcc BTL CH1,2,3,4 OUTPUT 27,28,29,30, 34,35,36,37 27 28 29 30 34 35 36 37 VCC 40K 7K parastic diode freewheeling diode VCC vcc BTL CH5 OUTPUT 24,25 24 VCC 25 60K 7K parastic diode 8 FAN8036 Equivalent Circuits (Continued) Description Pin No Internal Circuit 39 REGVCC 10K REGO1,2 31,32 31 10K 32 10K VCC RES1,2 6,7 50K 6 7 50K VCC REGCTL 8 VCC 2K 8 10K 9 FAN8036 Absolute Maximum Ratings ( Ta=25°C) Parameter Maximum Supply Voltage Symbol Value Unit SVCCMAX 18 V PVCC1 18 V PVCC2 18 V REGVCC 18 V note W Power Dissipation 3 PD Operating Temperature TOPR −35 ~ +85 °C Storge Temperature TSTG −55 ~ +150 °C Maximum Output Current IOMAX 1 A Note: 1. When mounted on the PCB of which size is 114mm × 76mm × 1.6mm. 2. Power dissipation is derated with the rate of -24mW/°C for TA≥25°C. 3. Do not exceed PD and SOA. Pd (mW) 3,000 2,000 1,000 0 0 25 50 75 100 125 150 175 Ambient temperature, Ta [°C] Recommended Operating Conditions ( Ta=25°C) Parameter Operating Supply Voltage 10 Symbol Min. Typ. Max. Unit SVCC 4.5 - 13.2 V PVCC1 SVCC - 13.2 V PVCC2 SVCC - 13.2 V REGVCC 7 - 13.2 V FAN8036 Electrical Characteristics (SVCC =5V, PVCC1 = PVCC2 = 8V, TA = 25°C, unless otherwise specified) Parameter Symbol Quiescent Circuit Current ICC *note1 Conditions Min. Typ. Max. Unit Under no-load - 20 - mA Under no-load - - 1 mA - 0.5 V Power Save On Current IPS Power Save On Voltage VPSON Pin21 = Variation - VPSOFF Pin21 = Variation 2 - - V Mute123 On Voltage VMON123 Pin19 = Variation - - 0.5 V Mute123 Off Voltage VMOFF123 Pin19 = Variation 2 - - V Power Save Off Voltage Mute4 On Voltage VMON4 Pin20 = Variation - - 0.5 V Mute4 Off Voltage VMOFF4 Pin20 = Variation 2 - - V -100 - +100 mV BTL DRIVER CIRCUIT Output Offset Voltage VOO VIN = 2.5V Maximum Output Voltage1 VOM1 RL = 10Ω, CH1,2 4.5 6.0 - V Maximum Output Voltage2 VOM2 RL = 18Ω, CH3,4,5 5.5 6.5 - V Closed-loop Voltage Gain AVF VIN = 0.1Vrms 16.8 18 19.2 dB RR VIN = 0.1Vrms, f = 120Hz - 60 - dB SR Square, Vout = 4Vp-p 1 2 - V/µs Ripple Rejection Ratio *note2 Slew Rate*note2 INPUT OPAMP CIRCUIT VOF1 - -10 - +10 mV IB1 - - - 400 nA High Level Output Voltage1 VOH1 - 4.4 4.7 - V Low Level Output Voltage1 VOL1 - - 0.2 0.5 V Output Sink Current1 ISINK1 RL = 50Ω 1 2 - mA ISOU1 RL = 50Ω 1 2 - mA -0.3 - 4.0 V Input Offset Voltage1 Input Bias Current1 Output Source Current1 Common Mode Input Range1 Open Loop Voltage Gain1 *note2 *note2 Ripple Rejection Ratio1*note2 Common Mode Rejection Ratio1*note2 Slew Rate1 *note2 Vicm1 - GVO1 VIN = −75dB - 80 - dB RR1 VIN = −20dB, f = 120Hz - 65 - dB VIN = −20dB - 80 - dB Square, Vout = 3Vp-p - 1.5 - V/µs CMRR1 SR1 Note : 1. When the voltage at pin 39 goes below 0.5V, the power save circuit makes the main bias current sources stop operating. As a result, the whole circuits are disable. ( The whole circuits mean the driver circuit, the input OP amp circuit, and the normal OP amp circuit.) 2. Guaranteed field.(No EDS/Final test) 11 FAN8036 Electrical Characteristics (Continued) (SVCC = 5V, PVCC1 = PVCC2 = 8V, TA = 25°C, unless otherwise specified) Parameter Symbol Conditions Min. Typ. Max. Unit VOF2 - -10 - +10 mV IB2 - - - 400 nA High Level Output Voltage 2 VOH2 - 4.4 4.7 - V Low Level Output Voltage 2 VOL2 - - 0.2 0.5 V Output Sink Current 2 ISINK2 RL= 50Ω 2 4 - mA ISOU2 RL= 50Ω 2 4 - mA -0.3 - 4.0 V NORMAL OP AMP CIRCUIT 1 Input Offset Voltage 2 Input Bias Current 2 Output Source Current 2 Common Mode Input Range 2 Open Loop Voltage Gain 2 *note *note Ripple Rejection Ratio 2*note Common Mode Rejection Ratio 2 Slew Rate 2 *note *note Vicm2 - GVO2 VIN = −75dB - 80 - dB RR2 VIN = −20dB, f = 120Hz - 65 - dB VIN = −20dB - 80 - dB Square, Vout = 3Vp-p - 1.5 - V/µs CMRR2 SR2 NORMAL OP AMP CIRCUIT 2 VOF3 - -15 - +15 mV IB3 - - - 400 nA High Level Output Voltage 3 VOH3 - 3 3.8 - V Low Level Output Voltage 3 VOL3 - - 1.0 1.5 V Output Sink Current 3 ISINK3 RL = 50Ω 10 - - mA Output Source Current 3 ISOU3 RL = 50Ω 10 - - mA Open Loop Voltage Gain 3*note GVO3 VIN = −75dB - 80 - dB RR3 VIN = −20dB, f = 120Hz - 65 - dB VIN = −20dB - 80 - dB Square, Vout = 3Vp-p - 1.5 - V/µs Input Offset Voltage 3 Input Bias Current 3 Ripple Rejection Ratio 3 *note Common Mode Rejection Ratio 3 Slew Rate 3 *note *note CMRR3 SR3 TRAY DRIVE CIRTUIT Input High Level Voltage VIH - 2 - - V Input Low Level Voltage VIL - - - 0.5 V Output Voltage 1 VO1 PVCC2 = 8V, VCTL = 3V, RL= 45Ω - 6 - V Output Voltage 2 VO2 PVCC2 = 8V, VCTL = 1.5V, RL = 10Ω - 3 - V Output Load Regulation ∆VRL VCTL=3V, IL=100mA → 400mA - 300 700 mV Output Offset Voltage 1 VOO1 VIN = 5V, 5V -40 - +40 mV Output Offset Voltage 2 VOO2 VIN = 0V, 0V -40 - +40 mV Note: Guaranteed field.(No EDS/Final test) 12 FAN8036 Electrical Characteristics (Continued) (SVCC = 5V, PVCC1 = PVCC2 = 8V, TA = 25°C, unless otherwise specified) Parameter Symbol Conditions Min. Typ. Max. Unit IL=0→ 200mA -80 0 0 mV IL=200mA,V=7V→ 9V -20 0 +30 mV REGULATOR1 CIRCUIT(REGVCC=8V) ∆VRL1 ∆VCC1 Load regulation Line regulation Regulator output voltage 1 VREG1 IL=100mA 4.75 5.0 5.25 V Regulator reset on voltage 1 Reson1 Pin6=Variation - - 0.5 V Regulator reset off voltage 1 Resoff1 Pin6=Variation 2 - SVCC V Vin=1Vp-p, f=120Hz - 55 - dB Ripple Rejection 1 *note RR1 REGULATOR2 CIRCUIT(REGVCC=8V) ∆VRL2 ∆VCC2 IL=0→ 200mA -80 0 0 mV Line regulation IL=200mA,V=7V→ 9V -20 0 +30 mV Regulator output voltage 2 range VREG2R IL=100mA 1.5 - 4.5 V IL=100mA,VREGCTL=0V 1.482 1.56 1.638 V IL=100mA,VREGCTL=1.9V 3.135 3.3 3.465 V Load regulation Regulator output voltage 2 VREG2 Regulator reset on voltage 2 Reson2 Pin7=Variation - - 0.5 V Regulator reset off voltage 2 Resoff2 Pin7=Variation 2 - SVCC V 0.75 0.95 1.15 V/V - 55 - dB Control Gain Ripple Rejection 2 GREGCTL *note RR2 Vin=1Vp-p, f=120Hz Note: Guaranteed field.(No EDS/Final test) 13 FAN8036 Application Information 1. Thermal Shutdown SVCC • The TSD circuit is activated at the junction temperature of 160°C and deactivated at 135°C with the hysteresis of 25°C. During the thermal shutdown, the TSD circuit keeps all the output driver off. IREF Output driver Bias R1 Q0 R2 Hysteresis Ihys R3 2. CH Mute Function • When the mute pin is high, the TR Q1 is on and Q2 is off, so the bias circuit is enabled. When the mute pin is low (GND), the TR Q1 is off and Q2 is on, so the bias circuit is disabled. • During the mute on state, all the circuit blocks except for the variable regulator remain off, and the low power quiescent state is established. • Truth table is as follows; Pin 19, 20 Mute High Mute-Off Low Mute-On SVCC Bias Blocks (4-CH BTL) 19 Q2 20 Q1 MUTE 3. Power Save Function • When the pin21 is high, the TR Q3 becomes on and Q4 off, so the bias circuit is enabled. When the pin21 is low (GND) , the TR Q3 becomes off and Q4 is on, so the bias circuit is disabled. • During the power save on state, this function keeps all the circuit blocks off, and the low power quiescent state is established. • Truth table is as follows; Pin21 Power Save High Power Save Off Low Power Save On SVCC M ain Bias Q4 21 Q3 4. TDS Monitor Function • Pin 22 is TSD monitor pin, which detects the state of the TSD block and generates the TSD-monitor signal. • In the normal state Q5 is on, and Q6 is off. When the TSD block is activated Q5 becomes off, and thus the voltage of pin22 keeps low. • Truth table is as follows; 14 TSD Pin22 TSD Off High TSD On Low SVCC VCC R(external) 20K 22 Q6 Q5 FAN8036 5. Focus, Tracking Actuator, Spindle, Sled Motor Drive Part 40K VREF 10K 43 DO+ 10K IN+ 48 3 9 4 10 13 2 5 11 14 30 28 36 34 29 27 M Vp IN1 35 40K Vin 12 37 40K OUT 10K PVCC1(PVCC2) DO- 10K + VDP - 40K 60K 62K Vp QP • The Vref at pin 43 is for eliminating the dc components from the input signals and can set by an exteranl circuit. • The voltage gain from Vin to output is as follows ; Vin = Vref + ∆V DOP = V D + 4 ∆V DON = V D – 4 ∆V Vout = DOP – DON = 8 ∆V Vout Gain = 20 log ------------- = 20 log 8 = 18dB ∆V • • • • Where ∆V means just ac component. The total input to output voltage gain is the sum of the input OP amp network gain and 18dB. The output stage is the balanced transformerless (BTL) driver. The bias voltage Vp is expressed as ; 62k V P = ( PVCC1 – V DP – V CESAT Q P ) × -------------------------- + V CESAT Q P 60k + 62k PVCC1 – V DP – V CESAT Q P = ------------------------------------------------------------------------- + V CESAT Q P 1.97 ---------- (1) 15 FAN8036 6. Tray, Changer,panel Motor Drive Part out 1 out 2 25 M 24 D D LEVEL SHIFT 6.0V M.S.C CTL V(out1,out2) 15 S.W 0 IN IN FWD REV 16 17 3.0V VCTL • Rotational direction control The forward and reverse rotational direction is controlled by FWD (pin16) and REV (pin17) and the input conditions are as follows; INPUT OUTPUT FWD REV OUT 1 OUT 2 State H H Vp Vp Brake H L H L Forward L H L H Reverse L L - - Hign impedance • Where Vp(Power reference voltage) is approximately 3.75V at PVCC2=8V according to equation (1). • Motor speed control (When SVCC=5V, PVCC2=8V) - The maximum torque is obtained when the pin15(CTL) is open. - If the voltage of the pin15 (CTL) is 0V, the motor will not operate. - When the control voltage (pin15) is between 0 and 3.0V, the differential output voltage V(out1,out2) is about two times of control voltage. The output gain is 6dB. - When the control voltage is greater than 3.0V, the output voltage is saturated at the 6.0V because of the output swing limitation. 16 FAN8036 7. Regulator1 Part REGVCC REGVCC 39 VREF1 2.5V 32 RES1 6 R1 10K R2 10K REGO1 33uF • The output voltage of the regulator1 is fixed to 5V. • When power save on or TSD on, regulator1 is disabled. • Truth table is as follows; RES1(Pin6) REGO1 HIGH Active LOW Deactive 17 FAN8036 8. Regulator2 Part REGVCC REGVCC R EG O 2 39 4.2V VREF2 2.5V RES2 REGCTL 7 R3 R4 8 10K 40K G ain=0.95 REGO2 31 1.77V 33uF 1.56V 0.3V R E G C TL • The output of the regulator2 is variable. • The input impedance of the REGCTL pin is 50kΩ. • The REGCTL input circuit is as follows; VCC FAN8036 R1 8 R2 REGCTL 50K • The output voltage(VREGO2) is decided as follows; VREGO 2 = (1.56V + VREGCTL ) × 0.95 • When the REGCTL pin is connect to the ground or open, the regulator output voltage becomse1.56V. • When power save on or TSD on, regulator2 is disabled. • Truth table is as follows; 18 RES2(Pin7) REGO2 HIGH Active LOW Deactive FAN8036 Test Circuits VCC OP-AMP IN- OUT 47 46 45 48 IN+ OP-AMP VREF IN+ 44 PVCC1 REGVCC 43 IN+ IN- OUT 42 41 40 39 38 37 OPIN2+ OPIN2- OPOUT2 PVCC1 REGVCC IN1+ OPIN1+ OPIN1- OPOUT1 SVCC VREF OP-AMP DO1+ RL1 IN- 1 IN1- DO1- 36 OUT 2 OUT1 DO2+ 35 IN+ 3 IN2+ DO2- 34 IN- 4 IN2- PGND1 33 OUT 5 OUT2 REGO1 32 6 RES1 REGO2 31 RL2 OP-AMP VRES1 FAN8036 IL1 IL2 DO3+ VRES2 7 RES2 VREGCTL 8 REGCTL DO3- 29 IN+ 9 IN3+ DO4+ 28 IN- 10 IN3- DO4- 27 OUT 11 OUT3 PGND2 12 IN4+ 30 RL3 RL4 OP-AMP IN+ 26 DO5+ 25 IN4- OUT4 CTL FWD REV SGND 13 14 15 16 17 18 IN- OUT VCTL VFWD VREV MUTE123 MUTE4 19 V MU123 20 PS TSD-M PVCC2 DO5- 21 VMU4 22 23 RL5 24 V PS OP-AMP PVCC2 OP-AMP IN+ IN- SW1 OUT SW2 RL SW4 VPULSE VAC VDC VA VCC SW3 VB 19 FAN8036 Typical Application Circuits 1 [Voltage control mode] REGVCC PVCC1 41 40 39 38 37 PVCC1 DO1+ OPOUT1 42 REGVCC OPIN1- 43 OPOUT2 OPIN1+ 44 OPIN2- 45 OPIN2+ 46 VREF 47 SVCC 48 IN1+ SVCC FOCUS DO1- 36 1 IN1- 2 OUT1 DO2+ 35 3 IN2+ DO2- 34 4 IN2- PGND1 33 5 OUT2 REGO1 32 REGO1 6 RES1 REGO2 31 REGO2 TRACKIN G FAN8036 VCC 7 RES2 DO3+ 30 8 REGCTL DO3- 29 9 IN3+ DO4+ 28 10 IN3- DO4- 27 11 OUT3 PGND2 26 12 IN4+ DO5+ 25 M SLED M 18 19 DO5- SGND 17 PVCC2 REV 16 TSD_M FWD 15 PS CTL 14 MUTE4 OUT4 13 MUTE123 IN4- SPINDLE 20 21 22 23 24 M TRAY PVCC2 VCC VREF FOCUS TRACKING SLED INPUT INPUT INPUT SPINDLE INPUT [SERVO PRE AMP] 20 REG1 RESET REG2 RESET TRAY CONTROL TRAY INPUT FOCUS TRACKING SLED MUTE [CONTROLLER] SPINDLE POWER TSD_M SAVE MUTE FAN8036 Typical Application Circuits 2 [Differential PWM control mode ] REGVCC 41 40 39 38 37 PVCC1 DO1+ OPOUT1 42 REGVCC OPIN1- 43 OPOUT2 OPIN1+ 44 PVCC1 OPIN2- 45 OPIN2+ 46 VREF 47 SVCC 48 IN1+ SVCC FOCUS DO1- 36 1 IN1- 2 OUT1 DO2+ 35 3 IN2+ DO2- 34 4 IN2- PGND1 33 5 OUT2 REGO1 32 REGO1 6 RES1 REGO2 31 REGO2 TRACKING FAN8036 VCC 7 RES2 DO3+ 30 8 REGCTL DO3- 29 9 IN3+ DO4+ 28 10 IN3- DO4- 27 11 OUT3 PGND2 26 12 IN4+ DO5+ 25 M SLED M 18 DO5- SGND 17 PVCC2 REV 16 TSD_M FWD 15 PS CTL 14 MUTE4 OUT4 13 MUTE123 IN4- SPINDLE 19 20 21 22 23 24 M TRAY PVCC2 VCC VREF FOCUS TRACKING SLED INPUT INPUT INPUT SPINDL E INPUT [SERVO PRE AMP] REG1 RESET REG2 TRAY RESET CONTROL TRAY INPUT FOCUS SPINDLE POWER TSD_M TRACKING MUTE SAVE SLED MUTE [CONTROLLER] Notes: Radiation pin is connected to the internal GND of the package. 21 FAN8036 Mechanical Dimensions Package 48-QFPH-1414 17.20 ±0.30 (4.85) 14.00 ±0.20 17.20 ±0.30 14.00 ±0.20 #48 #1 (0.825) 0.10MAX ° 0~8 +0.10 0.20 -0.05 2.60 ±0.10 3.00MAX 0.65 +0.10 0.30 -0.05 0.00~0.25 0.10MAX 22 0.80 ±0.20 FAN8036 DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com 5/22/03 0.0m 001 Stock#DSxxxxxxxx 2003 Fairchild Semiconductor Corporation