GTLP16612A 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 CMOS 18-Bit TTL/GTLP Universal Bus Transceiver Features Product Description Bidirectional interface between GTLP and TTL logic levels Pericom Semiconductors GTLP series of logic circuits are produced using the Companys advanced 0.5 micron CMOS technology, achieving industry leading performance. Designed with Edge Rate Control Circuit to reduce output noise The GTLP16612A 18-bit universal transceiver provides TTL to GTLP signal level translation. The device is designed to provide highspeed interface between cards operating at TTL logic levels and a back plane operating at GTLP logic levels. High-speed back plane operation is a direct result of GTLPs reduced output swing (<1V), reduced input threshold levels, and output edge-rate control which minimizes signal settling times. Its function is similar to BTL or GTL but with modified driver output levels and receiver threshold. GTLP output low voltage is typically less than 0.5V, the output high is 1.5V, and the receiver threshold is 1.0V. VREF pin provides external supply reference voltage for receiver threshold 5V tolerant inputs and outputs on A-Port Increased B-Port Drive, 50mA Bus-Hold data inputs on A-Port to eliminate the need for pull-up resistors for unused inputs Power up/down high impedance TTL compatible Driver and Control inputs A-Port Balanced Drive: 32mA/+32mA Pin Configuration Flow-through architecture Open drain on GTLP to support wired-or connection Package: 56-pin 240 Mil Wide Plastic TSSOP (A) Logic Block Diagram OEAB CEAB CLKAB LEAB LEBA CLKBA CEBA OEBA 1 56 55 2 28 30 29 27 1 of 18 Channels CE 1D CI CLK GTLP 54 B1 V A1 3 V CE 1D CI CLK OEAB 1 LEAB 2 55 CLKAB A1 3 54 B1 GND 4 53 GND A2 5 52 B2 56 CEAB A3 6 51 B3 VCC(3.3V) 7 50 VCCQ(5.0V) A4 8 49 B4 A5 9 48 B5 A6 10 47 B6 GND 11 46 GND A7 12 45 B7 A8 13 44 B8 56-Pin A,V A9 14 43 B9 A10 15 42 B10 A11 16 41 B11 A12 17 40 B12 GND 18 39 GND A13 19 38 B13 A14 20 37 B14 A15 21 36 B15 VCC(3.3V) 22 35 VREF A16 23 34 B16 A17 24 33 B17 GND 25 32 GND A18 26 31 B18 OEBA 27 30 CLKBA LEBA 28 29 CEBA 1 of 18 Channels 1 PS8431 09/24/99 GTLP16612A CMOS 18-Bit TTL/GTLP Universal Bus Transceiver 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Pin Descriptions Pin Name s D e s cription O EAB A- to- B O utput Enable (Active LO W) O EBA B- to- A O utput Enable (Active LO W) CEAB A- to- B Clock Enable (Active LO W) CEBA B- to- A Clock Enable (Active LO W) LEAB A- to- B Latch Enable (Transparent HIGH) LEBA B- to- A Latch Enable (Transparent HIGH) CLK AB A- to- B Clock Pulse CLK BA B- to- A Clock Pulse VREF GTLP Input Reference Voltage A- to- B TTL Data Inputs or B- to- A 3- State O utputs A1- A18 B1- B18 B- to- A GTLP Data Inputs or A- to- B O pen Drain O utputs Functional Description The PI74GTLP16612A combines a universal transceiver function with a TTL to GTLP translation. The A-Port and control pins operate at LVTTL or 5V TTL levels while the B-Port operates at GTLP levels. The transceiver logic includes D-type latches and D-type flip-flops to allow data flow in transparent, latched, and clock mode. The functional operation is described below: Truth Table(1) Inputs Output B M ode CEAB OEAB LEAB CLKAB A X H X X X Z L L L H X B0(2) L L L L X B0(3) X L H X L L X L H X H H L L L ↑ L L L L L ↑ H H Clocked Storage of A Data H L L X X B0(3) Clock Inhibit Latched Storage of A Data Transparent Notes: 1. A-to-B data flow is shown. B-to-A data flow is similar but uses OEBA, LEBA, CLKBA, and CEBA. 2. Output level before indicated steady-state input conditions were established, provided CLKAB was HIGH before LEAB went LOW. 3. Output level before indicated steady-state input conditions were established. 2 PS8431 09/24/99 GTLP16612A CMOS 18-Bit TTL/GTLP Universal Bus Transceiver 123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123 123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123 Absolute Maximum Ratings(4) (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature (TSTG) ............................................... 65°C to +150°C Supply Voltage (VCC, VCCQ) ................................................... 0.5V to +7.0V DC Input Voltage (VI) ........................................................... 0.5V to +7.0V DC Output Voltage (VO) Outputs 3-State .................................................................. 0.5V to +7.0V Outputs Active(5) ........................................................ 0.5V to VCC +0.5V DC Output Current into A-Port IOH /IOL ............................... 64mA/+64mA DC Output Sink Current into B-Port in LOW State IOL ...................... 100mA DC Input Diode Current (IIK) VI < 0V ............................................................................................ 50mA DC Output Diode Current (IOK) VO < 0V ........................................................................................... 50mA VO > VCC .......................................................................................... +50mA ESD Performance .............................................................................. >2000V Recommended Operating Condition(6) Supply Voltage (VCC) VCC ....................................................................................... 3.15V to 3.45V VCCQ ..................................................................................... 4.75V to 5.25V Bus Termination Voltage (VTT) .............................................. 1.35V to 1.65V Input Voltage (VI) on A-Port and Control Pins ........................ 0.0V to 5.5V HIGH Level Output Current (IOH) A-Port ............................................................................................ 32mA LOW Level Output Current (IOL) A-Port ............................................................................................ +32mA B-Port ............................................................................................. +50mA Operating Temperature (TA) ................................................ 40°C to +85°C Notes: 4. The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristic tables are not guaranteed at the absolute maximum rating. The Recommended Operating Conditions table will define the conditions for actual device operation. 5. IO Absolute Maximum Rating must be observed 6. Unused inputs must be held HIGH or LOW. 3 PS8431 09/24/99 GTLP16612A CMOS 18-Bit TTL/GTLP Universal Bus Transceiver 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 DC Electrical Characteristics (Over the Operating Free-Air Temperature Range, VREF = 1.0 (Unless otherwise noted) Symbol VIH VIL Te s t Conditions Min. B- Port VREF +0.1 Others 2.0 B- Port 0.0 Max. VREF 0.1 0.8 1.0 VIK A- Port VOH VCC = 3.15V, VCCQ = 4.75V II = 18mA VCC, VCCQ = Min. to Max(8) IOH = 100µA VCC = 3.15V VCCQ = 4.75V IOH = 8mA 2.4 IOH = 32mA 2.0 Max(8) 1.2 V VCC 0.2 IOL = 100µA 0.2 VCC = 3.15V VCCQ = 4.75V IOL = 32mA 0.5 B- Port VCC = 3.15V, VCCQ = 4.75V IOL = 50mA 0.65 Control Pins VCC, VCCQ = 0 or Max VI = 5.5V or 0V ±10 A- Port VCC = 3.45V VCCQ = 5.25V VI = 5.5V 20 VI = VCC 1 A- Port VOL VCC, VCCQ = Min. to II VI = 0 B- Port A- Port 30 VCC = 3.45V VI = VCCQ 5 VCCQ = 5.25V VI = 0 5 VCC = VCCQ = 0 VI or VO = 0 to 4.5V 100 II(HOLD) A- Port VCC = 3.15V, VCCQ = 4.75V VI = 0.8V 75 VI = 2.0V 20 IOZH VCC = 3.45V, VCCQ = 5.25V VO = 3.45V 1 VO = 1.5V 5 VCC = 3.45V VCCQ = 5.25V VO = 0 20 VO = 0.65V 10 Outputs HIGH 30 40 Outputs LOW 30 40 Outputs Disabled 30 40 Outputs HIGH 0 1 Outputs LOW 0 1 Outputs Disabled 0 1 0 1 A- Port B- Port IOZL Units VTT Others VREF IOFF Typ(7) A- Port B- Port ICCQ (VCCQ) A or B Ports VCC = 3.45V, VCCQ = 5.25V, IO = 0, VI = VCCQ or GND ICC (VCC) A or B Ports VCC = 3.45V, VCCQ = 5.25V, IO = 0, VI = VCCQ or GND One Input at 2.7V VCC = 3.45V, VCCQ = 5.25V, A or Control Inputs at VCC or GND ∆ΙCC(9) A- Port and Control Pins CIN Control Pins VI = VCCQ or 0 8 CI/O A- Port VI = VCCQ or 0 9 CI/O B- Port VI = VCCQ or 0 8 µA mA pF Notes: 7. All typical values are at VCC = 3.3V, VCCQ = 5.0V, and TA = 25°C 8. For conditions shown as Max. or Min., use the appropriate value specified under recommended operating conditions. 9. This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND. 4 PS8431 09/24/99 GTLP16612A CMOS 18-Bit TTL/GTLP Universal Bus Transceiver 123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123 123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123 AC Operating Requirements (Over recommended ranges of supply voltage and operating free-air temperature, VREF = 1.0 (Unless otherwise noted) Symbol fCLOCK tW tS tH M in. Max Clock Frequency Pulse Duration Setup Time Hold Time 175 LEAB or LEBA HIGH 3.0 CLK AB or CLK BA HIGH or LO W 3.2 A before CLK AB↑ 0.5 B before CLK BA↑ 3.1 A before LEAB↓ 1.3 B before LEBA↓ 3.7 CEAB before CLK AB↑ 0.4 CEBA before CLK BA↑ 1.0 A after CLK AB↑ 1.5 B after CLK BA↑ 0.0 A after LEAB↓ 0.5 B after LEBA↓ 0.0 CEAB after CLK AB↑ 1.5 CEBA after CLK BA↑ 1.7 5 M ax. Units MHz ns PS8431 09/24/99 GTLP16612A CMOS 18-Bit TTL/GTLP Universal Bus Transceiver 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 AC Electrical Characteristics (Over recommended ranges of supply voltage and operating free-air temperature, VREF = 1.0 (Unless otherwise noted) CL = 30pF for B-Port and CL = 50pF for A-Port. Symbol tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL From (Input) To (Output) A B LEAB B CLKAB B OEAB B M in. Typ.(10) M ax. 1.0 4.3 6.5 1.0 5.0 8.2 1.8 4.5 6.7 1.5 5.3 8.6 1.8 4.6 6.7 1.5 5.4 8.7 1.6 4.4 6.2 1.3 6.1 9.8 tRIS E Transition time, B outputs (20% to 80%) 2.6 tFALL Transition time, B outputs (20% to 80%) 2.6 tPLH tPHL tPLH tPHL tPLH tPHL tPZH, tPZL tPHZ, tPLZ B A LEBA A CLKBA A OEBA A Units ns 2.0 5.6 8.2 1.4 5.0 7.2 2.1 4.2 6.3 1.9 3.3 5.0 2.3 4.4 6.8 2.2 3.5 5.2 1.5 5.0 6.2 1.9 3.9 7.9 Note 10 : All typical values are at VCC = 3.3V, VCCQ = 5.0V, and TA= 25°C 6 PS8431 09/24/99 GTLP16612A CMOS 18-Bit TTL/GTLP Universal Bus Transceiver 123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123 123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123 Test Circuits and Timing Waveforms Test Circuit for B Outputs Test Circuit for A Outputs 1.5V (GTLP) 6V 500 Ω 1.2V (GTL) Open GND V From Output S Under Test 25Ω From 500 Output Ω V CL = 50pF Under 30pF Test CL includes probes and jig capacitance. CL includes probes and jig capacitance. For B-Port outputs, CL = 30pF is used for worst case edge rate Voltage Waveforms Propagation Delay Times (A-Port to B-Port) Voltage Waveforms Pulse Duration (Vm = 1.5V for A-Port and 1.0V for B-Port) 3.0V Input Vm V Vm V Voltage Waveforms Setup and Hold Times (Vm = 1.5V for A-Port and 1.0V for B-Port) Vm V tSU Data Input Vm V th 1.5V t PLH t PHL OUTPUT 0V Timing Input 1.5V INPUT tw 0V 1.0V 1.0V VOH VOL Voltage Waveforms Propagation Delay Times (B-Port to A-Port) 3.0V 0V Vm V 3.0V 1.0V 1.0V t PLH t PHL INPUT 3.0V OUTPUT 0V 1.5V 1.5V 0V 1.5V VOH VOL All input pulses have the following characteristics: frequency = 10 MHz, tp = 4 = 2ns, ZO = 50Ω. The outputs are measured one at a time with one transition per measurement. All input pulses have the following characteristics: frequency = 10 MHz, tr = tf = 2ns, ZO = 50Ω. The outputs are measured one at a time with one transition per measurement. Voltage Waveforms Enable and Disable Times (A-Port) Output Control Output Waveform 1 (S at 6V) Output Waveform 2 1.5V 3.0V 1.5V tPLZ tPZL 1.5V tPZH 1.5V 0V 3.0V VOL+0.3V VOL tPHZ VOH-0.3V VOH 0V Waveforn 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high when disabled by the output control. All input pulses have the following characteristics: frequency = 10 MHz, tr = tf = 2ns, ZO = 50Ω. The outputs are measured one at a time with one transition per measurement. 7 PS8431 09/24/99 GTLP16612A CMOS 18-Bit TTL/GTLP Universal Bus Transceiver 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 56-Pin TSSOP (240 MIL WIDE) - Package Code: A56 56 .236 .244 1 .547 .555 6.0 6.2 13.9 14.1 1.20 .047 Max. SEATING PLANE .004 0.09 .008 0.20 0.45 .018 0.75 .030 .0197 BSC 0.50 .07 .011 0.17 0.27 .002 .006 0.05 0.15 .319 BSC 8.1 X.XX DENOTES DIMENSIONS X.XX IN MILLIMETERS Ordering Information P/N GTLP16612AA De s cription 56- Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO- 153, 6.1mm Wide Pericom Semiconductor Corporation 2380 Bering Drive • San Jose, CA 95131 • 1-800-435-2336 • Fax (408) 435-1100 • http://www.pericom.com 8 PS8431 09/24/99