TI SN74GTLPH16612DL

SN74GTLPH16612
18-BIT LVTTL-TO-GTLP UNIVERSAL BUS TRANSCEIVER
SCES326 – MARCH 2000
D
D
D
D
D
D
D
Members of the Texas Instruments (TI)
Widebus Family
UBT  (Universal Bus Transceiver)
Combines D-Type Latches and D-Type
Flip-Flops for Operation in Transparent,
Latched, Clocked, or Clock-Enabled Mode
Translate Between GTLP Signal Levels and
LVTTL Logic Levels
Support Mixed-Mode (3.3 V and 5 V) Signal
Operation on A-Port and Control Inputs
B-Port Transition Time Optimized for
Distributed Backplane Loads
Ioff Supports Partial-Power-Down Mode
Operation
D
D
D
D
Bus Hold on A-Port Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
Distributed VCC and GND Pins Minimize
High-Speed Switching Noise
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
Package Options Include Plastic Shrink
Small-Outline (DL), and Thin Shrink
Small-Outline (DGG) Packages
NOTE: For tape and reel order entry:
The DGGR package is abbreviated to GR.
description
The SN74GTLPH16612 is a medium-drive, 18-bit UBT (universal bus transceiver) that provides
LVTTL-to-GTLP and GTLP-to-LVTTL signal-level translation. It allows for transparent, latched, clocked, or
clock-enabled modes of data transfer. This device provides a high-speed interface between cards operating at
LVTTL logic levels and backplanes operating at GTLP signal levels. High-speed (about two times faster than
standard LVTTL or TTL) backplane operation is a direct result of the reduced output swing (<1 V), reduced input
threshold levels, and OEC (output edge control ). These improvements minimize bus settling time and have
been designed and tested using several backplane models.
VTT
VTT
.25”
.25”
.875”
TI GTL16612
R TT
R TT
1.8
1.6
.625”
Conn.
1”
.625”
Conn.
1”
.625”
Conn.
1”
Conn.
Volts – V
1.4
.625”
Fairchild GTLP16612
1.2
1.0
TI GTLPH16612
0.8
1”
0.6
Rcvr
Rcvr
Rcvr
0.4
Drvr
Slot 1
Slot 2
Slot 8
0
Slot 16
20
10
30
t – Time – ns
Figure 1. Test Backplane Model With Output Waveform Results
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
TI, OEC, UBT, and Widebus are trademarks of Texas Instruments.
Copyright  2000, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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1
SN74GTLPH16612
18-BIT LVTTL-TO-GTLP UNIVERSAL BUS TRANSCEIVER
SCES326 – MARCH 2000
description (continued)
Figure 1 shows actual device output waveforms using a synchronous clock at 75 MHz. The test backplane is
a 16-slot, 14-inch board with loaded impedance of 33 Ω. VTT is 1.5 V, VREF is 1 V, and RTT pullup resistor is 50 Ω.
The driver is in slot 8, with receivers in alternate slots 1, 3, 5, 7, 10, 12, 14, and 16. Receiver slot 1 signals are
shown. The signal becomes progressively worse as the receiver moves closer to the driver or the spacing
between receiver cards is reduced. The clock is independent of the data and the system clock frequency is
limited by the backplane flight time to about 80 MHz to 90 MHz. This frequency can be increased even more
(30% to 40%) if the clock is generated and transmitted together with the data from the driver card (source
synchronous).
The SN74GTLPH16612 is a medium-drive (34 mA), 18-bit universal bus transceiver, containing D-type latches
and D-type flip-flops to allow data flow in transparent, latched, clocked, and clock-enabled modes. This UBT
can replace any of the functions shown in Table 1.
Table 1. SN74GTLPH16612 UBT Replacement Functions
8 BIT
9 BIT
10 BIT
16 BIT
18 BIT
Transceiver
FUNCTION
’245, ’623, ’645
’863
’861
’16245, ’16623
’16863
Buffer/driver
’241, ’244, ’541
’827
’16241, ’16244, ’16541
’16825
’16543
’16472
’16373
’16843
’16646, ’16652
’16474
Latched transceiver
’543
Latch
’373, ’573
Registered transceiver
’646, ’652
Flip-flop
’374, ’574
’843
’841
’821
’16374
Standard UBT
’16500, ’16501
Universal bus driver
’16835
Registered transceiver with CLK enable
’2952
Flip-flop with CLK enable
’377
’16470, ’16952
’823
Standard UBT with CLK enable
’16823
’16600, ’16601
SN74GTLPH16612 UBT replaces all above functions
GTLP is a TI derivative of the Gunning transceiver logic (GTL) JEDEC standard JESD 8-3. The ac specification
of the SN74GTLPH16612 is given only at the preferred higher noise-margin GTLP, but this device can be used
at either GTL (VTT = 1.2 V and VREF = 0.8 V) or GTLP (VTT = 1.5 V and VREF = 1 V) signal levels.
The B port normally operates at GTLP levels, while the A-port and control inputs are compatible with LVTTL
logic levels and are 5-V tolerant. VREF is the reference input voltage for the B port.
To improve signal integrity, the SN74GTLPH16612 B-port output transition time is optimized for distributed
backplane loads.
VCC (5 V) supplies the internal and GTLP circuitry, while VCC (3.3 V) supplies the LVTTL output buffers.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry holds unused or undriven LVTTL inputs at a valid logic state. Use of pullup or pulldown
resistors with the bus-hold circuitry is not recommended.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
The SN74GTLPH16612 is characterized for operation from –40°C to 85°C.
2
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SN74GTLPH16612
18-BIT LVTTL-TO-GTLP UNIVERSAL BUS TRANSCEIVER
SCES326 – MARCH 2000
DGG OR DL PACKAGE
(TOP VIEW)
OEAB
LEAB
A1
GND
A2
A3
VCC (3.3 V)
A4
A5
A6
GND
A7
A8
A9
A10
A11
A12
GND
A13
A14
A15
VCC (3.3 V)
A16
A17
GND
A18
OEBA
LEBA
1
56
2
55
3
54
4
53
5
52
6
51
7
50
8
49
9
48
10
47
11
46
12
45
13
44
14
43
15
42
16
41
17
40
18
39
19
38
20
37
21
36
22
35
23
34
24
33
25
32
26
31
27
30
28
29
POST OFFICE BOX 655303
CEAB
CLKAB
B1
GND
B2
B3
VCC (5 V)
B4
B5
B6
GND
B7
B8
B9
B10
B11
B12
GND
B13
B14
B15
VREF
B16
B17
GND
B18
CLKBA
CEBA
• DALLAS, TEXAS 75265
3
SN74GTLPH16612
18-BIT LVTTL-TO-GTLP UNIVERSAL BUS TRANSCEIVER
SCES326 – MARCH 2000
functional description
Data flow in each direction is controlled by the clock-enables (CEAB and CEBA), latch-enables (LEAB and
LEBA), clock (CLKAB and CLKBA), and output-enables (OEAB and OEBA).
For A-to-B data flow, when CEAB is low, the device operates on the low-to-high transition of CLKAB for the
flip-flop and on the high-to-low transition of LEAB for the latch path, i.e., if CEAB and LEAB are low, the A data
is latched, regardless of the state of CLKAB (high or low) and if LEAB is high, the device is in transparent mode.
When OEAB is low, the outputs are active. When OEAB is high, the outputs are in the high-impedance state.
The data flow for B to A is similar to A to B, except that CEBA, OEBA, LEBA, and CLKBA are used.
FUNCTION TABLE†
INPUTS
CEAB
OEAB
LEAB
X
H
L
L
L
OUTPUT
B
MODE
CLKAB
A
X
X
X
Z
Isolation
L
H or L
X
L
L
H or L
X
B0‡
B0§
Latched storage of A data
X
L
H
X
L
L
X
L
H
X
H
H
L
L
L
↑
L
L
L
L
L
↑
H
H
B0§
Transparent
Clocked storage of A data
H
L
L
X
X
Clock inhibit
† A-to-B data flow is shown. B-to-A data flow is similar, but uses OEBA, LEBA, CLKBA,
and CEBA.
‡ Output level before the indicated steady-state input conditions were established, provided
that CLKAB was high before LEAB went low.
§ Output level before the indicated steady-state input conditions were established.
4
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• DALLAS, TEXAS 75265
SN74GTLPH16612
18-BIT LVTTL-TO-GTLP UNIVERSAL BUS TRANSCEIVER
SCES326 – MARCH 2000
logic diagram (positive logic)
35
VREF
1
OEAB
CEAB
56
55
CLKAB
2
LEAB
28
LEBA
30
CLKBA
CEBA
29
27
OEBA
CE
1D
3
A1
54
B1
C1
CLK
CE
1D
C1
CLK
To 17 Other Channels
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5
SN74GTLPH16612
18-BIT LVTTL-TO-GTLP UNIVERSAL BUS TRANSCEIVER
SCES326 – MARCH 2000
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC: 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Input voltage range, VI (see Note 1): A-port and control inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
B port and VREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
Voltage range applied to any output in the high or power-off state, VO
(see Note 1): A port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
B port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
Current into any output in the low state, IO: A port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
B port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 mA
Current into any A-port output in the high state, IO (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 mA
Continuous current through each VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Package thermal impedance, θJA (see Note 3): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W
DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. This current flows only when the output is in the high state and VO > VCC.
3. The package thermal impedance is calculated in accordance with JESD 51.
recommended operating conditions (see Notes 4 through 6)
VCC
Supply voltage
VTT
Termination voltage
VREF
Supply voltage
VI
Input voltage
VIH
High level input voltage
High-level
VIL
Low level input voltage
Low-level
IIK
IOH
Input clamp current
IOL
MIN
NOM
MAX
3.3 V
3.15
3.3
3.45
5V
4.75
5
5.25
GTL
1.14
1.2
1.26
GTLP
1.35
1.5
1.65
GTL
0.74
0.8
0.87
GTLP
0.87
1
1.1
B port
VTT
5.5
Except B port
B port
Except B port
B port
Except B port
High-level output current
Low level output current
Low-level
VREF+50 mV
2
UNIT
V
V
V
V
V
VREF–50 mV
0.8
V
–18
mA
A port
–32
mA
A port
64
B port
34
mA
TA
Operating free-air temperature
–40
85
°C
NOTES: 4. All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application
report Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
5. Normal connection sequence is GND first, VCC = 5 V second, and VCC = 3.3 V, I/O, control inputs, VTT, and VREF (any order) last.
6. VTT and RTT can be adjusted to accommodate backplane impedances as long as they do not exceed the dc absolute IOL ratings.
Similarly, VREF can be adjusted to optimize noise margins, but normally is 2/3 VTT.
6
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• DALLAS, TEXAS 75265
SN74GTLPH16612
18-BIT LVTTL-TO-GTLP UNIVERSAL BUS TRANSCEIVER
SCES326 – MARCH 2000
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
VIK
VOH
A portt
TEST CONDITIONS
VCC (3.3 V) = 3.15 V,
VCC (5 V) = 4.75 V,
VCC (3.3 V) = 3.15 V to 3.45 V,
VCC (5 V) = 4.75 V to 5.25 V
3 V) = 3
15 V,
V
VCC (3
(3.3
3.15
VOL
II
A port
IOZL
ICC
(3.3
(3 3 V)
ICC
(5 V)
Ciio
75 V
VCC (5 V) = 4
4.75
IOH = –100 µA
VCC (3.3 V)
–0.2
IOH = –8 mA
IOH = –32 mA
2.4
UNIT
–1.2
V
V
2
IOL = 100 µA
IOL = 16 mA
VCC (5 V) = 4
4.75
75 V
MAX
0.2
0.4
IOL = 32 mA
IOL = 64 mA
0.55
0.5
0.65
VCC (3.3 V) = 3.15 V,
VCC (5 V) = 4.75 V,
IOL = 34 mA
VCC (3.3 V) = 0 or 3.45 V,
VCC (5 V) = 0 or 5.25 V,
VI = 5.5 V
10
A port
VCC (5 V) = 5.25 V
VI = 5.5 V
VI = VCC (3.3 V)
20
VCC (3.3 V) = 3.45 V,
VI = 0
VI = VCC (3.3 V)
–30
A port
A port
VCC (3
(3.3
3 V) = 3
3.45
45 V,
V
VCC (5 V) = 5
5.25
25 V
VCC = 0,
VI or VO = 0 to 4.5 V
VCC (3.3 V) = 3.15 V,
VCC (5 V) = 4.75 V
VCC (3.3 V) = 3.45 V,
VCC (3.3 V) = 3.45 V,
VCC (5 V) = 5.25 V,
VCC (5 V) = 5.25 V,
B port
VCC (3.3 V) = 3.45 V,
VCC (3.3 V) = 3.45 V,
VCC (5 V) = 5.25 V,
VCC (5 V) = 5.25 V,
A or B
ort
port
VCC (3
(3.3
3 V) = 3
3.45
45 V
V, VCC (5 V) = 5.25
5 25 V,
V IO = 0,
0
VI = VCC (3.3
(3 3 V) or GND§, VI = VTT or GND¶
B port
A port
A or B
ort
port
∆ICC (3.3 V)#
Ci
II = –18 mA
Control
inputs
Ioff
IOZH
VCC (3
(3.3
3 V) = 3
3.15
15 V,
V
TYP†
B port
B port
II(hold)
(
)
MIN
Control
inputs
A port
B port
VCC (3
(3.3
3 V) = 3
3.45
45 V
V, VCC (5 V) = 5.25
5 25 V,
V IO = 0,
0
VI = VCC (3.3
(3 3 V) or GND§, VI = VTT or GND¶
1
–5
100
µA
–75
±500
1
VO = 1.5 V
VO = 0
10
–1
VO = 0.65 V
Outputs high
–10
µA
µA
1
Outputs low
5
Outputs disabled
mA
1
Outputs high
120
Outputs low
120
Outputs disabled
120
VCC (3.3 V) = 3.45 V, VCC (5 V) = 5.25 V, One A-port or control input at 2.7 V,
Other A-port or control inputs at VCC (3.3 V) or GND
1
4
VO = 3.15 V or 0
VO = 1.5 V or 0
µA
75
VI = 0 to VCC (3.3 V)‡
VO = VCC (3.3 V)
VI = 3.15 V or 0
µA
µ
5
VI = 0
VI = 0.8 V
VI = 2 V
V
8.5
8
mA
mA
pF
pF
† All typical values are at VCC (3.3 V) = 3.3 V, VCC (5 V) = 5 V, TA = 25°C.
‡ This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another.
§ This is the VI for A-port or control inputs.
¶ This is the VI for B port.
# This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
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7
SN74GTLPH16612
18-BIT LVTTL-TO-GTLP UNIVERSAL BUS TRANSCEIVER
SCES326 – MARCH 2000
timing requirements over recommended ranges of supply voltage and operating free-air
temperature, VTT = 1.5 V and VREF = 1 V for GTLP (unless otherwise noted) (see Figure 2)
MIN
fclock
Clock frequency
tw
Pulse duration
tsu
th
Setup time
Hold time
LEAB or LEBA high
3.3
CLKAB or CLKBA high or low
5.7
A before CLKAB↑
1
B before CLKBA↑
1.8
A before LEAB↓
0.5
B before LEBA↓
1.2
CEAB before CLKAB↑
1.2
CEBA before CLKBA↑
1.4
A after CLKAB↑
1.9
B after CLKBA↑
0.5
A after LEAB↓
2.7
B after LEBA↓
3.5
CEAB after CLKAB↑
1.2
CEBA after CLKBA↑
1.1
MAX
UNIT
85
MHz
ns
ns
ns
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, VTT = 1.5 V and VREF = 1 V for GTLP (see Figure 2)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
fmax
B
LEAB
CLKAB
ten
tdis
tr
tf
B
OEAB
A
LEBA
OEBA
A
† All typical values are at VCC (3.3 V) = 3.3 V, VCC (5 V) = 5 V, TA = 25°C.
8
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
UNIT
MHz
6.9
3.2
7.3
3.4
7.8
2.8
7
2.8
7
2.6
Transition time, B outputs (80% to 20%)
CLKBA
ten
tdis
MAX
2.5
Transition time, B outputs (20% to 80%)
B
tpd
TYP†
85
A
tpd
MIN
ns
ns
ns
2.6
ns
1.5
5.7
1.8
5.7
2.3
5.5
1.8
6.1
1.8
6.1
ns
ns
SN74GTLPH16612
18-BIT LVTTL-TO-GTLP UNIVERSAL BUS TRANSCEIVER
SCES326 – MARCH 2000
PARAMETER MEASUREMENT INFORMATION
VTT
6V
500 Ω
From Output
Under Test
S1
Open
GND
CL = 50 pF
(see Note A)
500 Ω
25 Ω
S1
Open
6V
GND
TEST
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
From Output
Under Test
CL = 30 pF
(see Note A)
LOAD CIRCUIT FOR A OUTPUTS
LOAD CIRCUIT FOR B OUTPUTS
tw
3V
Input
3V
Timing
Input
1.5 V
0V
1.5 V
1.5 V
tsu
0V
VOLTAGE WAVEFORMS
PULSE DURATION
3V
Input
Test
Point
1.5 V
1.5 V
th
3V
Data Input
A Port
1.5 V
Data Input
B Port
VREF
1.5 V
0V
VTT
VREF
0V
0V
tPLH
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
tPHL
VTT
Output
VREF
VREF
3V
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
(A port to B port)
0V
tPLH
Output
Waveform 1
S1 at 6 V
(see Note B)
1.5 V
1.5 V
VOL
3V
1.5 V
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.3 V
VOL
tPHZ
tPZH
tPHL
VOH
Output
1.5 V
tPLZ
tPZL
VREF
VREF
1.5 V
0V
VTT
Input
Output
Control
1.5 V
VOH
VOH – 0.3 V
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
(A port)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
(B port to A port)
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
Figure 2. Load Circuits and Voltage Waveforms
POST OFFICE BOX 655303
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9
SN74GTLPH16612
18-BIT LVTTL-TO-GTLP UNIVERSAL BUS TRANSCEIVER
SCES326 – MARCH 2000
DISTRIBUTED-LOAD BACKPLANE SWITCHING CHARACTERISTICS
The previous switching characteristics table shows the switching characteristics of the device into a lumped load
(Figure 2). However, the designer’s backplane application most likely is a distributed load, the physical representation
as shown in Figure 3. This backplane, or distributed load, can be closely approximated to an RLC circuit, as in
Figure 4. This device has been designed for optimum performance into this RLC circuit. The following switching
characteristics table shows the switching characteristics of the device into the RLC load, to help the designer better
understand the performance of the GTLP device in this typical backplane. See www.ti.com/sc/gtlp for more
information.
38 Ω
.25”
Z0 = 70 Ω
2”
2”
.25”
38 Ω
1.5 V
1.5 V
1.5 V
Conn.
Conn.
Conn.
Conn.
19 Ω
1”
1”
1”
Rcvr
1”
Rcvr
From Output
Under Test
LL = 19 nH
Rcvr
CL = 9 pF
Drvr
Slot 1
Test
Point
Slot 2
Slot 9
Slot 10
Figure 3. Medium-Drive Test Backplane
Figure 4. Medium-Drive RLC Network
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, VTT = 1.5 V and VREF = 1 V for GTLP (see Figure 4)†
FROM
(INPUT)
PARAMETER
TO
(OUTPUT)
fmax
TYP‡
85
A
tpd
ten
tdis
MHz
4.3
ns
4.4
B
OEAB
tr
tf
UNIT
3.6
B
LEAB
CLKAB
4.1
4.3
ns
Rise time, B outputs (20% to 80%)
1.4
ns
Fall time, B outputs (80% to 20%)
2.1
ns
† TI SPICE simulation data
‡ All typical values are at VCC = 3.3 V, TA = 25°C.
10
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